CN117581366A - 3D semiconductor devices and structures - Google Patents

Abstract

The invention relates to a 3D device, the device comprising: a first level including a first transistor, the first level including a first interconnect; a second level including a second transistor, the second level overlying the first level; a third level including a third transistor, the third level overlying the second level; and a plurality of Electronic Circuit Units (ECUs), wherein each of the plurality of ECUs comprises a first circuit comprising a portion of the first transistor, wherein each of the plurality of ECUs comprises a second circuit comprising a portion of the second transistor, wherein each of the plurality of ECUs comprises a third circuit comprising a portion of the third transistor, wherein each of the ECUs comprises a vertical bus, and wherein each of the ECUs comprises at least one high resistivity trap rich layer.

Description

3D semiconductor devices and structures

Technical field

The present application relates to the general field of integrated circuit (IC) devices and fabrication methods, and more specifically to multi-layer or three-dimensional integrated memory circuit (3D memory) and three-dimensional integrated logic circuit (3D logic) devices and fabrication methods.

Background technique

Over the past 40 years, the functionality and performance of integrated circuits (ICs) have increased dramatically. This is largely due to the phenomenon of “scaling”; that is, with each successive generation of technology, component dimensions such as lateral and vertical dimensions within an IC decrease (“scale”). There are two main types of components in a complementary metal oxide semiconductor (CMOS) IC, namely transistors and wires. Through "scaling," transistor performance and density typically increase, which contributes to the previously mentioned increases in IC performance and functionality. However, the wires (interconnects) that connect transistors together degrade performance as they "scale." The current situation is that wires dominate the performance, functionality and power consumption of ICs.

3D stacking of semiconductor devices or chips is one way to solve the wire problem. By arranging transistors in three dimensions instead of two (as was the case in the 1990s), transistors in an IC can be placed closer together. This reduces wire length and keeps routing latency and routing low.

There are many technologies for building 3D stacked integrated circuits or chips, including:

·Through-silicon via (TSV) technology: multi-layer chips are constructed separately. After this, they can be bonded to each other and connected to each other through through silicon vias (TSVs).

·Monolithic 3D technology: With this method, multiple layers of transistors and wires can be built monolithically. Some monolithic 3D and 3D IC approaches are described in: U.S. Patents 8,273,610, 8,298,875, 8,362,482, 8,378,715, 8,379,458, 8,450,804, 8,557,632, 8,574,929, 8,581,349, 8,642,416, 8,669 ,778, 8,674,470, 8,687,399, 8,742,476, 8,803,206, 8,836,073, 8,902,663 , 8,994,404, 9,023,688, 9,029,173, 9,030,858, 9,117,749, 9,142,553, 9,219,005, 9,385,058, 9,406,670, 9,460,978, 9,509,313, 9,640,531, 9, Pending U.S. patent application publications and applications 14/642,724, 15/150,395, 15/173,686, 16/337,665, 16/558,304, 16/649,660, 16/836,659, 17/151,867, 62/651,722, 62/681,249, 62/713, 345 , 62/770,751, 62/952,222, 62/824,288, 63/075,067, 63/091,307, 63/115,000, 2020/0013791, 16/558,304; and PCT applications (and publications) PCT/US2010/052093, PCT/US201 1 /042071(W02012/015550), PCT/US2016/52726(WO2017053329), PCT/US2017/052359(W02018/071143), PCT/US2018/016759(WO2018144957); and PCT/US2018/523 32(WO 2019/060798). The contents of the above patents, publications, and applications are incorporated herein by reference in their entirety.

Electro-optical: There is also work on integrated monolithic 3D including different crystal layers, such as US patents 8,283,215, 8,163,581, 8,753,913, 8,823,122, 9,197,804, 9,419,031, 9,941,319, 10,679,977 and 10,943,934. The contents of the above patents, publications, and applications are incorporated herein by reference in their entirety.

In addition, U.S. Patent Application Publication 2018/0350823 and U.S. Patent Applications 62/963166, 62/963270, 62/983559, 62/986772, 63108433, 63/118908, 63/123464, 63/144970, 63/151664, and 17/151867 It is incorporated herein by reference in its entirety.

In addition, 3D technology according to some embodiments of the present invention may enable some very innovative IC device alternatives with reduced development costs, novel and simpler process flows, increased yield advantages, and other illustrative advantages.

Contents of the invention

The present invention relates to multilayer or three-dimensional integrated circuit (3D IC) devices and manufacturing methods. An important aspect of 3D IC is the technology that allows layer transfer. These include technologies that enable the reuse of donor wafers and those that enable the fabrication of active devices on transfer layers to be transferred with them.

Description of the drawings

Various embodiments of the present invention will be more fully understood and understood from at least the following detailed description taken in conjunction with the accompanying drawings, in which:

Figure 1 is an example illustration of 7nm 6T SRAM bit cell layout;

Figure 2 is an illustration of a memory structure with memory cells arranged in a 2D repeating pattern;

Figures 3A-3D are illustrative illustrations of various arrangements and customizations of the 2D repeating pattern memory structure of Figure 2;

Figures 4A-4C are illustrative cross-sectional views of Figures 3B-3D illustrating various cell-to-cell and intra-cell connections;

Figures 5A-5E are example illustrations of wordline pin/pad connection layouts and bitline pin/pad connection layouts;

Figure 6 is an example illustration of extending the memory layout concept to a multi-level memory structure;

Figure 7A is an illustration of Figure 43E of US application 16/558,304;

Figure 7B is an example illustration of a memory unit including a memory and a memory controller;

Figure 7C is an illustration of four memory cells formed into an array in Figure 7B;

Figure 7D is an example illustration of a wafer-sized array of memory cells;

Figures 7E-7G are cross-sectional views illustrating a memory layer formation process. The memory layer can be stored and then bonded to other device structures to form a system;

Figure 8 is an example illustration of the entire process flow for designing logic and memory;

9A-9G are illustrations of 3D layer formation processes that can form 3D computing devices;

10A-10D are illustrative illustrations of various power delivery substrate architectures that efficiently deliver power to multiple levels of active devices through heterogeneous integration;

Figure 10E is an example illustration of utilizing a buck converter or voltage regulator, which can be distributed to each area through a 3D system;

10F is an illustration of an example technology that provides an intentional stress relief mechanism that can be integrated into a 3D system;

Figure 11 is an example table illustrating that wafer processing costs are highly dependent on the type of process line used;

Figures 12A-12B are illustrative illustrations of coupling levels in preparation for hybrid bonding to pin/pad structures on a circuit;

Figures 13A-13B are illustrations of the staged integration of various 3D systems and the formation of various M levels;

Figures 14A-14E are illustrative illustrations of various levels of integration forming various types of 3D systems;

Figure 14F is an example illustration of various ESD protection functions connected to the Nano TSV and internal logic;

Figures 15A-15D are example illustrations of DieM levels as part of a 3D system with photonic X-Y connections;

Figure 15E is Figure 8 and Figure 9 of "Wireline/wirelessRF-Interconnect for future SoC" by Tam, Sai Wang et al., 2011 IEEE International Symposium on Radio Frequency Integration Technology, IEEE, 2011 copy. ;

Figure 15F is a schematic diagram of various structures and data of the on-chip transmission/interconnect network;

Figure 15G is a schematic diagram of an exemplary 3D system similar to the system shown in Figure 14E with an additional RF-M level;

Figure 15H is an illustration of an alternative 3D system device and structure to the meandering structure shown in Figure 15F;

15I is an example illustrative block diagram of a per-unit TL processor at the base level of the RF-M hierarchy with DMA options;

Figure 15J is an illustration of an alternative schematic diagram depicting data transfer direction change connections and logic;

Figure 15K is a simplified example illustration of a connection between two TLs;

Figure 15L shows a modified block diagram of Figure 15I, in which 4 units are aggregated to communicate with the RF-I fabric;

Figure 15M shows an example of an oversized reticle and the use of different field sizes for TL and (processor) circuitry;

15N is an illustration of an on-chip interconnect that can extend greater than 10 mm and multiple chips that can be grouped (eg, 4 chips);

Figure 15O is the paper "A28-mW 32-Gb/s/pin 16-QAM Single-Ended Transceiver for High-speed Storage Interface" by Du Jieqiong et al. -SpeedMemory Interface)", Figure 1 of 2020 IEEE VLSI Circuit Symposium, IEEE, 2020;

15P shows a cross-sectional view of the multi-layer TL, showing two levels of the X-direction TL and multiple levels of the Y-direction TL;

Figure 15Q shows the wafer-level engine proposed by I. Cutress "Hot Chips 31 Live Blogs: Cerebras' 1.2 Trillion Transistor Deep Learning Processor" For example, in order to save wasted area, you can consider using a non-rectangular 3D system;

Figure 15R not only shows the entire circular wafer, but half or quarter of the wafer can be used without losing any die near the edge;

Figure 15S is an illustration showing that the TL hierarchy can be placed below and/or above the processor and memory hierarchy;

Figure 15T is an example illustration showing various areas of the current panel; however, the smallest panel size is still larger than the size of the 300mm wafer;

Figure 15U is an example illustration of long-haul TL using NoC-type topology, i.e., 3D toms;

Figure 15V is an example illustration of long-distance TL using a NoC-type topology, i.e., butterfly-shaped;

Figure 15W is an example illustration of congestion-aware routing;

Figures 16A-16E are examples of various cooling technologies and structures built into 3D systems; for example, the SubstrateM-Level in a 3D system can include multiple computing levels and memory levels, with the X-Y connection level in between, and the system Heat can be managed through liquid cooling;

Figure 16F is an example illustration showing a wireless connection of a 3D system to an external device, which may be attractive because it can share the NOC and resources connected to the external device;

Figure 16G is an example illustration of a 3D system with additional coolant distribution structures;

Figure 16H is an additional example illustration of a 3D system with additional coolant distribution structures;

Figures 17A-17D are illustrative examples of multiple steps of simple bonding and thinning to form full M levels, and then using the TSV process to form vertical busbar pillars through level stacking, and then to form pins/pads;

18A-18F are exemplary illustrations of process steps that may be used to form a Schottky Barrier S/D junction to form a uniform suicide layer;

Figure 18G is an example illustration of bending and twisting changes at the top and bottom of a stacked 3D NAND structure;

19A-19E are illustrative illustrations of methods and structures for implementing a 3D NOR-P wafer with a stack of correctly connected multiple 3D NOR-P blocks;

19F-19H are illustrative illustrations of methods and structures for realizing 3D NOR-P wafers with metal-induced recrystallized silicon channels;

Figures 20A and 20B are illustrative illustrations of some advantages of metal bit lines in 3D NOR-P structures and devices;

Figure 20C is an exemplary illustration of a 2x2 array 3DNOR-P structure shared by various types of unselected cells for various WL/BL/SL combinations;

Figure 20D is an exemplary illustration of write voltages for the type of memory cell shown in Figure 20C, and is illustrated in four cases on a single cell;

Figure 20E is an example illustration of a 2x2 FG memory array connected to a sense amplifier in different ways;

Figure 20F is an exemplary illustration of voltage development of BL of S/A as a function of read time;

20G is an exemplary illustration of exemplary voltage conditions and associated energy band diagrams for read operations of the exemplary cells of FIG. 20C and read-inhibition of unselected cells;

20H is an exemplary illustration of bit line current and word line voltage characteristics for different storage states and read conditions of the exemplary cell of FIG. 20C;

Figure 21A is an exemplary illustration of a wafer-scale engine from Cerebras Systems;

21B is an exemplary illustration of a wafer-level 3D system that may include I/O pads along the circumference of the wafer edge; and

Figures 21C-21G are exemplary illustrations of wafer-level 3D system fixtures that can "expose" the system and provide better heat dissipation;

21H-21I are illustrative illustrations of various configurations of liquid cooling baths for wafer-scale 3D systems;

Figure 21J is an illustrative illustration of a fixture for a bare wafer-level 3D system including an Ethernet port and a power port;

Figure 21K is an exemplary illustration of a wafer-scale 3D system designed to be cut in half; and

Figure 21L is an exemplary illustration of the wafer-level 3D system of Figure 21K arranged by a printed circuit board.

Detailed ways

An embodiment of the present invention will now be described with reference to the accompanying drawings. It will be understood by those of ordinary skill in the art that the description and drawings illustrate rather than limit the invention, and that the drawings are generally not drawn to scale for clarity of presentation. Such skilled artisans will further appreciate that many more embodiments are possible by applying the inventive principles contained herein and that such embodiments are within the scope of the invention, which is not limited except by any additional claims. .

Some diagrams may depict the process flow of building components. A process flow may be a series of steps used to build a device, which may have many structures, numbers, and labels that may be common between two or more adjacent steps. In this case, some of the labels, numbers, and structures used in the diagram for a certain step may already be described in the diagram of the previous step.

The use of layer shifting in building 3D IC-based systems enables heterogeneous integration, where each layer can include MEMS sensors, image sensors, CMOS SoCs, volatile memories such as DRAM and SRAM, persistent memories, and non-volatile memories. One or more of the volatile memories (such as flash memory and OTP). This can include adding memory control circuitry, also known as peripheral circuitry, on top or below the memory array. The memory layer may contain only memory cells and no control logic, so the control logic may be included on a separate layer. Alternatively, the memory layer may contain memory cells and simple control logic, wherein the control logic on the layer may include at least one of a decoder, a buffer memory, and a sense amplifier. The circuits may include charge pumps and high voltage transistors, which may be fabricated on a layer using silicon transistors or other transistor types (eg, SiGe, Ge, CNT, etc.) using fabrication process lines that are different from the low voltage control circuit fabrication process lines. Analog circuits, such as those used in sense amplifiers and other sensitive linear circuits, can also be processed independently and transferred to 3D structures. Such 3D construction could include the "intelligent alignment" technology proposed in this invention, or exploit the repetitive nature of the memory array to reduce the impact of wafer bonder misalignment on integration effectiveness.

For example, in US Patent Application No. 15/173,395 and other patents, a layer transfer technology called epitaxial layer transfer (EL TRAN) is proposed, which may be part of the 3DIC formation process. ELTRAN technology utilizes one or more epitaxial processes on a porous layer. Alternatively, by taking advantage of the etch selectivity of these epitaxial layers, such as the very high etch selectivity of SiGe to silicon and other technologies such as silicon (monocrystalline or polycrystalline or amorphous), SiGe (mixture of silicon and germanium), P-doped silicon, Variations such as N-doped silicon, other epitaxy-based structures can be formed to support layer transfer techniques, and these layers can be joined with various types of separation processes such as "cold cracking", such as Silectra stress polymers and cryogenic shock treatments, To provide thin layer transfer process.

Recently, it has become a very attractive concept for processing omni-directional horizontal transistors with gates and has become a target flow for next-generation devices such as 5nm technology nodes. Jang Gn Yun et al. published an article in IEEE Transactions on Electronic Devices, Volume 58, Issue 4, April 2011 titled "Single-Crystalline Si Stacked Array (STAR) NAND Flash (Single-Crystalline Si Stacked Array) STAR) NAND Flash Memory)" paper introduces some work on selective etching of SiGe and silicon, and K.Wostyn et al. published in ECS Transactions, 69 (8) 147-152 (2015) titled "Using "Selective Etch of Si and SiGe for Gate All-Around Device Architecture" article, published by V.Destefanis et al. in EC Transactions, 16(10)427- 438 (2008) article titled "HC1 Selective Etching of Sil-xGex versus Si for Silicon On Nothing and Multi Gate Devices" Recent work is presented, and all of the above are incorporated by reference into this article. As the SiGe process on silicon substrates is maturing, this facilitates the use of SiGe layers as sacrificial layers for production-worthy 3D layer transfer.

In at least U.S. Patent 8,669,778, which is incorporated herein by reference, with respect to at least Figure 22, a technology is proposed with a general-purpose memory array customized for a specific application, such as SRAM, DRAM, FRAM, RRAM, or MRAM , and integrate it as part of the 3D device flow. At least in US Patent 9,021,414, which is incorporated herein by reference, processes and techniques for using electronic design automation ("EDA") tools for such 3D structures are proposed. At least in U.S. Patent Application No. 16/558,304, which is incorporated herein by reference, with respect to Figures 21A-25J, techniques are proposed to integrate general-purpose memory arrays with logic utilizing hybrid bonding as part of a 3D device flow. This article introduces further variations of these concepts. 3D devices may include custom designed logic levels to integrate memory levels using 3D integration such as hybrid bonding. The memory hierarchy can be fully customized to match the underlying custom logic, or by using a generic memory hierarchy that has been customized with several added steps to match the underlying custom logic, as shown herein. The memory hierarchy may be formed as an array of cells, where the cells are arrays of bit cells. The underlying custom logic can include memory control circuits such as decoders and sense amplifiers.

Several considerations are considered important drivers in the following memory stacking alternatives. First, the goal is to maintain or minimize the overall investment in custom devices using memory stacks. Thus, memory arrays can be designed as generic structures that can be customized with few customization steps, such as one or two metal layers and their associated via layers. Second, general-purpose memory structures use conventional and simple copper interconnects that are typically defined by chemical mechanical polishing (CMP) rather than etching. In other words, a universal memory structure can be provided by a dedicated supplier such as a semiconductor foundry, and the universal memory structure can be purchased and customized by many customers and reduce mask costs and other non-recurring costs ("NRE") according to their needs.

Therefore, a general memory structure can be designed as a cell array. Each cell may be a small two-dimensional array of bit cells in the plane of the wafer. Later, if a product or customer requires a higher bit cell density than that of a 2D single chip, multiple universal memory dies can be stacked to form a 3D stacked universal memory structure. When stacking general-purpose memory wafers of the same design and processing, the memory cells are repeated in the vertical direction, or along the outer plane of the wafer. Typically, the number of rows in a cell may range from 32 to 1028, and the number of columns in the cell may range from 32 to 1028. To provide customers with flexibility and versatility with minimal cost, power and performance reductions, relatively smaller unit sizes such as 32x 32 or 64x 64 may be favored instead of 512x 512. In this article, the minimum size of the cell will be referred to as the "original cell". If a 3D-stacked universal memory wafer should be considered a universal memory wafer, adjacent primitive cells can have some extra space for through silicon vias or layer vias. Customization in memory cell size can be provided by adding several custom process steps on a general-purpose memory wafer prior to the wafer stacking step. The customization step can be an additional metallization step processed on a general-purpose memory wafer that bridges and stitches several cells into a memory structure of the desired size. Multiple basic units spliced together to form a target size will be called "splice units". For example, four units of a 32x 32 base unit can be connected to form a 64x 64 patchwork unit. In addition to the stitching process, a pin pad formation step can also be included as part of these additional metal customization process steps. The custom memory wafer can then be flipped and bonded to the logic substrate using, for example, hybrid bonding, and connections to predefined pads are made at the logic substrate connecting the memory to the logic.

The smallest memory structures can be designed taking into account the accuracy of the bit cell size and hybrid bonding that defines the minimum pitch and size of the pads. The cells can be designed according to this minimal memory structure, or even smaller, allowing for more flexible placement and grid granularity.

Consider a bit cell of width W and length L with a total area W*L. Assuming a hybrid bonding process, the minimum pitch H represents the area H*H of a connection, where a connection area includes the actual pad and the space used for bonding. Assume the memory is a 6T SRAM with one word line per cell width and two bit lines per bit cell length. Assume that the minimum array is m cells wide and n cells long. Therefore, the following formula represents the requirements for this structure: m*W*2n*L>=m*H*H+n*H*H

As can be seen, the number of pads, and the corresponding area required for the pads, grows according to m+n, while the cell array area grows by m*n. Therefore, the minimum array size can be defined for a specific case of bit cells and a hybrid bonding process, given a specific number and aspect ratio selection.

For example, recent reports on hybrid bonding such as "1pm pitch direct hybrid bonding with <300nm Wafer-to-Wafer overlay accuracy" by Jouve, A. et al. 2017 IEEE SOI-3D Subthreshold Microelectronics Technology Unification Conference (S3S), IEEE, 2017; and Global Foundries published on August 7, 2019 titled "GLOBALFOUNDRIES and Arm Demonstrate High-Density 3D Stacking for High-Performance Computing Applications" The "Test Chip" article shows a hybrid bonding of 1 micron pitch (H = 1 micron). "Novel Cu/SiCN surface topography control for 1pm pitch hybrid wafer-to-waferbonding" by Kim, Soon Wook et al., 2020, IEEE No. 70 Similar results and bonding techniques were also presented at the 2020 Electronic Components and Technology Conference (ECTC), IEEE, 2020, which is incorporated by reference in its entirety.

An example of a 7nm 6T SRAM bit cell layout is shown in Figure 1: W = 108nm and L = 250nm. Based on the above formula and the approximately square memory structure, the smallest memory structure that can be used for hybrid bonding can have:

m～100 and n～85.

Figure 2 shows an exemplary memory structure with primitive cells 202. For such an example, the primitive cells may be configured as a minimum array with ~100*85 bit cells. These cells may be placed with bit-cell sized spaces 204 between them, forming a two-dimensional repeating pattern 200 of a general-purpose memory.

FIG. 3A shows four cells 202 of the cell array, as shown in FIG. 2 . The four units are arranged in a 2x2 configuration example.

Figure 3B shows four general-purpose cells 202 that connect word lines and bit lines by forming "bridges" 304 (or strap connections) between them, thereby controlling a 2x2 memory structure, which is customized for use as a memory structure. Bridges connect the word lines and bit lines of adjacent cells. The bridge may be copper, tungsten, or other conductive metal or material that conducts electricity as well as or better than copper.

Figure 3C shows an example of further customization achieved by adding pads or pins 306 in preparation for the subsequent hybrid bonding step. The pads or pins can be copper, aluminum or other metals. The pad or pin 306 layer can be processed in the same step as the bridge layer. Alternatively, the pad or pin 306 layer may be formed at a higher level than the bridging layer, so that when the pad and pin 306 layer is exposed, the bridging layer is internal to the dielectric layer.

Figure 3D illustrates an extension of the structure, showing an additional 2x2 memory structure (two 2x2 memory structures in total) and the space 308 between them without bridging. In the example, each 2x2 memory structure has four general-purpose cells 202.

Figure 4A shows a cross-sectional view of the area marked by oval 322 in Figure 3A. Figure 4A shows a gap 450 in memory control line 402. Memory control lines 402 may be bit lines or word lines, or in some cases another type of memory control line. Memory control lines 402 extend beyond the outer boundaries of the bit cell array.

Figure 4B shows a cross-sectional view of the area marked by oval 302 in Figure 3C. 4B shows bridge 404 with vias 409 connecting gaps 450 and connecting control lines 402 of one cell 202 with another control line 402 from another cell 202 . Pads/pins 406 and 408 illustrate potential conductive hybrid joints. An example via 407 [eg, a through silicon via (TSV) or a through layer via (TLV)] may connect the pad/pin 406 to an underlying control line within the example cell 202 . Likewise, the conductive connection from pad/pin 408 through hole 407 to another control line 410 from the edge is further shown in Figure 4D.

Figure 4C shows a cross-sectional view in the area marked by ellipse 312 in Figure 3D. The figure shows via 412 connecting control line 404 from the edge of the cell to pad/pin 406 with wire 414 and vias 407 and 412 for future bonding. Figures 4A, 4B, and 4C illustrate a portion of the edge of the universal unit 202, which is exemplary in nature. Engineering design choices can create many variations of the connectivity concepts presented in this article to optimize speed, power, and cost for the envisioned system/device. For example, the pads/pins, vias, control segments, etc. shown in Figures 4A-4C do not need to be symmetrical with respect to gap 450. Each part of unit 202 may have completely different connections. Likewise, connections between cells 202 may be programmable, for example, by laser blowing or blowing fuses, or may be electrically programmed to be conductive via antifuses, or non-conductive via fuses.

Figures 5A-5C show examples of memory cells with a 3D pin/pad connection structure using two metal layers and one pin/pad layer.

Figure 5A shows the pin/pad layer on top of the gate, showing the underlying bit line 502 with pitch 510 ("BLP") and the word line 504 with pitch 509 ("WLP"). The hybrid bond pin/pad spacing is 501 in the WE direction and 503 in the NS direction, which is approximately 4 times that of BLP and WLP. The basic concept is to redistribute control lines that may have close spacing requirements into a two-dimensional array of metal pads at larger intervals to accommodate mixed bonding capabilities. In this example, the bit line is the memory top metal in the WE base 500 direction and the word line in the NS base 500 direction. In the example described, the memory cell size is about 2x BLP*WLP - two grid squares if the complementary cell requires both BL and BL/e.g. SRAM, or if the cell only has one BL (e.g. DRAM, MRAM, PRAM or RRAM), it is approximately BLP*WLAN - a grid square. For simplicity, assume that one grid squared is one grid squared for subsequent explanations. The bond alignment indicates approximately two BLPs by two WLPs or 2x2 grid squares 505, 507 of pads/pins, which indicates the total area of one pad/pin of a 4x4 grid square. In other words, one pad/pin occupies a 16-bit cell area; space is required for the pin/pad's 4-bit cell area and 12-bit cell area. In this example, each memory cell has a word line and a bit line, such as those found in DRAM bit cells. The calculation of the minimum cell size can be applied accordingly to other types of memory cells, as shown below. In this example, the unit aspect ratio is approximately one square unit. For the following calculations, BLP is approximately the same as WLP or P. Therefore, the area of one pin/pad is 4x4xP ² =16P ² , and the number of word lines can be equal to the number of bit lines, or for a square cell structure, m, which is more than the formula suggests:

16P ² *(m+m)<=mP*mP, or 32<=m.

Thus, the example of Figure 5A illustrates a minimum cell of 32 bit lines by 32 word lines.

Figure 5A shows 32 pins/pads 507 for bitline connections, with the first 16 bitline address numbers 508, and 32pins/pads 505 for wordline connections. It also shows with dashed line 506 the allocation of the top surface to four areas, two for pins/pads for wordline connections and two for bitline connections. The specific pin/pad arrangements of Figures 5A-5C are exemplary, and specific arrangements may be designed based on engineering trade-offs, such as lithography and bonding alignment accuracy and accuracy, critical speed nets, memory cell size and aspect ratio, etc.

Figure 5B shows the metal connections of the bit lines. There is a connection between each bit line and a corresponding pin/pad. Connections are divided into two groups. The even-numbered 526-bit lines are connected from the south-using side via 516, while the odd-numbered ones are connected from the north-using side. This takes full advantage of the availability of each bit line on both sides of the cell. The connection layout is just an example. Qualified layouts can be designed by layout technicians in the field taking into account the design rules of the specific process. This layout may include extending the cell size to accommodate the layout constraints of this particular case. In Figure 5B, the top metal is assigned to pads/pins 522, 524. Connection is made to the underlying metal layer 514 with via 520, oriented W-E, and via 518 is connected to the underlying metal layer 512, oriented S-N in Figure 5B.

The connection layout of the bit lines (not shown) can be done in a similar manner in the area left for it, or take advantage of the availability of the bit line orientation W-E at the top of the memory array, using direct vias instead of west, east access vias hole.

Figure 5C shows the top three connection layers of Figure 5B without the grid to better see the wordline pin/pad connection layout. The drawing symbol legends are the same between Figures 5B and 5C.

Although not shown, many memory bit cells require power and ground wires, such as SRAM. It should be understood that the pads for power and ground are allocated at the top of the bridge area 304 of the figure. Power and ground lines are typically biased at quiescent voltages, and instead of rows or columns being controlled individually, power and ground lines from multiple rows or columns are grouped together so only a few pads are needed.

The top surface of the logic die will have a reversible pad/pin layout from the memory die or chip. The pad layout of the logic die and the memory die will be mirrored so that they can later be properly F2F bonded and electrically connected. The pads/pins of the logic die will be connected to the sense amplifier for the bit lines and the multiplexer for the word line pads.

Another option is to have a slightly larger cell size to allow regular pins/pads on the cell connections. This allows one metal layer to be used for routing and another for the pin/pad layer. To illustrate this alternative, the cell structure of Figure 5A and a better hybrid joint spacing ("H") are shown in Figure 5D. Bond pad pitch 541, 543 including pad/pin 547 is, for example, three times the word line pitch WLP 549 and bit line pitch BLP 550 of the memory array. The hybrid joint connection structure is similar to the structure cited in PCT/US2017/052359, incorporated herein by reference, as shown in Figures 21A-21C, folded over the storage unit as shown in Figure 5D. The ratio H/BLP between the hybrid bond pitch H and the bit line pitch BLP can derive the number of columns of bond pads/pins for the bit line (rounded), as shown in Figure 5D. Similarly, the ratio H/WLP between the hybrid bond pitch H and the word line pitch WLP can drive the number of rows of bond pads/pins for word lines (rounded), as shown in Figure 5D. As a result, the number of rows and columns of WL and the number of rows and columns of BL are determined respectively. Thus, the top surface of the unit may be labeled into four similarly sized quadrants by dashed N-S lines 545 and W-E dashed lines 546. The N-E quadrant 542 can be used to bond the pads/pins of one half of the bit line 554, while the W-S can be used to bond the pads/pins of the other half of the bit line 552, and in a similar manner for word line 552, the W-N quadrant is used for the first half and the S-E quadrant is used for the other half.

To evaluate the smaller cell size for this pin/pad connection, the following factors can be considered. Dashed line 556 represents the south oriented edge of the NE quadrant structure, while dashed line 557 represents the north edge of the SE quadrant connection structure. The distance between these structures 558 is needed to avoid these structures becoming too close. The length of the NE quadrant structure (in the NS direction) is approximately ~N/2*BLP+H. Here, N is the number of bit lines in the unit. The width of the SE quadrant structure (in the NS direction) is approximately ~H/WLP (rounded up)*H. For simplicity, it is assumed that the word line pitch is approximately equal to the bit line pitch, and can be expressed as P. The unit size in the NS direction is approximately N*P. Therefore, the formula expressing the condition with respect to 558 is: H/P*H+H+n/2*P<n*P, which can be written as: n>2H ² /P ² +2H/P. For example, assume H=1 micron, P=0.1 micron, and n>220. Therefore, a memory array constructed as a cell array with dimensions of 200μ*200μ and a control line spacing of 0.1μ will have enough cell area on top to form a pin/pad connection structure as shown in Figure 5D, where 5D has n～2000>>220. FIG. 5E is a schematic diagram of FIG. 5D with the grid and other markings removed and markings added for the boundaries of the underlying memory cells 560 .

Figure 6 illustrates the extension of the described concept to a multi-level memory structure. This approach can be used in situations where memory requirements are very high and a single level of memory will not provide sufficient memory. Figure 6 is similar to Figure 22F of US application 16/558,304, which is incorporated herein by reference. The vertical pillars of the Global Line of Control, such as 2246 and 2258 in Figure 22F (16/558,304), are replaced by two sets of vertical pillars 645, 646 replaced by 2246, 655, 656 replaced by 2258, and so on. And the bridging concept of Figure 4B or the pad/pin extension for bonding of Figure 4C can be used for customization of multi-level memory structures. Each level selection 647, 657 can be connected to control logic to enable complete control of the specific level selected.

Figure 7A is a copy of Figure 43E of US Application No. 16/558,304, which is incorporated herein by reference. 7A illustrates a multi-level device that may include logic levels as described herein, custom memory levels to support logic levels such as Cache 1, Cache 2, or last level cache-type memory, Additional memory levels and memory control levels including decoding and sense amplifier circuits, which may be in the form of multi-level stacks of high-speed memories such as DRAM, memory structures such as 3D NOR and memory structures such as 3D NAND. Additionally, layers of global X-Y interconnects can utilize electromagnetic waves on transmission lines or have waveguides with supporting RF or optical circuits. Various tiers may include feedthrough connections to allow vertical connections across tiers. Heterogeneous integration can be achieved using layer transfer in the construction of such 3D IC based systems, where each layer/layer/level can include, for example, MEMS sensors, image sensors, CMOS SoCs, volatile memories such as DRAM and SRAM, One or more of persistent memory, ferroelectric memory, and non-volatile storage such as flash memory and OTP. This can include adding memory control circuitry, also known as peripheral circuitry, on top or below the memory array. The memory layer may contain only memory cells and no control logic, so the control logic may be included on a separate layer. Alternatively, the memory layer may contain memory cells and simple control logic, wherein the control logic on the layer may include at least one of a decoder, a buffer memory, and a sense amplifier. Peripheral/control circuitry may include charge pumps and high-voltage transistors, which may be fabricated on a layer-by-layer basis using silicon transistors or other transistor types (e.g., SiGe, Ge, CNT, etc.), using fabrication process lines that may be, and often are, different from the low-voltage control circuitry fabrication processes Wire. Analog circuits (such as those used in sense amplifiers) and other sensitive linear circuits can also be processed independently and layer-transferred onto 3D structures. Such 3D construction could include references to "smart alignment" techniques or bonding proposed in this disclosure, or exploit the repetitive nature of memory arrays to reduce the impact of wafer bonder misalignment on integration effectiveness. As described in PCT/US2017/052359 (WO2018/071143), the entire contents of which are incorporated herein by reference. Specifically, it is discussed with respect to FIGS. 11A to 12J , or a hybrid bonding technique is used as shown in FIGS. 20A to 25J . Hybrid bonding between levels reduces the process steps required for this 3D integration but provides less flexibility to overcome misalignment challenges. "Smart alignment" technology can overcome this alignment challenge, but it requires etching and deposition steps to achieve this level, adding steps to the stacking process. Vertical connection challenges can be very different between different levels of a 3D stacked structure. Stacked memory levels without intra-level decoders may require vertical connections for word lines, bit line spacing, etc. at the decoder level, which are relatively more demanding than the connections at other levels in the stack. Therefore, the stacking process can be different to accommodate the alignment requirements between these levels. Furthermore, if the wafers come from the same process line, the sources of alignment errors may be different, such that the errors are sometimes smaller, such as may be expected for a memory hierarchy (eg, minimum step matching). These selections and 3D engineering designs may use various 3D integration techniques incorporated herein by reference to those skilled in the art.

Memory layers can include a variety of types and memory technologies and can be placed at different levels of the 3D device structure, as shown in Figure 7A. It can include high-speed memory closer to the computing logic and high-density memory closer to the XY interconnect structure. The high-density tier could be in the form of what is known in the industry as 3D NAND, V-NAND, X-point memory or Optane, while the high-speed memory could be similar to the so-called 3D NOR-P proposed in PCT/US2018/016759 and 62/952,222 , both of which are incorporated herein by reference. The memory layer may be a cell array structure. Figure 7B shows that such a unit may have dimensions of about 0.04mm2, about ^0.1mm2 , about ^0.4mm2 , about ^0.1mm2 , about ^0.4mm2 . Or even larger than about 1mm2. It can be a structured array of cells like 2x2, 4x4, 8x8, 32x32, 256x256, 1024x1024 or any combination of these numbers like 16x64. The memory hierarchy may include memory control circuits 710, 714 (also referred to as memory peripheral circuits) and approximately 100 feedthroughs 718 per cell to support vertical connectivity throughout the 3D structure 700. The control circuitry may be configured so that each memory cell has its own control at the top 710 and/or below 714 of the memory array 712 . Connections between the memory controller and the memory array may utilize hybrid bonding and pad/pin structures, as shown herein with reference to Figures 5A-5C, or other structures, as shown in the prior art incorporated by reference, such as PCT/US2017/052359, incorporated herein by reference, is shown in Figures 21A-21C. Connections from control circuitry 714 to other device levels such as computing logic 716 may be relatively easier since dozens or hundreds of connections may be required for an area of a cell because the memory control circuitry includes address sections within the vertical bus address decoder. Therefore, within a cell, the connection requirements from the memory control circuitry to the memory array (2D or 3D) can include thousands of connections to bit lines and word lines - in the case of 3D memory, about a hundred connections for feeding Feed-through, dozens to hundreds of connections are used for layer selection. A few hundred extra connections could be added on the top of the cell or its sides as even for pads/pins with 1 micron spacing on the side length of a 200 micron or larger cell it would only add 1% to the structure of overhead area. The memory layer can be a standard module integrated with other structures to form a custom or semi-custom product. The structure size may be a full wafer or any smaller structure, such as a single field even smaller than 100 ^mm2 size, as described in PCT/US2018/523 32, incorporated herein by reference. The memory controller may include built-in tests and redundancy activation that operate during device setup and operation. Activation and reporting of these built-in tests and redundancies are available as part of these hundreds of connections and pass-through connectivity capabilities.

The bus bars of such a unit may be different for different units throughout the structure, and the size of the units in the structure may also be different. The bus can be 1, 2, 4, 8, 16, 32 or 64 bits as is common in the industry, but can also be extremely wide buses of hundreds or even thousands of bits to support processor designs with extremely wide data buses, or Features additional on-chip buffers to increase data speed from memory to the processor level.

FIG. 7C shows tiling the cell structure of FIG. 7B to form an array of cells 740. This tiling can span the entire wafer or any part of it. Figures 7A-7C are side views along the X-Z 702 direction. Figure 7D is a plan view of a wafer-scale array of cells 704 along the X-Y 703 direction.

The process flow to form a full 3D heterogeneous integration, as shown in Figure 7A, may include several steps of wafer bonding and substrate removal, such as "dicing" using dicing layers or thinning using grinding and etching, which may Including using the cut layer as an etch stop layer. The formation of this 3D structure can include mixing and matching joints of different layers, such as regular layers, semi-custom layers and fully custom layers. The memory layer may include the steps of forming a 3D NOR memory array and then bonding a memory control level thereon. Figures 7E-7G illustrate this process flow using the small cross-section X-Z 702 cross-section.

Figure 7E shows a small portion of the memory control circuit 739 (peripheral circuit). The sections correspond to the edges of the two units. It illustrates the four top bonding pins/pads 736738 to be bonded into the memory pins/pads as shown in Figure 5E. It shows the feedthrough structure 735 and the two bottom pins/pads 737 designated to be connected to the logic level. The substrate may include base silicon 742 and dicing/etch stop layer 740. Bottom bond pads can be placed in areas between cells that are cleared of active circuitry. The bottom 737 pin/pad may be part of the first metal or contact layer. Alternatively, taking advantage of the etch selectivity of the dicing layer 740, it can even be formed under the dicing layer 740 (not shown) to simplify the subsequent steps of exposing it to prepare it as a pin/pad. Other options do exist, including allocating more area to these pins/pads and using a technology called TSV. The structure includes a top oxide 733 for protection and will be part of future hybrid bonding.

Figure 7F shows flipping and engaging memory control circuit 744 (from Figure 7E) on top of memory layer 743. Memory layer 743 may be an array 752 of 3D NOR-P or any other memory option previously discussed. Memory layer 743 may be formed on substrate 756 with its own dicing layer (which may also be referred to as an etch stop layer) 752. Feedthroughs 755 may be placed between storage cells. Memory pin/pad 735736738 in Figure 7E may be connected to control stage pin/pad 750 using hybrid bonding.

7G illustrates the structure after thinning the memory control circuit 744 to form the memory control 745 by techniques such as grinding and etch back using an etch stop layer or any other cutting technique previously proposed herein or in the cited literature. The pins/pads 758, 760 are exposed or formed by opening top vias and forming metal top pins/pads using conventional semiconductor processes. The process steps required to form these pins/pads 758, 760 are part of the overall flow design. In the case where wafer processing as shown in Figure 7E includes forming metal connections to contact level 733, this may be a relatively simple process, or it may involve more steps to form metal connections down through the backside of the wafer. vias, all the way down to the appropriate metal levels for the appropriate signal lines. Figure 7G shows a small portion of a complete memory layer with the memory array and its controls ready to be bonded on top of the logic die to form the type of structure shown in Figure 7A. It is contemplated that the number of connections from the memory control layer to the memory array 750 may be in the thousands per unit to provide control of word lines, bit lines, and other memory control lines. As mentioned previously, the number of feedthroughs 755,758 per unit can be in the tens, as can the number of connections 760 to the processor logic level.

The memory controller may be integrated using bonding technology or other technologies, such as those common to 3D NAND with Peripheral Units Under ("PUC").

The memory layer may be configured to function as a dual-port memory, for example one memory controller 714 may be controlled by the underlying processing logic, while an upper controller 710 may be controlled by upper layer processing circuitry, which may operate to move data into or out of the fabric ( "I/O") part of the circuit.

The memory layer can be configured to function as content addressable memory (CAM).

The stack-up may utilize pin/pad connections as shown in Figures 5A-5E, or other technologies such as smart alignment and electronic alignment incorporated through reference technology, or any mix and match of these technologies.

FIG. 8 illustrates an exemplary overall process flow for designing logic wafer 802 and processing logic wafer 804 . Design customization of memory die 822. There may be a full set of general-purpose wafers, offering multiple process nodes and other memory options, such as high density and high speed, for designers to choose from. The selected universal memory die can then be customized 824 for a specific design and then flipped and bonded to the logic die using, for example, hybrid bonding 828 .

Logic die and general die structures may also include power line connections using hybrid bonding. These power connections can be made at the cell level memory fabric level and/or at the chip level. The figures do not show these power connections. Final processing in the steps may include back grinding, dicing and packaging.

General-purpose memory can be customized to support more than one level of memory using join-by-reference techniques.

EDA tools for such 3D logic memory designs may incorporate at least the techniques set forth in U.S. Patent 9,021,414, incorporated herein by reference. For the flow shown in Figure 8, the EDA tool can include a grid for memory decoder placement to support this universal cell-based memory structure.

There are many options for forming a 3D system using the techniques incorporated in this article or through reference techniques. These techniques can include adding pins/pads on the memory cells as shown in Figures 5A-5D. This may include stacking several memory levels, one on top of another, forming a 3D memory layer formed by stacking memory levels which may be 2D levels or 3D levels which may be multi-layer memory, for example, such as 3D NAND or 3D NOR. wait. Such 3D structures may include sharing common global memory control lines or hierarchy select signals between hierarchies and independent layers. Such memory 3D structures may be controlled by one or several memory control layers that control each of the memory tiers using a common memory control pillar and individual tier selections. This three-dimensional layer formation process is shown in Figures 9A-9F.

Figure 9A shows an X-Z 902 cross-sectional view of a cell domain similar to the memory control layer in Figure 7E. The structure includes a substrate 912 having an etch stop layer 910 and memory control circuitry 909 . The memory control circuit 909 structure may include "bottom" connections 904, 907 between cells for future connections to the processor logic hierarchy, and feedthroughs 905. It also includes pins/pads 906, 908 on the control circuit for the "global pillars" of the memory control lines. The global memory control connection does not look like a pillar because it remains folded over the top of the cell surface to accommodate the relatively low pitch associated with hybrid bonding.

9B shows an X-Z 902 cross-sectional view of a cell domain of a 3D memory 922 built on a substrate 926 with an etch stop "cut layer" 924. Likewise, the structure includes cell feedthrough 925 and above cell bonding pins/pads 920 .

9C shows the structure after transferring memory structure 913 over the memory control structure of FIG. 9A and removing substrate 926, such as controlled etch stop by grinding and wet and/or dry etching using etch stop layer 924.

Figure 9D shows the structure after adding pins/pads 928 on the 3D memory 922 cell using the layout shown in Figures 5A-5E.

Figure 9E shows an X-Z 902 cross-sectional view of additional cell domains of memory 914 built on a substrate with an etch stop "cut layer" between the cell's feedthrough and the cell's bonding pins/pads.

Figure 9F shows the structure after transferring the 3D memory structure 914 on the structure of Figure 9D, using hybrid bonds to connect various memory control lines (such as word lines, bit lines, etc.), and connecting feedthroughs. Thus, memory control circuitry 909 may be used to control overlapping memory cells of first layer 922 and overlapping memory layer 914 . The memory layers can be designed to have the same memory cell size and the same number of memory control lines, and utilize standard pin/pad layouts to achieve this system-level integration using hybrid bonding. These memory layers can be 2D memory arrays or 3D memory arrays. This may be a very similar memory technology, or in other cases a different memory technology. Memory controls can be 2D structures or 3D structures. A variety of mix-and-match styles can be constructed. As discussed previously, using global bitlines in 3D structures requires controlling layer selection. Such hierarchical control needs to be properly connected in the memory control circuit 909. There are few options for doing this, for example:

A. Select a separate layer that is directly connected to the memory control circuitry. In this case, the internal level selection can be connected to the global level selection of the memory circuit.

B. Each memory tier can have dedicated connections for its tier selection. It is expected that the number of layer selections can be less than 100, so allocating an area of pins/pads to each of them would be a reasonable area overhead.

C. In cases where the goal is to stack the same type of memory layer multiple times, a good option is to use the technique proposed in Figures 22A-22B of PCT/US2017/052359, which is incorporated herein by reference.

Figure 9G shows the structure after removing the top substrate 913, adding pins/pads, and repeating the process by adding more memory layers 934, 932, 930. Thus, the structure may include a carrier substrate 942, a memory control layer 940, a first 3D memory layer 938, and a stack of four memory layers 930, 932, 934, 936. The structure of Figure 9G can be used as a memory building block, integrated with the computing logic layer to form a 3D computing structure.

One of the challenges of 3D systems with multiple layers of active devices is power transfer. The concept of heterogeneous integration can be extended to include substrate designs that support power transfer. Figure 10A is a vertical cross-sectional view 1002 showing a substrate similar to that shown in Figure 7A with the addition of global power delivery structures. This may include deep trench capacitors 1016 and power distribution network ("PDN") 1014. Deep trench capacitors can be formed inside silicon wafers. In this case, the silicon substrate 1001 will be heavily doped to form the bottom electrode of the trench capacitor, as shown in Figure 10A. Alternatively, deep trench capacitors can be formed within the oxide. In this case, the bottom electrode may be a metal pad (not drawn). The structure of the capacitor can be one of planar, crown, cylindrical or cylindrical. In a cylindrical shape, the top plate electrode may be heavily doped (eg phosphorus or boron doped) polysilicon or silicon germanium. One side of capacitor electrode 1014A will be connected to the ground/power line, while the other side of capacitor electrode 1012B will be connected to the power/ground line. This can be formed using one thick metal layer or multiple metal layers. Integrating trench capacitors in PDN may be an effective way to reduce local voltage changes caused by circuit operation. Figure 10B shows the structure after adding the various levels of logic, memory, EM interconnect level and IO level 1022 shown in Figure 7A. This may include hybrid engagement and multi-level horizontal transfers.

Another embodiment of the invention is the integration of inductors for use in power delivery networks. This may include MEMS or CMOS-BEOL based inductors 1017 which may be air, oxide, iron or ferrite. When using a ferrite core, the core material can be manganese-zinc, nickel-zinc, iron-silicon or iron-silicon-aluminum. The structure of the inductor can be a spiral thin film. As shown in Figure 10C, one side of the inductor electrode 1014A will be connected to the ground/power line and the other side of the inductor electrode 1014B will be connected to the power/ground line. The core material of the inductor 1017, Figure 10D shows the structure after adding the various logic, memory, EM interconnect levels and IO levels 1022 shown in Figure 7A. This may include hybrid engagement and multi-level horizontal transfers.

Another embodiment of the present invention is to simultaneously integrate the capacitor shown in FIG. 10A and the inductor shown in FIG. 10C for use in a power transmission network.

Power distribution is the basic function of providing various voltages and currents to various units in a 3D chip-level system (3D system). The supply voltage can be designed to be constant with a narrow range of variation throughout the 3D system. The power distribution system in a three-dimensional system is critical to its reliable operation. From a static operating perspective, IR drop is highest near the center of the 3D system and lowest near the Vdd and Vss connections. However, IR degradation is a dynamic phenomenon due to the time-varying power requirements of individual circuits/memory blocks. In U.S. Patent 8,273,610 with reference to Figure 162 thereof, which is incorporated herein by reference in its entirety, a hierarchical power distribution system is supplemented on a 3D system. An alternative technique is to distribute a supply voltage that is at least 10% greater than the required voltage of the circuit block. The overdriven power supply is able to accommodate worst-case dynamic IR drops. For example, as shown in Figure 10E, this may include buck converters or voltage regulators, which can be distributed in each area on the 3D system. Region here can refer to blocks, chips or cells. The voltage regulator ("VR") may be a DC-DC converter, a low dropout (LDO), or other form of power regulator. Such a voltage regulator can be dedicated to stabilizing the power supply in its own non-isolated area. By doing this, power management can be highly granular and controlled individually for different load blocks. Another alternative could be a multi-level distributed power architecture. Another level of power distribution or a single intermediate bus converter can be added between the external power source and the zone VR point. The intermediate bus converter may be a separate (isolated) voltage regulator such as a DC-DC converter, low dropout or other form of power regulator. The intermediate bus converter can be a discrete module that regulates external voltages relatively loosely, and it can be integrated within the hierarchical power backplane. Alternatively, the Zone Point VR could have a digital interface and some programmability, where it is controlled via its digital interface from a central controller within the 3D system, or the signals going in and out of the 3DSYSTEM could be external control signals.

In a 3D system, the donor wafer and the host wafer can have different coefficients of thermal expansion. The donor wafer to host wafer bonding process should control stress and warpage to produce a reliable donor to host connection. The master wafer in this article may refer to a single wafer or a multi-layer stack structure. "Thermal Analysis of Si/GaAs Bonding Wafers and MitigationStrategies of the Bonding Stresses" by Qiu, Yuanying et al., Progress in Materials Science and Engineering 2017 (2017) According to research, which is incorporated herein by reference in its entirety, bonding processes at room temperature reduce stresses compared to processes that require elevated temperatures; furthermore, the research shows that the bonded wafers are thinner, e.g., less than 1 μm thick. Stresses are reduced compared to bonding of thicker wafers. Stresses can also occur dynamically during the operating process of a 3D system in the field due to uneven heating of the structure during the operating process. Furthermore, when stacking multiple wafers, stress may accumulate, at least proportionally with the number of levels. Technology that provides assistance through intentional stress relief mechanisms can be integrated into such a 3D system, as shown in Figure 10F. Step s1 shows a master wafer with three levels stacked and connected to adjacent levels with through-wafer vias, such as through-silicon vias (TSVs) or nano-TSVs. To engage the damping function to mitigate stress accumulation, an array of stress damping trenches arranged in the horizontal and vertical directions is patterned as shown in step s2. Then, as shown in step s3, another wafer is then bonded and transferred to the main wafer. Depending on the required number of layers, a stress damping trench is formed on the uppermost layer as shown in step s4, followed by wafer transfer. For example, other types of stress relief structures, such as trenches or holes, can be formed, as shown in SR (stress relief) structures: discontinuous linear SR trenches 1042, square or rectangular SR trenches with rounded or chamfered corners 1044 , circular or oval SR grooves 1046 and stress damping SR holes 1048.

Level transfer and hybrid bonding may require special interconnect layers to form pads/pins, as shown in Figures 5A-5E. Forming such structures beneath active circuitry may require first level transfer and substrate removal, such as shown in Figures 9B-9D. Wafer processing costs are highly dependent on the type of process line used, as shown in the table in Figure 11. The table in Figure 11 was published in a report titled "Al Chips: What They Are and Why They Matter, An Al Chips Reference" in April 2020. Written by Saif M. Khan, Alexander Mann, incorporated herein by reference. It shows the order of magnitude cost and price difference from 90nm line to 5nm process line. Therefore, it may be useful to construct special coupling hierarchies that may include electronic alignment capabilities similar to those of Figures 1A-3C of PCT/US2018/052332, which is incorporated herein by reference. middle. Such coupling levels can help build heterogeneous integrated 3D systems, where memory levels can be between cell bottom pins like 907 of Figure 9A and over cell top pads like 906, 908. Using a coupling hierarchy, the pins 907 between cells can be coupled to the circuit pad structure, as shown in Figure 5A, using only hybrid bonding.

A 3D system like the 700 can be built with all layers customized for the specific system in question, or with many layers being generic, utilizing agreed-upon standards for pin/pad locations and cell sizes. Therefore, the coupling level can be made consistent with such 3D heterogeneous integration standards. In some cases, the on-circuit pin/pad locations may be part of the standard, while the pins/pads or control lines within the cell pins/pads may be customized to better fit a specific memory or other type of circuit technology.

Figure 12A is a cross-sectional view of cross-section X-Z 1202 at the coupling level. On the removable substrate 1204, switchable bottom pins/pads 1218 are constructed according to the concept shown in reference to Figures 1A-3C of PCT/US2018/052332. Transistor selection 1216 may be similar to Figure 12B in Figure 2E of PCT/US2018/052332. Selected signals, referred to as BL1-BL4, may be connected to circuit pin/pad structures 1214, which may be formed according to standards. The coupling level may have very simple control circuitry 1212 to perform electronic alignment selection such as between GLS to GRS. The structure may include larger pins/pads for power connections, not shown. The control circuit 1212 can measure connectivity using the two connected test pins/pads in the target hierarchy and select between which GLS to GRS accordingly. Additional larger pins/pads are available to connect optional stratum select control pins. Such level selection control signals can be used to disable GLS and GRS. Such hierarchical selection is useful in situations where it is difficult to formulate hierarchical selection in the target wafer, as shown in the DRAM discussed with reference to Figure 26A of US 16/558,304, which is incorporated herein by reference.

While using a coupling hierarchy with hierarchy selection or the technique discussed with reference to at least Figure 26A of US Patent Application No. 16/558,304 (US Patent Publication 2020/0176420) is an alternative to hierarchy selection within a memory hierarchy, memory hierarchy processing may be preferred. Adds the additional processing steps required to make level selections within it. The type of tier selection can be designed as part of such an M-tier design. Such a design can accommodate a single transistor type such as n-type and some relaxed selection of transistor specifications compensated by other elements of the M level, such as the design of sense amplifiers to support intra-memory level, level selection, as described in US patent application 16 /558,304 (U.S. Patent Publication 2020/0176420A1) as shown in at least Figures 22C-22E.

Figure 12A illustrates the coupling levels in preparation for hybrid bonding to the pin/pad structure on the circuit. If you need to bond to the structure between the pins/pads, you can use a carrier wafer to flip the structure so that it will bond to the structure in the middle of the pins/pads first.

The use of horizontal transfer in 3D integration is often referred to as parallel device integration, rather than sequential integration. In parallel device integration, two wafers are processed separately (usually after transistor formation and some metallization), and then they are integrated using a main process step (e.g., hybrid bonding). This concept can be further extended to methods that integrate 3D systems, see, for example, Figure 7A of this article. Such 3D systems may accordingly utilize more than one type of memory and memory technology. The most common memories in computing systems are SRAM or ferroelectric memory developed by FMC for ultra-fast memories such as caches, DRAM for most fast memories such as main memory, and DRAM for high-density memories ( Such as data storage) NAND flash memory. Systems may include NOR-type flash memory and other types of memory such as cross-point memory, MRAM, or RRAM for program code storage. In a 3D heterogeneous integrated system, these memories can be integrated by horizontal transfer of memory wafers processed on appropriate wafer fabrication lines utilizing the specific processing required by the memory technology. Parallel integration processes can be used to complete integration in stages. The first stage may be to process the required wafers in an appropriate wafer production line, which may include front-end line processing (transistors) and back-end line processing (interconnects). The second stage may include level transfer to form a "main level" or "memory level", which may be referred to as the M level.

Thus, the memory control wafer (possibly formed via the first stage) can be transferred on top of the memory wafer (possibly formed via the first stage, possibly in a different sector line) to form an M-level wafer. M-level wafers can be stored while awaiting use in 3D systems. After the M-level wafers are formed and possibly stored, these M-level wafers can be transferred and integrated to form the desired 3D system, as shown in Figure 13. Memory control may include circuitry (also called "memory peripherals", especially in 2D devices) such as decoders, sense amplifiers, charge pumps, self-test logic, and similar memory control circuitry. It can include vertical connections to the memory hierarchy, providing word lines, bit lines, hierarchy selection, and so on. The memory controller may use hybrid bonding connection technology, see for example Figures 4A-4C, Figures 5A-5E, and Figures 12A-12B herein, and Figures 21A-27D of U.S. Patent Application No. 16/558,304, Publication No. 2020/0176420, and Figures 1A to 3C of PCT application PCT/US2018/52332, all of which are incorporated herein by reference in their entirety.

Figure 13A is an X-Z 1302 side view of the wafer area. It illustrates the phased integration of a three-dimensional system. In the first phase, each wafer is processed in its respective process line, such as logic lines for processor stage 1320, DRAM lines for flash memory 1318, DRAM memory control 1316, high density memory 1314 3D NAND lines and 3D NAND control logic circuit 1312. Alternatively, the DRAM memory control logic wafer 1316 may be processed from a different logic fab than the DRAM line. Likewise, the 3D NAND control logic die 1312 may be processed from a different logic fab than the 3D NAND lines. DRAM memory die 1318 may include only memory cells. Alternatively, DRAM memory die 1318 may include memory cells and some core logic functions, such as sense amplifiers and row/column decoders. The 3D NAND wafer 1314 may only include memory cells. Alternatively, the 3D NAND die 1314 may include memory cells and some core logic functions such as sense amplifiers, row/column decoders, and control line select gates. The DRAM memory control logic circuit 1316 and the 3D NAND control logic circuit 1311 include at least one of a data buffer, an address buffer, a control buffer, a mode resistor, an error correction control circuit, and a built-in test.

In a second stage, the M level is formed by flipping and bonding (hybrid bonding) the DRAM control circuit 1316 on the DRAM circuit 1318 and the substrate backside cut, such as by using etching, grinding or polishing the DRAM control substrate to create the bonding structure 1324 , and adding pin/pad levels to produce at least one of the M levels of DRAM 1334 . Similarly, the 3D NAND circuitry 1314 and the backside of the substrate, such as by using etching, grinding, or polishing the 3D NAND control substrate to create bonding structures 1322 and adding pin/pad levels to create at least one of the M levels of DRAM 1332 The 3D NAND control circuit 1312 is flipped and bonded on the cut. Then in the third stage, the DRAM M level 1334 is flipped and bonded on the processor level 1320, the DRAM substrate is cut to obtain the bonding structure 1330, and the pin/pad structure is added as needed, then flipped and bonded on the structure 1330 The NAND M level 1332 is bonded, and the NAND substrate is cut to obtain a bonded structure 1340.

Memory control signals, such as data paths, addresses, and recommendation lines, may be shared between the DRAM M level 1334 and the 3D NAND M level 1332. DRAM MM level 1334 and 3D NAND M level 1332 may have their own dedicated control signals.

Figure 13B is an X-Z 1302 side view of an alternative stage integration forming a 3D system. The M level of DRAM 1334 and the M level of 3D NAND 1332 may be processed separately and possibly banked. The DRAM M level 1334 and the 3D NAND M level 1332 are flipped and joined on the processor level 1320 in, for example, a side-by-side arrangement (other arrangements are possible, touching edges, touching only one corner, etc., all determined by engineering and manufacturing considerations) to form 3D System Architecture 1350.

It should be noted that the use of DRAM or 3D NAND in this article represents high-speed/volatile memory or high-density/non-volatile storage. As other memory technologies become useful, such as SRAM, cross-point memory, PCRAM, RRAM, FRAM and MRAM, these memories can be integrated in 3D systems like the proposed concept.

As mentioned previously, 3D systems can be built using industry standards for cell size and pin/pad location. Using a structure such as the M hierarchy can allow compliance with standards while maintaining system architectural flexibility. This may be through the hierarchical control circuitry grouping multiple units into M hierarchies for a specific application.

There are many variations to such a flow, including including multiple memory levels within an M-level that are first joined to form a 3D memory structure, see for example at least Figure 21H of U.S. Patent Application No. 16/558,304, Publication 2020/0176420 , Figure 25C, Figure 25J, and Figure 26A, which are incorporated herein by reference in their entirety.

With M-level integration, the 3D system vertical connections of each unit can be reduced to a busbar format. Therefore, the vertical bus connections may include address lines, which may be decoded into word lines and bit lines by each M-level memory control circuit. System-level vertical connections per unit can count around a hundred lines, rather than thousands. Feedthrough concepts, such as per-unit feedthrough 718 in Figure 7B, can be used for such vertical per-unit buses. Vertical lines or columns can be assigned, for example, 32 data, 34 addresses, 4 system types, 16 controls, and 14 feedthroughs. Certain systems may use more or less than 100 leg line buses per unit. This vertical bus can utilize computer system bus technologies common in the industry, such as multiplexed data or address lines, or use industry standards such as AMB A, Avalon, and others. Milica and MileStojcev review a series of industrial chip bus standards in a paper: "Overview of On-Chip Busbars," Factauniversitatis Series: Electronics and Energetics 19.3(2006):405-428, which is incorporated by reference in its entirety.

Figures 14A-14B are vertical X-Z 1402 cross-sections of a region of such a 3D system at different scale factors. Figure 14A shows several cells 1406 and a central vertical busbar 1408. The 3D system can be constructed on a functional substrate 1403 including thermal removal structures, trench capacitors or integrated inductors as previously described. Power distribution network and stack 1404 of heterogeneous integration of energy levels and M-levels as previously discussed. In addition to vertical busbars, the system may also include power busbars to support power distribution to various levels. The vertical power bus can be on the same side of the unit or on another side. For example, other vertical common columns can be used, such as common clocks and test signals. The unit side dimensions may be 200gm as often mentioned herein, or other dimensions including different dimensions in the X direction and Y direction, for example, about 0.1 mm, about 0.2-0.4 mm, about 0.4-0.8 mm, about 0.8-1.2 mm, about 1.2-1.6mm, about 1.6-2.2mm, about 2.2-3.5 or even greater than about 3.5mm.

Figure 14A illustrates the use of redundancy for the vertical struts 1414 of this busbar common vertical connection. Figure 14B shows three vertical struts 1414 carrying the same signals of the vertical bus and being connected together to provide a common horizontal signal 1416 for the M levels to be used. M-level control circuits may include decoders and other control circuits including bus multiplexing, level selection, power generation including voltage pump circuits, and other circuits such as what are commonly referred to as memory peripheral circuits.

Figure 14B shows a portion of a 3D system with a functional substrate 1411, a processor stage 1420, a high-speed M-level 1422, a high-density memory M-level 1424, a horizontal electromagnetic interconnect M-level 1426, and an M-level for connecting the 3D system to the outside. The input and output M levels of the device 1428. The 3D system may also include a thermal isolation layer 1421 for isolating processor heat from the overlying memory level and a shielding layer 1425 for protecting the underlying layers from Effects of EMI noise that may be associated with the electromagnetic interconnection M level 1426.

The 3D system of Figures 14A-14B may include coupling hierarchies as previously discussed, or coupling hierarchies that connect industry standards used in the system to hierarchies or M-levels built for other standards. Such a coupling level can be considered a standard-to-standard coupling level.

Figure 14C is a horizontal cross-sectional view X-Y 1432 of an area of the 3D system showing a sub-array of 6x3 cells 1438 and its associated side vertical struts of busbars 1434 and 1436; these may include its layoff struts. Although Figure 14C shows the vertical busbar struts 1434, 1436 as blocking gaps between cells, it is contemplated that the design of such a 3D system can support gaps between adjacent cells and across cells (not shown). Connect the X-Y connection. These designs can be made by engineers in their field to accommodate the trade-offs associated with the number of vertical pillars, pin/pad design rules and vertical pillars and their redundancy, cell size and other system considerations and design rules.

An additional alternative to accommodate joint misalignment while still using hybrid joints may be the techniques proposed with reference to at least Figures 93A-94C of US Patent 8,395,191, which is incorporated herein by reference in its entirety.

Another advantage of using the M-level concept is for pretesting. With reference at least to Figure 86C of US Patent 8,395,191, which is incorporated herein by reference in its entirety, the concept of contactless or wireless testing is proposed. This can be used to perform tests at the M level specified for integration into the 3D system. Probe testing or other forms of testing, including the use of self-tests and scan-based testing, can be used to test a hierarchy and flag any units with faults that cannot be overcome by unit-level redundancy. This pre-testing can be an important part of 3D system integration to achieve overall system yield. Additionally, the M-level can include post-packaging repair capabilities by including redundant rows and columns of memory cells, address mapping/remapping blocks, built-in tests, and antifuses. The M level can even further include soft packaging post-repair circuitry. In addition, the M level may also include on-chip error correction circuitry.

In this manufacturing operation, there are several advantages and operational alternative options after such level and M-level testing before 3D integration using, for example, hybrid bonding. One option is to select high yield levels and M levels for 3D integration, while lower yield levels can be used for other applications, such as standard memory products or other standard functions. Lower yield levels can also be integrated in 3D technology into structures with fewer levels where this loss of yield can be accepted or repaired. Another option is to perform matching of levels to maximize 3D system yield, by aligning faults to match levels to minimize yield loss, such that many faulty cells cover other faulty cells. Cell-based 3D system architects, where each cell has its own vertical connections and power delivery, can be used to support the functionality of the entire system, even if some of the cells do fail and should be disabled. This can be thought of as a redundant or agile system reconfiguration. Therefore, using tests such as scan-based or other types of built-in testing ("BIST"), the system disables units that cannot be repaired through their built-in redundancy.

14E vertical In such an alternative, the upper region of the M level may have coarser cell partitions 1448 than the lower partitions 1446 . The upper M levels may include one or more levels including high density memory, for example, 3D NAND type memory. Such memory is associated with longer access times and can support system performance with reduced vertical connections. Other variations of 3D system modularity may be useful in some applications.

Another option for 3D systems is shown in the figure. 14E is a memory-centric architecture that moves processes rather than data. For many years, common practice was to bring data to the processor to compute the required instructions. As the amount of data continues to grow, another approach that may be more effective is to introduce processing units to the data. In the 3D system described in this article, a large amount of data can be stored in the 3D system to form a pool memory. For example, data related to the United States may be stored in a location marked by US data (bubble) 1452, while data related to Europe may be stored in a location marked by European data (bubble) 1453. Therefore, if you want to compare US data To perform a search or other operation, the appropriate program may be transferred to a processor close to the US data, marked by a compact processor (bubble) 1454. In some systems, the processor may include programmable logic such as FPGA gates and The associated structure of the programmable logic. Therefore, the appropriate bitstream for programming the configurable logic can be passed to the closed processor (bubble) 1454 close to the data designated for the processor 1452. In this case, the process It may be more efficient to store the resulting data near the original data (bubble) 1452 and move it closer to the processor (bubble) 1454 in the new program for the next processing step. Therefore, since the data and processor are in close proximity, the processing energy will Significantly lower, while raw performance will be higher.

The processor level itself may be an M-level with processor program memory, and the L1 cache level may be integrated using 3D technology, as described herein and in the technology incorporated by reference.

The 3D system introduced herein with reference to Figures 13A to 14E is about various heterogeneous structures of modular 3D systems. The M level can have very high connectivity between the memory control level and the memory level, with hundreds or thousands of vertical connections per unit of bit lines and word lines, as well as additional controls as needed, such as level selection. Such vertical connections may utilize hybrid bonding and pin/pad structures similar to those set forth herein with reference to Figures 5A-5E, or at least with reference to the drawings of U.S. Patent Application No. 16/558,304, Publication No. 2020/0176420 21H, Figure 25C, Figure 25J, and Figure 26A, the entire contents of which are incorporated herein by reference. It can also use technologies such as those cited in this article, for example, as electronic alignment. It can also use other techniques, such as smart alignment by reference in the merge-by-reference technique. This rich per-unit vertical connection can be used in the M hierarchy, while in 3D systems looser vertical connections can be used leveraging the per-unit vertical bus concept - for example, see Figures 14A-14C. Therefore, each level in the 3D system can support the vertical connection of the busbars of each unit. Some levels can support this as a feedthrough, while others can also support it by connecting busbars or busbars between levels in the system. Referring to FIG. 7G , a vertical bus signal 758 is shown feeding the memory control 739 of the M level, and is also shown feeding the memory level 752 via 755 . As mentioned previously, the design of the memory hierarchy can include the design of feedthrough columns to support connections to the vertical unit system buses. Thus, a 3D system can include modest vertical connections per cell, such as about a hundred columns per cell bus, and rich connections within the M hierarchy, such as a thousand columns per cell, to support memory control levels with word lines and bits Line 753 is the connection between the memory arrays. Different vertical connection techniques and alignment techniques can be used for vertical busbars and internal vertical connections per M level.

In some 3D systems, vertical connections may include more than one vertical busbar per unit. These vertical buses can have different functions. For example, a vertical bus that connects the memory M level to the processor level can be called an M bus. There is an additional vertical bus that connects the X-Y connection M level to the processor level, which can be called the C bus. For example, the M bus in some systems may not even extend to the X-Y connection M level, while in some systems the C bus may not only feed through the memory M level. The C busbar can be similar to the M busbar, or it can be very different, for example, utilizing different industrial busbar standards, etc. The bus of each function can be expanded into a bus for high-speed memory (which can be called an SM bus) and a bus for high-density memory, which can be called a DM bus. The SM bus may be designed for high speed, e.g. using wide data within a bus with more than 16 legs for data, while the DM bus may be designed for high integrity with e.g. built-in redundancy and error correction features.

In some systems, the unit may have sub-units, as shown in Figure 14D, the X-Y 1442 cross-sectional view shows an example of a unit 1430 with a sub-unit of the communications processor 1432 and 16 sub-units 1436 of the Al processor. The communications processor 1432 may have a C bus 1434 for communicating with the X-Y connection M level, and an M bus for connecting it to its overlay memory. The Al processor 1436 may have an M bus to connect it to the memory it overlays. Additionally, the processor stage may have a horizontal bus (not shown) connecting the A1 processor to the communications processor 1432. Subunits 1436 may have side dimensions of 100 pm or other dimensions, as mentioned previously for unit dimensions. The system may include a mix of different types of units optimized for different types of tasks. Many other variations of these concepts can be designed by engineers in the field to build 3D systems capable of efficient parallel processing as well as serial processing with efficient connections across systems.

An additional alternative is to extend the M bus to a larger number of data columns, for example, 80, 160 or even beyond 320. This expanded M-bus increases data communication between processing and memory levels to support increases in overall processing speed/performance.

Due to the ultra-wide data in the bus and cell-level partitions of the memory array, the memory hierarchy based on 3D NAND technology can provide reasonable data rates and provide the system with the role of high-speed memory. Such 3D NAND technology could be modified to utilize extremely thin tunnel oxides, thereby giving up retention time for faster write and erase times and better endurance, as described in at least US Patent 10515981 and PCT application PCT/ are discussed in US2018/016759, which application is incorporated herein by reference. Samsung has practiced in the industry modifying 3D NAND technology into ultra-low latency memory through its product line called Z-NAND. Such a concept can be further enhanced by using extremely thin tunnel oxides, very wide data busses, and partitioning the memory array into hundreds of cells that take advantage of memory-controlled stacking of 3D NAND memory arrays, as described in this article and Some of the joint references are described in the literature.

In general, the 3D system proposed in this article may be similar to existing systems for connecting chips and packages employing printed circuit boards ("PCBs"). Many system architectures of these PCB integrated systems can be mapped to the vertical 3D systems presented in this article.

The M-level concept can be extended beyond memory to other functional components of the 3D system. This can be an X-Y interconnect using electromagnetic waves. The connectivity M level may include control level, modulation and decoding level, and transmission line/waveguide level. Therefore, the bus vertical connection can be used by the X-Y interconnect controller, which can then propagate the information to the X connection channel and the Y connection channel.

For thin wafer transfer processes, electrostatic chucks are becoming increasingly popular as wafer handlers due to their long-term electrostatic retention capabilities and reversible attachment of thin wafers. When wafers are stacked to configure a wafer-scale 3D system, as shown in the figure. 13A Degradation of transistor oxides may occur due to electrostatic discharge (ESD) current stress. This gate oxide degradation can lead to functional failure and result in shortened lifetime. To protect the gate oxide from the hybrid bonding process of Nano-TSVs, ESD protection functions can be connected on the Nano-TSVs. Figure 14F shows an enlarged view of the ESD protection features connected to the Nano TSV and internal logic. A variety of ESD structures are known in the art and can be used to support 3D system manufacturing. These ESD structures are usually quite large. Here, nanoTSV and vertical busbar pillars may be mentioned interchangeably. For 3D systems and supporting vertical busbar struts, as shown in Figure 14B, these structures can be scaled down 1:10 or even 1:100 to lay in a rectangle of approximately 1x1 gm ² , or if multiple vertical struts 1414 are specified Support the same signal as redundancy, e.g. Figure 14B. Then a normal ESD can support it and can have a rectangular size of about ^2x2gm2 . Figure 14F shows the structure of Figure B 1460 with multiple ESD surrogate structures 1462, 1464, 1466, 1458, 1470, 1472. Depending on the type of wafer surface side to be bonded, the connections can be front-to-front, front-to-back, or back-to-back. ESD protection functions can be individual devices or circuits. ESD protection features shunt or bypass ESD current with limited voltage drop. In traditional CMOS, ESD protection of I/O pads is widely used and is incorporated into this article by reference, such as "Low-C ESD Protection Design in CMOS Technology" by Lin and Chun-Yu CMOS Technology)”, From Microgap Breakdown to Electrostatic Discharge in Nanogenerators, IntechOpen, 2019 and Albert ZH Wang, On-chip ESD Protection of Integrated Circuits: An IC Design Perspective, Volume 663, Springer Science and Business Media, 2006. Similar ESD devices or ESD circuits may be used in the present invention. Assuming that the internal circuit operates between Vdd and Vss, the EDS function does not conduct in the normal voltage region. For ESD induced voltages greater than Vdd, the ESD function shunts the ESD current. Common ESD protection functions can be diodes, MOSFETs, silicon controlled rectifiers (SCRs), and combinations thereof, as shown in Figure 14F. Several options (but not limited to) are shown as cross-section views. One option for ESD functionality could be a ground gate N-type MOSFET 1464, where the gate, source and body are connected to ground to keep it off during normal operation. This type of ESD was previously studied in Lee, Jian Xing, et al., “Dynamic current distribution of multi-finger GGNMOS under high current stress and HBMESD events,” 2006, Proceedings of the IEEE International Symposium on Reliability Physics, IEEE, 2006 , which is incorporated herein by application. Another option for ESD functionality can be a Silicon Controlled Rectifier (SCR) 1468, which consists of PNP BJT and NPN B JT. The positive feedback mechanism of cross-coupled PNP and NPN results in ESD shunting. NPN and PNP B JTs can be defined by shallow trench oxide or dummy gates. This type of ESD was previously described in Ker Ming Dou and KC Hsu, "Overview of Design of On-Chip Electrostatic Discharge Protection for SCR-Based Devices in CMOS Integrated Circuits," IEEE Transactions on Device and Materials Reliability 5.2 (2005): 235-249 conducted research, which is incorporated herein by reference. Another option for ESD functionality could be an SCR device with a trigger terminal connected to the base of one of the BJTs. The trigger terminal can be further coupled to another device, such as the MOSFET's gate, substrate, and diode. An example of a GGNMOS coupled SCR is drawn as example 1464. Diode-type ESD creates a unidirectional discharge path. The dual diode ESD 1470 uses two unidirectional ESD devices to create a bidirectional discharge path. In CMOS processes, n-type wells and p+ diffusions and p-type wells and diffusions can cause bidirectional ESD in bidirectional diodes. The n+ and p+ diffusion regions can also be separated by STI or dummy gate. In another example of ESD, diodes can be stacked to reduce parasitic capacitance or provide a higher trigger voltage, as shown with stacked bidirectional diodes. This type of ESD was previously studied in Son Minoh and Changkun Park, "Electrostatic discharge protection devices using distributed battery-based diode series connections," Electronic Letters 50.3 (2014): 168-170, which is incorporated by reference in this article. In another example, SRCs can be embedded into stacked diodes, as shown in Stacked Diodes with Embedded SCR 1462, as previously described in Lin Chun Yu et al., “Improving Stacking with Embedded SCR Applications in 65nm CMOS” ESD Robustness of Diodes," studied in 2014 IEEE International Symposium on Reliability Physics, IEEE, 2014, which is incorporated herein by reference. Another example of ESD provides bidirectional discharge in a single ESD device. The cross-sectional view of the SCR and diode shows that the SCR path is responsible for the ESD discharge between nTSV and Vss, and the diode path is responsible for the ESD discharge between nTSV and Vdd.

A small ESD, such as a regular ESD of about 1:100, can be integrated at each M level to support its vertical busbar pillars. The M-tier can be designed to be pre-tested to support the various integration strategies discussed earlier. The test process may be related to electrostatic charge, and appropriate ESD may be important to support M-level pre-test and integration strategies. If desired, the full level with conventional ESD can be integrated into an ESD level for applications where protection from high voltage ESD may be required. Reduced ESD can be designed by engineers in the ESD design based on design choices for the final (after transfer bonding and refinement) substrate thickness of the M-level silicon to support this M-level.

The wafer-scale 3D system proposed in this paper may require redundancy and yield fixes or yield flexibility to become a commercially viable technology. This has been suggested herein and in the art incorporated by reference, including various techniques, such as with reference to Figures 35A-35C and Figures 38A-38C of U.S. Patent Application No. 16/558,304 (Publication 2020/0176420), incorporated herein by reference. . Additional 3D-based redundancy and repair techniques are proposed with reference to Figures 17 and 24A-44B of US Patent 8,994,404, which is incorporated herein by reference. Each M-level in the 3D system may include its own self-test and repair technology, such as memory and mission-critical circuitry known in the art. Additional techniques for 3D systems may include adding redundant M-levels, such as a second backup level for X-Y connected M-levels. Or add a redundant vertical busbar to each unit. These layers of redundancy can be connected to enhance the system and provide fault tolerance, defect flexibility, and graceful aging.

The 3D system described in this article utilizes a number of units that have processor memory and can be interconnected using a hierarchy of X-Y connections. Such systems are sometimes called "networks on a chip" (NoC). Such a system can manage defects by calling up spare units to be activated to replace defective units or by providing pre-tasking capabilities to allocate workloads to available good operating units. The concept of such complex systems with self-healing and operational flexibility is well known in the art and is used, for example, with server farms and other multi-computer systems. This technique can include the use of a circuit called a "monitor" in which a good operating unit will periodically trigger the monitor circuit, announcing that the unit is in good operating condition. If a monitor is left for too long without this trigger, it may activate unit failsafe mode. Therefore, once a faulty unit is detected, the monitor circuit can activate a controlled vertical bus disconnect to isolate the faulty processor from the vertical bus, thereby preventing the faulty unit from affecting the operation of other units of the 3D system. In this case, the circuitry can also initiate a processor restart to overcome the temporary failure and restore unit operation. If the fault is permanent, then in addition to bus isolation, the monitor circuit can control the processor central operating clock circuit to further reduce damage to the failed unit processor and reduce its power consumption. Additionally, the 3D system may include a system process in which each unit is periodically pinged by the 3D system tasker processor. If a unit is deemed faulty by the task allocator processor, recovery operations can be activated to allocate a spare unit to replace the failed unit. Alternatively, the 3D system may include the flexibility to redistribute system tasks between operating units. Those skilled in the field of large-scale multi-computer systems can engineer this built-in test, detection and recovery technology into the design of 3D systems.

Another alternative to such a 3D system is to have a level constructed by transferring multiple dies instead of one wafer as shown in Figures 43A-43E of U.S. Patent Application No. 16/558,304, Publication No. 2020/0176420. These patent applications are incorporated herein by reference. Such chip-level transfer can also be exploited Inoue, Fumihiro et al., "Advanced dicing technology for wafer-to-wafer and collective chip-to-wafer direct bonding," 2019 IEEE 69th Electronic Components and Technology Conference (ECTC) A proposed technology called "Collective die-to-wafer direct bonding", IEEE, 2019; also, Nick Flaherty's titled "Collective die-to-wafer bonding with 3D packaging accuracy below 2|im", European EE News, 2020 October 19, 2020; "High-speed ultra-precise direct C2W bonding" by Brandstatter, Birgit et al., 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), IEEE, 2020; All content above is incorporated by reference in full. in this article. Such chip-level transfer can use the M-level concept to transfer the chip to the base layer, thereby forming an M-level that can be called a chip level, and then transfer it together to the 3D system stack.

This DieM level concept can be used to utilize X-Y junction M levels of lasers, photodetectors, and waveguides, as shown in reference to at least Figures 35A-37B of U.S. Patent Application No. 16/558,304, Publication No. 2020/0176420, which is incorporated by reference are incorporated into this article. This DieM hierarchy can be achieved through silicon photonics, which includes photodetectors made of silicon-germanium alloys. The wavelength of the photon connection may be about 1.3 microns or about 1.5 microns, but other useful wavelengths are possible. Such a DieM hierarchy may be part of a 3D system, such as reference numeral 1447 in Figure 14E herein. An example is given with reference to Figures 15A-15D, which are cross-sectional views of X-Z 1502.

Figure 15A shows a drive and control wafer 1504 with waveguides 1512 positioned over control and drive circuitry 1514 on a cutting layer (eg, SiGe 1516) on a substrate 1518. The driver and control die 1504 may include vertical connection pads 1506 for connecting the driver and control die 1504 to one or more laser diode chips 1520 , which may be bonded on top, and transparent vias 1508 for directing the laser beam to the beam splitter and direction changing assembly 1510 and thereby direct the laser beam(s) to the appropriate waveguide. Techniques for processing such waveguide and optical interconnect structures are known in the art and are set forth, for example, in at least U.S. Patent Nos. 5,485,021, 5,987,196, 6,791,675, 7,203,387, 8,548,288, 9,197,804; Lo Shih-Shou, Mou-Sian Wang, and Chii-ChangChen's paper "Semiconductor Hollow Optical Waveguides Formed by Omnidirectional Reflectors," Optics Express 12.26 (2004): 6589-6593, all of which are incorporated herein by reference. Laser diode chip 1520 may also be built on substrate 1530 with optional dicing layer 1528. Laser diode chip 1520 may include a number of diodes with each diode's pins/pads connected in clear via outputs and supporting structures such as ground/power connections. The laser diode may be built on a crystal 1526 that is well suited for laser generation, such as GaAs, InP, GaSb, GaN, etc. Crystal layer 1526 may be a different material than substrate 1530. For example, crystal laser 1526 may be a crystalline direct bandgap semiconductor grown on silicon substrate 1530 through a buffer layer. Alternatively, a crystalline direct bandgap semiconductor (so-called chip) is transferred and bonded to the silicon substrate 1530. The laser diode chip may include pins 1522 and transparent vias 1524. In many cases, the crystals used for laser diodes are not available on 300mm wafers, so wafer-level transfer may be preferable for 3D integration applications.

Figure 15B shows the bonding of several laser diode chips 1520 on top of the driver and control wafer 1504.

15C shows the bonding structure 1540 after detailing the substrate of the laser diode chip 1520. If the laser diode chip 1520 has a dicing layer built into it, such a dicing layer, such as the dicing layer 1528 shown in Figure 15A, can be used in the thinning step. Many crystals used in laser diodes are built using epitaxial growth on another crystal. This process can be used to form an etch stop cut layer between the carrier substrate and the diode laser crystal. After the thinning process, other process steps can be used, such as conformal oxide deposition for filling the gaps between laser diode chips, followed by CMP to provide planarization. If desired, the step of forming connection pins/pads on the now top surface can be utilized.

Figure 15D shows the structure of Figure 15C after flipping it onto another substrate 1548 with cutting layer 1546 and removing its substrate 1538. The structure of Figure 15D can be prepared as a DieM layer by adding pads/pins (not shown) for future vertical connections to the C bus.

Optical X-Y interconnects can also utilize silicon wafers, making them easier to integrate into the 3D systems presented here. For example, the paper by XuKaikai et al. "Silicon light-emitting devices for fast optical interconnection and fast sensing applications in the GHz frequency range in standard IC technology", Optoelectron.Adv.Mater.-Rapid Commun 11(2017): 164-166 and Snyman, Lukas W. et al., "Stimulating light emission at 700-900nm wavelengths from Si AMLEDs and coupling into SiN waveguides using RF silicon integrated circuit processes," OSAContinuum 3.4 (2020): 798-813, Both are incorporated herein by reference in their entirety.

As shown in the steps between Figures 15B to 15C, after bonding the chip substrate to the target wafer, the chip substrate can be refined by grinding and wet chemical/plasma etchback. For silicon-based chips, SiGe-based dicing layers can achieve extreme thinning, even to final thicknesses below 500nm. In some cases, thinning of the chip substrate may be terminated using other forms of etching, or may be carried out to smaller extremes such as the 20 or 10 pm level without the use of a dicing layer. This will be designed to determine the best process for specific product and structural requirements. Many of these engineering trade-offs and possibilities have been discussed in the various components incorporated by reference.

Some techniques and processes for integrating optical waveguides have been proposed in US patents, such as at least 10,587,026 and 10,770,414, both of which are incorporated herein by reference in their entirety.

In some 3D systems, the need for X-Y connections can justify adding an M level of RF connections, which will be referred to as the RF-M level in this article. While optical connectivity can provide excellent bandwidth and minimal crosstalk, it is relatively bulky and uses components not commonly found in silicon processing. Optical connections can be used for longer X-Y connections, for example longer than 150mm, while RF connections can preferably be used in the range of 10mm to 300mm. Some 3D systems may use more than one technology for X-Y connectivity – just as more than one type of memory technology may be required, as shown in Figure 15E, “Wired/Wireless RF Interconnects for Future SoCs” by Tam Sai-Wang , 2011 IEEE International Symposium on Radio Frequency Integration Technology, IEEE, 2011, is a copy of Figures 8 and 9, the foregoing content of which is incorporated herein by reference.

Radio frequency interconnect (RF-I) has been considered the technology of choice for NoC-enabled on-chip multicore interconnects, as discussed in the following publication: Architectural Integration of Radio Frequency Interconnects to Enhance Multicore by Kaplan, Adam Blake, and Glenn Reinman On-Chip Communications for Chip Multiprocessors, University of California, Los Angeles, 2008 et al., Radio Frequency Interconnect (RF-I) has been regarded as the preferred technology for interconnecting NoC-enabled multi-core chips; Chang, M-C. Frank, et al. "Radio Frequency Interconnects for On-Chip Communications", Proceedings of the 2008 International Physical Design Symposium, 2008; Chang, M. Frank et al., "Covering On-Chip CMP Networks with Multi-band RF Interconnects", 2008 IEEE 14th International Symposium on High Performance Computer Architecture, IEEE, 2008; "Compact design of 60GHz CMOS amplifiers using transformer coupling and artificial dielectric differential transmission lines" by LaRocca, Tim, Jenny Yi-Chun Liu, and Mau-Chung Frank Chang, IEEE Journal of Solid State Circuits 44.5(2009): 1425-1435; "Simultaneous Tri-Band On-Chip RF Interconnects for Future On-Chip Networks" by Tam Sai-Wang et al., 2009 VLSI Symposium, IEEE, 2009; Wu Hao et al. "60GHz On-Chip RF Interconnect with X/4 Couplers for 5Gbps Bidirectional Communication and Multipoint Arbitration," Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, IEEE, 2012; all content above is incorporated by reference in full. . 1551 and 1552 of Figure 15F illustrate the transmission line configuration proposed and replicated in the work described. Such transmission lines ("TL") may have a pitch of approximately 12pm and may be formed on top of the active CMOS circuit using upper metal layers such as M7 and M8. These publications show that a set of such TLs can be arranged in a meandering topology connecting many computing cores, as shown at 1557 in Figure 15F herein.

The following disclosures are additional work such as: "8Gbps 2.5mW on-chip pulsed current mode transmission line with stacked switch Tx interconnect" by Maekawa, Tomoaki, Hiroyuki Ito, and Kazuya Masu, ESSCIRC 2008 34th European Solid State Circuits Conference, IEEE, 2008; Carpenter, Aaron et al., “The Case for Global Shared Media On-Chip Interconnects,” Proceedings of the 38th Annual International Symposium on Computer Architecture, 2011; Carpenter, Aaron et al., “Improving Effective Throughput of Transmission Line-Based Buses,” 2012 39th Annual International Symposium on Computer Architecture (ISCA), IEEE, 2012; and "Global on-chip communications using transmission lines" by Carpenter, Aaron et al., IEEE Journal of Emerging Topics in Circuits and Systems 2.2 (2012): 183-193, all of which are incorporated herein by reference in their entirety. These works proposed a similar concept but with a wider TL, as shown at 1554 in Figure 15F, with a pitch of approximately 45pm.

For example, follow-up work to the following publications demonstrating similar concepts: Drillet, Frédéric et al., “Flexible Radio Interfaces for NOCRF Interconnections,” 2014 17th European Micro-Digital Systems Design Conference, IEEE, 2014, which is cited in full Incorporated into this article, but with a wider TL, as shown at 1556 in Figure 15F, with a pitch of approximately 75pm.

These on-chip RF-I can be applied to the 3D system described in this article, as shown in Figure 15G. The meandering concept can be changed to an X-Y connected structure similar to that shown in Figure 33A of US application 16/558304, which is incorporated herein by reference. The choice of TL configuration can be designed to accommodate the X-Y dimensions of the 3D system and other parameters, such as the size of the cells and the need for X-Y connections. Although the shape of the TL is shown in Figure 15F as coplanar strips, other variants have been developed that can be integrated into such 3D systems. TL can be constructed as a repeating band in the X direction covered by a repeating band in the Y direction. The frequency bands may include a mixture of TL shapes, allowing for tight spacing for shorter distances and wide spacing and low attenuation for longer distances. These bands as TLs for paths over the units may include dropped connections for each unit, or have some TLs skipping some units, providing options for system architecture and usage protocols. An important aspect of this TL is the strong relationship between TL attenuation per millimeter length and carrier frequency and TL spacing, as shown in graph 1555 of Figure 15F.

Engineering of such 3D systems can include utilizing high frequencies for relatively short distance connections and low frequencies for relatively longer distance connections. In some cases, it can be designed so that one TL can be used for one area of the high-frequency local connection, while a distant area can utilize the same frequency for another local connection, thereby taking advantage of the attenuation effect of the signal in the first area. The width and thickness of the TL can be similarly tuned, using wider, thicker wires for longer distances and higher frequencies.

Figure 15G is an X-Z 1503 cross-sectional view of a 3D system similar to that shown in Figure 14E. Figure 15G shows an additional RF-M level 1570 disposed below the optical X-Y interconnect M level 1547. The process of forming RF-M level 1570 can be similar to the process shown in Figure 13A, except that 1314 can be a level of an array of RF receivers, transceivers, and supporting circuitry, with metal layers of TL in the in the Y direction. 1312 may be a layer of RF-oriented processors designed to support corresponding communication protocols for various communication links. Thus, RF-M-level 1570 may include an RF-oriented processor level 1572, level 1573 may provide RF shielding and RF matching levels, such as high defect substrates, and level 1574 may provide RF receivers, transceivers, and support circuitry. This level can utilize RF oriented crystals such as SiGe. Level 1575 may provide a bundle of Y-directed TLs, level 1576 may provide a bundle of X-directed TLs, level 1577 may provide a bundle of Y-directed TLs, and level 1578 may provide an X-directed bundle of TLs. Substrates designed to support RF circuitry on top are known in the art and are often offered as SOI high resistivity (HR) substrates or trap-rich HR substrates, such as, for example, Neve, Cesar Roda and Jean-Pierre Rask, "RF Harmonic Distortion of CPW Lines on HR-Si and Trap-Rich HR-Si Substrates," IEEE Transactions on Electronic Devices 59.4 (2012): 924-932, entire content Incorporated herein by reference. Another option is to utilize porous layers, as in the paper by Sarafis, Panagiotis, and Androula G. Nassiopoulou, “Porous silicon as a substrate for monolithic integration of RF and millimeter-wave passive devices (transmission lines, inductors, filters, and antennas): Current State of the Technology and Prospects," Applied Physics Reviews 4.3 (2017): 031102 and Gautier, Gael, and Philippe Leduc, "Porous Silicon for Electrical Isolation in Radio Frequency Devices: A Review," Applied Physics Reviews 1.1 (2014): 011101, All of the foregoing are incorporated herein by reference in their entirety. Integrating such RF-friendly substrates can help reduce power and improve the performance of such 3D systems, and can take advantage of the architecture and layer transfer techniques presented here and incorporated in the technology.

One of the advantages of RF X-Y interconnects is that it is relatively easy to access incoming and outgoing signals. TL maintains a larger distance between conductors, as shown in Figure 15F. Therefore, there is enough room for a via (eg, via 1553) to pass from the transceiver through the TL or to the receiver. Multiple levels of TL can be placed one on top of the other and connected to level 1574 - the RF receiver transceiver and support circuitry. These vertical connections are short, have acceptable attenuation even with conductor width connections of about 1pm, and can be impedance matched for optimal power transfer.

The connection to the TL can include a transistor switch to reduce the effects of inactive connections, as described in Hamieh, Mohamad et al.'s paper "A new interconnect approach to RF intra-chip communications using transistor-based distributed access," Microwave and Optical Technology Express 61.2 (2019): 297-302 is shown in Figures 2, 6, and 7, which are incorporated into this article by full text citation. Another alternative to multipoint TL uses L/4 directional couplers, as in the paper "60GHz On-Chip RF Interconnect with L/4 Couplers for 5Gbps Bidirectional Communication and Multipoint Arbitration" by Wu Hao et al., IEEE Presented in Proceedings of the 2012 Custom Integrated Circuits Conference, IEEE, 2012, which is incorporated by reference in its entirety. Electromagnetic coupling to TL is also proposed in US Patent 7,889,022, which is incorporated herein by reference in its entirety.

The hierarchy of RF oriented processors 1572 and the hierarchy of RF receiver transceivers and support circuits 1574 may be constructed as units aligned and corresponding to the underlying unit structure and connected to it using vertical busbars. The BEOL (back end of line) may be adapted to support the TL, for example having a thickness greater than 0.5 gm for the layer assigned to the TL. The metal thickness of the TL can be adjusted to be greater than about 0.8 grams or about 1.4 grams or even greater than 2 grams. The TL is shown in Figure 15F, and the related disclosure is designed to be suitable for general CMOS process lines, such as the IBM 90nm process, to support integration with the underlying SOC circuit. For a 3D system as shown in Figure 15G, it is best to have a dedicated process flow to support RF-M level processing.

As shown at 1557 in Figure 15F, the TL bundle is a meandering connection of 64-core processors with 16 communication nodes. Several publications proposed meandering, and other publications proposed U-shapes, Z-shapes, and X-shapes. These publications suggest using RF-I at the chip level, preferably with TLs connecting all central nodes in the system. Such an approach can be applied to the 3D system proposed in this paper. However, the 3D system in this article can be made much larger than the chip sizes previously discussed in this article, for example, by reticle size or 50cm x 50cm or 100cm x 100cm or larger than 200cm x 200cm, like full-size wafer or panel size. Such an approach may not be very attractive for such large area 3D systems, especially for large arrays of 3D systems with relatively small cells of area such as 200gm x 200gm. An alternative is shown in Figure 15H, top view X-Y 1580, with TL lines extending in the X direction 1582 and TL lines extending in the Y direction 1581. Each TL line can be connected to its underlying unit (not shown). At 200cm in length, a TL can have 1000 drop-off connections to its underlying units. To provide a connection between two units within a 3D system, a TL in the X direction and a TL in the Y direction can be used.

The use of X-TL and Y-TL can be done through direct connection or using the underlying 1572TL processor.

Figure 151 shows a block diagram of a per-unit TL processor of the base layer 1572 of the RF-M hierarchy 1570. It may include a processor 1583 with functionality connected to the per-unit vertical bus 1587 and, accordingly, connected to one of the overlapping TLs to transmit data to or from another unit in the system. The 3D system can utilize communication protocols for each of the types of communication links being used. Examples include communication protocols for vertical bus 1597 and communication protocols for inter-unit RF interconnection.

Additional processor 1584 may be a direct memory access processor (DMA). Such a processor can utilize direct access to the underlying memory to transfer blocks of data from or to another unit in the system. The 3D system may include an additional memory control level 1571 and dedicated memory access buses 1569 and 1588 to provide a second port to the memory bank.

Additional processors 1586 may be used to facilitate data transfer from the X-to-TL to the Y-to-TL. These processors can be used for system-level interconnects and leave the base processors for data processing. This approach can help provide system-level integration for 3D systems with 10,000 processing units, each with its own memory and communication links.

There are several options for transferring data, for example, from a TL in the X direction to a TL in the Y direction. Once the system selects the unit where a direction change should occur, the corresponding direction change processor 1586 will control and manage the X to Y connection. Figure 15J illustrates some alternative schematics of this connection. A simple method is to use transfer gate 1591. In some cases, such as when using a frequency on the TL, an amplifier can be added at the signal drop-off point with minimal additional overhead. This circuit functions similarly to a programmable via, which is simple but may not be as attractive if the TL carries multiple data signals modulating multiple carrier frequencies. A method that can be used for such multi-band connections is frequency band allocation. This method of band allocation is exemplified in U.S. Patent 9,806,787 and the paper "TLSync: Support for multiple fast barriers using on-chip transmission lines" by Oh Jungju, Milos Prvulovic, and Alenka Zajic, 2011 38th Annual International Symposium on Computer Architecture (ISCA), IEEE, 2011, which is incorporated by reference in its entirety.

An alternative concept is to have an attenuated signal from the source TL and then use a programmable band pass filter (BPF) to transmit only the selected carrier frequency and then re-amplify the signal using for example a programmable gain amplifier 1592 and then connect the amplified signal to Destination TL. A method that can be used for such a TL programmable connection is to allocate frequency bands for specifying signals used for the TL connection. This may include allocating lower frequency bands for TL connections such as X-Y. Lower frequencies can have lower attenuation and fit better into longer signal paths. This concept can be extended to include lower bands designated as broadcast channels, such as one-to-many. The low frequency band can then be used for longer signal paths, such as X-Y connections, and the mid and high frequency bands can be used for a single TL connection. In some cases, such as when using a frequency on the TL, the signal drop-off point can be the amplifier with minimal overhead. The amplifier or BPF and transmission gate can be designed together, allowing each direction (X-to-Y and Y-to-X) to be used one at a time, but still taking advantage of the bidirectionality of the TL waveguide.

Another alternative is to first reconstruct the data stream from the attenuated signal of the source TL, then remodulate the data with the target carrier frequency 1593 and attenuate it to the target TL. In this way, the system can select a different carrier for the first TL and a different carrier for the second TL. A higher level of flexibility can be achieved through more support circuitry for the direction change processor 1586, which can include full data drop and storage followed by full data transfer. In this way, when data is transmitted from the first TL to the second TL connection, the carrier frequency and data time transmission slot can change, where the data is demodulated and routed as digital data. The digital data can include short periods of time commonly known as queues. storage. This is very common in data switches and routers, but also in on-chip circuits, as shown in U.S. Patent 7,362,125 and the paper "Cost-effective routing techniques in 2D meshNoC using on-chip transmission lines" by Deb, Dipika et al., Parallel and Distributed Journal of Computing 123(2019):118-129, which is incorporated by reference in its entirety.

Figure 15K is a simplified schematic diagram of the connection between two TLs 15810, 15820. For example, in Figure 15H, any intersection between the X direction TL 1582 and the Y direction TL 1581 may include programmable connection options using the underlying unit processor 1586 to form a data transfer connection. The connection may use techniques as discussed with reference to Figure 15J. The system may include data routing connections that change direction simultaneously or change the TL in the same direction. Taps and conductors 15811, 15821 to and from the data routing processor 15861 may include transistor controlled connections to the TL or other tap/turn technology, such as the V4 discussed previously. Connection lines 15811, 15821 are for the signal and its return, and for the differential pair TL for both signals and their return.

As shown in Figure 15E, the preferred interconnect technology depends largely on the length of the route or the distance between connected elements. For the 3D systems described in this article, X-Y connections can utilize wires with RC for relatively short interconnects such as RF-I between adjacent cells (0.2 to 2mm), across longer routes (1 to 300mm) and optical interconnects for longer routes (over 100mm). The use of these techniques may include the use of hybrid techniques, such as using RF signals to modulate optical signals, as proposed in US Patent 10,502,987, which is incorporated herein by reference in its entirety.

X-Y connections can utilize multiple tiers, each supporting one of the connectivity technologies. Much of what is incorporated herein by reference suggests RF-I between nodes as well as wired (RC) connections to these nodes. Figure 15L shows a modified block diagram of Figure 151 where 4 units are aggregated to communicate with the RF-I fabric. Processor 15830 with the function of four vertical buses connecting four aggregation units connected to one of the overlapping TLs to transmit data to or from another unit in the system . Processor 15840 may be a direct memory access processor (DMA). Such a processor can utilize direct access to the memory of the four underlying units to transfer blocks of data from or to another unit in the system. Additional processors 15860 may be used to facilitate data transfer from an X-oriented TL to a Y-oriented TL, or between TLs with the same direction with different capabilities (e.g., long connections and short connections). Engineering of 3D system X-Y interconnects may include using wires to aggregate cells in 2x2, 3x3, 4x4 or other configurations before moving to TL connections. This kind of engineering can take into account the size of the unit and the performance cost of adding drop-off/pick-up on the TL. 3D systems can include a combination of these technologies, including slave cells and slave cell aggregator connections to the TL.

In addition, through the standardized structure of the vertical busbar positions, mixing and matching of elements in the 3D system can be used. Hierarchies of processors and memory can utilize different levels of X-Y connections or different levels of memory, etc. The modularity of the concept can be expanded to support different 3D system sizes by cutting according to application needs. The 3D system architecture presented here can support X-Y and Z modularity and customization.

The interconnect layer can also be connected to its own built-in self-test and monitor circuitry, as large RF wires can have transient or permanent internal errors. The interconnect layer connected to the built-in self-test can further include training modules and on-chip termination. Terminating resistors for impedance matching in transmission lines can be located inside the silicon chip. The impedance value of the terminating resistor can be further fine- and coarse-tuned to account for process, voltage, and temperature variations. The training and calibration circuit determines the optimal termination impedance to reduce signal reflectivity and compensate for variability. These monitor circuits can send test messages and, in the event of an error message, redirect traffic away from the failed line. Redundant interconnect lines may be available because the RF hierarchy will contain sufficient area to accommodate duplication. Since these large wafer-scale systems require longevity, these fault-tolerant tests and redundancies will extend their lifespan and allow for graceful degradation techniques.

Traditionally, the light field area of the photomask used for the photolithography step is the same throughout the process, which determines the maximum size of the chip. To implement TL across multiple chips, the light field area of the reticle used to process the TL can be larger than that of the processor chip 15902 due to the relatively low resolution requirements of the TL features. Figure 15M shows an example of an oversized reticle 15904. In addition, multiple oversized photomask TL patterns can be spliced to form the pattern of the entire TL layer. Figure 15M shows a large area chip 4 times the size of the reticle. In addition, one-to-one contact aligners or nearly non-contact aligners can be used for lithography of TL.

The TL layer can be processed at the same fab as the processor wafer; alternatively, the TL layer can be processed at a different fab, such as a dedicated packaging fab. This TL layer processing can be done as part of the redistribution layer (RDL) processing. TL implemented using dedicated packaging fabs can provide thicker metals and dielectrics than those found in logic or RF lines. In this case, organic resin such as polyimide can be used as the dielectric. Thick resin can help isolate the TL layer from the silicon substrate. As a result, the increased Q factor can reduce power consumption and reduce transmission attenuation. This type of TL processing is proposed in: Balachandran, Jayaprakash et al., “Expanding on-chip routing levels with wafer-level packaging concepts,” Proceedings of the IEEE 2004 International Conference on Interconnect Technology (IEEE Cat. No. 04TH8729), IEEE, 2004; Balachandran , Jayaprakash et al., "Wafer-scale packaging interconnect options," IEEE Transactions on Very Large Scale Integration (VLSI) Systems 14.6 (2006): 654-659; Itoi, Kazuhisa et al., "Wafer-level chip-scale integration for silicon RF applications." "On-Chip High-Q Spiral Cu Inductors Embedded in Packages," Abstracts of the 2004 IEEE MTT-S International Microwave Symposium (IEEE Cat. No. 04CH37535), Volume 1, IEEE, 2004; Lahiji, R.R. et al., "Multilayer Polyethylene Low-loss coplanar waveguide transmission lines and vertical interconnects on -N,” 2009 IEEE Symposium on Silicon Monolithic Integrated Circuits in Radio Frequency Systems, IEEE, 2009. All the above content is incorporated by reference in its entirety.

In one embodiment of the invention, a hybrid interconnect across devices is proposed. As shown in Figure 15N, hybrid multi-chip interconnect uses direct RC interconnects to connect adjacent chips through scribe lines 15912 and multi-layer overlapping TL interconnects to connect separate chips 15910. The RC part may be referred to as the scribe line interconnect and the TL part may be referred to as the on-chip interconnect 15918. Scored interconnects connect short distances, such as less than 1 mm, for which ordinary RC interconnects may be effective. Striped link protocols can include high-speed parallel interconnects. On-chip interconnects can extend greater than 10mm, and multiple chips can be grouped, such as 4 chips 15914 as shown in Figure 15N or more than 4, as units of TX/RX for TL interconnects 15916. TL link protocols can use high-speed SerDes such as DDR memory bus, USB and PCIe.

In another embodiment of the invention, a multi-layer TL is proposed. 1, 2, 3, 4, 6 or x64 lanes per channel and long haul connections with thicker conductors and larger spaces between conductors 15922 can use fewer TL lanes such as xl or x2 lanes. Figure 15P shows a cross-sectional view of the multi-layer TL, showing two levels of the X-direction TL and the Y-direction TL. Each of the various technologies, especially TL and photonics, can also be arranged in different topologies depending on the needs of the system or subsystem, including high-radix routers. These routers can be included in the communications layer with available zones to amplify and direct the signal. These topologies serve as possible alternatives to direct X-Y routing. These long-distance TLs as shown in Figures 15P and 15S may use additional NoC-type topologies, such as a 3D torus as shown in Figure 15U or a butterfly topology as shown in Figure 15V, but other network topologies may also be included. Research on these networks can be found in the following previous literature: "Performance Analysis and Optimization of Homogeneous Multicore Systems Based on 3D Torus Network-on-Chip" by Jiao et al., IEEE NEWCAS 2010; and "Flat Butterfly Topology for On-Chip Networks" by Kim et al. ”, IEEE Computer Architecture Letters 2007, all of which are incorporated by reference in their entirety. Traditionally, semiconductor processors and so-called wafer-scale engines have been rectangular. Figure 15Q shows an example of the wafer-scale engine proposed in I. Cutress’s “Hot Chip 31 Live Blog: Cebebras’ 1.2 Trillion Transistor Deep Learning Processor,” which is incorporated herein by reference. However, to save the wasted area shown in Figure 15Q, one could consider using a non-rectangular 3D system in which multiple chips are connected via on-wafer TLs. As shown in Figure 15R, even for large-area chips, the entire circular wafer can be used, and half or quarters of the wafer can be used without losing any chip near the edge.

The TL hierarchy can be placed below and/or above the processor and memory hierarchy as shown in the figure. 15S uses the hierarchical transmission technology described in this article. This use of circular wafers or portions of circular wafers further benefits from the use of small cell sizes such as approximately 200x200μ2 or approximately 150x150μ2. The use of arrays of relatively small cells further improves the utilization of circles with rectangular cells. Additionally, the use of wireless interconnects, as shown herein with reference to Figure 16F, where mating wafers provide connections between the 3D system and other systems, and enables full use of the wafer round shape without the need to waste wafers associated with square end product shapes part.

Recently, a technology that transcends wafer-level packaging (WLP), namely panel-level packaging (PLP), is emerging to provide lower-cost fan-out. In PLP, a large square panel or LCD substrate is used. Various panel areas are provided; however, the smallest panel size is still larger than the size of the 300mm wafer, as shown in Figure 15T. Multilayer TLs spanning multiple chips can be fabricated on a PLP substrate, and then the entire CMOS wafer can be transferred and bonded to the PLP substrate.

The transformation of data flows from one TL to another may be part of the overall system data routing. It can be part of a change in direction, such as from X to Y (or from Y to X), or moving in the same direction but from long TL to short TL (or from short TL to long TL). As shown in Figure 15F, TLs can be designed at different spacings 1555 with a trade-off between density and attenuation. 3D systems can be composed of TLs designed to support data transmission over long distances, such as Federal Highway For highways, there is the option of transitioning to a shorter TL, such as a state highway, and then once converted back to the voltage type signal of the RC line, the connection is just like a local road. This concept may include conversion to and from optical waveguide 1547 for very long data transmission. Another conversion can utilize a structure such as 1593 to move data from one frequency carrier to another.

Other aspects that RF-I may include are the use of low-frequency carriers to support, for example, system management including route distribution. As we can see from the frequency versus attenuation plot 1555 (part of Figure 15F), low carrier frequencies can have very low attenuation, making them ideal for system control and broadcast functions. Therefore, in such a 3D system, the source unit can broadcast data by using the TL in one directional column as the source, and then broadcast the data using the orthogonal TL of each row. For example, these can be structured as system-wide broadcasts or selective broadcasts by defined areas.

For broadcasts, a TL network can leverage its broadcast capabilities to quickly spread packets in the X direction and then fan out in the Y direction. The same operation can also be done in reverse for all-to-one, all-to-all, or other multicast operations where multiple senders are sending related messages (such as acknowledgment messages or barrier synchronization). As shown in Figure 15G, this can be achieved with existing structures.

Messages can be aggregated at the processor or network interface at the RF level and then sent as combined messages to reduce congestion and increase throughput of large multicasts. Since the nodes sharing the X direction TL 1582 in Figure 15H respond to many-to-one messages, the interface between the X and Y TLs 1581 and 1582 can keep the messages in buffers. After some time, the buffer can combine the responses into a single larger message and send it as one message in the Y direction 1581, thus responding with less congestion. The buffer can be in the interface as part of the amplification and routing of the system 15861, as shown in Figure 15K.

This can be accomplished using a software control mechanism or a routing protocol that can be built into the hardware. The many-to-one level may be a standalone level, such as 1579 of Figure 15G, or integrated as part of the RF-M level 1570. The use of aggregation in large supercomputer-scale interconnection networks has been demonstrated at macroscale: Chen et al., “Looking Under the Hood of The IBM Blue Gene/Q Network,” IEEE SC 2012; and Bui et al., “Using Compression, Topology-Aware Data Aggregation, and Scalable Parallel I/O on the Blue Gene/Q Supercomputer for Subfiles," and Network-Based Processing 2014, all of which are incorporated by reference in their entirety.

Traditional on-chip TL uses coplanar waveguides. More techniques have been developed and can be engineered as improvements. In the paper "Sub-terahertz characteristics of CMOS on-chip transmission lines" by Feng Zijun, Nan Li, and Xiuping Li, 2015, IEEE\HT-S International Conference on Numerical Electromagnetics and Multiphysics Modeling and Optimization (NEMO), IEEE, 2015 (full text available (Incorporated into this article by reference), the TL, known as grounded coplanar waveguide (GCPW), shows attenuation as low as 0.06dB/mm, 0.08dB/mm, and 0.04dB/mm, supporting sub-terahertz (over 100GHz) carrier connections . In LaRocca, Tim, Jenny Yi-Chun Liu, and Mau-Chung Frank Chang, "60GHz CMOS Amplifier, Compact Design Using Transformer Coupling and Artificial Dielectric Differential Transmission Lines," IEEE Solid-State Circuits Magazine 44.5 (2009): 1425-1435 ( Incorporated herein by reference in its entirety), it was proposed that artificial dielectric strips provide substrate shielding and increase the effective dielectric constant to 54 for further size reduction. Additional changes in the mix between CPW and CPWG result in Shielded CPW (SCPW). SCPW does not have a solid ground plane beneath the signal path, but rather a grid of metal segments connecting two coplanar ground paths, acting as a shield, in "Parametric Analysis of Millimeter-Wave Transmission Lines in nm CMOS and by Lourandakis, Errikos et al. Design Guide,” IEEE Transactions on Microwave Theory and Technology 66.10 (2018): 4383-4389, which is incorporated by reference in its entirety. A new comb-shaped slow-wave grounded coplanar waveguide (comb-S) is proposed in Bjomdal, Oystein. Millimeter wave interconnects and slow-wave transmission lines in CMOS. - Another variant of GCPW) with an effective dielectric constant of 140 and an 83% reduction in size compared to conventional CPW. Another approach supports ultra-slow wave on-chip coplanar waveguide (CPW) transmission lines with inter-digit loading stubs and floating bars, which offer smaller size and lower loss than traditional on-chip CPW transmission lines : Arigong, Bayaner et al., "Ultra-slow wave transmission lines in CMOS technology", Microwave and Optical Technology Letters 59.3 (2017): 604-606 (incorporated into this article by full citation)

Another technology that can be integrated into such 3D systems is “one-to-many” interconnects utilizing surface wave interconnects, as detailed in the following publication: Karkar, Ammar, and Alex Yakovlev, “Utilizing Wired Surface Wave Interconnects. Architecture to Enable One-to-Many Services in On-Chip Networks” and Karkar, Ammar et al., “A Multicast Architecture for On-Chip Networks Using Hybrid Wired and Surface Wave Interconnects”, IEEE Transactions on Emerging Topics in Computing 6.3 (2016): 357- 369, all contents of which are incorporated herein by reference in their entirety. As mentioned above, surface waves (SW) or sky-neck surface waves are non-uniform electromagnetic (EM) waves supported by metallic dielectric surfaces. The designed surface is a waveguide that traps EM signals in a two-dimensional medium rather than in three-dimensional free space. Therefore, the E-field attenuation rate in SWI from the source along the boundary level is approximately (1/√d), which makes the SWI technology attractive in addition to the TL interconnect level. The one-to-many layer can be an independent layer, such as 1579 in Figure 15G, or it can be integrated as part of the RF-M layer 1570. Another option to add broadcast capabilities to such 3D systems is to use wireless technologies as proposed in Abadal, Sergi et al., "Broadcast-supported large-scale multicore architectures: a wireless RF approach," IEEE micro35.5 (2015 ): , which is incorporated herein by reference in its entirety.

3D system X-Y interconnects can include multi-layer electromagnetic interconnects such as RF-I using TLs of varying size lengths and orientations, SWI levels for broadcast portions of X-Y connections, and optical waveguides for longer portions. This heterogeneous X-Y connection can support large chip/device areas, such as wafer-level integration of large array units of 3D systems connecting hundreds of thousands or even millions of computing elements. Management of the system may utilize elements designated as system managers or distributed computing networks. Technologies developed for server farms can be used to help organize and operate such 3D systems.

Multiple interconnect technologies can be used in a collaborative manner to improve overall system connectivity. This can be effectively exploited in the 3D system described herein, which can be used to add 3D system stacking levels optimized to support different interconnect technologies, such as RF, plain wire, SWI, and optical interconnects. This hybrid approach is proposed in: Krishna, Tushar et al. “NoC with near-ideal fast virtual channels using global wire communication” 2008 16th IEEE High Performance Interconnect Symposium, IEEE, 2008; Oh Jungju , "Flow control between low-latency switchless TL rings and high-throughput switching on-chip interconnects" by Alenka Zajic and Milos Prvulovic, Proceedings of the 22nd International Conference on Parallel Architecture and Compilation Technology, IEEE, 2013, all of the above It is incorporated herein by reference in its entirety.

In recent years, the surface wave concept of RF-I has been further developed. This led to the development of "transmission and detection of surface plasmon polaritons (SPP)", a special TM polarized surface wave localized at the metal/dielectric interface. By artificially designing periodic subwavelength metal strips on metal wires, or called spoofing SPP, TM mode surface wave signals can be established and propagated between metals and dielectrics in the sub-terahertz region, as proposed by Liang Yuan, "D-band surface wave modulator and signal source with 40dB extinction ratio and 3.7mW output power in 65nm CMOS" et al., ESSCIRC 2018 - IEEE 44th European Solid-State Circuits Conference (ESSCIRC), IEEE, 2018; Liang Yuan et al. "Sub-terahertz surface plasmon transmission lines on CMOS mode converter chips" Scientific Reports 6 (2016): 30063; "Energy-efficient low-crosstalk sub-terahertz I/O for surface plasmon interconnects in CMOS" by Liang Yuan et al. ", IEEE Transactions on Microwave Theory and Technology 65.8 (2017): 2762-2774; Joy, Soumitra Roy et al. "Spoof Plasma Interconnect Communication Beyond RC Limits" IEEE Transactions on Communications 67.1 (2018): 599-610; Qi "Low-loss BiCMOS deception surface plasmon transmission lines in the sub-terahertz region" by Zihang, Xiuping Li and Hua Zhu, IET Microwaves, Antennas and Propagation 12.2 (2017): 254-258; "With reduced Linewidth and enhanced field-limited Spoof surface plasmon transmission lines", International Journal of RF and Microwave Computer-Aided Engineering (2020): e22276; Chen Qian et al.'s "Utilizing field-limited slow-wave transmission lines to achieve multi-channel FSK inter-chip/ "Intra-Chip Communication", 2020 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, 2020; "False Surface Plasmon Transmission Lines with High Isolation and Low Propagation Loss" by Singh, Surya Prakash, Nilesh Kumar Tiwari, and M. Jaleel Akhtar ” Applied Optics 59.5(2020):1371-1375, all contents are incorporated by reference in their entirety. These TLs, intermediate between metallic conducting TLs and dielectric conducting waveguides, offer an attractive option with the relative ease of on-chip integration of RF-I and the low crosstalk of optical interconnects. These spoof SPPs may use conventional coplanar strip (CPS) guidance to feed signals in and out, as described in detail above by the reference technology.

These spoofing SPPs can be designed to support sub-terahertz carriers or lower frequencies, as published in "Low-loss spoofing surface plasmon slow-wave transmission lines with compact transitions and high isolation," published by Kianinejad, Amin, Zhi Ning Chen, and Cheng Wei Qiu, IEEE Transactions on Microwave Theory and Technology 64.10 (2016): 3078-3086; "A novel three-dimensional integrated deception surface plasmon transmission line" by Shen Sensong et al., IEEE Access 7 (2019): 26900-26908; and Ye Longfang "Efficient and low-coupling deception of surface plasmons enabled by V-shaped microstrips" et al. Optics Letters 27.16 (2019): 22088-22099, all of which are incorporated by reference in their entirety.

3D system X-Y interconnects and connections on system networks can leverage knowledge and tools developed for large integrated computing systems such as server farms. Other work includes work on known network-on-chip-NOCs, such as "Designing single-cycle long links in hierarchical NOCs" by Manevich, Ran et al., Microprocessors and Microsystems 38.8 (2014): 814-825; "Threshold-based routing algorithm for RF NoC OFDMA architecture" by Lahdhiri, Habiba, Jordane Lorandel, and Emmanuelle Bourdel, 2019 14th International Symposium on Reconfigurable Communication Center Systems-on-Chip (ReCoSoC), IEEE, 2019; Spyropoulou, Maria, et al. "Towards 1.6T Data Center Interconnect Technologies: A TWILIGHT Perspective" by Al., Journal of Physics: Photonics 2.4 (2020): 041002; and "A Design Exploration and Performance Analysis Framework for RF NoC Manycore Architectures" by Lahdhiri, Habiba et al., Journal of Low Power Electronics and Applications 10.4(2020):37, all contents are incorporated by reference in full.

The said industries are continuously advancing communication technologies to support better use of communication media such as TL to enable higher data transmission per second with lower data power per bit. Advanced data modulation techniques have been developed for this purpose, such as: Du, Jason Y.'s paper "RF Modulated Signal Interconnects for Memory-to-Processor and Processor-to-Processor Interfaces: An Overview", arXiv preprint arXiv: 1612.0652(2016); Hamieh, Mohamad et al., “Sizing the Physical Layer for Communication Within RF Chips,” 2014 21st IEEE International Conference on Electronics, Circuits, and Systems (ICECS), IEEE, 2014; and Chang, Mau Chung F et al., "Multiband Radio Frequency Interconnect (MRFI) Technology for Next-Generation Mobile/Airborne Computing Systems," University of California, Los Angeles, 2017, all incorporated by reference. This advanced modulation technology can be used for X-Y connections in 3D systems. The TL used for X-Y connections may have multiple drop points. Therefore, when the TL is running on the individual units, it can have connections to allow data to be transferred to or loaded from the underlying units. Multiple TLs can run in parallel on the same row or column of cells and connect to all or part of the underlying cells. The connection to the underlying unit can be divided among TLs running in parallel to share the data transfer load between these TLs running in parallel. Modulation techniques can allow multiple data channels to operate on the same TL without interfering with each other. These modulation channels can be allocated as part of the 3D system setup process, or dynamically allocated as part of system operation. Other communication technologies may be used to manage this allocation as part of the 3D system control structure. These can include using broadcast techniques or utilizing low frequency bands to transmit control information to support better overall X-Y connectivity.

Multi-band communication in TL can also be used for congestion management. Routers can be designed to include traffic monitoring and adaptive routing algorithms. If traffic congestion is high on a link, one or more bands can be reserved for these routers to ensure communication moving forward. Elbrahimi et al., “HARAQ: A Congestion-Aware Learning Model for Highly Adaptive Routing Algorithms in Networks on a Chip,” International Symposium on Networks on a Chip, 2012 (incorporated into this article by reference), includes methods for learning from traffic patterns and responding accordingly Adjusted algorithm. Figure 15W illustrates this congestion-aware routing as messages avoid high-congestion areas. In a TL network, these X and Y directions will look like Figure 15K.

Alternatives to 3D systems may include adaptive allocation of channels within the TL. Therefore, a unit can use more channels of the TL to transmit at a higher data rate, or leave some channels to other units and reduce its own data rate during selected time periods. To illustrate some of these ideas, we can refer to Figure 150, which is from DuJieqiong et al.'s paper "28mW 32Gb/s/pin 16-QAM single-ended transceiver for high-speed memory interfaces" 2020 IEEE VLSI Symposium, IEEE , Figure 1 of 2020, which is incorporated herein by reference. Figure 15Q shows 16 QAM modulation circuits combining two QPSK modulation sub-circuits. In a 3D system, the data routing processor 15861 may use the combined signal 15926 to drive one TL, or have a programmable option to use part of the modulation signal 15922 for one TL and another part 15924 of the other TL, both TLs can run in parallel, or be designed with one in the X direction and the other in the Y direction. 3D systems with multiple TLs covering the same unit can take advantage of advanced signal modulation techniques produced by relatively complex modulation circuits that share resources and drive multiple TLs. For example, this advanced modulation technique can utilize a clock circuit such as the one labeled CCK 15928 in Figure 150. The CCK clock can be shared by multiple units or even across the entire 3D system X-Y connection to support advanced and efficient data modulation techniques for better X-Y connections. The distribution of clock signals can be achieved by using traditional clock trees, advanced types such as harmonic resonant clocks, or by using some TL structures.

An additional alternative is to structure the XY interconnect as a hierarchy with at least 3 steps. It is first decomposed into X direction and Y direction, then into global lines, and finally into local lines. For example, a 3D system with a rectangular shape of 259.2x 259.2 ^mm has an array with a cell size of 0.2x0.2 ^mm , resulting in an array of 1296 by 1296 cells. The advantage of the proposed XY interconnection hierarchy is the reduced number of drop locations and associated attenuation. Therefore, the global TL can have 36 drop-off locations from which data can be transferred to the local TL which has 36 drop-off locations to the destination unit, 36x36=1296. Global TL can be constructed with thicker and/or wider metal to have minimal attenuation, effectively covering the entire length of the 3D system - 259.2mm. The structure shown in Figure 15J can be utilized from drop to drop, and signal re-buffering can also be provided if engineering trade-offs and considerations require it. This layered XY connection can be complementary to other XY connection structures proposed in this article, which will be designed for specific 3D system requirements.

Another consideration for such a 3D system is the removal of heat from upper layers, such as the heterogeneous integrated stack of layer and M-layer 1404 in Figure 14A. U.S. Patent 8,674,470, which is incorporated herein by reference in its entirety, teaches the use of power lines to provide a heat removal path from a level in a 3D structure to the bottom or top surface where heat can pass through the air or fluid conduction removal. This can be an additional feature of the unit's vertical struts, such as struts for vertical busbars. For example, these struts, such as vertical struts 1414 in Figure 14B, can be designed to provide good power conduction to specific levels and to remove heat from levels where heat removal may be required. These heat dissipation pillars can be considered as "thermal vias". These pillars can be designed to have a good thermal path to the cooling substrate 1401 of Figure 14A herein while being electrically insulating. Methods of forming and utilizing thermally conductive contacts without being electrically conductive are, for example, as shown in reference to at least FIG. 6 of US Pat. No. 8,674,470. In a similar manner, the pillars may be thermally connected and electrically isolated up to and including the top layer, which may include a heat sink structure for removing heat by air or fluid conduction. In one embodiment, these vias can be designed in a way to mitigate or even shield electromagnetic interference.

Additionally, thermal isolation techniques, methods, materials and structures, such as those disclosed throughout U.S. Patent 9,023,688, may be used with the 3D systems and devices disclosed herein. The above-mentioned U.S. patents and their entire contents are incorporated herein by reference.

Figure 16A shows an X-Z 1602 side cutaway view of a 3D system similar to that disclosed in Figure 14E herein, including an upper layer 1604 of computational logic. Thermal isolation layer 1605 may be used to prevent heat from computing logic 1604 from substantially reaching the memory stack 1603 disposed therebelow, and heat sink 1606 may be used to remove heat to and from the device/system. Typically conductive power lines (not shown) may be partially thermally connected and electrically isolated relative to the heat sink 1606 to assist in removing the formation and operating heat generated by the internal stack 1603 from the top, as well as channeling the heat through its liquid microchannel cooling 1610 Remove to bottom substrate 1601.

Figure 16B shows a similar 3D system where the upper layer of computing logic has its own liquid cooling substrate 1614, which may include power delivery lines and trench capacitors in a similar manner to the bottom substrate 1601. The liquid cooling substrate 1614 may be part of the silicon interposer, or be fabricated separately and bonded into the 3D system, or even monolithically integrated with the base of the 3D system's silicon substrate.

The motivation for ultra-scale integration may suggest adding more computational layers to 3D systems. However, this level of computing may generate too much heat for powerline networks to remove. It may be necessary to embed the liquid levels with liquid microchannel cooling inside the 3D stack, rather than just the bottom and top, as shown in Figure 16B. Microchannel cooling can be fluid channels for coolant or heat pipes. These microchannels can be further coupled with traditional passive cooling, such as finned heat sinks and ventilation slots. In one embodiment of the invention, the microchannels may include forced convection devices such as fans and nozzles. Coolant can be pumped in a circuit with heat exchangers and cold plates outside the 3D system.

The challenge is to manage system vertical (Z-direction) connections through thick substrates that can support microchannel cooling, as described in Colgan, Evan G. et al., “Practical Implementation of Silicon Microchannel Coolers for High-Power Chips” ” IEEE Transactions on Components and Packaging Technology 30.2 (2007): 218-225 (incorporated herein by reference). Such a substrate may be at least 50 microns thick and may require TSVs of about 5 microns in diameter to pass through. Pillars for vertical busbars can use through-layer vias less than 1 micron in diameter, also known as nano-TSVs. One way to manage this vertical connectivity challenge could be to modulate the signal via TSV, for example by using RF interconnects or optical interconnects similar to those proposed in this article for X-Y connectivity.

Figure 16C shows a side X-Z 1602 cross-sectional view of a 3D system with an embedded microchannel cooling substrate 1624. The substrate may include TSVs 1622, which may be used to connect power lines through the substrate and carry electromagnetic waves that modulate data. Layers below 1623 and above 1626 may include circuitry for controlling, generating, and detecting electromagnetic modulated data propagated through TSV 1622. The top layer may include additional X-Y electromagnetic connections 1628 or connections to external devices that may support wireless connectivity.

Transporting data input and output (I/O) of a 3D system can utilize many technologies, such as routing and bonding techniques. The use of wireless technologies may be an attractive option to exploit the layer transport concept proposed in this paper. Therefore, the upper layers 1626, 1628 may have M levels designated for system-level IO. Advances in mobile technologies such as G5 have promoted the rapid development of on-chip RF circuits. Multiple papers propose the use of wireless technologies for network-on-chip ("NOC") applications, as presented in: "Wireless NOCs as an interconnect backbone for multicore chips: Prospects and challenges" by DebSujay et al. IEEE Circuits and Systems Emerging and Journal of Selected Topics 2.2 (2012): 228-239; "Structure and Design of Multi-Channel Millimeter Wave Wireless NoC" by Yu Xinmin et al., IEEE Design and Test 31.6 (2014): 19-28; Mineo, Andrea et al. “Exploiting Antenna Directivity in Wireless NoC Architectures,” Microprocessors and Microsystems 43 (2016): 59-66; Kim, Ryan Gary, et al. “Wireless NoCs for VFI-Enabled Multicore Chip Design: Performance Evaluation and Design Tradeoffs ” IEEE Transactions on Computers 65.4 (2015): 1323-1336, all patents and papers mentioned above are incorporated herein by reference. Some have suggested using TL and/or hybrid system connections of waveguide and wireless, such as the paper "Resilient 2D Waveguide Communication Structures for Hybrid Wired-Wireless NoC Design" by Agyeman, Michael Opoku, et al. IEEE Transactions on Parallel and Distributed Systems 28.2(2016):359-373, incorporated herein by reference. These wireless connectivity technologies can also be used to connect 3D systems to external devices that provide system-level I/O. This may also include plasmonic technologies presented in the paper "Plasmonic pathways for integrated wireless communications for sub-diffraction limited signals" by Zhang, Hao Chi et al., Light: Science and Applications 9.1 (2020): 1-9, All of the above are incorporated by reference in their entirety. Extending the use of wireless, such as that provided for the NOC, to connect the 3D system to external devices may be attractive as it can share the resources of the NOC and connections to external devices. Figure 16F illustrates such a concept. 3D system 1662 may be placed close to connecting structure 1664 as appropriate (determined by engineering considerations and trade-offs). There can be dozens or hundreds of wireless channels connecting the 3D system to external connectivity devices. This parallel connection can enhance the overall system by providing extensive and parallel distributed connections to the 3D system. Connectivity fabric 1664 may use fiber optics 1666 to connect to upstream data sources. Depending on the engineering and business trade-offs, the connection structure 1664 may be constructed using similar techniques as the 3D system, or utilizing traditional PCB-type integration techniques. The 3D system I/O structure of Figure 16F can be applied to other types of wireless connections, such as optical connections through the use of diode lasers, and can include high-level signals such as orbital angular momentum (0AM). This can be used for either RF type or optical type wireless connections. In the recent paper "Photonic Quantum Hall Effect and Multiplexed Light Sources with Large Orbital Angular Momentum" by Bahari, Babak et al., Nature Physics (2021): 1-4 (incorporated herein by reference), An "unlimited" data capacity using 0AM is proposed. Other techniques may also be used to exploit the proximity between the structures 1662, 1664 forming such wireless connections to increase channel capacity.

For electromagnetic modulated optical types, vias can be made optically clear with or without appropriate oxide filling. Similar optical via connections have been proposed in US Patent Nos. 7,203,387 and 8,916,910, which are incorporated herein by reference.

For RF type electromagnetic modulation, the vias can be copper filled, or a quasi-coaxial TSV transmission line using conformal sidewalls filled with metal shell, then inner oxide, then metal. This structure can be achieved using ALD or other types of conformal deposition. RF type TSVs are known in the art and are proposed, for example, in U.S. Patents 8,618,629, 8,759,950, 8,916,471 and Bleiker, Simon J. et al.'s paper "High Frequency Applications Fabricated by Magnetic Assembly of Gold-Coated Nickel Wires" High aspect ratio through-silicon vias," IEEE Transactions on Components, Packaging, and Manufacturing Technology 5.1 (2014): 21-27; Vitale, Wolfgang A. et al., "Fine-pitch 3D-TSV-based TSVs for RF MEMS applications. High Frequency Components," 2015 IEEE 65th Electronic Components and Technology Conference (ECTC), IEEE, 2015; Ebefors, Thorbjbm et al., "Development and Evaluation of RF TSVs for 3D IPD Applications," 2013 IEEE International 3D System Integration Conference (3DIC), IEEE, 2013. The contents of all above-mentioned patents and papers are incorporated by reference in their entirety.

Another option is to build special M levels for cooling substrates inserted inside the 3D stack. Such substrate M levels can utilize conventional TSVs with redistribution layers that connect these large TSVs to relatively smaller TSVs between cells for per-cell vertical busbars. For a cell size of about 200μm X 200μm, 100 large TSVs 5μm

Figure 16D shows an two).

Figure 16E shows a side X-Z 1698 cross-sectional view of substrate M layer 1650 formed by adding a top redistribution layer 1654 to the hybrid bonding structure of Figure 16D. Per unit vertical bus pins/pads 1632, 1652 use TSV 1646 to connect the vertical bus through the cooling substrate. A cutting layer 1656 may be used to separate the substrate M level from the carrier substrate 1658.

Using such a substrate M hierarchy, 3D systems can include multiple compute and memory stages, with X-Y connectivity stages in between, while system heat can be managed with liquid cooling.

Figure 16G shows an X-Z 1698 side cross-sectional view of the 3D system with additional coolant distribution structure, and Figure 16H shows an X-Y 1699 cross-sectional view. The arrows in Figures 16G and 16H illustrate the flow direction of the coolant or coolant. Similar techniques, such as oxide-to-oxide bonding, are used to bond thicker substrates 1674, which may be made from glass-type materials or silicon wafers. The thicker substrate 1674 may be formed with Y-wide tunnels 1672, 1676, with widths and depths of, for example, sub-millimeter, several millimeters, or even tens of millimeters. The XY dimensions of the thicker substrate 1674 can be larger than the rest of the 3D system so that the thicker substrate can accommodate the 3D system with sufficient thermal area margin/overlap at its edge areas. The Y-wide tunnel 1672 may be an odd array, while the other Y-wide channel 1676 may be an even array. Each Y-direction wide tunnel group 1672 and 1676 can be connected into one tunnel near the edge of the 3D system, as shown in Figure 16H. Each Y-direction channel group shares its respective inlet or outlet of the external coolant circulation system. These tunnels 1676, 1672 serve as main pipes for circulating cooling fluid to the X-direction tunnels within the silicon (eg, 1670, 1610, and 1624) and are designed to have several times the fluid transfer capacity. Therefore, although the silicon tunnel is embedded near the active devices of the 3D system and is designed to have low thermal resistance from the active transistors, the thicker substrate 1674 is designed to support overall higher cooling cycles to transfer heat Removed from intra-silicon tunnels such as 1670, 1610, 1624. Some of the tunnels 1676 will be used to introduce 1678 cooling liquid, such as water, through dedicated pipes 1680 to the X-direction tunnels 1670 of the base of the 3D system. And some channels 1672 will be used to lead out the heat transfer liquid. This multi-level liquid distribution network can be used in large-area 3D systems to achieve effective cooling and heat removal. Such a multi-stage liquid distribution network may include larger tubes 1676, 1672 as a first level supporting thinner tubes 1610, 1624, which are located close to the device stage where heat is generated. The manufacturing process may use techniques known in the art, such as etched deposition and horizontal bonding. Specific designs may take into account specific cooling needs and fluid dynamics considerations that can be devised by those skilled in the art. Detailed design can include layout optimization to further equalize the overall fluid flow in the 3D system. This may include narrowing the intra-silicon tunnel 1670 closer to the edge of the device (near the cold coolant inlet), where the main tubes 1676, 1672 may have higher fluid pressures. This may also include narrowing the main pipe inlet 1676 and widening the main pipe outlet 1672 as it gets further away from the "cold coolant inlet" and closer to the "hot coolant outlet". Making the wide tunnel in the Y direction and the narrow tunnel in the X direction parallel will result in minimizing the temperature gradient within said area compared to a spiral single channel solution or a one-way solution. The use of coolants to cool semiconductor circuits and their use in substrate etching tubes is proposed in Wang Shaoxi et al., "3D Integrated Circuit Cooling with Microfluidics," Micromachines 9.6(2018):287; and C.J. Wu, S.T. Hsiao "Ultra-high power cooling solutions for 3D ICs" et al., VLSIT JFS1-4 (2021), both of which are incorporated herein by reference.

For multi-level 3D systems, it may be necessary to add a level of logic that can be optimized for data movement rather than data processing, for example, as we have seen in the past with Direct Memory Access (DMA) as part of the MCS 85 microprocessor system )Controller Intel 8237. As shown in Figure 16C, such a 3D system could include a water-cooled processor-level foundation covered by M levels of high-speed memory, overlaid by M levels of high-density memory, overlaid by M levels of dedicated data movement, overlaid by M levels of X-Y connections, High-density storage M levels overlap and are covered by M levels of high-speed storage, M levels of additional water-cooled processors, and M levels of device-to-external system connections. Radiator layers can be used to even out the heat between units to reduce local hot spots. Layers of phase change materials can be used to average heat over time to reduce instantaneous heat spikes. Active thermal management can be used by integrating each zone, for example, a per-unit temperature sensor integrated with the temperature control circuitry. Such temperature control circuitry may also control the operation of the unit's processor to prevent overheating. This can be achieved by slowing down the processor clock or reducing the processor supply voltage or changing periodic quiet times or activating a shutdown. These active technologies manage operating speed to avoid overheating. The outlined 3D system integration reduces the overall interconnection of the system and therefore allows for more energy efficient and efficient computing systems. However, power budget and thermal budget limit the operation of 3D systems. These thermal management techniques allow optimized operation within such an overall thermal budget.

Another option is to include multiple steps using simple bonding and thinning, then using TSV processing to form vertical busbar pillars through level stacking and then forming pins/pads for the entire M level for the following hybrid bonding integration step . Figures 17A-17D illustrate this flow. The advantage of this flow is that it saves the formation of internal horizontal pins/pads for this horizontal stack.

Figure 17A shows a side X-Z 1702 cross-sectional view of the bottom level 1706 and the interior level 1704. Each of these levels is constructed with spaced apart cells 1724 and between connections 1722 that may be used for later connection to vertical busbar struts 1726 . Figure 17A also shows two levels of F2F joined to each other, forming a structure 1708 in which the inner level 1704 is flipped over and joined to the base layer 1706.

17B shows the structure after removal, ie, the "cut" of the inner level 1704 of the carrier substrate 1705.

Figure 17C shows the structure after repeating the process five times, forming a layer stack consisting of a base layer and six inner layers bonded on top.

Figure 17D shows the structure after forming through stack vias (TSVs) 1726 and bonding pins/pads 1724. The internal level thickness may be about 100 nm or greater, such as about 0.5 μm, about 1 μm, about 2 μm, about 4 μm, or even greater than about 6 μm. Through stack vias (TSVs) 1726 (through the horizontal stack) can pass through tens of microns, which is common for TSVs in the industry. The metal filling of the vias can simultaneously form connections to the horizontal plane between cells between connection lines 1722 . Such situations are uncommon and require technicians in the semiconductor process to make appropriate adjustments to the process. It is reasonable to expect that such through-stack vias would require larger space between cells 1730 than would be required if the vias were to be formed independently for each level, thus increasing the structure size, however the The simplicity of the process may make it attractive in some applications. The industry is improving etching techniques for such vias and has demonstrated an aspect ratio of 1:20. Therefore, for a horizontal stack of 20 μm thickness, vias with a diameter of about 1 μm can be made.

An important aspect of such 3D systems is the memory technology used for the memory hierarchy. A specific memory technology named 3D NOR-P was proposed at least in US Patent 10,892,016 and US Application 16/483,431 (now US2020/0013791), which are incorporated herein by reference. In the following, some enhancements of this 3D NOR-P technology are given.

Another embodiment of the present invention relates to process steps that can be used to form a Schottky barrier S/D junction. More specifically, a method of accurately forming a silicide layer. 18A-18F are cross-sectional views of XY and XZ sections of an exemplary 3D NOR-P structure showing exemplary process steps.

Figure 18B shows metal deposition of metals such as Ni, Co, Ti, Ta, W, Cu, Pt, Al or alloys thereof for a silicide process. In said step, a very thin metal liner is deposited by a capable method/machine, such as Atomic Layer Deposition (ALD) or Molecular Beam Epitaxy (MBE). The thickness of the atomic thickness controlled metal liner ranges from 3nm to 20nm. For a nominal process, the volume of metal will be deposited so that it is completely consumed and forms silicide, leaving essentially no unreacted metal.

Figure 18C shows the structure after siliconization by annealing. Annealing can be performed by a process that promotes the silicide reaction, such as rapid thermal annealing, laser spike annealing, microwave annealing, or various combinations thereof. By limiting the metal supply and fully depleting the metal, the silicide depth and interface will be uniform. Using thin metal will result in self-limiting reaction properties. After self-limiting silicide, the remaining holes can be filled with other metals to form the majority of s/D, as shown in Figure 18D. One skilled in the art can adapt the formation of this Schottky barrier S/D junction to other memories utilizing the Schottky barrier S/P junctions proposed herein or incorporated herein by reference. structure.

One advantage of 3D NOR-P compared to many other 3D memory structures is the variability tolerance of its architecture. Typically, high aspect ratio etching inevitably involves bending and twisting changes at the top and bottom, as shown in Figure 18G. In the 3D NAND architecture, these changes are directly reflected in program and read operations because the NAND architecture uses a very long shared channel called a "string." Sometimes, the variability is too high and the device is considered defective. In many cases, the variability of each cell will require different operating voltages for different WLs. Additionally, 3D NAND programming requires Incremental Step Pulse Programming (ISSP), which uses multiple iterations of gentle programming operations followed by verification. Such an approach inevitably slows down programming operations. In contrast, the 3D NOR-P architecture uses one channel per corresponding bit unit. Therefore, the variability issue will be much smaller than that of 3D NAND. In one embodiment of the invention, the program and erase voltages can be constant at different WL levels. Additionally, while 3D NAND uses ISSP and ISSE, 3D NOR-P’s program and erase voltage pulses can use only a single pulse, providing faster program and erase operations than 3D NAND.

Another advantage of 3D NOR-P technology with Schottky barrier S/D is related to immunity to source and drain separation variations. Typically, the current-voltage characteristics of standard transistors with degenerate doped (n+)S/D are affected by source and drain separation or gate length. Programming efficiency can also be significantly affected by gate length, since electrons need to travel different channel lengths to be used for programming as hot electrons. In other words, the drain-side injection used for programming is naturally affected by any changes in channel length. Therefore, standard transistor-based NOR flash memories tend to suffer from variability issues. However, the current flowing into the channel in the Schottky barrier S/D is limited by the source barrier. As a result, the Schottky barrier S/D is inherently insensitive to gate length. Proof of Sporea, Radu A., et al., “The Effect of Process Variations on Schottky Barrier Source-Gate Transistor Current,” 2009 International Semiconductor Conference, Volume 2, IEEE, 2009 (incorporated herein by reference) This gate length is insensitive. This advantage is even more important for high-speed applications, where using techniques such as Incremental Step Pulse Programming (ISSP) can slow the write cycle to the detriment of high-speed targets.

Thermomechanical stress may occur during the processing of NOR-P structures. Thermomechanical stress can cause reliability issues such as warping of wafers. This is mainly due to the coefficient of thermal expansion (CTE) mismatch between the materials used in the structure. The major CTE mismatch can occur between metals such as metal S/D and non-metals such as oxides, nitrides and polysilicon. In one embodiment of the invention, empty spaces or voids are intentionally introduced to relieve thermomechanical stress. An example is shown in Figure 18E. The void is located inside the S/D metal pillar. The voids may be formed during metal deposition. When a thermal expansion mismatch occurs, the voids act as stress dampeners because stress will be absorbed.

The modification process above follows the steps in Figure 18B, with additional metal 1854 being deposited as shown in Figure 18F. Accordingly, a first thin metal 1852 may be selected to have high silicide capabilities, such as, but not limited to, nickel (Ni), titanium (Ti), or cobalt (Co), while a second and thicker metal 1854 may be selected to have slower silicide abilities, such as Tungsten (W). Alternatively, the first thin metal 1852 may be selected from metals that react with silicon at relatively low temperatures, e.g., below 400°C, while the second thick metal 1854 may be selected from metals that react only at relatively high temperatures (e.g., high A metal that reacts with silicon at 600°C. Therefore, the post-metal deposition annealing step is performed at a relatively low temperature such that silicide proceeds primarily with the first thin metal 1852 and less with the second thicker metal 1854, resulting in a structure similar to that shown in Figure 18E structure. Through this flow, the presence of the second metal 1854 during annealing can aid in the annealing heat transfer of the second metal to reduce thermal exposure to temperature changes between the various Schottky barrier S/D junction locations. time. This results in a more uniform Schottky barrier S/D junction depth and shape, resulting in more uniform device characteristics up and down the array memory cells.

Another modified process (not shown) is to add a thin amorphous silicon layer between the channel polysilicon and the metal used for silicide to form the Schottky barrier s/D. As the metal silicidation anneal proceeds, the metal diffuses faster along the grain boundaries of the polysilicon channel. This rapid diffusion through grain boundaries can lead to silicide spikes, which can lead to device failure. To avoid direct contact between the metal and grain boundaries, a thin amorphous phase silicon film is inserted between the polysilicon channel and the metal used for silicide. The interface of amorphous silicon may have a thickness ranging from 5 nm to 10 nm, for example. The interfacial amorphous silicon may optionally include n-type dopants, such as phosphorus or arsenic, to help form a dopant-isolated Schottky barrier S/D.

Another alternative is to utilize the concept of MIS-metal insulator-semiconductor contact. Dispersion of dopants may be responsible for the increase in contact resistance variation as device scale shrinks. Very thin interlayer dielectric semiconductors and metals can reduce atomic changes. In conventional approaches to MIS contact, the interlayer oxide not only needs to be thin enough, but also needs to have conduction band edge Fermi level pinning so as not to reduce the contact resistance itself, as in at least US 9,240,480B2, 9,735,111B2 and 9,613,855B1 As stated above, the above content is incorporated herein by reference in its entirety. However, the difference of the present invention is that the Fermi level of the interlayer dielectric can be formed 0.1 to 1.0 eV lower than the conduction band edge in order to maintain the hot carrier generation capability near the Schottky junction. Therefore, referring to Figure 1W, thin oxide layer 152 may serve as a barrier between metallized S/D pillar 154 and the channel. Oxide layer 152 may be about 0.1 nm to about 0.3 nm, about 0.3 to about 0.6 nm, about 0.6 nm to about 1 nm, or even thicker, depending on product, engineering, circuit and design considerations and trade-offs. Thin barriers can help achieve consistent S/D-to-channel barriers and stable Schottky barriers for all cells in the memory array. This approach not only reduces variability due to dopant dispersion; it also reduces variability due to grain boundaries in the metal and polysilicon channels.

The memory capacity requirements of each chip may exceed the memory capacity of the wafer manufacturing technology. To increase the memory capacity of each chip, multiple memory dies can be stacked on top of each other. In one embodiment, as shown in Figures 19A-19E, a 3D NOR-P wafer may include multiple stacks of 3D NOR-P blocks, where each of the 3D NOR-P blocks 1950A, 1950B, and 1950C are in different fabricated on wafers. For example, memory wafers can be stacked using wafer bonding techniques. To this end, each 3D NOR-P block will include bonding pads 1960. Figure 19A shows an example of stacked 3D NOR-P blocks. The S/D lines are vertically aligned such that each vertically stacked S/D line shares the same BL and SL address. However, in this case, WLs in one wafer block should not share corresponding WLs in another wafer block. Therefore, steps of WL contact are necessary for all individual WL layers. In order to achieve individual/unique WL addresses for all individual WL layers, an example of forming a wafer block ladder WL is given below, where the ladder WL is also formed within the wafer block, as shown in Figures 19B-19E. In the following, the steps WL within the wafer are called local WL steps. The staircase WL connecting the staircase WL of one wafer and the staircase WL of another wafer is called a global WL staircase.

In one embodiment of the invention, each local ladder WL contact is connected to its own vertical jump metal plug 1970 via a local ladder jumper 1980, as shown in Figure 19B. Jump Metal Plug 1970 penetrates essentially the entire height of the NOR-P level. For multiple stacked NOR-P blocks, a global WL staircase is required. Depending on the number of NOR-P wafers to be stacked, add the same number of jump metal plug sets as shown in the example in Figure 19C. Additional jump metal plugs are connected via Global Ladder Jumpers 1990. In order to better observe the local stair jumper 1980, the global stair jumper 1990, and the jumping metal plug, Figure 19D is a side view of Figure 19C. The left side of the global staircase 1990 _n and the right side of the local staircase 1990 _n are open (not electrically connected and not conductive), while the right side of the global staircase 1990 _n and the left side of the local staircase 1990 _n+1 are short-circuited (electrically connection, conduction). Figure 19E shows the global WL staircase connection with three NOR-P blocks stacked. The first jumper 1970i connects the local WL-stairs of the first NOR-P block 1950A, the second jumper 1970j connects the local WL-stairs of the second NOR-P block 19500B, and the third jumper 1970-j connects the third NOR - Partial WL staircase of P block 195 0C. By doing this, each individual WL in the stacked WL can have a dedicated WL control signal from the peripheral logic circuitry. This method of connecting local ladders and global ladders can be applied to other control lines such as BL and SL. Furthermore, the same approach can be used for other 3D memories, such as 3D stacked NAND, RRAM and PCRAM. The stacking concept described above is similar to that presented in Figures 22A-22B and Figures 27A-27D of US Patent Application No. 16/558304 (now US Patent Publication 2020/0176420), the entire contents of which are incorporated herein by reference.

One example of an Aa 3D NOR-P memory device is a process step for a metal-induced crystalline silicon channel. Three-dimensional NOR-P. Process steps may be used to form substantially large grain size metal induced crystallization (MIC) silicon channels from small grain size polysilicon or amorphous silicon channels. Small grain size polysilicon or amorphous silicon refers to the semiconductor phase deposited by the chemical vapor deposition process. For simplicity, "polysilicon" in this invention refers to deposited silicon before the crystallization process, and "MICSi" refers to recrystallized polysilicon after the metal-induced crystallization process. Seed metal and crystallization temperature requirements can be found in Yoon, Soo-Young et al., "Metal-Induced Crystallization of Amorphous Silicon," Solid Thin Films 383.1-2 (2001):34-38 (incorporated herein by reference) turn up. In addition, the channel material of the 3D NOR-P proposed in the present invention can be, but is not limited to, polycrystalline germanium, amorphous germanium, polycrystalline silicon germanium, amorphous silicon germanium or metal-induced crystallization semiconductors thereof. The seed metal and temperatures required for crystallization are described in Kang Dong-Ho and Jin-Hong Park, "Indium (In) and tin (Sn)-based metal-induced crystallization (MIC) on amorphous germanium (α-Ge)," Materials Research Bulletin 60 (2014): 814-818 and "Low-temperature al-induced crystallization of hydrogenated amorphous Si _1-x Ge _x (0.2≤x≤1) thin films" by Peng Shanglong et al., Solid Thin Films 516.8 (2008): 2276 -2279, which is incorporated herein by reference. The device structure of 3D NOR-P is proposed in US10892016, which is hereby incorporated by reference. Figure 19F shows a prior art method of forming MIC silicon in 3D NOR-P. Figures 19G and 19H illustrate another method of forming MIC silicon in 3D NOR-P in the present invention. For simplicity, only a single layer of unit storage cells is drawn. Prior art 19F, shown in the figure, describes a metal-induced crystallization process that occurs laterally. Step si shows the formation of multiple stacked horizontal layers of material alternating silicon oxide as inter-WL oxide and degenerately doped polysilicon as word lines (WL). For better observation, only a single layer of WL is shown here, but the inter-WL oxide is not drawn. The unit memory cell consists of three holes of hollow cylindrical polysilicon extending vertically relative to the wafer substrate, where a part of the polysilicon near the center hole can become the channel area, and the polysilicon near the left and right holes Parts can become source and drain regions. The memory layer is formed between the outer surface of the hollow cylindrical polysilicon and WL. The storage layer may be a tunnel oxide, a charge trapping layer such as silicon nitride or a floating gate, and a stack of blocking oxides. Step s2 shows a thin layer of metal, such as Ni, Al or Cu, deposited on the inner surface of the polycrystalline silicon hole as a source or drain. Step s3 shows the intermediate stage of the MIC process, indicating that the metal is migrating laterally in the opposite direction, leaving behind MIC-Si. Step s4 shows the final stage of the MIC process, indicating that the metal reaches the drain or source region and the polysilicon in the channel region becomes MIC-Si. Step s5 shows the device structure after subsequent source and drain processes. Compared with the process shown in Figure 19F, the process proposed in the present invention can provide shorter process time. Figure 19G depicts the MIC process proposed in the present invention. Step si shows the formation of multiple stacked horizontal layers of material similar to that shown in Figure 19F, alternating silicon oxide as inter-WL oxide and degenerately doped polysilicon as word lines (WL). The storage layer is formed between the outer surface of the hollow cylindrical polysilicon and WL. The storage layer may be a tunnel oxide, a charge trapping layer such as silicon nitride or a floating gate, and a stack of blocking oxides. Step s2 shows a thin layer of metal such as Ni, Al or Cu deposited on the inner surface of the polysilicon hole as the channel region. Step s3 shows the intermediate stage of the MIC process, indicating that the metal first migrates radially from the inner surface to the outer surface of the hollow polysilicon in the channel, and then migrates laterally to the source and drain regions, leaving behind the MIC Si. Step s4 shows the final stage of the MIC process, indicating that the metal reaches the drain or source region and the polysilicon in the channel region becomes MIC-Si. Step s5 shows the device structure after subsequent source and drain processes. Figure 19H depicts another embodiment of the MIC process proposed in this invention. Step si shows multiple stacked horizontal layers of materials that will be replaced with metal or other conductive WL materials, silicon oxide as the inter-WL oxide, and silicon nitride as the sacrificial layer. Step s2 shows the device structure after selective removal of sacrificial silicon nitride, followed by deposition of a thin layer of metal such as Ni, Al or Cu on the outer surface of the polysilicon. Step s3 shows the final stage of the MIC process, indicating radial migration of metal from the outer surface to the inner surface of the hollow polysilicon, leaving behind the MIC Si. Step s4 shows the removal of metal reaching the inner surface of the MIC Si, followed by the formation of the memory layer and the device structure of the WL. The storage layer may be a tunnel oxide, a charge trapping layer such as silicon nitride or a floating gate, and a stack of blocking oxides. Step s5 shows the device structure after subsequent source and drain processes.

An important advantage of 3D NOR architectures, especially 3D NOR-P with metallized S/D pillars, is the ability to stack hundreds of levels with less impact on device performance, especially the sensed current value. Common 3D NAND architectures are very sensitive to the number of levels because the channels are in series with adjacent transistors, which, as mentioned earlier, are called strings. Therefore, when a random cell is accessed, current must flow through every transistor in the string. Since the current through the channel decreases as the number of layers increases, there is a limit to the number of layers that can be stacked. In 3D NOR-P, when a random cell is accessed, current flows through only one selected transistor. Punch holes through the level stack are specified for S/D, and for metallized S/D, the conductivity is orders of magnitude better than that of the 3D NAND channel, allowing for relatively orders of magnitude more 3D levels. As a result, the size of manufacturable memory can quickly and easily grow to densities of 100X/1000X or higher with little loss in performance.

Figures 20A and 20B provide tables of the main properties of high-speed memories such as SRAM and DRAM; as well as medium-speed memories such as NOR, storage class (SCM); and high-density memories such as NAND. As we have seen, these memory technologies offer trade-offs between density, access time, and power. Power tradeoffs can include write power and spare power; access time tradeoffs can include read access and write access. Density trade-offs may include cell size, number of levels, and the number of bits programmable per cell. These tradeoffs can be made to better support the desired application. For example, in artificial intelligence (AI) applications, there may be built-in physical and electrical differences between the portion of memory used for data and the portion of memory used for weights, which typically require many more reads than writes. Therefore, for the example described, data can be stored in cells with no tunnel oxide or with minimal tunnel oxide, while weights can be stored in cells with greater than about 1 nm tunnel oxide for longer write times. Reduce refresh requirements and power at the cost.

3D NOR-P can be constructed to support the design and processing of memory cells by changing the cell structure (such as thin or thick tunnel oxide) to better match these trade-offs. This can be done in the X-Y direction with an appropriate mask, or in the Z direction with a stack etc. - e.g. Figure 19A. To better match the application, this can also be achieved through memory control, for example by using mirrored bits or multi-level cell memory technology.

The term "electron charging" as used herein refers to increasing the net density of electrons by trapping electrons or detrapping holes in a charge trapping layer. Similarly, the term "electron discharge" describes reducing the net density of electrons by trapping electrons or trapping holes in a charge trapping layer. In binary-bit or one-bit-per-cell operations, the terms "program" and "erase" are interchangeable with "write 0" and "write 1" respectively.

A method of operating 3D NOR-P is proposed to compensate for cell-to-cell changes. In conventional memory operation, a storage state such as a threshold voltage is compared to a reference level, which may be generated by an external voltage generator or a control line such as the bit line of an unselected adjacent block. Fixed value. However, process-induced variability and variability in program and erase operations can lead to wide spreads in threshold voltage distributions. In the case of large threshold voltage distributions, a fixed reference voltage level for read operations may cause malfunctions, or additional read time may be required to resolve the read operation. Self-referenced or differential operating modes and control circuitry can overcome this cell-to-cell variation.

The differential operating mode and control circuit scheme utilizes the memory cell itself to generate the reference signal for the read operation of the cell. The concept described is a modified technique of mirrored bit cells originally applied to differential operating modes. It exploits the charge trapping aspect and the non-conductivity of the trap layer to create an asymmetry in the channel resistance distribution along the source to drain side.

Figure 20C illustrates the 2x2 array structure of 3D NOR-P. Figure 20D shows examples of write voltages to such memory cells, and is shown in four cases on a single cell. Arrows indicate the direction of electron charging. Filled circles in the charge trap layer show filled local electron charge regions, and only outline (empty) circles within the charge trap layer show empty local electron charge regions (holes). It should be noted that the absolute voltage values used as examples of these values will be set for a specific memory structure.

This charge trap memory cell can be used for self-referenced (differential) read operations. For state "1", the local threshold voltage on the drain side is lower than the local threshold voltage on the source side. For state "0", the local threshold voltage on the drain side is higher than the local threshold voltage on the source side. Therefore, read operations perform sensing of local imbalances or skews in threshold voltages. Therefore, self-referenced reads can tolerate large cell-to-cell variability.

Figure 20E shows a 2x2 array connected to a sense amplifier (S/A). In conventional memory, the differential inputs of the S/A are connected to one BL and another BL in different columns of the memory array. For self-referenced readings, the differential inputs are connected to BL and SL from the same column.

Figure 20F illustrates the voltage development of the S/A's BL as a function of read time. Figure 20G shows example voltage conditions and associated band diagrams for read operations. First, the same voltage (such as 0.5V) is precharged to the SL/BL of the selected column. This operation may be called "SL/BL precharge". Next, a WL voltage (eg, 1V) greater than the local threshold voltage for reading is applied to the selected row. Then, although SL/BL are precharged to the equal potential, due to the asymmetric distribution of the local threshold voltage of the cell, a small amount of electrons may flow from the source side to the channel in state "1", or from the source side in state "0" The drain side flows to the channel. When a small current flow occurs from one of the source line or bit line to the channel, the precharge potential level of the source line or bit line drops slightly. Next, enable S/A to amplify small changes in BL and SL for a given column. Therefore, storage states can be sensed through self-reference.

Figure 20G also shows the voltage conditions and associated band diagrams for suppressed readings for unselected cells. A WL voltage less than the local threshold voltage for reading (eg, 0V) is applied to the unselected row shared SL/BL. Since the read inhibit WL voltage is less than the local threshold voltage, no channel current will flow. BL/SL can be floated for unselected columns sharing WL. When BL/SL is floating, no channel current flows. For 3D NOR-P memory structures with a body in contact with the channel, as shown in Figures 27A-27C of US application 16/483431, the body can be biased to 0 volts to highly accelerate the development of such differential cell structures and methods. Read.

Another example of a read method is acceleration sensing timing. A WL voltage of 1V for reading is illustrated with reference to the read voltage conditions shown in Figure 5E of US Patent 11018156 and US Patent 10892016, which are incorporated herein by reference. In such embodiments, the gate overdrive voltage for readout may be greater than 1V, such as 1.5V or 2V, in order to speed up the channel current or reduce the minimum time required for induction. However, the gate overdrive voltage can be limited to a value that rarely causes soft write or read disturbance to unselected cells sharing the same BL or to the storage state of the selected cell during read operations. For example, at a given write voltage difference ΔV _{WL_SL/BL} between WL and SL/BL, the read gate voltage can be between 50% and 75% of ΔV _{WL_SL/BL} .

An additional alternative to a self-referenced read scheme could utilize overdrive to read the saturation current of the memory cell to be used as a read reference signal. The technique described can use two read cycles, the first for the reference signal and the second for the cell storage status signal. FIG. 20H shows the characteristics of bit line current and word line voltage under different storage states and read conditions. The first set of read bias conditions {Vread1} is applied to the selected cell, and the drain current IBL1 of the bit line current is obtained based on the {Vread1}-cell storage state signal. A second set of read bias conditions {Vread2} greater than the first set of read bias conditions {Vread1} is applied to the same selected cell {Vread2}, and the drain of the bit line current is obtained based on the {Vread2}-reference signal Current IBL2 (saturation current). The difference in bit line current (IBL2-IBL1) due to changes in the applied bias conditions {Vread2}-{Vread1} depends on the state of the selected memory cell. For example, the word line voltage of {Vread2} may be much greater than the threshold voltage of state "0", while the word line voltage of {Vread1} may be much greater than the threshold voltage of state "1", but fall into the sub-threshold of state "0"). threshold area. The current difference in state "1" (IBL2-IBL1) may be much larger than the current difference in state "0" (IBL2-IBL1). For example, for state "0", very small bit line current differences can be observed, such as less than 100 nA, but for state "1", large bit line voltage differences can be observed, such as greater than 5 μm cells. Sense amplifier circuits can use ratiometric rather than differential techniques.

Such sense amplifier technology is known in the memory field, and such technology and circuits have been proposed in at least U.S. Patent 7,590,003 and the following papers: "0.24-μm 2.0 with self-reference sensing scheme" by Jeong, Gitae et al. -V 1T1MTJ 16kb non-volatile magnetoresistive RAM," IEEE Solid-State Circuits Magazine 38.11 (2003): 1906-1910; "A. High-density and high-speed 1T-4MTJ MRAM with voltage offset self-referencing" by Tanizaki, Hiroaki et al. Sensing Scheme," 2006 IEEE Asian Solid-State Circuits Conference, IEEE, 2006; Choi, Jun-Tae et al., "A Novel Self-Referencing Sense Amplifier for Spin-Transfer Torque Magnetoresistive Random Access Memory," JSTS: Semiconductors Journal of Technology and Science 16.1 (2016): 31-38; and Na, Taehui et al., "Data cell variation tolerant dual-mode sensing scheme for deep submicron STT-RAM", IEEE Transactions on Circuits and Systems I: Regular Papers 65.1 (2017):163–174, all of which are incorporated by reference in their entirety.

Another alternative to self-referenced reading is to use 3D NOR memory and instead of utilizing the mirrored bit concept of two bits per cell, the drain side area is used not as a bit storage location but as a location where the self-referenced signal is formed. Reference location. Therefore, in this case, only the source side of the cell is used for programming and erasing, while the drain side is used only for reading the reference signal. In this approach, two read cycles can be used in a manner similar to that shown in Figure 20H. A read cycle reads the unprogrammed drain side and uses it as a reference to compare with the read of the memory site on the source side. The sense amplifier may use a circuit similar to that shown with reference to the self-referencing method and structure shown in Figure 20H.

Systems with such multi-level 3D NOR-P structures may include one or several levels of memory control circuitry that may support efficient intra-system transfer of memory data from one device area to another, e.g., from a high-density area. to the highway area. As shown in Figures 15A-17 and 34A-35D of US Patent 10,515,981, the entire contents of which are incorporated herein by reference. In some cases this can be controlled by connecting data lines from one bank directly to another, or by first transferring data from one zone to buffer memory and then from buffer memory to another. kind of transmission.

Another advantage of 3D memory with memory control logic is the option of constructing the memory with extremely wide data buses. General-purpose memories in industry with relatively narrow busbars are limited by the number of I/O and pins available in low-cost device packages and by the use of general-purpose printed circuit board routing busbars. A 3D architecture in which device control and connection to the processor can occur vertically can support very wide databases, for example, 32, 64, 128, 256, 512 or even more than 1024 rows. This extremely wide bus increases data rates and memory-to-processor bandwidth, especially for multi-core architectures. At least one 3D memory chip could be integrated on the processor chip via 3D stacking, which may require close collaboration between processor and memory designers. Alternatively, at least one 3D memory chip could be integrated with the processor chip through a 2.5D interposer, so the processor and memory designs could be decoupled. Additionally, multiple 3D memory chips and multiple processors can be routed through an on-chip network topology. The on-chip network can be a traditional metal wire-based network. Or it could be an optical or RF interposer based network. Processors can not only be multi-core but also heterogeneous. Heterogeneous integration can include any other exotic device. Different types of memory such as MRAM, PCRAM and RRAM can be integrated into 3D systems. Sensors such as lidar, 3D cameras and metal-induced crystallization can be integrated directly on the 3D system. In addition to wide data buses, the advantages of this 3D integration include a reduction in wire lengths and a consequent reduction in power compared to traditional PCB integration.

Another advantage of 3D memories with memory control logic placed at least one on top and/or below the memory array is that some simple arithmetic/logic units can be included in the memory control logic. Two up. Therefore, simple arithmetic and logical operations can be completed in the memory chip, significantly improving system performance and reducing power consumption. ALU functions can also be performed and optimized in the memory itself.

Because the buses are very wide, slow memories are sometimes used in high-speed computing applications. One example of high-speed computing could include Al accelerators for the cloud and edge. In this case, relatively slower memory architectures such as 3D NAND can be used to form mid-speed systems. Therefore, it may be desirable in some systems to utilize 3D NAND architectures with thin tunnel oxides to support moderately good memory speeds with good memory density and low off-state current.

In Al calculations, it may be necessary to use different Al algorithms to perform some different Al tasks. Due to different requirements for performance, efficiency and parameter size, its configuration may need to be generic. To accommodate configurability, 3D systems with 3D memory can include FPGA elements. Alternatively, an array of many processing cores and many 3D memory blocks can be configured through an on-chip network. The software can reconfigure memory bandwidth and memory bit width. In some 3D systems, for example in mobile systems, alternative (not liquid cooling unless recycled) thermal management techniques may be used.

The 3D systems described herein can be full wafer or cut into sub-wafer sizes. Such dicing can be performed in regular patterns that can be designed to match throughput to maximize good throughput structures in multi-layer wafer structures. This scribing can be accomplished by many scribing techniques used in industry. More advanced dicing techniques, such as using plasma etching, can be effective and allow for flexible dicing patterns as well as reducing the width of dicing lanes (often called streets) and the associated waste of active device wafer utilization. Cutting or singulation patterns may use masked patterns or maskless patterns for greater flexibility, particularly when employing directional etching/substance removal techniques, such as, for example, plasma-based etching. Laser cutting technology is another alternative to cutting or singulation.

Typically, the construction of the 3D systems described herein involves multiple steps of layer transfer. This layer transfer may include flipping the donor wafer over the target wafer and performing hybrid bonding. The donor wafer substrate is then ground and etched back using a built-in cutting layer (eg SiGe). If needed, form pins/pads for next step. These steps may include reversing the roles of the donor wafer or the target wafer and substantially removing the substrate from one or both of them, as shown with reference to at least FIG. 13A. This article and the many incorporated references. These steps of layer transfer can include the use of carrier wafers, as proposed several times in the technology incorporated by reference, or as in the paper "Extreme wafer thinning and nano-TSV processing for 3D heterogeneous integration" by Jourdain, Anne et al. , 2020 IEEE 70th Electronic Components and Technology Conference (ECTC). Proposed in IEEE, 2020, which is incorporated by reference in its entirety. The use of a carrier wafer helps perform backside addition of pins/pads on the side wafer rather than on the target 3D structure. Additionally, it effectively flips the transfer layer back into alignment with the target wafer in a non-flip form. Thus, for example, referring to Figure 13A herein, structure 1318 would be a carrier wafer, and then flow formation to structure 1330 may represent the carrier wafer used prior to the final step of removing the carrier wafer. The carrier wafer removal process/method may be similar to removing the substrate by using grinding and etching back to the built-in etch stop layer.

Therefore, the 3D system proposed in this paper can provide a flexible framework for the formation of the final system. It can support the mixing and matching of device-level processing at various fabs using multiple processes. 3D systems can be built like Lego bricks, where engineering can include using "off-the-shelf" generic layers. Industry standards for vertical bus and cell dimensions may help support the availability of such common tiers for LEGO-like system construction. The tiers may also include at least one programmable core array. Other forms of flexibility can take advantage of technologies such as (embedded) field programmable logic and semi-custom logic incorporated herein or through reference technologies. The flexible framework can include building the system with a choice of various layers stacked in the Z direction, as well as full wafer level or dicing options, including dicing options in the X/Y direction. Engineers in their field can design specific systems and devices based on the flexible 3D system framework proposed in this article.

FIG. 21A shows a Cerebras Systems wafer-level engine as a prior art. After cutting four pieces of silicon from a round wafer, the wafer-scale engine takes on a square shape. Input/output connection pins or pads are then located on both edges of the square wafer-scale engine.

As an alternative to wafer-level 3D systems, it could include IO pads along the circumference of the wafer edge. The IO pins can be in at least one row, as shown in the enlarged view of Figure 2IB. Although IO pads are usually arranged linearly in traditional semiconductor systems, IO pads can be arranged axially. I/O pads may be placed within approximately 110 microns of the wafer edge, within approximately 220 microns of the wafer edge, within approximately 300 microns of the wafer edge, or within 500 microns of the wafer edge. The orientation of the IO pads can all be aligned in one direction, with the preferred direction being directly "up" or "north" relative to the wafer stepper layout, or they can all be pointed towards the center of the circular wafer, as if from the center of the circle Either on a radial ray, or in a changing direction with a position that allows an optimal angle of attack for the pad bonding/connection process. By using the full die size to configure wafer-scale 3D systems, the real estate utilization of the wafer is unparalleled.

Another embodiment relates to a clamp for a 3D wafer scale system. Traditionally, semiconductor chips have been packaged to protect them from the external environment, such as shock, light, humidity, and dust. The components of encapsulating materials often include inorganic fillers such as silica and epoxy resins. Chips for consumer electronics, especially for mobile applications, need to be protected from these environmental threats. However, enterprise applications, such as supercomputers, data centers, and servers, may not require encapsulation because such applications typically operate in well-light/humidity/dust-controlled environments and the chip is rarely repositioned after installation. A major disadvantage of the package is that its thermal resistance inhibits heat dissipation.

Therefore, to better dissipate heat from a wafer-level 3D system, a fixture that allows the system to be "exposed" can be used, as shown in Figures 21C to 21E. Clamps can be made to hold and clamp the edge areas of the wafer-scale 3D system, while the center area can be exposed. The clamp can be configured to connect the IO pads of the wafer-level 3D system through the gripping area. The clamp may include indentations according to the shape of the wafer-level 3D system so that it seats and securely holds the wafer/3D system. As shown in Figures 21C-21E, the wafer-level 3D system is drawn as a circle; however, if the wafer-level 3D system is to be sawed, the system shape can be a square, a rectangle, a truncated square, or a truncated rectangle. Wafer-level 3D systems may include IO pads along the edge region of the wafer, as shown in Figure 2IB. Materials for the bottom of the chassis can include aluminum, stainless steel, silicon, silicon carbide, glass, or their metal coatings (such as nickel or gold). Fixtures can hold wafers in a variety of ways.

Figure 21C shows a screw clamp. The top and bottom of the clamp are separate. These two parts hold the wafer in place using a screw and spring mechanism. The number and location of screws and springs depends on engineering considerations and may differ from the 4 screws/springs shown in the clamp locations shown. Figure 21D shows a clamp type fixture. The upper and lower parts of the clamp are connected by vertical hinges. Figure 21E shows a clamshell clamp. The top and bottom of the clamp are connected by horizontal hinges. The hinge mechanism clamps and holds the wafer as it is mounted. Figure 21F shows an internal view of the bottom of such a clamp. The bottom of the clamp can include a resilient material, such as a rubber o-ring or polyimide, which can apply gentle pressure to hold the wafer when the clamp is closed. Figure 21G shows an interior view of the top of the clamp. The top of the fixture may include printed circuit board systems for signal integrity, power integrity, and other control functions. The PCB may also include pins for probing the IO pads of the wafer-level 3D system.

Another embodiment may use a liquid immersion cooling bath that may contain multiple wafer-scale 3D systems mounted through a bare fixture, as shown in Figures 21C-21E. Multiple fixtures with bare wafer-level 3D systems can be immersed in a bath of dielectric heat transfer liquid. If the fluid requires circulation such as single-phase cooling, the bath may optionally contain inlet and outlet holes.

Alternatively, the bath may include a two-phase cooling fluid. In two-phase cooling, the fluid evaporates on the surface of the hot portion of the wafer-scale 3D system, thereby removing heat from the hot area on the wafer. Circulation of the fluid occurs passively through the evaporation and condensation of the coolant. Figure 21H shows Gigabyte Technology’s two-phase cooling bath (https://www.gigabyte.com/Solutions/Cooling/immersion-cooling). The PCB board on which multiple packaged chips are mounted is immersed in the bath. As an alternative embodiment, a liquid cooling bath may contain multiple bare wafer level 3D systems, as shown in Figure 21I.

Another option is to use a fixture of a bare wafer-level 3D system, which may further include an Ethernet port and a power port, as shown in Figure 21J. The Ethernet and power ports are connected to the wafer-level 3D system via a PCB similar to that shown in Figure 21G.

In another alternative, the wafer-scale 3D system can be designed to be cut in half, as shown in Figure 21K. Semi-wafer-scale 3D systems can be arranged via printed circuit boards, as shown in Figure 21L. Input/output (I/O) pads can be formed on the centerline of the die, as shown in Figure 21K. As shown in Figure 21L, when multiple dies are arrayed, data channels and addresses can be shared. The semi-wafer-level 3D system can be mounted directly to the socket. Semi-wafer-scale 3D systems can be bare or encapsulated with epoxy molding compound or polyimide. To address the issue of which die information should be communicated to and from, the I/O pads may include appropriate die identification numbers (IDs). In such an alternative, the array wafer-scale 3D system may be a staggered 3D system. By distributing addresses evenly across the die but distinguishing them by die ID, memory accesses, instructions and other programming can be interleaved by the master controller.

The 3D system proposed in this paper can be considered as a semiconductor device and uses other integration technologies used in the industry such as printed circuit boards (PCB), interposer, substrate and integration technology (also known as 2.5D) and other technologies, integration into a larger system.

It will further be understood by those of ordinary skill in the art that the present invention is not limited to what is specifically shown and described above. For example, the use of SiGe as a designated sacrificial layer or etch stop layer may be replaced by compatible materials or a combination of other materials including additives to SiGe such as carbon or various doping materials such as boron or other modified materials. body. For example, drawings or illustrations may not show n or p wells for clarity. Furthermore, any transfer layer or donor substrate or wafer preparation shown or discussed herein may include one or more undoped regions or layers of semiconductor material. Additionally, when transferred, one or more transferred layers may have regions of STI or other transistor elements within or on them. For example, the order of energy levels and their functionality may differ from that shown here, the use of hybrid bonding or other types of bonding and associated alignment techniques and their vertical connections may use the techniques incorporated herein or by reference or other techniques. Mix and match. Furthermore, a modular approach to typical cell-based architectures can support the required flexible system construction, such as dicing a 3D heterogeneous integrated wafer to the size of ^a 40x40mm system, or too large a size, such as a 100x 100mm ^system , or Even using 3D chips as the final system. Furthermore, the system may be designed as a mixture of units with different sizes and/or different functions, including units supporting Al calculations and units supporting data management and system management. Additionally, 3D systems can be scaled beyond the wafer size by utilizing panels with built-in waveguides or transmission lines, as shown in Figures 43A-43E of U.S. Patent Application No. 16/558,304, Publication No. 2020/0176420, which is incorporated by reference. into this article.

There are many options and engineering considerations for building a specific system using the techniques presented in this article, as those skilled in the art can apply. Rather, the scope of the invention includes combinations and subcombinations of the various features described above, as well as the modifications and changes that may occur to those skilled in the art on reading the foregoing description. Accordingly, the invention is limited only by the appended claims.

Claims (23)

1. A 3D device, the device comprising:

a first level including a first transistor, the first level including a first interconnect;

a second level including a second transistor, the second level overlying the first level;

A third level including a third transistor, the third level overlying the second level; and

a plurality of Electronic Circuit Units (ECU),

wherein each of the plurality of ECUs comprises a first circuit comprising a portion of the first transistor, wherein each of the plurality of ECUs comprises a second circuit comprising a portion of the second transistor, wherein each of the plurality of ECUs comprises a third circuit comprising a portion of the third transistor, wherein each of the ECUs comprises a vertical bus,

wherein the vertical bus comprises more than eight struts and less than three hundred struts,

wherein the vertical bus provides an electrical connection between the first circuit and the second circuit,

wherein each of the ECUs includes a vertical control line,

wherein the vertical control line comprises greater than eight hundred struts, an

Wherein the vertical control line provides an electrical connection between the second circuit and the third circuit.

2. The device according to claim 1,

wherein the vertical bus is compatible with at least one industry accepted standard computer bus.

3. A 3D device, the device comprising:

a first level including a first transistor, the first level including a first interconnect;

a second level including a second transistor, the second level overlying the first level;

a third level including a third transistor, the third level overlying the second level; and

a plurality of Electronic Circuit Units (ECU),

wherein each of the plurality of ECUs comprises a first circuit comprising a portion of the first transistor, wherein each of the plurality of ECUs comprises a second circuit comprising a portion of the second transistor, wherein each of the plurality of ECUs comprises a third circuit comprising a portion of the third transistor, wherein each of the ECUs comprises a vertical bus,

wherein the vertical bus comprises more than eight struts and less than three hundred struts,

wherein the vertical bus provides an electrical connection between the first circuit and the third circuit,

wherein each of the ECUs includes a vertical control line,

wherein the vertical control line comprises greater than eight hundred struts, an

Wherein the vertical control line provides an electrical connection between the second circuit and the third circuit.

4. A device according to claim 2,

wherein the second level is joined to the first level, and

wherein the bond includes an oxide-to-oxide bond region and a metal-to-metal bond region.

5. A device according to claim 2,

wherein the vertical bus includes less than one hundred twenty struts.

6. A 3D device, the device comprising:

a first level including a first transistor, the first level including a first interconnect;

a second level including a second transistor, the second level overlying the first level;

a third level including a third transistor, the third level overlying the second level; and

a plurality of Electronic Circuit Units (ECU),

wherein each of the plurality of ECUs comprises a first circuit comprising a portion of the first transistor, wherein each of the plurality of ECUs comprises a second circuit comprising a portion of the second transistor, wherein each of the plurality of ECUs comprises a third circuit comprising a portion of the third transistor, wherein each of the ECUs comprises a vertical bus,

wherein the vertical bus comprises more than eight struts and less than three hundred struts,

Wherein the vertical bus provides an electrical connection between the first circuit and the second circuit,

wherein the third level comprises an array of memory cells, and wherein the second circuit comprises a memory control circuit.

7. The device according to claim 6,

wherein the second level is joined to the first level, and

wherein the bond includes an oxide-to-oxide bond region and a metal-to-metal bond region.

8. A 3D device, the device comprising:

a first level including a first transistor, the first level including a first interconnect;

a second level including a second transistor, the second level overlying the first level;

a third level including a third transistor, the third level overlying the second level; and

a plurality of Electronic Circuit Units (ECU),

wherein each of the plurality of ECUs comprises a first circuit comprising a portion of the first transistor, wherein each of the plurality of ECUs comprises a second circuit comprising a portion of the second transistor, wherein each of the plurality of ECUs comprises a third circuit comprising a portion of the third transistor, wherein each of the ECUs comprises a first vertical bus,

Wherein the first vertical bus includes more than eight first struts and less than three hundred first struts,

wherein the first vertical bus provides an electrical connection between the first circuit and the second circuit; and

a second vertical bus bar is provided which is arranged on the first vertical bus bar,

wherein the second vertical bus includes more than eight second struts and less than three hundred second struts,

wherein the second vertical bus provides an electrical connection between the second circuit and the third circuit, an

Wherein the first leg is not in direct contact with the second leg.

9. A 3D device, the device comprising:

a first level including a first transistor, the first level including a first interconnect;

a second level including a second transistor, the second level overlying the first level;

a third level including a third transistor, the third level overlying the second level; and

a plurality of Electronic Circuit Units (ECU),

wherein each of the plurality of ECUs comprises a first circuit comprising a portion of the first transistor, wherein each of the plurality of ECUs comprises a second circuit comprising a portion of the second transistor, wherein each of the plurality of ECUs comprises a third circuit comprising a portion of the third transistor, wherein each of the ECUs comprises a vertical bus,

Wherein the vertical bus comprises more than eight struts and less than three hundred struts,

wherein the vertical bus provides an electrical connection between the first circuit and the second circuit, an

Wherein the vertical bus includes a plurality of redundant struts.

10. A 3D device, the device comprising:

a first level including a first transistor, the first level including a first interconnect;

a second level including a second transistor, the second level overlying the first level;

a third level including a third transistor, the third level overlying the second level; and

a plurality of Electronic Circuit Units (ECU),

wherein each of the plurality of ECUs comprises a first circuit comprising a portion of the first transistor, wherein each of the plurality of ECUs comprises a second circuit comprising a portion of the second transistor, wherein each of the plurality of ECUs comprises a third circuit comprising a portion of the third transistor, wherein each of the ECUs comprises a vertical bus,

wherein the vertical bus comprises more than eight struts and less than three hundred struts,

Wherein the vertical bus provides an electrical connection between the first circuit and the second circuit, an

Wherein the vertical bus includes a plurality of power delivery struts.

11. A 3D device, the device comprising:

a first level including a first transistor, the first level including a first interconnect;

a second level including a second transistor, the second level overlying the first level;

a third level including a third transistor, the third level overlying the second level; and

a plurality of Electronic Circuit Units (ECU),

wherein each of the plurality of ECUs comprises a first circuit comprising a portion of the first transistor, wherein each of the plurality of ECUs comprises a second circuit comprising a portion of the second transistor, wherein each of the plurality of ECUs comprises a third circuit comprising a portion of the third transistor, wherein each of the plurality of ECUs comprises a vertical bus,

wherein the vertical bus comprises more than eight struts and less than three hundred struts,

wherein the vertical bus provides an electrical connection between the first circuit and the second circuit, an

Wherein the vertical bus meets industry standards regarding the position of the pillar relative to the ECU edge.

12. A 3D device, the device comprising:

a first level including a first transistor, the first level including a first interconnect;

a second level including a second transistor, the second level overlying the first level;

a third level including a third transistor, the third level overlying the second level; and

a plurality of Electronic Circuit Units (ECU),

wherein each of the plurality of ECUs comprises a first circuit comprising a portion of the first transistor, wherein each of the plurality of ECUs comprises a second circuit comprising a portion of the second transistor, wherein each of the plurality of ECUs comprises a third circuit comprising a portion of the third transistor, wherein each of the ECUs comprises a vertical bus,

wherein the vertical bus comprises more than eight struts and less than three hundred struts,

wherein the vertical bus provides an electrical connection between the first circuit and the second circuit, an

Wherein the vertical bus includes a plurality of data columns and a plurality of address columns.

13. The device according to claim 12,

wherein the vertical bus comprises at least 8 data columns.

14. The device according to claim 12,

wherein the ECU size is greater than 2500 square microns and less than 4 square millimeters.

15. A 3D device, the device comprising:

a first level including a first transistor, the first level including a first interconnect;

a second level including a second transistor, the second level overlying the first level;

a third level including a third transistor, the third level overlying the second level; and

a plurality of Electronic Circuit Units (ECU),

wherein each of the plurality of ECUs comprises a first circuit comprising a portion of the first transistor, wherein each of the plurality of ECUs comprises a second circuit comprising a portion of the second transistor, wherein each of the plurality of ECUs comprises a third circuit comprising a portion of the third transistor, wherein each of the ECUs comprises a vertical bus, and

wherein each of the ECUs includes a plurality of trench capacitors.

16. A 3D device, the device comprising:

A first level including a first transistor, the first level including a first interconnect;

a second level including a second transistor, the second level overlying the first level;

a third level including a third transistor, the third level overlying the second level; and

a plurality of Electronic Circuit Units (ECU),

wherein each of the plurality of ECUs comprises a first circuit comprising a portion of the first transistor, wherein each of the plurality of ECUs comprises a second circuit comprising a portion of the second transistor, wherein each of the plurality of ECUs comprises a third circuit comprising a portion of the third transistor, wherein each of the ECUs comprises a vertical bus,

wherein the vertical bus comprises more than eight struts and less than three hundred struts,

wherein the vertical bus provides an electrical connection between the first circuit and the second circuit, an

Wherein a portion of the pillars each comprise an electrostatic surge discharge ("ESD") structure.

17. A 3D device, the device comprising:

a first level including a first transistor, the first level including a first interconnect;

A second level including a second transistor, the second level overlying the first level;

a third level including a third transistor, the third level overlying the second level; and

a plurality of Electronic Circuit Units (ECU),

wherein each of the plurality of ECUs comprises a first circuit comprising a portion of the first transistor, wherein each of the plurality of ECUs comprises a second circuit comprising a portion of the second transistor, wherein each of the plurality of ECUs comprises a third circuit comprising a portion of the third transistor, wherein each of the ECUs comprises a vertical bus, and

wherein each of the ECUs includes a plurality of power conditioners.

18. A 3D device, the device comprising:

a first level including a first transistor, the first level including a first interconnect;

a second level including a second transistor, the second level overlying the first level;

a third level including a third transistor, the third level overlying the second level; and

a plurality of Electronic Circuit Units (ECU),

wherein each of the plurality of ECUs comprises a first circuit comprising a portion of the first transistor, wherein each of the plurality of ECUs comprises a second circuit comprising a portion of the second transistor, wherein each of the plurality of ECUs comprises a third circuit comprising a portion of the third transistor, wherein each of the ECUs comprises a vertical bus, and

Wherein each of the ECUs includes a plurality of charge pump circuits.

19. A 3D device, the device comprising:

a first level including a first transistor, the first level including a first interconnect;

a second level including a second transistor, the second level overlying the first level;

a third level including a third transistor, the third level overlying the second level; and

a plurality of Electronic Circuit Units (ECU),

wherein each of the plurality of ECUs comprises a first circuit comprising a portion of the first transistor, wherein each of the plurality of ECUs comprises a second circuit comprising a portion of the second transistor, wherein each of the plurality of ECUs comprises a third circuit comprising a portion of the third transistor, wherein each of the ECUs comprises a vertical bus, and

wherein each of the ECUs includes at least one high resistivity trap rich layer.

20. A 3D device, the device comprising:

a first level including a first transistor, the first level including a first interconnect;

a second level including a second transistor, the second level overlying the first level;

A third level including a third transistor, the third level overlying the second level; and

a plurality of Electronic Circuit Units (ECU),

wherein each of the plurality of ECUs comprises a first circuit comprising a portion of the first transistor, wherein each of the plurality of ECUs comprises a second circuit comprising a portion of the second transistor, wherein each of the plurality of ECUs comprises a third circuit comprising a portion of the third transistor, wherein each of the ECUs comprises a vertical bus, and

wherein each of the ECUs includes at least one monitor circuit.

21. A 3D device, the device comprising:

a first level including a first transistor, the first level including a first interconnect;

a second level including a second transistor, the second level overlying the first level;

a third level including a third transistor, the third level overlying the second level; and

a plurality of Electronic Circuit Units (ECU),

wherein each of the plurality of ECUs comprises a first circuit comprising a portion of the first transistor, wherein each of the plurality of ECUs comprises a second circuit comprising a portion of the second transistor, wherein each of the plurality of ECUs comprises a third circuit comprising a portion of the third transistor, wherein each of the ECUs comprises a vertical bus, and

Wherein each of the ECUs includes at least one temperature sensor.

22. A 3D device, the device comprising:

a first level including a first transistor, the first level including a first interconnect;

a second level including a second transistor, the second level overlying the first level;

a third level including a third transistor, the third level overlying the second level; and

a plurality of Electronic Circuit Units (ECU),

wherein each of the plurality of ECUs comprises a first circuit comprising a portion of the first transistor, wherein each of the plurality of ECUs comprises a second circuit comprising a portion of the second transistor, wherein each of the plurality of ECUs comprises a third circuit comprising a portion of the third transistor, wherein each of the ECUs comprises a vertical bus, and

wherein each of the ECUs includes a first liquid cooling structure and a second liquid cooling structure, an

Wherein the second liquid cooling structure is disposed above the first liquid cooling structure.

23. A 3D device, the device comprising:

a first level including a first transistor, the first level including a first interconnect;

A second level including a second transistor, the second level overlying the first level;

a third level including a third transistor, the third level overlying the second level; and

a plurality of Electronic Circuit Units (ECU),

wherein each of the plurality of ECUs comprises a first circuit comprising a portion of the first transistor, wherein each of the plurality of ECUs comprises a second circuit comprising a portion of the second transistor, wherein each of the plurality of ECUs comprises a third circuit comprising a portion of the third transistor, wherein each of the ECUs comprises a vertical bus, and

wherein each of the ECUs includes a first electromagnetic interconnect structure and a second electromagnetic interconnect structure, an

Wherein the second electromagnetic interconnect structure is disposed over the first electromagnetic interconnect structure.