CN117581203A - Multi-bit shift instruction - Google Patents

Abstract

An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions that cause a processor to execute a shift instruction. The shift instruction is to shift source data in the memory to the left or to the right. The shift instruction includes a source parameter and a bit size parameter. The processor executes the shift instruction by: shifting a first source word of the source data by the bit size parameter to produce a first intermediate word; shifting a second source word of the source data by the bit size parameter to produce a second intermediate word and a first set of shifted-out bits; and performing a logical OR operation on the first intermediate word and the first set of shifted-out bits to produce a first result word.

Description

Multi-bit shift instruction

Priority

The present application claims priority from U.S. provisional patent application 63/285,752 filed on month 3 of 2021, the contents of which are hereby incorporated by reference in their entirety.

Technical Field

The present disclosure relates to computer processing, and more particularly to multi-bit shift instructions.

Background

A computer processor (e.g., microprocessor, central Processing Unit (CPU), digital Signal Processor (DSP), digital Signal Controller (DSC), etc.) may shift or rotate data by various instructions. Performing such shifting or rotating operations in software through large blocks of data, such as data spread over multiple bytes or words, may be too slow and may require a programmer to utilize multiple commands and multiple data structures.

Examples of the present disclosure address one or more of these issues.

Drawings

FIG. 1 is an illustration of an exemplary system for variable precision multi-bit shift or rotate instructions according to an example of the present disclosure.

Fig. 2 is a diagram of an exemplary microcontroller for variable precision multi-bit shift or rotate instructions according to an example of the present disclosure.

FIG. 3 is a diagram of the execution of a processor of a variable precision multi-bit shift or rotate instruction according to an example of the present disclosure.

Fig. 4 is a diagram of execution of a processor of a left shift instruction according to an example of the present disclosure.

FIG. 5 is an illustration of an example method for executing a variable precision multi-bit shift instruction according to an example of the present disclosure.

FIG. 6 is a more detailed illustration of an exemplary method for executing a multi-bit shift instruction according to an example of the present disclosure.

Detailed Description

FIG. 1 is an illustration of an exemplary system 100 for variable precision multi-bit shift or rotate instructions according to an example of the present disclosure. The system 100 may include an article 104. The article 104 may include a non-transitory machine-readable medium such as memory. The medium may include instructions for execution by the processor 102 to load and execute other instructions. For example, instructions of the article 104, when read and executed by a processor, may cause the processor to load the shift instruction 106. The shift instruction 106 may cause the source data 108 in memory to shift left or right. The source data 108 may include a plurality of source words, such as source word 1 110 and source word 2 112. The shift instruction 106 may include a SOURCE parameter, which is given in terms of a SOURCE (SOURCE). The source parameters may identify the source data 108 to be shifted by the shift instruction 106, for example, by identifying a memory address of the source data 108 or a register containing the source data 108. The shift instruction 106 may include a target parameter, which is given in DESTINATION. The target parameters may identify where to store the shifted source data. The shift instruction 106 may include a BIT SIZE parameter given in BIT SIZE (BIT SIZE). The bit size parameter may identify a specified number of bits to shift. Processor 102 may be configured to execute shift instruction 106 by performing a logical shift of source word 1 110 of source data 108 by a specified number of BITs (as indicated by BIT SIZE) to produce a first intermediate word, such as first intermediate word 1 114. Processor 102 may be configured to perform a logical shift of source word 2112 of source data 108 by BIT SIZE of a specified number of BITs to produce a second intermediate word, such as second intermediate word 2 118 and first set of shifted-out BITs 116. The processor 102 may be configured to cause a logical OR operation to be performed on the intermediate word 1 114 and the first set of shifted-out bits 116 to produce a first result word 120. The or operation may be performed in hardware. The complete result of the shift instruction 106 may include a concatenation of the first result word 120 and the second intermediate word 2 118.

The register containing the first intermediate word 114 and the second intermediate word 118 and the register containing the first result word 120 may be the same register, with the result being executed in place or written back into the register containing the first intermediate word 114 and the second intermediate word 118.

Fig. 2 is an illustration of an exemplary microcontroller 200 for variable precision multi-bit shift or rotate instructions according to an example of the present disclosure.

The microcontroller may include a source register 206, a processor 202, and a destination register 208. The source register 206 and the destination register 208 may be the same size or different sizes. For example, each of the registers 206, 208 may have a size or capacity of M words. The source register 206 may include M source words 210. The destination register 208 may include M destination words 208. The processor 202 may be configured to execute a shift instruction 204. The shift instruction 204 may cause the cascaded content of the source register 206 to shift left or right into the destination register 208. The source register 206 and the destination register 208 may be the same register, with shifting performed in place and the result written to the source register 206. The shift instruction 204 may be configured to cause the processor 202 to shift such content left or right.

Depending on whether the shift instruction 204 shifts the contents of the source register 206 to the left or right, the shift instruction 204 may be executed starting with the least significant word or the most significant word of the source register 206. For example, in a left shift execution, execution may begin with the last source word M of source words 210, which is the most significant word. For example, in right shift execution, execution may begin with the first source word of source word 210, which is the least significant word.

The processor 202 may be configured to execute the shift instruction 204 to shift the contents of the source register 206 and store the result in the destination register 208. The shift instruction 204 may include identifiers of the source register 206 and the destination register 208. The shift instruction 204 may include an identifier of a specified number of BITs of the source register 206 for which the instruction is to shift the source, the identifier being given in BIT SIZE. Executing the shift instruction 204 may include an iterative shift of the source word 210 of the source register 206. The iterative shifting of the source word 210 of the source register 206 may include a given iteration.

A given iteration of the shift may include selecting the N-1 word of the source word 210. In the left shift, the N-1 st word may be the most significant word that has not yet been processed. In the right shift, the N-1 st word may be the least significant word that has not yet been processed. The selected N-1 st word 210 (N-1) may be shifted left or right by a number of BITs according to BIT SIZE using instruction 216. This may result in an N-1 th intermediate word 220 (N-1) and an N-1 th group shifted-out bit 222 (N-1). In addition, instruction 214 may be used to shift the nth word (labeled 210N) left or right according to BIT SIZE. This may result in an nth intermediate word 220N and an nth set of shift-out bits 222N. The N-1 th intermediate word 220 (N-1) may be operated on with a logical OR 218 having an N-th set of shift-out bits 222N to produce an N-1 th target word 212N. The shift-out bit may be replaced with zero. The N-1 th most significant target word 212 (N-1) may be stored in the target register 208 as a corresponding one of the target words 212. The logical OR 218 may be implemented in hardware.

An iterative shift from the least significant word of the source word 210 to the most significant word of the source word 210 may be performed.

The target register 208 and the register containing the intermediate word 220 may be the same register, with either 218 being performed in place, and the result written back into the register containing the intermediate word 220.

Fig. 3 is a diagram of the execution of a processor 300 of a variable precision multi-bit shift or rotate instruction according to an example of the present disclosure. Processor 300 may implement, in whole or in part, processor 102 or processor 202 executing shift instruction 106 or 204. The processor 300 may execute instructions 302 that may implement the instructions 106, 204 in whole or in part. Instruction 302 may support multi-bit shifting or rotation of data of any precision and thus width.

The instruction 302 may be a left shift or a right shift. In the example of fig. 3, instruction 302 may be executed as a right shift. Instruction 302 may shift the content from source word 304 and store the result in result word 306. Source word 304 may implement source data 108 or source registers 206 in whole or in part. The result word 306 may implement, in whole or in part, the result word 120 or the destination register 208. The source word 304 and the result word 306 may be stored within the processor 300 or may not be stored within the processor 300. During execution of the instruction 302, the results may be stored in the intermediate word 310. The intermediate word 310 may implement the intermediate words 114, 118, 222 in whole or in part. In some examples, intermediate word 310 may be included in an intermediate register. In some examples, the register including result word 306 and the register including intermediate word 310 may be the same register, with either or 316 being performed in place and the result being written back into the register containing intermediate word 310.

Processor 300 may include shifter logic 308. Shifter logic 308 may be implemented by analog circuitry, digital circuitry, or any suitable combination thereof to implement shift and rotate instructions. Shifter logic 308 may be configured to execute iterative shift instructions. Although a single instance of shifter logic 308 is shown, any suitable number of instances of shifter logic 308 may be used.

Registers including source word 304, intermediate word 310, or result word 306 may be included in processor 300 or in a memory accessible to processor 300.

Instruction 302 may specify a left shift or right shift operation, a SOURCE denoted SOURCE, a target denoted destation, and an indicator of the bits for which the instruction will shift the SOURCE and store the result in the target. The indicator may be given as BIT SIZE. For example, instruction 302 may be given as "shift, w3:w0, w9:w6,12", where the contents of register or concatenated register w3:w0 may be shifted 12 bits to the right and the result stored in register or concatenated register w9:w6.

An exemplary value for W3:W0 is shown in FIG. 3, which may be source word 304. An exemplary value for W3:W0 may be 128 bits long and may be 89abcdef01234567fedcba9876543210.0x89abcdef may be stored in W3, 0x01234567 may be stored in W2, 0xfedcba98 may be stored in W1, and 0x76543210 may be stored in W0.

The processor 300 may be configured to iteratively execute the instructions 302 using a series of shift instructions. The series of shift instructions may be conventional arithmetic, logic, or other suitable shift instructions. The number of shift instructions used to iteratively execute instructions 302 may depend on the number of source words 304. For example, for four source words 304, the processor 300 may be configured to iteratively execute the instructions 302 using four constituent shift instructions. Thus, the instruction 302 may shift or rotate data that is larger than the data directly supported by the native or existing byte or word shift or rotate instruction of the processor. Examples of the present disclosure may include a constituent shift instruction to execute instruction 302 that effectively performs a multi-bit shift or rotation of data having a size that is larger than the native data size of the processor. For example, the native data size may be, for example, 32 bits, and the instruction 302 may rotate or shift 128 bits or more of data. Examples of the present disclosure may include constituent shift instructions that may be executed in two cycles or less. The sequence of constituent shift instructions that are executed to implement instruction 302 may require fewer execution cycles than other solutions.

The constituent shift instructions to execute instruction 302 may include a logical right shift (LSR), a logical Left Shift (LSL), an arithmetic right shift (ASR), and an arithmetic left shift (ASL). The iterative shift instruction may include an execution option such as ". L", ". W", or ". B" to specify the length of the constituent registers. For example, ".L" may specify an operation on a 32-bit long word, ".W" may specify an operation on a 16-bit long word, and ". B" may specify an operation on an 8-bit long word. Furthermore, the iterative shift instruction may inherently or with an execution option specify whether BIT SIZE is referenced as a specified constant value, has a fixed SIZE specified in another way (such as inherently through a particular instance of an iterative shift function), or is referenced in a memory location such as a register.

Further, in one example, the constituent shift instructions to execute instruction 302 may include a shift instruction in which the shift-out bit 318 from another shift instruction is used. The shift-out bits 318 may be generated from bits shifted out of the source word 304 to which the shift instruction has been applied. The shift-out bit 318 may implement the shift-out bits 116, 222 in whole or in part. The shift-out bit 318 may be combined with the result of an immediately preceding shift operation (such as the intermediate word 310) to produce a result (such as the result word 306). In one example, the shift-out bit 318 may be captured and stored in digital logic of the shifter 308 without external storage in a register. In the example of fig. 3, merging is shown with or function 316. Or function 316 may be implemented in digital logic.

Shifter 308 may be configured to shift out the number of bits specified by the constituent shift instruction. The memory locations within shifter 308 including shift-out bit 318 may have a value of zero. The contents of constituent shift-out bits 318 from shifter 308 may be written to intermediate word 310. Those contents and memory locations of shifter 308 that are shifted but not shifted out to make up shift-out bit 318 may retain their existing values. Such bits may therefore remain in shifter 308 after performing the shift-out. This functionality may be used such that bits remaining in shifter 308 after performing the shift-out may be combined with the contents of OR function 316 and intermediate word 310 with the immediately previously shifted word, where such bits are reserved.

The constituent shift instruction may specify (a) that the contents of source word 304 are shifted and the result written to intermediate word 310, and (B) that shift-out bit 318 of the shift operation, when resident in shifter 308, is to be combined with previous intermediate word 310 using or function 316, to be executed by the same constituent shift instruction. This may be performed in two execution cycles. Such constituent shift instructions may be specified in any manner, such as a separate instruction or a flag or other designation on a conventional shift instruction. Such instructions of the present disclosure may be referred to by an "M" designation at the end of the instruction name.

Or the result of function 316 may be written to the corresponding result word 306. In one example, the result word 306 may be identical to the intermediate word 310 implemented in the same register, such that the or function 316 is applied to the intermediate word 310 where the result is stored in place.

In the example of fig. 3, instruction 302 may be configured to shift the contents of a specified portion of quad-word wide or long data, i.e., the contents of registers W3, W2, W1, W0, to the right. The target of the shift may be the four word width or the contents of the long-registers W9, W8, W7, W6. The data may be shifted 12 bits to the right.

Thus, the processor 300 may load a shift instruction 302, wherein the shift instruction 302 causes SOURCE data in memory as SOURCE words 304 to be shifted to the right, the SOURCE data comprising a plurality of SOURCE words 304, and the shift instruction 302 comprises a SOURCE parameter, such as SOURCE, for identifying the SOURCE data and a BIT SIZE parameter, such as BIT SIZE, for identifying a specified number of BITs to which the SOURCE data is to be shifted.

To implement instruction 302, the processor may execute four iterative shift instructions, one for each word. Iterative shift instructions that are part of instruction 302 may include lsr.1, LSRM, and ASRM. Lsr.1 may be a logical right shift of data of word length. The LSRM may be a logical right shift with a merge operation to merge the shift-out bit 318 with the previously shifted intermediate word 310. ASRM may be similar to LSRM except that the sign of a word is shifted into bits, rather than a value of "0" being shifted into bits. When shifting words during the last iterative shift operation, ASRM may be used in order to preserve the resulting data symbols.

Source word 304 may include the contents of register w3:w0. Intermediate word 310 and result word 306 may include the contents of registers W9:W6.

The right shift operation may operate from the least significant word to the most significant word. Thus, instruction 302 may be executed by first executing an instruction that shifts W0 by BIT SIZE and places the content in W6. The instruction lsr.1w0, #12, W6 can shift the contents of W0 right by 12 bits and put the result in W6. The shift-out bit 318A may be lost. The content of W0 may be 0x76543210, the least significant 32 bits of source word 304. After shifting with the instruction lsr.1w0, #12, W6 may comprise 0x00076543, where the value 0 is shifted into bits.

Next, instruction 302 may continue by executing the instruction of shifting W1 by BIT SIZE and placing the content in W7, and further causing shift-out BIT 318B to reside in shifter 308 and be combined with the content of W6 using OR function 316 and storing the result in result word 306. Or the result of the function may be stored in the appropriate location in W6. LSRM W1, #12, W7 can be used. The content of W1 may be the next most significant bit 0xfedcba98 of source word 304. After shifting with instructions LSRM W1, #12, W7 may comprise 0x000fedcb, where the value of 0 is shifted into bits. The shifted-out bit values 318B may be 0xa98 and these values may be stored in shifter 308 while the remaining shifters 308 may have stored value 0 because such values are in the memory locations where the content was shifted out of bits. The contents of shifter 308 may then be combined with W6 using or function 316 and the result stored back in W6. This may be a value of 0xa 9876543. W6 may also be a result word 306.

Thus, the shifting of a first source word, such as source word W0, of source data of source word 304 may be performed by a specified number of BITs BIT SIZE to produce a first intermediate word, such as W6. Further, a shift of a second source word, such as W1, may result in a second intermediate word, such as W7, and a first set of shifted-out bits, such as 318B. In addition, the logical OR operation performed by OR function 316 may be performed on a first intermediate word, such as W6, and a first set of shifted-out bits, such as 318B, to produce a first result word, such as W6, in result word 306. A logical or operation, such as or function 316, on the first intermediate word W6 and the first set of shift-out bits 318B may be performed at an appropriate location on the first intermediate word W6 to make the first intermediate word the first result word W6 stored in the result word 306. A logical or operation may be applied to the shift-out bit 318 as the most significant bit of the first intermediate word W6. BIT SIZE may be smaller than the SIZE of a given source word 304. In the example of fig. 3, the shift instruction 302 may shift source data in memory, such as source word 304, to the right, the first source word W0 may not be as efficient as the second source word W1; and shifting of the first source word W0 will be performed before shifting the second source word W7 to produce the first intermediate word W6.

Further, source word 304 may be considered to be stored in a source register and result word 306 may be considered to be stored in a destination register. The result word 306 may also be referred to as a target word. Processor 300 may execute shift instruction 302 to shift the contents of a source register that includes source word 304 and store the result in a target register that includes a target word, also referred to as result word 306. Instruction 302 may include a specified number of BITs that the source register will shift, given in BIT SIZE, and executing instruction 302 may include iteratively shifting words of the source register that include source word 304. Thus, shifting to execute the instruction 302 may include selecting an nth word of the plurality of source words 304. In the right shift, the least significant word that has not been shifted may be selected, while in the left shift, the most significant word that has not been shifted may be selected.

Shifting of an nth word, such as W1, of the plurality of source words 304 may result in an nth intermediate word, such as W7, and an nth set of shifted-out bits, such as 318B. The execution instruction 302 may include a shift of the N-1 th word, such as W0, to produce the N-1 th intermediate word, such as W6, and the N-1 th group shift-out bit, such as 318B. Executing instruction 302 may include performing a logical OR operation u, such as OR function 316, on the N-1 th intermediate word, such as W6, and the N-th group of shift-out bits, such as 318B, to produce the N-1 th target word, such as W6, in result word 306 in the target register.

Also, therefore, when the shift instruction 302 is a right shift instruction, the nth source word (such as W1) may be more efficient than the nth-1 source word (such as W0) and the shift of the nth word of the source register may be performed after the shift of the nth-1 word of the source register is performed to produce the nth intermediate word (such as W7).

Next, execution of instruction 302 may continue by executing the instruction of shifting W2 and placing the content in W8, and further causing shift-out bit 318C to still reside in shifter 308 and merging it with the content of W7 using OR function 316 and storing the result in result word 306. The results may be stored in the appropriate location in W7. LSRM W2, #12, W8 can be used. The content of W2 may be 0x01234567, the next most significant bit of source word 304. After shifting with instructions LSRM W2, #12, W8 may comprise 0x00001234, where the value 0 is shifted into bits. The shifted-out bit values 318C may be 0x567 and these values may be stored in shifter 308 while the remaining shifters 308 may store a value of 0, with the remaining content shifted. The contents of shifter 308 may then be combined with W7 using or function 316 and the result stored back into W7. This may be a value of 0x567fedcb. W7 may also be a result word 306.

Thus, executing instruction 302 may include shifting a third source word, such as W2, by a specified number of BITs provided by BIT SIZE to produce a third intermediate word, such as W8, and a second set of shifted-out BITs, such as 318C. Further, executing the instruction 302 may include a logical OR operation, such as an OR function 316, on a second intermediate word, such as W7, and a second set of shift-out bits 318C to produce a second result word, such as W7, that is stored in the result word 306.

Further, the execution instruction 302 may thus shift the N-th word (such as W2), shift the N-1 th word (such as W1), and perform a logical OR operation, such as an OR function 316, on the N-1 th intermediate word (such as W7) and the N-th set of shift-out bits (such as 318C) to produce the N-1 th target word (such as W7 in the result word 306), at least the intermediate words (such as W1 and W2) for the plurality of source words in the source register between the first word (such as W0) and the last word (such as W3) of the plurality of source words 304.

In addition, a logical OR operation, such as OR function 316, is performed on the N-1-th intermediate word (such as W7) and the N-th set of shift-out bits (such as 318C) in place of the N-1-th intermediate word, thereby making the N-1-th intermediate word the N-1-th target word, such as W7 in result word 306.

Next, execution of instruction 302 may continue by executing the instruction of shifting W3 and placing the content in W9, and further causing shift-out bit 318D to still reside in shifter 308 and merging it with the content of W8 using OR function 316 and storing the result in result word 306. The results may be stored in the appropriate location in W8. ASRM W3, #12, W9 can be used. The content of W3 may be the most significant bit 0x89abcdef of source word 304. After shifting with instructions ASRM W3, #12, W9 may include 0xFFF89abc, where the value of F is shifted into bits. By using ASRM instead of LSRM, values of F instead of 0 can be shifted into bits, and these shifted-in bit values F can be used as sign bits. The shifted-out bit value 318D may be 0xdef and these may be stored in shifter 308, while the remaining shifters 308 may store a value of 0, with the remaining content shifted. The contents of shifter 308 may then be combined with W8 using or function 316 and the result stored back into W8. This may be a value of 0xdef 01234. W8 may also be a result word 306. Further, when the execution of instruction 302 ends, the result stored in W9 may also be a result word 306.

Thus, executing instruction 302 may include shifting the last source word, such as W3, by a specified number of BITs specified by BIT SIZE to produce the last result word W9 and the last set of shifted-out BITs, such as 318D. Further, executing instruction 302 may include performing a logical OR operation, such as OR function 316, on the penultimate intermediate word, such as W8, and the last set of shifted-out bits, such as 318D, to produce the penultimate result word W8 stored in result word 306.

Further, executing instruction 302 may include shifting a last source word (such as W3) of the source register by a specified number of BITs (such as BIT SIZE) to produce a last target result word (such as W9) and a last set of shifted-out BITs (such as 318D), and performing a logical or operation (such as or function 316) on a next-to-last intermediate word (such as W8) and a last set of shifted-out BITs (such as 318D) may produce a next-to-last target word (such as W8 stored in result word 306).

Fig. 4 is a diagram of execution of a left shift instruction processor 300 that is similar to the right shift operation shown in fig. 3, according to an example of the present disclosure.

Instruction 402 may be a left shift instruction. Instruction 402 may shift the content from source word 304 and store the result in result word 306. During execution of instruction 402, the results may be stored in intermediate word 310.

Instruction 402 may specify a left shift or right shift operation, a SOURCE denoted SOURCE, a target denoted destation, and a plurality of bits of indicators by which the instruction will shift the SOURCE and store the result in the target. The indicator may be given as BIT SIZE. For example, instruction 402 may be given as "SHIFTR, W3:W0, W9:W6,12", where the contents of register or concatenated register W3:W0 may be left shifted by 12 bits, and the result stored in register or concatenated register W9:W6.

Exemplary values for W3:W0 are shown in FIG. 4, which may be the same as that shown in FIG. 3. An exemplary value may be 128 bits long and may be 89abcdef01234567fedcba9876543210.0x89abcdef may be stored in W3, 0x01234567 may be stored in W2, 0xfedcba98 may be stored in W1, and 0x76543210 may be stored in W0.

The processor 300 may be configured to iteratively execute the instructions 402 using a series of shift instructions. The series of shift instructions may be conventional arithmetic, logic, or other suitable shift instructions. The number of shift instructions used to iteratively execute instructions 402 may depend on the number of source words 304. For example, for four source words 304, the processor 300 may be configured to iteratively execute the instruction 402 using four constituent shift instructions. Thus, the instruction 402 may shift or rotate data that is larger than the data directly supported by the native or existing byte or word shift or rotate instruction of the processor. Examples of the present disclosure may include a constituent shift instruction to execute instruction 402 effective to perform a multi-bit shift or rotation of data having a size greater than a native data size of a processor. For example, the native data size may be, for example, 32 bits, and the instruction 402 may rotate or shift 128 bits or more of data. Examples of the present disclosure may include constituent shift instructions that may be executed in two cycles or less. The sequence of constituent shift instructions that are executed to implement instruction 402 may require fewer execution cycles than other solutions.

The constituent shift instructions of the execution instruction 402 may include a left Shift (SL). The iterative shift instruction may include an execution option such as ". L", ". W", or ". B" to specify the length of the constituent registers. For example, ".L" may specify an operation on a word that is 32 bits long. Furthermore, the iterative shift instruction may inherently or with an execution option specify whether BIT SIZE is referenced as a specified constant value, has a fixed SIZE, or is referenced in a memory location such as a register.

Further, in one example, the constituent shift instructions to execute instruction 402 may include a shift instruction in which the shift-out bit 318 from another shift instruction is used. The shift-out bits 318 may be generated from bits shifted out of the source word 304 to which the shift instruction has been applied. The shift-out bit 318 may implement the shift-out bits 116, 222 in whole or in part. The shift-out bit 318 may be combined with the result of an immediately preceding shift operation (such as the intermediate word 310) to produce a result (such as the result word 306). In one example, the shift-out bit 318 may be captured and stored in digital logic of the shifter 308 without external storage in a register. In the example of fig. 4, merging is shown with or function 316. Or function 316 may be implemented in digital logic.

Shifter 308 may be configured to shift out the number of bits specified by the constituent shift instruction. The memory locations within shifter 308 including shift-out bit 318 may have a value of zero. The contents of constituent shift-out bits 318 from shifter 308 may be written to intermediate word 310. Memory locations within shifter 308 that do not include those bits to be shifted out by the constituent shift instruction may retain their existing values. Such bits may therefore remain in shifter 308 after performing the shift-out. This functionality may be used such that bits remaining in shifter 308 after performing the shift-out may be combined with the contents of OR function 316 and intermediate word 310 with the immediately previously shifted word, where such bits are reserved.

The constituent shift instruction may specify (a) that the contents of source word 304 are shifted and the result written to intermediate word 310, and (B) that shift-out bit 318 of the shift operation, when resident in shifter 308, is to be combined with previous intermediate word 310 using or function 316, to be executed by the same constituent shift instruction. This may be performed in two execution cycles. Such constituent shift instructions may be specified in any manner, such as a separate instruction or a flag or other designation on a conventional shift instruction. Such instructions of the present disclosure may be referred to by an "M" designation at the end of the instruction name.

Or the result of function 316 may be written to the corresponding result word 306. In one example, the result word 306 may be identical to the intermediate word 310 implemented in the same register, such that the or function 316 is applied to the intermediate word 310 where the result is stored in place.

The example of fig. 4 may differ from fig. 3 in that, in contrast to the iterative shifting of the least significant word to the most significant word with the constituent shift instruction as shown in fig. 3, the word is iteratively shifted from the most significant word (i.e., W3) to the least significant word (i.e., W0) with the constituent shift instruction as shown in fig. 4 to achieve a left shift.

In the example of fig. 4, instruction 402 may be configured to shift the contents of the specified portion of quad-word wide or long data-the contents of registers W3, W2, W1, W0-to the left. The target of the shift may be the four word width or the contents of the long-registers W9, W8, W7, W6. The data may be shifted 12 bits to the right.

Thus, processor 300 may load shift instruction 402, where shift instruction 402 causes SOURCE data in memory as SOURCE words 304 to be shifted to the left, the SOURCE data including a plurality of SOURCE words 304, and shift instruction 302 includes a SOURCE parameter, such as SOURCE, for identifying the SOURCE data and a BIT SIZE parameter, such as BIT SIZE, for identifying a specified number of BITs that SOURCE words 304 are to be shifted.

To implement instruction 402, processor 300 may execute four iterative shift instructions, one for each word. The iterative shift instructions that are part of instruction 402 may include SLM and sl.1.Sl.1 may be the left shift of the word length data. The SLM may be a shift-left merge operation to merge the shifted-out bits 318 with the previously shifted intermediate word 310.

Source word 304 may include the contents of register w3:w0. Intermediate word 310 and result word 306 may include the contents of registers W9:W6.

The left shift operation may operate from the most significant word to the least significant word.

Thus, instruction 402 may be executed by first executing an instruction that shifts W3 and places content in W9. The shift-out bit 318D may be discarded. The content of W3 may be the most significant 32 bits 0x89abcdef of source word 304. After shifting W3, #12, W9 with instruction sl.1, W9 may include 0xbcdef000, where the value 0 is shifted into bits.

Next, execution of instruction 402 may continue by executing the instruction of shifting W2 and placing the content in W8, and further causing shift-out bit 318C to remain resident in shifter 308 and merging it with the content of W9 using OR function 316 and storing the result in result word 306. The results may be stored in the appropriate location in W9. The SLMs W2, #12, W8 can be used. The content of W2 may be the next most significant bit 0x01234567 of source word 304. After shifting with the instruction SLM W2, #12, W8 may comprise 0x34567000, where the value 0 is shifted into bits. The shift-out bit values 318C may be 0x012 and these values may be stored in shifter 308 while the remaining shifters 308 may store a value of 0, with the remainder shifted. The contents of shifter 308 may then be combined with W9 using or function 316 and the result stored back into W9. This may be a value of 0xbcdef 012. W9 may also be a result word 306.

Thus, a shift of a first source word, such as source word W3, of source data of source word 304 may be performed by a specified number of BITs BIT SIZE to produce a first intermediate word, such as W9. Further, a shift of a second source word, such as W2, may result in a second intermediate word, such as W8, and a first set of shifted-out bits, such as 318C. In addition, the logical OR operation performed by OR function 316 may be performed on a first intermediate word, such as W9, and a first set of shifted-out bits, such as 318C, to produce a first result word, such as W9, in result word 306. A logical or operation, such as or function 316, on the first intermediate word W9 and the first set of shift-out bits 318C may be performed at an appropriate location on the first intermediate word W9 to make the first intermediate word the first result word W9 stored in the result word 306. A logical or operation may be applied to the shift-out bit 318C as the least significant bit of the first intermediate word W9. BIT SIZE may be smaller than the SIZE of a given source word 304. In the example of fig. 4, the shift instruction 302 may cause source data in memory, such as source word 304, to be shifted to the left, the first source word W3 being potentially more efficient than the second source word W2; and shifting of the first source word W3 will be performed before shifting the second source word W9 to produce the first intermediate word W2.

Further, source word 304 may be considered to be stored in a source register and result word 306 may be considered to be stored in a destination register. The result word 306 may also be referred to as a target word. Processor 300 may execute shift instruction 302 to shift the contents of a source register that includes source word 304 and store the result in a target register that includes a target word, also referred to as result word 306. Instruction 302 may include a specified number of BITs that the source register will shift, given in BIT SIZE, and executing instruction 302 may include iteratively shifting words of the source register that include source word 304. Thus, shifting to execute the instruction 302 may include selecting an nth word of the plurality of source words 304. In the right shift, the least significant word that has not been shifted may be selected, while in the left shift, the most significant word that has not been shifted may be selected.

Shifting of an nth word, such as W2, of the plurality of source words 304 may result in an nth intermediate word, such as W8, and an nth group of shifted-out bits, such as 318C. The execution instruction 302 may include a shift of the N-1 th word, such as W3, to produce the N-1 th intermediate word, such as W9, and the N-1 th group shift-out bit, such as 318D. Executing the instruction 302 may include performing a logical OR operation, such as an OR function 316, on the N-1 th intermediate word, such as W9, and the N-th group of shift-out bits, such as 318C, to generate the N-1 th target word, such as W9, in the result word 306 in the target register.

Also, therefore, when the shift instruction 302 is a left shift instruction, the nth source word (such as W2) may not be as efficient as the N-1 th source word (such as W3), and the shift of the nth word of the source register may be performed after the shift of the N-1 th word of the source register is performed to produce the nth intermediate word (such as W8).

Next, execution of instruction 402 may continue by executing the instruction of shifting W1 and placing the content in W7, and further causing shift-out bit 318B to remain resident in shifter 308 and merging it with the content of W8 using OR function 316 and storing the result in result word 306. The results may be stored in the appropriate location in W8. The SLMs W1, #12, W7 can be used. The content of W1 may be the next least significant bit 0xfedcba98 of source word 304. After shifting with the instruction SLM W1, #12, W7 may comprise 0xcba98000, where the value 0 is shifted into bits. Shifted-out bit value 318B may be 0xfed and these values may be stored in shifter 308 while the remaining shifters 308 may store a value of 0, with the remaining content shifted. The contents of shifter 308 may then be combined with W8 using or function 316 and the result stored back into W8. This may be the value 0xcba 98765. W8 may also be a result word 306.

Thus, executing instruction 302 may include a shift that may be applied to a third source word such as W1 provided by BIT SIZE, may result in a third intermediate word such as W7, and a second set of shift-out BITs such as 318B. Further, executing the instruction 302 may include a logical OR operation, such as an OR function 316, on a second intermediate word, such as W8, and a second set of shift-out bits 318B to produce a second result word, such as W8, that is stored in the result word 306.

Further, the execution instruction 302 may thus shift the N-1 th word (such as W1), shift the N-1 th word (such as W2), and perform a logical OR operation, such as an OR function 316, on the N-1 th intermediate word (such as W8) and the N-th set of shift-out bits (such as 318B) to produce the N-1 th target word (such as W8 in the result word 306), at least the intermediate words (such as W1 and W2) for the plurality of source words in the source register between the first word (such as W3) and the last word (such as W0) of the plurality of source words 304.

In addition, a logical OR operation, such as OR function 316, is performed on the N-1-th intermediate word (such as W8) and the N-th set of shift-out bits (such as 318B) in place of the N-1-th intermediate word, thereby making the N-1-th intermediate word the N-1-th target word, such as W8 in result word 306.

Finally, execution of instruction 402 may continue by executing the instruction of shifting W0 and placing content in W6, and further causing shifted-out bit W6 to still reside in shifter 308 and merging it with the content of W7 using OR function 316 and storing the result in result word 306. The results may be stored in the appropriate location in W7. The SLMs W0, #12, W6 can be used. The content of W0 may be the least significant bit 0x76543210 of source word 304. After shifting with the instruction SLM W0, #12, W6 may comprise 0x43210000, where the value 0 is shifted into bits. W6 may be stored as result word 306. The shift-out bit value 318A may be 0x765 and these may be stored in shifter 308, while the remaining shifters 308 may store a value of 0, with the remaining content shifted. The contents of shifter 308 may then be combined with W7 using or function 316 and the result stored back into W7. This may be the value 0xcba 98765. W7 may also be a result word 306.

Thus, executing instruction 302 may include shifting the last source word, such as W0, by a specified number of BITs specified by BIT SIZE to produce the last result word W6 and the last set of shifted-out BITs, such as 318A. Further, executing instruction 302 may include performing a logical OR operation, such as OR function 316, on the penultimate intermediate word, such as W7, and the last set of shifted-out bits, such as 318A, to produce the penultimate result word W7 stored in result word 306.

Further, executing instruction 302 may include shifting the last source word (such as W0) of the source register by a specified number of BITs (such as BIT SIZE) to produce the last target result word (such as W6) and the last set of shifted-out BITs (such as 318A), and performing a logical or operation (such as or function 316) on the next-to-last intermediate word (such as W7) and the last set of shifted-out BITs (such as 318A) to produce the next-to-last target word (such as W7 stored in result word 306).

As indicated above, the instructions 302, 402 may support multiple word shift instructions. These instructions may be accelerated as compared to performing multiple shifts in other software solutions, as multiple registers may need to be used in such other software solutions. As indicated above, the instructions 302, 402 may be implemented by a constituent instruction, which is a set of 2-cycles, cascaded shifts, and logical or instructions that may be used with the shifter 302. The number of constituent instructions to implement a given instruction 302, 402 may depend on the size of shifter 308.

The instructions 302, 402 may be used or modified to effect rotation by using the data shift-out bits 318 from the executed first constituent instruction, where the shift-out bits 318 would otherwise be discarded. The shift-out bit 318 may be saved in any suitable register or memory and may be restored to any suitable location after iterative execution of the constituent instructions.

Fig. 5 is an illustration of an example method 500 for executing a variable precision multi-bit shift instruction according to an example of the present disclosure.

Method 500 may be performed with more or fewer steps than shown in fig. 5. The steps of method 500 may optionally be repeated, omitted, performed in a different order, performed recursively, performed in parallel, or multiple instances of method 500 may be performed in parallel. Method 500 may be performed by any suitable mechanism, such as those of fig. 1-4. In particular, the method 500 may be performed by the processor 102, 202, 300 or the microcontroller 200.

At 505, a shift instruction may be loaded. The shift instruction may cause source data in memory to be shifted to the left or to the right. The source data may include source words. The shift instruction may include a source parameter for identifying source data. The shift instruction may include a bit size parameter for a specified number of bits that the source data is to be shifted.

At 510, a shift instruction may be executed by shifting a first source word of source data by a specified number of bits to produce a first intermediate word.

At 515, the shift instruction may continue by shifting the second source word of the source data by a specified number of bits to produce a second intermediate word and a first set of shifted-out bits.

At 520, the shift instruction may continue by performing a logical OR operation on the first intermediate word and the first set of shift-out bits to produce a first result word. If the shift instruction shifts the source word right, the intermediate word may contain the shifted source word as the least significant bit and the shift-out bit may be the most significant bit. If the shift instruction shifts the source word to the left, the intermediate word may contain the shifted source word as the most significant bit and the shift-out bit may be the least significant bit.

Fig. 6 is a more detailed illustration of an exemplary method 600 for executing a multi-bit shift instruction according to an example of the present disclosure.

Method 600 may be performed with more or fewer steps than shown in fig. 6. The steps of method 600 may be optionally repeated, omitted, performed in a different order, performed recursively, performed in parallel, or multiple instances of method 600 may be performed in parallel. Method 600 may be performed by any suitable mechanism, such as those of fig. 1-4. In particular, the method 600 may be performed by the processor 102, 202, 300 or the microcontroller 200. Method 600 may be a more detailed implementation of method 500 of fig. 6.

At 605, a shift instruction may be loaded. The shift instruction may cause source data in memory to be shifted to the left or to the right. The source data may include source words. The shift instruction may include a source parameter for identifying source data. The shift instruction may include a bit size parameter for a specified number of bits that the source data is to be shifted. The specified number of bits may be smaller than the word.

At 610, a shift instruction may be executed by shifting a first source word of source data by a specified number of bits to produce a first intermediate word.

At 615, the shift instruction may continue by shifting the second source word of the source data by a specified number of bits to produce a second intermediate word and a first set of shifted-out bits.

At 620, the shift instruction may continue by performing a logical OR operation on the first intermediate word and the first set of shift-out bits to produce a first result word. A logical or operation may be performed at the appropriate location of the first intermediate word to make the first intermediate word the first result word. An or operation may be performed on the first set of shifted-out bits that are the most significant bits.

At 625, execution of the shift instruction may continue by shifting the third source word of the source data by a specified number of bits to produce a third intermediate word and a second set of shifted-out bits. A logical OR operation is performed on the second intermediate word and the second set of shift-out bits to produce a second result word.

At 630, step 625 may be repeated for additional source words until the last source word is reserved.

At 635, the shift instruction may continue by shifting the last source word of the source data by a specified number of bits to produce the last result word and the last set of shifted-out bits. Logical OR operations may be performed on the penultimate intermediate word and the last set of shifted-out bits to produce the penultimate result word.

Examples of the present disclosure include an article of manufacture comprising a non-transitory machine-readable medium. The medium may include instructions. The instructions, when read and executed by the processor, may cause the processor to execute a shift instruction.

In combination with any of the above examples, the shift instruction may cause source data in the memory or source register to shift left or right. The source data or source register may include a plurality of source words. The shift instruction may include a source parameter or a source register for identifying source data. The shift instruction may include a bit size parameter for identifying a specified number of bits for the source data or source register to be shifted. Performing a shift of a specified number of bits of a first source word that may include the source data or source register to produce a first intermediate word, the shift of a specified number of bits of a second source word of the source data or source register to produce a second intermediate word and a set of shifted-out bits, and performing a logical OR operation of the first intermediate word and the first set of shifted-out bits to produce a first result word.

In combination with any of the above examples, the instructions may cause the processor to execute the shift instruction by shifting a specified number of bits of a third source word of the source data or source register to generate a third intermediate word and a second set of shift-out bits, and performing a logical OR operation on the second intermediate word and the second set of shift-out bits to generate a second result word.

In combination with any of the above examples, the instructions may cause the processor to execute the shift instruction by shifting a last source word of the source data or the source register by a specified number of bits to produce a last result word and a last set of shift-out bits, and performing a logical OR operation on the penultimate intermediate word and the last set of shift-out bits may produce the penultimate result word.

In combination with any of the above examples, performing a logical or operation on the first intermediate word and the first set of shift-out bits may be performed in place of the first intermediate word such that the first intermediate word is the first result word.

In combination with any of the above examples, the logical OR operation may use the first set of shifted-out bits as the most significant bits.

In combination with any of the above examples, the specified number of bits is a number of bits that is less than a word size of the source word.

In combination with any of the above examples, the shift instruction may cause source data or source registers in the memory to shift to the left, the first source word may be more efficient than the second source word, and the shifting of the first source word may be performed prior to the shifting of the second source word to produce the first intermediate word.

In combination with any of the above examples, the source register may have the capacity of multiple source words. The destination register may have the capacity of a plurality of destination words. The shift instruction may be to shift the contents of the source register and store the result in the destination register. The shift instruction may include an identifier of a specified number of bits to be shifted by the source register. The execution may include an iterative shift of the words of the source registers. The iterative shifting may include shifting of an nth word of the plurality of source words, which may result in an nth intermediate word and an nth set of shifted-out bits. Shifting of the N-1 th word of the plurality of source words may result in the N-1 th intermediate word and the N-1 th group shifted-out bit. Logical OR operations are performed on the N-1 th intermediate word and the N-th set of shift-out bits to generate the N-1 th target word for the target register.

In combination with any of the above examples, the processor may shift the nth word, shift the N-1 th word, and perform a logical or operation on the N-1 th intermediate word and the nth group shift bit to generate the N-1 th target word for at least the intermediate word of the plurality of source words in the source register between the first word and the last word of the plurality of source words.

In combination with any of the above examples, the processor may execute the shift instruction by shifting a last source word of the source register by a specified number of bits to produce a last target result word and a last set of shift-out bits, and performing a logical OR operation on a penultimate intermediate word and the last set of shift-out bits to produce a penultimate target word. In combination with any of the above examples, performing a logical OR operation on the N-1 th intermediate word and the N-th group shift-out bit may be performed at an appropriate position of the N-1 th intermediate word such that the N-1 th intermediate word becomes the N-1 th target word.

In combination with any of the above examples, the nth source word may be more efficient than the N-1 th source word, the shift instruction may be a right shift instruction, and the shifting of the nth word of the source register may be performed after the shifting of the N-1 th word of the source register is performed to generate the nth intermediate word.

In combination with any of the above examples, the nth source word may not be as efficient as the N-1 th source word, the shift instruction may be a left shift instruction, and the shift of the nth word of the source register may be performed after the shift of the N-1 th word of the source register is performed to produce the nth intermediate word.

Examples of the present disclosure may include a microcontroller. The microcontroller may include a source register and a destination register to include a source word and a destination word, respectively. The microcontroller may include a processor to execute any of the shift instructions of any of the above examples.

Examples of the present disclosure may include methods of executing any of the instructions of the examples above. Examples of the present disclosure may include the operation or execution or method of any of the microcontrollers described above.

Embodiments of the present disclosure may include a method. The method may include executing a shift instruction. The shift instruction may cause source data in memory to be shifted to the left or to the right. The source data may include a plurality of source words, and the shift instruction includes a source parameter for identifying the source data. The shift instruction may include a bit size parameter for a specified number of bits that the source data is to be shifted. Executing the shift instruction may include: the method includes performing a logical shift function of a specified number of bits of a first source word of source data to produce a first intermediate word, performing a logical shift function of a specified number of bits of a second source word of source data to produce a second intermediate word and a first set of shift-out bits, and performing a logical OR operation on the first intermediate word and the first set of shift-out bits to produce a first result word.

In combination with any of the above examples, the method may include performing the shift instruction by performing a shift of a specified number of bits of a third source word of the source data to generate a third intermediate word and a second set of shift-out bits, and performing a logical OR operation on the second intermediate word and the second set of shift-out bits to generate a second result word.

In combination with any of the above examples, the method may include performing a shift instruction by performing a shift of a last source word of the source data by a specified number of bits to produce a last result word and a last set of shift-out bits, and performing a logical OR operation on a penultimate intermediate word and the last set of shift-out bits to produce a penultimate result word.

In combination with any of the above examples, the method may include performing a logical or operation on the first intermediate word and the first set of shift-out bits at an appropriate location of the first intermediate word to make the first intermediate word a first result word.

In combination with any of the above examples, the method may include applying a logical or operation using the first set of shifted-out bits as the most significant bits.

In combination with any of the above examples, the specified number of bits may be a number of bits that is less than a word size of the source word.

In combination with any of the above examples, the shift instruction may shift source data in the memory to the left, the first source word may be more efficient than the second source word, and the method may be included shifting the first source word before shifting the second source word to produce the first intermediate word.

Although an illustrative example has been described above,

other variations and examples may be made from the disclosure without departing from the spirit and scope of these examples.

Claims (20)

1. An article of manufacture comprising a non-transitory machine-readable medium, the medium comprising instructions that when read and executed by a processor cause the processor to execute a shift instruction that causes source data in a memory to be shifted left or right, the source data comprising a plurality of source words, the shift instruction comprising a source parameter for identifying the source data, the shift instruction comprising a bit size parameter for identifying a specified number of bits that the source data is to be shifted by:

shifting a first source word of the source data by the specified number of bits to produce a first intermediate word;

shifting a second source word of the source data by the specified number of bits to produce a second intermediate word and a first set of shifted-out bits; and

A logical or operation is performed on the first intermediate word and the first set of shifted-out bits to produce a first result word.

2. The article of manufacture of claim 1, wherein the instructions cause the processor to execute the shift instruction by:

shifting a third source word of the source data by the specified number of bits to produce a third intermediate word and a second set of shifted-out bits; and

a logical or operation is performed on the second intermediate word and the second set of shifted-out bits to produce a second result word.

3. The article of manufacture of any of claims 1-2, wherein the instructions cause the processor to execute the shift instruction by:

shifting a last source word of the source data by the specified number of bits to produce a last result word and a last set of shifted-out bits;

a logical or operation is performed on the penultimate intermediate word and the last set of shifted-out bits to produce the penultimate result word.

4. An article of manufacture as claimed in any of claims 1 to 3, wherein performing the logical or operation on the first intermediate word and the first set of shift-out bits is performed at an appropriate location of the first intermediate word to make the first intermediate word the first result word.

5. The article of manufacture of any of claims 1-4, wherein the logical or operation uses the first set of shift-out bits as the most significant bits.

6. The article of manufacture of any of claims 1 to 5, wherein the specified number of bits is a number of bits less than a word size of the source word.

7. The article of any one of claims 1 to 6, wherein:

the shift instruction causes the source data in memory to shift to the left;

the first source word is more efficient than the second source word; and is also provided with

The shifting of the first source word will be performed before the shifting of the second source word to produce the first intermediate word.

8. A method, the method comprising:

executing a shift instruction that causes source data in a memory to be shifted left or right, the source data comprising a plurality of source words, the shift instruction comprising a source parameter for identifying the source data, the shift instruction comprising a bit size parameter for a specified number of bits to be shifted by the source data; and

the shift instruction is executed by:

performing a logical shift function of the specified number of bits of the first source word of source data,

To generate a first intermediate word;

performing a logical shift function of the specified number of bits of a second source word of the source data to produce a second intermediate word and a first set of shifted-out bits; and

a logical or operation is performed on the first intermediate word and the first set of shifted-out bits to produce a first result word.

9. The method of claim 8, the method comprising executing the shift instruction by:

performing a shift of the specified number of bits of a third source word of the source data to produce a third intermediate word and a second set of shifted-out bits; and

a logical or operation is performed on the second intermediate word and the second set of shifted-out bits to produce a second result word.

10. The method of any of claims 8 to 9, the method comprising executing the shift instruction by:

performing a shift of the specified number of bits of a last source word of the source data to produce a last result word and a last set of shifted-out bits;

a logical or operation is performed on the penultimate intermediate word and the last set of shifted-out bits to produce the penultimate result word.

11. A method according to any one of claims 8 to 10, comprising performing the logical or operation on the first intermediate word and the first set of shift-out bits at appropriate locations of the first intermediate word to make the first intermediate word the first result word.

12. The method of any of claims 8 to 11, comprising applying the logical or operation with the first set of shifted-out bits as the most significant bits.

13. The method of any of claims 8 to 12, wherein the specified number of bits is a number of bits less than a word size of the source word.

14. The method of any one of claims 8 to 13, wherein:

the shift instruction shifts the source data in memory to the left;

the first source word is more efficient than the second source word; and is also provided with

The method includes shifting the first source word before shifting the second source word to produce the first intermediate word.

15. A microcontroller, comprising:

a source register having the capacity of a plurality of source words;

a destination register having a capacity of a plurality of destination words; and

a processor for executing a shift instruction to shift the contents of the source register and store a result in the target register, the shift instruction including an identifier of a specified number of bits to which the source register is to be shifted, the executing including iteratively shifting words of the source register, comprising:

Shifting an nth word of the plurality of source words to produce an nth intermediate word and an nth set of shifted-out bits;

shifting an N-1 th word of the plurality of source words to generate an N-1 th intermediate word and an N-1 th group shift-out bit; and

a logical or operation is performed on the N-1 th intermediate word and the nth set of shift-out bits to generate an N-1 th target word for the target register.

16. The microcontroller according to claim 15, wherein the processor shifts the nth word, shifts the N-1 th word, and performs a logical or operation on the N-1 th intermediate word and the nth set of shift bits to generate the N-1 th target word for at least intermediate words of the plurality of source words in the source register between a first word and a last word of the plurality of source words.

17. The microcontroller according to one of claims 15 to 16, wherein the processor executes the shift instruction by:

shifting a last source word of the source register by the specified number of bits to produce a last target result word and a last set of shifted-out bits;

a logical or operation is performed on the penultimate intermediate word and the last set of shifted-out bits to produce the penultimate target word.

18. The microcontroller according to one of claims 15 to 17, wherein performing the logical or operation on an N-1 th intermediate word and the nth group of shift-out bits is performed at an appropriate position of the N-1 th intermediate word such that the N-1 th intermediate word becomes the N-1 th target word.

19. The microcontroller according to any one of claims 15 to 18, wherein:

the nth source word is more efficient than the N-1 th source word;

the shift instruction is a right shift instruction; and is also provided with

After performing the shift of the N-1 th word of the source register, performing the shift of the N-th word of the source register to generate the N-th intermediate word.

20. The microcontroller according to any one of claims 15 to 19, wherein:

the nth source word is less efficient than the N-1 th source word;

the shift instruction is a left shift instruction; and is also provided with

After performing the shift of the N-1 th word of the source register, performing the shift of the N-th word of the source register to generate the N-th intermediate word.