CN117580366A - Magnetic random access memory, manufacturing method thereof and electronic equipment - Google Patents

Abstract

A magnetic random access memory, a manufacturing method thereof and an electronic device are provided, the magnetic random access memory comprises: a plurality of memory cells distributed in an array, each memory cell comprising a magnetic tunnel junction and a read transistor, one end of each magnetic tunnel junction of the memory cells in the same row being connected to a read bit line, the other end of each magnetic tunnel junction being connected to the read transistor; a plurality of first write transistors, which are arranged in sequence in the column direction and are positioned around the memory cells, and are connected with the first write signal lines; a plurality of second write transistors arranged in sequence in a row direction around the memory cell, connected to the second write signal line; the first write signal line and the second write signal line are configured to drive a free layer of the magnetic tunnel junction through a magnetic field direction flip; wherein the read transistor is a buried gate transistor. The magnetic random access memory has the advantages of high storage density, small read current, simple structure, low manufacturing cost and the like.

Description

Magnetic random access memory, manufacturing method thereof and electronic equipment

Technical Field

The present invention relates to the field of semiconductor devices, and more particularly, to a magnetic random access memory, a method of manufacturing the same, and an electronic apparatus.

Background

Magnetic random access memory (Magnetic Random Access Memory, MRAM) is a random access memory that stores data in magnetoresistive properties. Magnetic field-inverted MRAM (toggle-MRAM) belongs to magnetic field-driven MRAM, and is the first generation of magnetic random access memory. The magnetic field overturning MRAM has the excellent characteristics of infinite erasing times, good high-temperature stability, irradiation resistance and the like, and has great application potential in the fields of aerospace, automobiles, electronics and the like.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the application.

The embodiment of the application provides a magnetic random access memory, a manufacturing method thereof and electronic equipment.

The embodiment of the application provides a magnetic random access memory, which comprises:

a plurality of memory cells distributed in an array on a substrate, each memory cell comprising a magnetic tunnel junction and a read transistor, the magnetic tunnel junction comprising a free layer capable of achieving magnetic field direction reversal;

one end of each magnetic tunnel junction of the memory cells positioned in the same row is connected with a read bit line, and the other end of each magnetic tunnel junction is connected with the read transistor; further comprises: a plurality of first write transistors sequentially arranged in a column direction at the periphery of the memory cells distributed in the array, each first write transistor being connected to one end of a first write signal line, the other end of the first write signal line being disposed on a first side of a free layer of the magnetic tunnel junction;

a plurality of second write transistors arranged in sequence in a row direction at the periphery of the memory cells distributed in the array, each of the second write transistors being connected to one end of a second write signal line, the other end of the second write signal line being disposed at a second side of the free layer of the magnetic tunnel junction opposite to the first side;

the free layer of each magnetic tunnel junction, the first write signal line arranged on the first side of the free layer, and the second write signal line arranged on the second side of the free layer have overlapping areas in projection on the substrate;

the first write signal line and the second write signal line are configured to signal a reversal of a magnetic field direction of the free layer;

wherein the read transistor is a buried gate transistor.

In an embodiment of the present application, the read transistor may include a source electrode, a drain electrode, a semiconductor layer, and a gate electrode;

the source electrode and the drain electrode are both positioned on the substrate and are arranged at intervals, and projections of the source electrode and the drain electrode on the substrate are not overlapped;

the semiconductor layer is disposed between the source electrode and the drain electrode and has a ring shape, an outer surface of the ring-shaped semiconductor layer is in contact with the source electrode and the drain electrode, and the gate electrode is located inside the ring-shaped semiconductor layer and surrounded by the ring-shaped semiconductor layer.

In an embodiment of the present application, the read transistors of two adjacent memory cells located in the same row may share one of the sources.

In an embodiment of the present application, the magnetic random access memory may further include a read word line extending in a column direction, the read word line being connected to the gate.

In an embodiment of the present application, the magnetic tunnel junction may further include a bottom electrode and an interconnection line, the free layer of the magnetic tunnel junction is disposed on the bottom electrode, one end of the interconnection line is connected to the bottom electrode, and the other end of the interconnection line is connected to the read transistor.

In an embodiment of the present application, the magnetic tunnel junction may further include a top electrode disposed on a side of the free layer remote from the bottom electrode, and the magnetic tunnel junction may be connected to the read bit line through the top electrode.

In an embodiment of the present application, the read bit lines may extend in a row direction.

In an embodiment of the present application, the magnetic random access memory may further include a first write signal line address decoder and driver connected to the first write transistor and a second write signal line address decoder and driver connected to the second write transistor.

The embodiment of the application also provides a manufacturing method of the magnetic random access memory, which comprises the following steps:

preparing the read transistor by adopting a process platform of a dynamic random access memory;

preparing the first writing transistor and/or the second writing transistor by adopting a process platform of the dynamic random access memory, connecting the first writing transistor with the first writing signal line, and connecting the second writing transistor with the second writing signal line;

the magnetic tunnel junction is formed and one end of the magnetic tunnel junction is connected with the read bit line, and the other end of the magnetic tunnel junction is connected with the read transistor.

The embodiment of the application also provides electronic equipment comprising the magnetic random access memory.

The magnetic random access memory provided by the embodiment of the application adopts the buried gate transistor as the reading transistor, so that the density of the reading transistor can be improved, the storage density of the magnetic random access memory is improved, and the manufacturing cost of the magnetic random access memory is reduced.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. Other advantages of the present application may be realized and attained by the structure particularly pointed out in the written description and drawings.

Drawings

The accompanying drawings are included to provide an understanding of the technical aspects of the present application, and are incorporated in and constitute a part of this specification, illustrate the technical aspects of the present application and together with the examples of the present application, and not constitute a limitation of the technical aspects of the present application.

Fig. 1 is a schematic longitudinal sectional view of a magnetic random access memory according to an exemplary embodiment of the present application;

FIG. 2 is a logic diagram of a magnetic random access memory according to an exemplary embodiment of the present application;

FIG. 3 is a schematic longitudinal cross-sectional view of another MRAM in accordance with an exemplary embodiment of the present application;

fig. 4 is a flow chart of a manufacturing process of a mram according to an exemplary embodiment of the present application.

The meaning of the individual reference symbols in the drawings is:

10-a first write transistor; 11-a second source; 12-a second drain; 13-a second semiconductor layer; 14-a second gate; 20-a second write transistor; 30-a first write signal line; 40-a second write signal line; a 50-magnetic tunnel junction; a 60-read transistor; 61-a first source; 62-a first drain; 63—a first semiconductor layer; 64-a first gate; 70-reading the bit line; 80-reading word lines; 90-bottom electrode; 100-interconnection lines; 110-top electrode; 120-dielectric; 130-a first write signal line address decoder and driver; 140-a second write signal line address decoder and driver; 150-a first set of write transistors; 160-a second set of write transistors; 170-a memory unit; 180-a substrate; 1000-memory array.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in detail hereinafter with reference to the accompanying drawings. It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be arbitrarily combined with each other.

Embodiments of the present application provide a magnetic random access memory. Fig. 1 is a schematic longitudinal sectional view of a magnetic random access memory according to an exemplary embodiment of the present application; fig. 2 is a logic circuit diagram of a magnetic random access memory according to an exemplary embodiment of the present application. As shown in fig. 1 and 2, the magnetic random access memory according to the embodiment of the present application includes: a plurality of memory cells 170, a first write transistor 10, a second write transistor 20, a first write signal line 30, and a second write signal line 40 arrayed on a substrate;

wherein, as shown in FIG. 2, each memory cell 170 comprises a magnetic tunnel junction 50 and a read transistor 60, the magnetic tunnel junction 50 comprises a free layer capable of realizing the reversal of the magnetic field direction, one end of each magnetic tunnel junction 50 of the memory cells 170 in the same row is connected with the read bit line 70 in FIG. 1 or one read bit line 70 in FIG. 2, and the other end of the magnetic tunnel junction 50 is connected with the read transistor 60; for example, the magnetic tunnel junction 50 may include, in order, a reference layer, a barrier layer, and a free layer, which may be connected to the read bit line 70 in FIG. 1, and the reference layer may be connected to the read transistor 60;

a plurality of first write transistors 10 are arranged in the column direction around the array of memory cells 170, one end (e.g., source) of each first write transistor 10 is connected to one end of a first write signal line 30, and the other end of the first write signal line 30 is arranged on a first side of the free layer of the magnetic tunnel junction 50

A plurality of second write transistors 20 are located at the periphery of the array-distributed memory cells 170 and are sequentially arranged in the row direction, one end (for example, may be a source) of the second write transistors 20 is connected to one second write signal line 40, and the other end of the second write signal line 40 is disposed at a second side of the free layer of the magnetic tunnel junction 50 opposite to the first side;

there is an overlap area of the free layer of each magnetic tunnel junction 50, the first write signal line 30 disposed on a first side of the free layer, and the second write signal line 40 disposed on a second side of the free layer projected onto the substrate 180; the first write signal line 30 and the second write signal line 40 are configured to be able to drive the inversion of the magnetic field direction of the free layer by a signal, for example, the first write signal line 30 and the second write signal line 40 are configured to be able to generate a signal that is able to drive the inversion of the magnetic field direction of the free layer after a current is applied thereto;

wherein the read transistor 60 is a buried gate transistor. In an embodiment of the present application, as shown in fig. 1, the read transistor 60 may be disposed on a semiconductor substrate 180, the read transistor 60 including a first gate 64, the first gate 64 may be formed within a trench of the substrate 180, thereby forming a buried gate transistor with a gate buried in the substrate.

The magnetic random access memory of the embodiment of the application adopts the buried gate transistor as the reading transistor, and the grid electrode of the buried gate transistor is buried (for example, buried in the substrate) without occupying the space of the semiconductor device alone, so that the density of the reading transistor can be improved, thereby improving the storage density of the magnetic random access memory and reducing the manufacturing cost of the magnetic random access memory.

The left and right sides of fig. 1 show schematic vertical cross-sectional structures of the first write transistor 10 and the memory cell 170 located in the same row as the first write transistor 10, respectively, where the write transistor (i.e., the first write transistor 10) is connected to the first write signal line 30 and disconnected from the second write signal line 40 (as shown by the second write signal line 40 shown by the left side with a broken line); alternatively, the left and right sides of fig. 1 respectively show schematic vertical cross-sectional structures of the second write transistor 20 and the memory cell 170 in the same column as the second write transistor 20, and the write transistor (i.e., the second write transistor 20) is connected to the second write signal line 40 and disconnected from the first write signal line 30 (as shown by the first write signal line 30 shown by the dotted line between the left and right sides).

In the embodiment of the present application, as shown in fig. 2, the first write signal lines 30 may extend in the row direction, and the second write signal lines 40 may extend in the column direction.

In embodiments of the present application, the mram may be disposed on a semiconductor substrate, and the row direction and the column direction may be parallel to the substrate and extend in a plane parallel to the substrate.

In an embodiment of the present application, as shown in fig. 1, the read transistor 60 may include a first source electrode 61, a first drain electrode 62, a first semiconductor layer 63, and a first gate electrode 64, the first source electrode 61 and the first drain electrode 62 being located on the substrate 180 and disposed at a distance, projections of the first source electrode 61 and the first drain electrode 62 on the substrate 180 not overlapping; the first semiconductor layer 63 is disposed between the first source electrode 61 and the first drain electrode 62 and has a ring shape, an outer surface of the ring-shaped first semiconductor layer 63 is in contact with the first source electrode 61 and the first drain electrode 62, the first gate electrode 64 is located inside the first semiconductor layer 63 and surrounded by the first semiconductor layer 63, and the read word line 80 extends in the column direction and is connected to the first gate electrode 64. A gate insulating layer is further disposed between the first semiconductor layer 63 and the first gate electrode 64 to isolate the first gate electrode 64 from the first semiconductor layer 63 (not shown).

In the embodiment of the present application, as shown in fig. 2, a plurality of memory cells may be arranged in a row direction and a column direction to form a memory array 1000, and as shown in fig. 1, the read transistors 60 of two adjacent memory cells in the row direction may share one first source 61.

In an embodiment of the present application, as shown in fig. 1, the magnetic tunnel junction 50 of each memory cell may further include a bottom electrode 90 and an interconnection line 100, where a reference layer, a barrier layer and a free layer of the magnetic tunnel junction 50 are stacked on the bottom electrode 90, one end of the interconnection line 100 is connected to the bottom electrode 90, and the other end of the interconnection line 100 is connected to the first drain electrode 62 of the read transistor 60, so as to connect the magnetic tunnel junction 50 to the read transistor 60.

In an embodiment of the present application, the interconnect lines may be metal contact pillars. The material of the metal contact stud may be selected from any one or more of tungsten, copper, tantalum, titanium nitride, carbon nitride and molybdenum, and may be tungsten, for example.

In an exemplary embodiment of the present application, as shown in FIG. 1, one end of the magnetic tunnel junction 50 may be directly connected to the read bit line 70. Fig. 3 is a schematic cross-sectional structure of another magnetic random access memory according to an exemplary embodiment of the present application. Alternatively, as shown in FIG. 3, in an exemplary embodiment of the present application, each magnetic tunnel junction 50 may further include a top electrode 110, the top electrode 110 may be disposed on one side of the free layer, and the magnetic tunnel junction 50 may be connected to the read bit line 70 through the top electrode 110. At this time, the read bit line 70 and the first write signal line 30 may share one signal line. When the read bit line 70 and the first write signal line 30 share one signal line, the one shared signal line can function as the read bit line 70 or the first write signal line 30, respectively, at different times, and thus the read bit line 70 and the first write signal line 30 can share one signal line. Moreover, when the read bit line 70 and the first write signal line 30 share one signal line, the first write signal line 30 may be closer to the magnetic tunnel junction 50, which is more advantageous for achieving a reversal of the magnetic field direction of the free layer of the magnetic tunnel junction 50.

In an embodiment of the present application, as shown in FIG. 2, the read bit lines 70 may extend in the row direction. In the magnetic random access memory shown in fig. 2, a plurality of read bit lines 70 extending in the row direction may be included; a plurality of read word lines 80 extending in the column direction may also be included. Each column of read transistors corresponds to a read word line, and each read word line is connected with the gate of each read transistor on one column.

In an embodiment of the present application, the magnetic random access memory may be a magnetic field inverted magnetic random access memory (toggle-MRAM), and specifically, the inversion of the magnetic direction of the free layer is controlled by a signal.

In an embodiment of the present application, each of the memory cells may include one of the magnetic tunnel junctions and one of the read transistors, i.e., the memory cell is a 1t 1mtj structure.

In embodiments of the present application, the read transistor may be fabricated using a process platform for dynamic random access memory (Dynamic Random Access Memory, DRAM). For example, the read transistor of the embodiments of the present application may be fabricated using a fabrication process for array transistors of a DRAM process platform for storing data, resulting in a high density read transistor array.

The read transistor of the magnetic random access memory has smaller read current, and the drive current of the DRAM process platform is smaller, so that the magnetic random access memory can be just used for preparing the read transistor with smaller read current; in addition, the DRAM process platform is suitable for preparing the transistors with simple structure, high density and low power consumption, and has lower energy consumption, so that the read transistors with simple structure, high density and low power consumption can be prepared by utilizing the DRAM process platform, and the manufacturing cost of the magnetic random access memory can be reduced.

In an embodiment of the present application, the first writing transistor and/or the second writing transistor may be manufactured by using a process platform of a dynamic random access memory. The write current required for the write transistor of the magnetic random access memory is larger, but the write transistor is not a 1T 1MTJ structure, and can be shared by a plurality of MTJs, so that a DRAM (dynamic random access memory) process platform can be used for preparing a first write transistor and/or a second write transistor with larger write current. The manufacturing cost of the magnetic random access memory can be reduced by utilizing the DRAM process platform to prepare the writing transistor with simple structure.

In an embodiment of the present application, the first writing transistor and/or the second writing transistor may be planar transistors.

In an embodiment of the present application, as shown in fig. 1, the first write transistor 10 (or the second write transistor 20) may include a second source electrode 11, a second drain electrode 12, a second semiconductor layer 13, and a second gate electrode 14, the second semiconductor layer 13 being disposed between the second source electrode 11 and the second drain electrode 12, the second semiconductor layer 13 extending in a row direction, the second gate electrode 14 being disposed at one side of the second semiconductor layer 13. In addition, a gate insulating layer (not shown) may be further provided between the second gate electrode 14 and the second semiconductor layer 13.

In an embodiment of the present application, the gate insulation layer (including a read crystalThe material of the gate insulating layer of the body tube and the gate insulating layer of the write transistor may be selected from silicon oxide (e.g., siO) ₂ ) And any one or more of a high dielectric constant (K) material, such as hafnium oxide (e.g., hfO ₂ ) Zirconium oxide (e.g., zrO) and aluminum oxide (e.g., al) ₂ O ₃ ) Etc. The gate insulating layer may be a single-layer or multi-layer structure, for example, may be made of SiO ₂ And a bilayer structure formed of a high-K material.

In the embodiment of the present application, as shown in fig. 1, between the first write transistor 10 and the first write signal line 30, or between the second write transistor 20 and the second write signal line 40, may be connected by an interconnection line 100, for example, here, one end of the interconnection line 100 may be connected to the second source 11 of the first write transistor 10 or the second write transistor 20, and the other end of the interconnection line 100 may be connected to the first write signal line 30 or the second write signal line 40. The interconnect 100 may be a metal contact stud. The material of the metal contact stud may be selected from any one or more of tungsten and molybdenum, for example, may be tungsten.

In an embodiment of the present application, as shown in fig. 1, the voids of the mram (e.g., voids around the magnetic tunnel junction 50, voids between the bottom electrode 90 and the read transistor 60, etc.) may be filled with a dielectric 120.

In the embodiment of the present application, the material of the dielectric may be selected from any one or more of silicon dioxide, silicon nitride, silicon carbonitride oxide and silicon carbonitride.

In an embodiment of the present application, as shown in fig. 2, the mram may further include a first write signal line address decoder and driver 130 and a second write signal line address decoder and driver 140, where the first write signal line address decoder and driver 130 is connected to the first write transistor 10, and the second write signal line address decoder and driver 140 is connected to the second write transistor 20; the first write signal line address decoder and driver 130 and the first write transistor 10 constitute a first set of write transistors 150, and the second write signal line address decoder and driver 140 and the second write transistor 20 constitute a second set of write transistors 160.

In embodiments of the present application, the magnetic tunnel junction may include a plurality of film layers; for example, the magnetic tunnel junction may include a reference layer, a barrier layer, and a free layer; for another example, the magnetic tunnel junction may include a synthetic antiferromagnetic layer, a reference layer, a barrier layer, and a free layer; for another example, the magnetic tunnel junction may include a synthetic antiferromagnetic layer, a ferromagnetic coupling layer, a reference layer, a barrier layer, and a free layer.

In embodiments of the present application, the magnetic tunnel junction may have a total thickness of 15nm to 30nm and have a Bottom Pinned (Bottom Pinned) or top Pinned structure, for example, the magnetic tunnel junction may have a total thickness of 20nm.

In embodiments of the present application, the reference layer has magnetic polarization invariance, and the reference layer generally comprises [ Co/Ni] _n Co/(Ru or Ir)/Co [ Ni/Co ]] _m 、[Co/Pd] _n Co/(Ru or Ir)/Co [ Pd/Co ]] _m Or [ Co/Pt ]] _n Co/(Ru or Ir)/Co [ Pt/Co] _m M is more than or equal to 0 and less than or equal to 3, n is more than or equal to 2 and less than or equal to 7, and ferromagnetic coupling with cobalt iron boron (CoFeB), cobalt iron (CoFe)/nickel iron alloy (NiFe), cobalt boride (CoB) or iron boride (FeB) can be realized through a lattice separation layer; the total thickness of the reference layer may be 4nm to 15nm.

In the embodiment of the present application, the material of the barrier layer may be a non-magnetic metal oxide, for example, may be magnesium oxide (MgO), magnesium zinc oxide (MgZnO), magnesium boron oxide (MgBO), magnesium aluminum oxide (MgAlO), preferably magnesium oxide (MgO); the barrier layer may have a thickness of 0.5nm to 2.5nm.

In an embodiment of the present application, the free layer has a variable magnetic polarization, and the material of the free layer may be cobalt iron boron (CoFeB), coFe/cobalt iron boron (CoFeB), iron (Fe)/cobalt iron boron (CoFeB), cobalt iron boron (CoFeB)/tungsten (W)/cobalt iron boron (CoFeB), cobalt iron boron (CoFeB)/molybdenum (Mo)/cobalt iron boron (CoFeB); the thickness of the free layer may be 0.8nm to 2.3nm.

In an embodiment of the present application, the material of the bottom electrode may include any one or more of Ta, taN, W, WN, ti, tiN, co, cu, al and Pt, for example, the material of the bottom electrode may be TaN or TiN. The bottom electrode may be single-layered or multi-layered.

In the embodiment of the application, the material of the top electrode may include any one or more of Ta, taN, W, WN, ti, tiN, co, cu, al and Pt; the top electrode may have a thickness of 20nm to 100nm, for example, 20nm, 40nm, 50nm, 60nm, 80nm, 100nm.

In embodiments of the present application, the material of the read bit line may include any one or more of tungsten, copper, cobalt, and titanium.

In an embodiment of the present application, a material of the first gate (or the read word line) and/or the second gate may be Indium Tin Oxide (ITO), or the like. The ITO material has smaller resistance;

the materials of the first and second semiconductor layers may be metal oxide semiconductor materials, for example, the materials of the first and second semiconductor layers may each be independently selected from indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO), zinc stannate (ZTO), indium zinc oxide (Indium Zinc Oxide, IZO), zinc oxide (ZnO _x ) Indium tungsten oxide (InWO), indium zinc tin oxide (Indium Zinc Tin Oxide, IZTO), indium oxide (InO) _x For example, in ₂ O ₃ ) Tin oxide (SnO) _x For example, snO ₂ ) Titanium oxide (TiO) _x ) Zinc oxynitride (Zn) _x O _y N _z ) Magnesium zinc oxide (Mg) _x Zn _y O _z ) Zirconium indium zinc oxide (Zr) _x In _y Zn _z O _a ) Hafnium indium zinc oxide (Hf) _x In _y Zn _z O _a ) Aluminum tin indium zinc oxide (Al _x Sn _y In _z Zn _a O _d ) Indium zinc silicon oxide (Si _x In _y Zn _z O _a ) Aluminum zinc tin oxide (Al _x Zn _y Sn _z O _a ) Gallium zinc tin oxide (Ga _x Zn _y Sn _z O _a ) Zirconium zinc tin oxide (Zr) _x Zn _y Sn _z O _a ) And indium gallium silicon oxide (InGaSiO) _x ) Any one or more of the following. For another example, the material of the semiconductor layer may be IGZO.

In embodiments of the present application, the material of the first gate (or read word line) and/or the second gate may be each independently selected from any one or more of polysilicon and polysilicon germanium; the materials of the first semiconductor layer and the second semiconductor layer may be each independently selected from any one or more of group IVA semiconductor materials, for example, the materials of the first semiconductor layer and the second semiconductor layer may be monocrystalline silicon.

In addition, the material of the first gate electrode may be tungsten, titanium nitride (TiN), or the like.

The embodiment of the application also provides a manufacturing method of the magnetic random access memory, and fig. 4 is a flowchart of a manufacturing process of the magnetic random access memory according to the exemplary embodiment of the application. As shown in fig. 4, in an embodiment of the present application, the method for manufacturing a magnetic random access memory includes:

the read transistor 60 is fabricated using a dynamic random access memory process platform;

preparing a first write transistor 10 and/or a second write transistor 20 by adopting a process platform of the dynamic random access memory, connecting the first write transistor 10 with a first write signal line 30, and connecting the second write transistor 20 with a second write signal line 40;

a magnetic tunnel junction 50 is formed and one end of the magnetic tunnel junction 50 is connected to a read bit line 70 and the other end of the magnetic tunnel junction 50 is connected to a read transistor 60.

The embodiment of the application also provides electronic equipment, which can comprise a storage device, a smart phone, a computer, a tablet computer, an artificial intelligent device, a wearable device, a mobile power supply and the like.

Although the embodiments disclosed in the present application are described above, the embodiments are only used for facilitating understanding of the present application, and are not intended to limit the present application. Any person skilled in the art to which this application pertains will be able to make any modifications and variations in form and detail of implementation without departing from the spirit and scope of the disclosure, but the scope of the application is still subject to the scope of the claims that follow.

Claims (10)

1. A magnetic random access memory comprising:

a plurality of memory cells distributed in an array on a substrate, each memory cell comprising a magnetic tunnel junction and a read transistor, the magnetic tunnel junction comprising a free layer capable of achieving magnetic field direction reversal;

one end of each magnetic tunnel junction of the memory cells positioned in the same row is connected with a read bit line, and the other end of each magnetic tunnel junction is connected with the read transistor; further comprises:

a plurality of first write transistors sequentially arranged in a column direction at the periphery of the memory cells distributed in the array, each first write transistor being connected to one end of a first write signal line, the other end of the first write signal line being disposed at a first side of a free layer of the magnetic tunnel junction;

a plurality of second write transistors arranged in sequence in a row direction at the periphery of the memory cells distributed in the array, each second write transistor being connected to one end of a second write signal line, the other end of the second write signal line being disposed at a second side of the free layer of the magnetic tunnel junction opposite to the first side;

the free layer of each magnetic tunnel junction, the first write signal line arranged on the first side of the free layer, and the second write signal line arranged on the second side of the free layer have overlapping areas in projection on the substrate;

the first write signal line and the second write signal line are configured to signal a reversal of a magnetic field direction of the free layer;

wherein the read transistor is a buried gate transistor.

2. The magnetic random access memory of claim 1 wherein the read transistor comprises a source, a drain, a semiconductor layer, and a gate;

the source electrode and the drain electrode are both positioned on the substrate and are arranged at intervals, and projections of the source electrode and the drain electrode on the substrate are not overlapped;

the semiconductor layer is disposed between the source electrode and the drain electrode and has a ring shape, an outer surface of the ring-shaped semiconductor layer is in contact with the source electrode and the drain electrode, and the gate electrode is located inside the ring-shaped semiconductor layer and surrounded by the ring-shaped semiconductor layer.

3. The mram of claim 2, wherein the read transistors of two adjacent memory cells in the same row share one of the sources.

4. The magnetic random access memory of claim 2 or 3, further comprising a read word line extending in a column direction, the read word line being connected to the gate.

5. The magnetic random access memory according to any one of claims 1 to 3, wherein the magnetic tunnel junction further comprises a bottom electrode on which a free layer of the magnetic tunnel junction is provided, and an interconnect line having one end connected to the bottom electrode and the other end connected to the read transistor.

6. The magnetic random access memory of claim 5 wherein the magnetic tunnel junction further comprises a top electrode disposed on a side of the free layer remote from the bottom electrode, the magnetic tunnel junction being connected to the read bit line through the top electrode.

7. The mram of any of claims 1-3, wherein the read bit line extends in a row direction.

8. The mram of claim 1, further comprising a first write signal line address decoder and driver connected to the first write transistor and a second write signal line address decoder and driver connected to the second write transistor.

9. The method of manufacturing a magnetic random access memory according to any one of claims 1 to 8, comprising:

preparing the read transistor by adopting a process platform of a dynamic random access memory;

preparing the first writing transistor and/or the second writing transistor by adopting a process platform of the dynamic random access memory, connecting the first writing transistor with the first writing signal line, and connecting the second writing transistor with the second writing signal line;

the magnetic tunnel junction is formed and one end of the magnetic tunnel junction is connected with the read bit line, and the other end of the magnetic tunnel junction is connected with the read transistor.

10. An electronic device comprising a magnetic random access memory according to any one of claims 1 to 8.