CN117579833B - Video compression circuit and chip - Google Patents
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Abstract
The embodiment of the invention discloses a video compression circuit and a chip. The video compression circuit comprises a video processing module, a video processing module and a video processing module, wherein the video processing module is used for analyzing initial video data and matching the initial video data with pixels to output pixel count data; the pixel processing module is connected with the video processing module and is used for processing the pixel count data into pixel matrix data; the pixel matrix calculation module is connected with the pixel processing module and is used for carrying out matching compression on the pixel matrix data, the size data of the input video window and the size of the target video window, determining the coefficient of a matrix formula based on the precision parameter of the bicubic interpolation algorithm and calculating a set of pixel values; the video time sequence conversion module is connected with the pixel matrix calculation module and is used for converting the set of pixel values into a target video of continuous pixels; the number of pixels of the target video is greater than the number of pixels of the initial video data. The technical scheme provided by the embodiment reduces visual loss of the compressed video.
Description
Technical Field
The embodiment of the invention relates to the technical field of chips, in particular to a video compression circuit and a chip.
Background
With the development of chip technology, the requirements of people on chips are increasing. In the chip design field and the FPGA application field, when the video window size compression is required for high-speed video forwarding, two algorithms are used: adjacent interpolation algorithms and bilinear interpolation algorithms. These two conventional algorithms generally cause visual loss of video.
The problem that the video is lost in vision due to the compression of the video by the existing video compression circuit becomes a technical problem to be solved in the industry.
Disclosure of Invention
The embodiment of the invention provides a video compression circuit and a chip, which are used for solving the problem that video is visually lost due to the compression of the video by the video compression circuit.
In order to realize the technical problems, the invention adopts the following technical scheme:
the embodiment of the invention provides a video compression circuit, which comprises: the video processing module is used for analyzing the initial video data and pairing the initial video data with pixels to output pixel count data; the pixel processing module is connected with the video processing module and is used for processing the pixel count data into pixel matrix data; the pixel matrix calculation module is connected with the pixel processing module and is used for carrying out matching compression on pixel matrix data, size data of an input video window and size of a target video window, determining coefficients of a matrix formula based on precision parameters of a bicubic interpolation algorithm and calculating a set of pixel values; the video time sequence conversion module is connected with the pixel matrix calculation module and is used for converting the set of pixel values into a target video of continuous pixels; the number of pixels of the target video is greater than the number of pixels of the initial video data.
Optionally, the video processing module includes:
the video analysis unit is connected with the first buffer unit, and the first buffer unit is connected with the pixel processing module;
the video analysis unit is used for analyzing the initial video data and outputting 1 vertical count and n horizontal counts, wherein each clock period of the initial video data comprises n pixels; n is an integer greater than 1;
the first buffer unit is used for carrying out line buffer on 1 vertical count and n horizontal counts and outputting pixel count data, wherein the pixel count data comprises 1+n vertical counts and n horizontal counts.
Optionally, the pixel matrix calculating module includes:
the position matching unit is connected with the pixel processing module;
the position matching unit is used for matching the pixel matrix data with the window size of the initial video data and the size of the target video window, and determining the counting relation of the target video and the decimal value of the corresponding position of the pixel of the target video in the window of the initial video data;
wherein the pixel matrix data includes an (n+1) × (n+1) pixel matrix.
Optionally, the pixel matrix calculating module further includes:
the matrix coefficient determining unit is connected with the position matching unit;
the matrix coefficient determining unit is used for determining the coefficient of the matrix formula according to the decimal value of the corresponding position of the pixel of the target video in the window of the initial video data based on the precision parameter of the bicubic interpolation algorithm.
Optionally, the pixel matrix calculating module further includes:
the pixel value determining unit is connected with the pixel processing module and the matrix coefficient determining unit and is used for carrying out weighted average calculation according to the pixel matrix data and the coefficient of the matrix formula and outputting a set of pixel values; wherein the set of pixel values comprises a set of color component values for each pixel.
Optionally, the location matching unit includes:
a first count-up point subunit and a vertical matching subunit;
the first forward counting point subunit is connected with the vertical matching subunit and is used for matching the height of the initial video data with the height of the target video;
the vertical matching sub-unit is connected with the pixel processing module and is used for matching the (n+1) x (n+1) pixel matrix with the height of the initial video data and the height of the target video, and outputting the height count of the target video and the decimal value of the corresponding height position of the pixel of the target video in the window of the initial video data.
Optionally, the position matching unit further includes: the second forward counting point subunit and the horizontal matching subunit;
the second forward counting point subunit is connected with the horizontal matching subunit and is used for matching the width of the initial video data with the width of the target video;
the horizontal matching subunit is connected with the pixel processing module and is used for matching the (n+1) x (n+1) pixel matrix with the width of the initial video data and the width of the target video, and outputting the width count of the target video and the decimal value of the corresponding width position of the pixel of the target video in the window of the initial video data.
Optionally, the position matching unit further includes:
a vertical circulation control subunit and a horizontal circulation control subunit;
the vertical circulation control subunit is connected with the vertical matching subunit, and is used for entering the matching of the height position of the input pixel of the next clock period after adding 1 according to the matching result output by the vertical matching subunit;
the horizontal circulation control subunit is connected with the horizontal matching subunit, and the horizontal circulation control subunit is used for entering the matching of the width position of the input pixel of the next clock cycle after adding 1 according to the matching result output by the horizontal matching subunit.
Optionally, the video timing conversion module includes:
a cache FIFO write control unit, a line cache FIFO unit, and a cache FIFO read control unit;
the buffer FIFO write control unit is connected with the pixel value determining unit and the position matching unit and is used for writing the set of pixel values according to the time sequence of the target video;
the line cache FIFO unit is connected with the cache FIFO write control unit and is used for carrying out line cache on the written pixel value set;
the buffer FIFO read control unit is connected with the line buffer FIFO unit and is used for rearranging and combining the set of pixel values into continuous target video with n+1 pixels in each clock period according to the relation between the length count and the width count of the target video.
According to another aspect of the invention there is provided a chip comprising the video compression circuit of any of the first aspects.
The video compression circuit provided by the embodiment of the invention analyzes the initial video data and pairs the initial video data with pixels by arranging the video processing module to generate pixel count data. And the pixel matrix calculation module is used for carrying out matching compression on the pixel matrix data, the size data of the input video window and the size of the target video window, determining the coefficient of a matrix formula based on the precision parameter of the bicubic interpolation algorithm, and calculating the set of pixel values. Video input of n pixels per clock period and video output of n+1 pixels per clock period are supported, configurable window size input before and after video compression is supported, and precision configuration of bicubic interpolation algorithm is supported. The coefficient of the matrix formula calculated by the pixel matrix calculation module is more accurate, so that the visual effect of the target video data output after the initial video data is compressed is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following description will briefly explain the drawings needed in the description of the embodiments of the present invention, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the contents of the embodiments of the present invention and these drawings without inventive effort for those skilled in the art.
Fig. 1 is a schematic diagram of a video compression circuit according to an embodiment of the present invention;
fig. 2 is a schematic diagram of another video compression circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a video compression circuit according to an embodiment of the present invention;
fig. 4 is a schematic diagram of matching of a position matching unit of a video compression circuit according to an embodiment of the present invention;
fig. 5 is a schematic diagram of matching of a position matching unit of another video compression circuit according to an embodiment of the present invention;
fig. 6 is a schematic diagram of matching of a position matching unit of a video compression circuit according to another embodiment of the present invention;
fig. 7 is a schematic diagram of matching of a position matching unit of a video compression circuit according to another embodiment of the present invention;
fig. 8 is a schematic diagram of matching of a matrix coefficient determining unit of a video compression circuit according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of a chip according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
Based on the above technical problems, the present embodiment proposes the following solutions:
fig. 1 is a schematic diagram of a video compression circuit according to an embodiment of the present invention. Fig. 2 is a schematic diagram of another video compression circuit according to an embodiment of the present invention. Referring to fig. 1 and fig. 2, a video compression circuit 10 according to an embodiment of the present invention includes a video processing module 1, where the video processing module 1 is configured to analyze initial video data and pair the initial video data with pixels to output pixel count data; the pixel processing module 2 is connected with the video processing module 1, and the pixel processing module 2 is used for processing the pixel count data into pixel matrix data; the pixel matrix calculating module 3 is connected with the pixel processing module 2, and the pixel matrix calculating module 3 is used for carrying out matching compression on pixel matrix data, size data of an input video window and size of a target video window, determining coefficients of a matrix formula based on precision parameters of a bicubic interpolation algorithm and calculating a set of pixel values; the video time sequence conversion module 4 is connected with the pixel matrix calculation module 3, and the video time sequence conversion module 4 is used for converting the set of pixel values into a target video of continuous pixels; the number of pixels of the target video is greater than the number of pixels of the initial video data.
In particular, the pixel count data may include a height count value and a width count value of the initial video data. The pixel matrix data may include a matrix of pixels corresponding to the initial video data. The size data of the input video window may include information of the size of the window of the initial video data, such as the height and width of the window. The target video window may include a window size of the outputted video data after the initial video data is compressed.
The video processing module 1 and the pixel processing module 2 convert the timing of the initial video data into the timing of the pixel matrix. The pixel matrix calculating module 3 matches the 4x4 pixel matrix time sequence with the size of the input video window and the size of the output video window to obtain the time sequence of the output video and the decimal value of the corresponding position of the output video pixel in the input video window. And determining coefficients of a matrix formula according to the time sequence of the output video and decimal values of corresponding positions of pixels of the output video in an input video window based on precision parameters of the bicubic interpolation algorithm. The set of pixel values is calculated from the coefficients of the matrix formula and the pixel matrix data output by the pixel processing module 2. The video timing conversion module 4 converts 3 sets of discrete pixel video timing into 1 set of continuous video output of 4 pixels per clock period. This arrangement makes the coefficients of the matrix formula calculated by the pixel matrix calculation module 3 more accurate. And then the visual effect of the target video data output after the initial video data is compressed is better.
For example, referring to fig. 2, the video compression circuit may further include an input reset signal i_rstn and an input clock signal i_clk.
The video compression circuit provided by the embodiment analyzes the initial video data and pairs the initial video data with pixels by arranging the video processing module 1 to generate pixel count data. And the pixel matrix calculation module 3 is used for carrying out matching compression on the pixel matrix data, the size data of the input video window and the size of the target video window, determining the coefficient of a matrix formula based on the precision parameter of the bicubic interpolation algorithm, and calculating the set of pixel values. Video input of n pixels per clock period and video output of n+1 pixels per clock period are supported, configurable window size input before and after video compression is supported, and precision configuration of bicubic interpolation algorithm is supported. The coefficient of the matrix formula calculated by the pixel matrix calculation module 3 is more accurate, so that the visual effect of the target video data output after the initial video data is compressed is improved.
With continued reference to fig. 2, based on the above embodiment, the video processing module 1 may include: the video analysis unit 11 and the first buffer unit 12, the video analysis unit 11 is connected with the first buffer unit 12, and the first buffer unit 12 is connected with the pixel processing module 2; the video analysis unit 11 is configured to analyze initial video data including n pixels per clock cycle, and output 1 vertical count and n horizontal counts; n is an integer greater than 1; the first buffer unit 12 is configured to buffer 1 vertical count and n horizontal counts in a line, and output pixel count data including 1+n vertical counts and n horizontal counts.
Specifically, the video analysis unit 11 receives input initial video data. The initial video data includes a signal i_video_vsync, a signal i_video_hsync, a signal i_video_de, a signal i_video_pixel0, a signal i_video_pixel1, and a signal i_video_pixel2. The video analysis unit 11 analyzes the initial video data and outputs 1 vertical count and n horizontal counts. Illustratively, n=3.
The first Buffer unit 12 may include a Buffer write control unit, a line Buffer unit, and a Buffer read control unit. The first buffer unit 12 buffers 1 vertical count (vertical count) and n horizontal counts (horizontal count) in a line, and outputs pixel count data including 1+n vertical counts and n horizontal counts. For example, the line Buffer unit may pass through the line Buffer subunit line_buffer_0, the line Buffer subunit line_buffer_1, and the line Buffer subunit line_buffer_2.
Illustratively, the first buffer unit 12 stores 3 lines of video pixel data and composes 4 lines of video pixel data together with the current line. The Buffer write control unit outputs 4 vertical counts and 3 horizontal counts. 1 vertical count and n horizontal counts are used to pair with (n+1) ×n pixels.
Optionally, the pixel processing module 2 is configured to arrange the pixels into (n+1) × (n+1), for example, 4×4 matrices, where 4×4 pixels in each matrix may correspond to a pixel of the target video output after compression in the next matching. N pixels are input per cycle, with n=3, as an example. Since there are 3 pixel inputs per clock cycle, the pixel processing module 2 outputs 3 sets of 4x4 pixels as pixel matrix data to the pixel value determining unit 33 of the pixel matrix calculating module 3. With 3 sets of 4x4 pixels (pixel 3x 4), there are also 3 sets of vertical and horizontal counts, 4 vertical and 4 horizontal counts being set in each set.
Alternatively, with continued reference to fig. 2 on the basis of the above-described embodiment, the pixel matrix calculation module 3 may include a position matching unit 31. The position matching unit 31 is connected with the pixel processing module 2; the position matching unit 31 is configured to match the pixel matrix data with a window size of the initial video data and a size of a target video window, and determine a count relationship of the target video and a decimal value of a corresponding position of a pixel of the target video in the window of the initial video data; wherein the pixel matrix data includes an (n+1) × (n+1) pixel matrix.
Specifically, the position matching unit 31 may include 3 sets. The position matching unit 31 refers to whether or not the 4 vertical counts and the 4 horizontal counts currently input can match to the vertical counts and the horizontal counts of the pixels of the target video. If the two images can be matched, the positions of the pixels of the target video are marked at the corresponding positions in the window of the initial video data. The noted positions include decimal values, and the count relationship of the target video and the decimal values of the corresponding positions of the pixels of the target video in the window of the initial video data are output to the matrix coefficient determination unit 32.
Fig. 3 is a schematic diagram of a video compression circuit according to another embodiment of the present invention. On the basis of the above embodiments, referring to fig. 3, the position matching unit 31 may include a first count-up point sub-unit 311 and a vertical matching sub-unit 312. The first forward count point subunit 311 is connected to the vertical matching subunit 312, where the first forward count point subunit 311 is configured to match the height i_config_vactive_before of the initial video data with the height i_config_vactive_after of the target video; the vertical matching subunit 312 is connected to the pixel processing module 2, and the vertical matching subunit 312 is configured to match the (n+1) × (n+1) pixel matrix with the height i_config_vactive_before of the initial video data and the height i_config_vactive_after of the target video, and output a small value of the height count of the target video and the corresponding height position of the pixel of the target video in the window of the initial video data.
In another alternative implementation, with continued reference to fig. 3 based on the above embodiments, the position matching unit 31 may further include a second count-up point sub-unit 313 and a horizontal matching sub-unit 314. The second count-up point subunit 313 is connected to the horizontal matching subunit 314, where the second count-up point subunit 313 is configured to match the width i_config_have_before of the initial video data with the width i_config_have_after of the target video; the horizontal matching subunit 314 is connected to the pixel processing module 2, and the horizontal matching subunit 314 is configured to match the (n+1) × (n+1) pixel matrix with the width i_config_have_before of the initial video data and the width i_config_have_after of the target video, and output a width count of the target video and a fractional value of a corresponding width position of the pixel of the target video in the window of the initial video data.
Still another alternative embodiment, with continued reference to fig. 3, may further include a vertical loop control subunit 315 and a horizontal loop control subunit 316. The vertical circulation control subunit 315 is connected to the vertical matching subunit 312, and the vertical circulation control subunit 315 is configured to enter the matching of the input pixel height position of the next clock cycle after adding 1 according to the matching result output by the vertical matching subunit 312; the horizontal circulation control subunit 316 is connected to the horizontal matching subunit 314, and the horizontal circulation control subunit is configured to enter the matching of the input pixel width position of the next clock cycle after adding 1 according to the matching result output by the horizontal matching subunit 314.
It should be noted that fig. 3 exemplarily illustrates a case where the vertical loop control subunit 315 and the horizontal loop control subunit 316 include D flip-flops. The D flip-flop may include an enable terminal EN, a clock control terminal CLK, an input terminal D, and an output terminal Q.
Specifically, fig. 4 is a schematic diagram of matching of a position matching unit of a video compression circuit according to an embodiment of the present invention. Fig. 5 is a schematic diagram of matching of a position matching unit of another video compression circuit according to an embodiment of the present invention. Fig. 6 is a schematic diagram of matching of a position matching unit of a video compression circuit according to another embodiment of the present invention. Fig. 7 is a schematic diagram of matching of a position matching unit of a video compression circuit according to another embodiment of the present invention. Referring to fig. 3 to 7, fig. 3 exemplarily illustrates a case where the height i_config_active_before=5 of the initial video data, the width i_config_active_before=5 of the initial video data, the height i_config_active_after=4 of the target video, and the width i_config_active_after=4 of the target video.
Illustratively, fig. 4 corresponds to a window size of the initial video data. Fig. 5 corresponds to the window size of the target video. Fig. 6 is a position diagram corresponding to the pixel position of P (1, 1) in fig. 5 to fig. 4. Fig. 6 is a schematic diagram of fig. 5 overlaid on fig. 4, and fig. 7 exemplarily shows that P (1, 1) in fig. 5 has a lower case P (1.33) in fig. 4. p (1.33) radiates a distance of two pixels to the surroundings for a total of 4x4 pixel positions, as in the D1 region of fig. 7.
The forward count point formula may calculate p (1.33) using the following formula.
，
cnt int=int(cnt point)，
cnt minus2=cnt int-1，
cnt minus1=cnt int，
cnt plus1=cnt int+1，
cnt plus2=cnt int+2。
Uppercase P in fig. 5 corresponds to cnt_out. cnt_out is the position of the target pixel, and cnt.point is calculated. Point is a fractional value of the corresponding position of a pixel of the target video in a window of the initial video data. cnt_int is the integer part of cnt. The positions (cnt_minus2, cnt_minus1, cnt_plus_1, cnt_plus_2) of the 4x4 pixels, which result from the radiation of p (1.33), are matched to the positions (cnt_0, cnt_1, cnt_2, cnt_3) of the 4x4 pixels that are input. In the above formula, vactive before represents the position of the initial video data, and vactive_after represents the position of the target video.
If pairing is successful, the vertical loop control subunit 315 and the horizontal loop control subunit 316 output the vertical count and the horizontal count of the target pixel, respectively. And performing +1 operation, and further performing matching of the input pixel position of the next clock cycle.
Optionally, fig. 8 is a schematic diagram of matching of a matrix coefficient determining unit of a video compression circuit according to an embodiment of the present invention. On the basis of the above embodiment, referring to fig. 2 and 8, the pixel matrix calculating module 3 may further include: a matrix coefficient determination unit 32 connected to the position matching unit 31; the matrix coefficient determining unit 32 is configured to determine the coefficient of the matrix formula according to the decimal value of the corresponding position of the target video pixel in the window of the initial video data based on the precision parameter of the bicubic interpolation algorithm.
Specifically, p (1.33) in fig. 4 to 7 is marked in fig. 8, and the horizontal decimal value hdecnt_point of the corresponding position of the pixel of the target video in the window of the initial video data and the vertical decimal value vdecnt_point of the corresponding position of the pixel of the target video in the window of the initial video data are (x ', y'). The D1 region in fig. 7 is a position of 4×4 pixels adjacent to p (1.33).
The matrix coefficient determination module may include at least three arrays, and the matrix coefficient determination module may calculate using the following formula:
where di and dj are values of the distance (x ', y') of the respective pixels p (i, j) in both the horizontal and vertical directions. And a used in the calculation of a matrix formula w (d) used for calculating the matrix coefficients is an accuracy parameter of a bicubic interpolation algorithm. W (i, j) is a coefficient of the matrix formula, W (i, j) includes a fractional part.
As can be calculated from the above formula, if (x ', y') and p (1, 1) overlap, only W (1, 1) =1, and the values of the remaining W (i, j) are each=0. Similarly, if (x ', y') overlaps p (i) or p (j) only in the horizontal direction or the vertical direction, only 4W (i) or 4W (j) have values, and the values of the remaining W (i, j) each=0.
Alternatively, with continued reference to fig. 2 on the basis of the above-described embodiment, the pixel matrix calculation module 3 may further include a pixel value determination unit 33. The pixel value determining unit 33 is connected with the pixel processing module 2 and the matrix coefficient determining unit 32, and the pixel value determining unit 33 is used for carrying out weighted average calculation according to the pixel matrix data and the coefficient of the matrix formula and outputting a set of pixel values; wherein the set of pixel values comprises a set of color component values for each pixel.
Specifically, the pixel value determining unit 33 receives the pixel matrix data output from the pixel processing module 2 and the coefficients of the matrix formula output from the matrix coefficient determining unit 32, and may perform a weighted average operation using the following formula:
where I (I, j) is the input pixel matrix data, e.g., the value of each color component of 4x4 pixels; w (i, j) is a coefficient of a matrix formula; the set of pixel values is a set of values of the color component I (x ', y') of each pixel of the output.
Optionally, with continued reference to fig. 2, the video timing conversion module 4 may include a cache FIFO write control unit 41, a line cache FIFO unit 42, and a cache FIFO read control unit 43. The buffer FIFO write control unit 41 is connected to the pixel value determining unit 33 and the position matching unit 31, and the buffer FIFO write control unit 41 is configured to write a set of pixel values according to a timing sequence of the target video; the line buffer FIFO unit 42 is connected to the buffer FIFO write control unit 41, and the line buffer FIFO unit 42 is configured to buffer a set of written pixel values; the buffer FIFO read control unit 43 is connected to the line buffer FIFO unit 42, and the buffer FIFO read control unit 43 is configured to rearrange and combine the set of pixel values into a continuous target video having n+1 pixels per clock cycle according to a relationship between the length count and the width count of the target video.
Illustratively, the cache FIFO write control unit 41 stores 1 line of video pixel data, with the signal input to the cache FIFO write control unit 41 having a set of 3 sets of discrete pixel values, and a vertical count and a horizontal count of 3 sets of discrete target pixels per clock cycle.
The line buffer FIFO unit 42 rearranges and combines the inputted set of 3 sets of pixel values into 1 set of target video timings of 4 pixels per clock period in accordance with the count relationship between the vertical count and the horizontal count of the target pixels, and valid data signals of the video timings are continuous in a line.
The buffer FIFO read control unit 43 rearranges and combines sets of pixel values into a continuous target video having n+1 pixels per clock cycle in accordance with the relationship between the length count and the width count of the target video. For example, fig. 2 exemplarily shows that the target video output by the buffer FIFO read control unit 43 includes a signal o_video_vsync, a signal o_video_hsync, a signal o_video_de, a signal o_video_vcnt, a signal o_video_hcnt, a signal o_video_pixel 0, a signal o_video_pixel 1, a signal o_video_pixel 2, and a signal o_video_pixel 3. The target video is a video signal after compressing the initial video data.
The video compression circuit 10 provided in this embodiment more accurately supports video input of 3 pixels per clock period and video output of 4 pixels per clock period through the coefficients of the matrix formula calculated by the pixel matrix calculation module 3, supports window size input before and after configurable video compression, supports precision configuration of bicubic interpolation algorithm, and further improves visual effects of target video data output after initial video data is compressed.
Fig. 9 is a schematic structural diagram of a chip according to an embodiment of the present invention. On the basis of the above embodiments, referring to fig. 9, the chip provided in this embodiment includes the video compression circuit 20 provided in any of the above embodiments, and has the beneficial effects of the video compression circuit 10 provided in any of the above embodiments, which are not described herein again.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (4)
1. A video compression circuit, comprising:
the video processing module is used for analyzing the initial video data, pairing the initial video data with pixels and outputting pixel count data;
the pixel processing module is connected with the video processing module and is used for processing the pixel count data into pixel matrix data;
the pixel matrix calculation module is connected with the pixel processing module and is used for carrying out matching compression on the pixel matrix data, the size data of the input video window and the size of the target video window, determining the coefficient of a matrix formula based on the precision parameter of a bicubic interpolation algorithm and calculating a set of pixel values;
the video time sequence conversion module is connected with the pixel matrix calculation module and is used for converting the set of pixel values into a target video of continuous pixels; the number of pixels of the target video is greater than the number of pixels of the initial video data;
the video processing module comprises a video analysis unit and a first buffer unit, wherein the video analysis unit is connected with the first buffer unit, and the first buffer unit is connected with the pixel processing module; the video analysis unit is used for analyzing initial video data and outputting 1 vertical count and n horizontal counts, wherein each clock period of the initial video data comprises n pixels; n is an integer greater than 1; the first buffer unit is used for performing line buffer on the 1 vertical count and the n horizontal counts and outputting pixel count data, wherein the pixel count data comprises 1+n vertical counts and n horizontal counts;
the pixel matrix calculation module comprises a position matching unit and is connected with the pixel processing module; the position matching unit is used for matching the pixel matrix data with the window size of the initial video data and the size of a target video window, and determining the counting relation of the target video and the decimal value of the corresponding position of the pixel of the target video in the window of the initial video data; wherein the pixel matrix data includes an (n+1) × (n+1) pixel matrix;
the pixel matrix calculation module further comprises a matrix coefficient determination unit which is connected with the position matching unit; the matrix coefficient determining unit is used for determining the coefficient of a matrix formula according to the decimal value of the corresponding position of the pixel of the target video in the window of the initial video data based on the precision parameter of the bicubic interpolation algorithm;
the pixel matrix calculation module further comprises a pixel value determination unit which is connected with the pixel processing module and the matrix coefficient determination unit, wherein the pixel value determination unit is used for carrying out weighted average calculation according to the pixel matrix data and the coefficients of the matrix formula and outputting a set of pixel values; wherein the set of pixel values comprises a set of color component values for each pixel;
the position matching unit comprises a first forward counting point subunit and a vertical matching subunit;
the first forward counting point subunit is connected with the vertical matching subunit, and is used for matching the height of the initial video data with the height of the target video;
the vertical matching subunit is connected with the pixel processing module, and is used for matching the (n+1) x (n+1) pixel matrix with the height of the initial video data and the height of the target video, and outputting the height count of the target video and the decimal value of the corresponding height position of the pixel of the target video in the window of the initial video data;
the position matching unit further comprises a second forward counting point subunit and a horizontal matching subunit; the second forward counting point subunit is connected with the horizontal matching subunit, and is used for matching the width of the initial video data with the width of the target video; the horizontal matching subunit is connected with the pixel processing module, and is used for matching the (n+1) x (n+1) pixel matrix with the width of the initial video data and the width of the target video, and outputting the width count of the target video and the decimal value of the corresponding width position of the pixel of the target video in the window of the initial video data.
2. The video compression circuit of claim 1, wherein the position matching unit further comprises:
a vertical circulation control subunit and a horizontal circulation control subunit;
the vertical circulation control subunit is connected with the vertical matching subunit, and is used for entering the matching of the height position of the input pixel of the next clock period after adding 1 according to the matching result output by the vertical matching subunit;
the horizontal circulation control subunit is connected with the horizontal matching subunit, and the horizontal circulation control subunit is used for entering the matching of the input pixel width position of the next clock period after adding 1 according to the matching result output by the horizontal matching subunit.
3. The video compression circuit of claim 1, wherein the video timing conversion module comprises:
a cache FIFO write control unit, a line cache FIFO unit, and a cache FIFO read control unit;
the buffer FIFO write control unit is connected with the pixel value determining unit and the position matching unit, and is used for writing the set of pixel values according to the time sequence of the target video;
the line cache FIFO unit is connected with the cache FIFO write control unit and is used for carrying out line cache on the written set of pixel values;
the buffer FIFO read control unit is connected with the line buffer FIFO unit and is used for rearranging and combining the set of pixel values into continuous target video with n+1 pixels in each clock period according to the relation between the length count and the width count of the target video.
4. A chip comprising the video compression circuit of any one of claims 1 to 3.
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