CN117579250A - Mobile equipment message compression quick implementation method and system based on cryptographic algorithm - Google Patents
Mobile equipment message compression quick implementation method and system based on cryptographic algorithm Download PDFInfo
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- 238000007906 compression Methods 0.000 title claims abstract description 185
- 230000006835 compression Effects 0.000 title claims abstract description 180
- 238000000034 method Methods 0.000 title claims abstract description 44
- 238000004422 calculation algorithm Methods 0.000 title claims abstract description 39
- 229910052754 neon Inorganic materials 0.000 claims abstract description 104
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 claims abstract description 104
- 230000006870 function Effects 0.000 claims abstract description 78
- 230000015654 memory Effects 0.000 claims abstract description 44
- 238000012545 processing Methods 0.000 claims abstract description 20
- CJBPIZBHRWDBGQ-COSFPPCYSA-N rfa-1 Chemical compound C1([C@H]2N[C@H](CC3(N=C4C=5C6=C7O[C@](C6=O)(C)O/C=C/[C@@H]([C@H]([C@@H](OC(C)=O)[C@@H](C)[C@@H](O)[C@H](C)[C@@H](O)[C@@H](C)\C=C\C=C(C)/C(=O)NC(=C4N3)C(=O)C=5C(O)=C7C)C)OC)C2)C=2C=CC=CC=2)=CC=CC=C1 CJBPIZBHRWDBGQ-COSFPPCYSA-N 0.000 claims description 8
- 101100033865 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) RFA1 gene Proteins 0.000 claims description 6
- 239000000203 mixture Substances 0.000 claims description 2
- 230000008569 process Effects 0.000 abstract description 3
- 238000004590 computer program Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000012795 verification Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000013496 data integrity verification Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/0643—Hash functions, e.g. MD5, SHA, HMAC or f9 MAC
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
- H04L2209/122—Hardware reduction or efficient architectures
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
- H04L2209/125—Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/30—Compression, e.g. Merkle-Damgard construction
Abstract
The invention discloses a mobile equipment message compression quick implementation method and a system based on a national cryptographic algorithm, which are characterized in that an input message is hashed by adopting the national cryptographic algorithm to obtain a digital abstract; a hash process comprising: carrying out message expansion and iterative compression on an input message, and outputting a hash value, wherein the hash value is a hash processing result; wherein said performing message expansion and iterative compression on the input message, outputting a hash value, comprises: applying for a stack space, and storing a register into the stack space; reading N message words from the output hash value memory address, and storing the N message words into a designated general register of the aarch64 processor; performing iterative compression, copying the bit words from the neon register of the aarch64 processor to a designated general register of the aarch64 processor, performing a message expansion function, saving the obtained new bit words to the neon register of the aarch64 processor, and finally outputting a hash value.
Description
Technical Field
The invention relates to the technical field of message compression, in particular to a method and a system for quickly realizing message compression of mobile equipment based on a national encryption algorithm.
Background
The statements in this section merely relate to the background of the present disclosure and may not necessarily constitute prior art.
The SM3 algorithm is widely applied to data integrity verification, digital signature, key negotiation and public key encryption and decryption as a hash algorithm, but the message compression of the mobile equipment is generally realized by the conventional SM3 algorithm based on high-level languages such as C language, and the like, so that the universality of the algorithm is ensured, but the problems of large memory occupation, low speed and the like are also caused.
The message compression process based on the SM3 algorithm is low in efficiency in the process of realizing message compression by the mobile equipment, a large amount of internal computing resources are wasted, the computing mode of the existing message compression algorithm improves the complexity of time, and when the message compression algorithm runs on a chip, the power consumption of the chip is high, the message compression process is slow, and the use experience of a user is influenced.
Disclosure of Invention
In order to solve the defects of the prior art, the invention provides a mobile equipment message compression quick implementation method and a system based on a national encryption algorithm;
on one hand, a mobile device message compression quick implementation method based on a national encryption algorithm is provided;
a mobile device message compression quick implementation method based on a cryptographic algorithm comprises the following steps:
Carrying out hash processing on the input message by adopting a national encryption algorithm to obtain a digital abstract;
wherein the hash processing includes: carrying out message expansion and iterative compression on an input message, and outputting a hash value, wherein the hash value is a hash processing result;
wherein said performing message expansion and iterative compression on the input message, outputting a hash value, comprises:
defining a message extension function format: function name (output hash value memory address, input message length);
applying for a stack space, and storing a register into the stack space; reading N message words from the output hash value memory address, and storing the N message words into a designated general register of the aarch64 processor;
performing iterative compression, copying the bit words from the neon register of the aarch64 processor to a designated general register of the aarch64 processor, performing a message expansion function, saving the obtained new bit words to the neon register of the aarch64 processor, and finally outputting a hash value.
On the other hand, a mobile equipment message compression rapid implementation system based on a national encryption algorithm is provided;
a mobile device message compression rapid implementation system based on a cryptographic algorithm comprises: carrying out hash processing on the input message by adopting a national encryption algorithm to obtain a digital abstract;
Wherein the hash processing includes: carrying out message expansion and iterative compression on an input message, and outputting a hash value, wherein the hash value is a hash processing result;
wherein said performing message expansion and iterative compression on the input message, outputting a hash value, comprises:
defining a message extension function format: function name (output hash value memory address, input message length);
applying for a stack space, and storing a register into the stack space; reading N message words from the output hash value memory address, and storing the N message words into a designated general register of the aarch64 processor;
performing iterative compression, copying the bit words from the neon register of the aarch64 processor to a designated general register of the aarch64 processor, performing a message expansion function, saving the obtained new bit words to the neon register of the aarch64 processor, and finally outputting a hash value.
In still another aspect, there is provided an electronic device including:
a memory for non-transitory storage of computer readable instructions; and
a processor for executing the computer-readable instructions,
wherein the computer readable instructions, when executed by the processor, perform the method of the first aspect described above.
In yet another aspect, there is also provided a storage medium non-transitory storing computer readable instructions, wherein the instructions of the method of the first aspect are executed when the non-transitory computer readable instructions are executed by a computer.
In a further aspect, there is also provided a computer program product comprising a computer program for implementing the method of the first aspect described above when run on one or more processors.
One of the above technical solutions has the following advantages or beneficial effects:
by optimizing the iterative compression process encountered in the mobile device message compression process by adopting the SM3, the time complexity of the mobile device message compression process is greatly reduced, and the message compression algorithm has lower power consumption when running on a chip, so that the operation speed of mobile device message compression is improved, the overall performance of the system is improved, and the user experience is improved.
The core of the SM3 algorithm is an iterative compression function. According to the invention, through the methods of redesigning the iterative compression function, recombining the instruction and circularly shifting the constant to obtain the constant of each round, expanding the message based on the neon register and the instruction and the like, the safe and efficient SM3 realization of the full register realization is realized by utilizing the characteristics of rich general registers and the large quantity of the neon registers of ARM aarch64 architecture, the attack of a memory side channel is effectively resisted, and the method has important value for pushing SM3 algorithm to be applied to scenes such as mobile Internet, internet of things and the like.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention.
Fig. 1 is a flow chart of a method according to a first embodiment.
Detailed Description
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the invention. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.
Term interpretation:
message words, which are strings of bits of any finite length. Dividing the message according to 32 bits, wherein each section of bit string of 32 bits is a message word;
the bits are preceded by a number, typically a 32 bit word, representing a length of 32 bits. Example 1
As shown in fig. 1, the embodiment provides a quick implementation method for signing verification based on a cryptographic algorithm;
a mobile device message compression quick implementation method based on a cryptographic algorithm comprises the following steps:
carrying out hash processing on the input message by adopting a national encryption algorithm to obtain a digital abstract;
wherein the hash processing includes: carrying out message expansion and iterative compression on an input message, and outputting a hash value, wherein the hash value is a hash processing result;
Wherein said performing message expansion and iterative compression on the input message, outputting a hash value, comprises:
s100: defining a message extension function format: function name (output hash value memory address, input message length);
s101: applying for a stack space, and storing a register into the stack space; reading N message words from the output hash value memory address, and storing the N message words into a designated general register of the aarch64 processor;
s102: performing iterative compression, copying the bit words from the neon register of the aarch64 processor to a designated general register of the aarch64 processor, performing a message expansion function, saving the obtained new bit words to the neon register of the aarch64 processor, and finally outputting a hash value.
It should be appreciated that in the embodiments of the present application, the hash value is a digital digest.
Further, the step S100: defining a message extension function format: function name (output hash value memory address, input message length), further comprising:
the output hash value memory address is associated with the x0 register, the input message memory address is associated with the x1 register, and the input message length is associated with the x2 register.
Further, the step S101: applying for a stack space, and storing a register into the stack space; reading N message words from the output hash value memory address, and storing the N message words into a designated register, wherein the method specifically comprises the following steps:
stack pointer reduction 104, apply for 104 byte stack space, R19-R30 registers store 96 byte space from 8 th byte of stack; saving an x0 register to a stack 0 byte, calculating the sum of an x1 register and an x2 register, and saving the obtained sum to an x7 register; the x1 register is copied to the x16 register and 8 words are read from the output hash address to the w 19-w 26 registers.
Further, the step S102: performing iterative compression, copying a bit word from a neon register of the aarch64 processor to a designated general register of the aarch64 processor, performing a message expansion function, saving the obtained new bit word to the neon register of the aarch64 processor, and finally outputting an expanded message word, wherein the method specifically comprises the following steps:
s102-1: reading 64 bytes from the memory address corresponding to the x16 register to the V0-V3 register, and simultaneously, adding 64 to the value of the x16 register to update the result into the x16 register;
for the V0-V3 registers, realizing the reverse order of 32-bit bytes; reading the 32-bit unsigned integer 0x79cc4519 to w30 register; copying the values of the w 19-w 26 registers into the w 8-w 15 registers; copying the first 7 32-bit word messages from the neon register to w 0-w 6 registers;
S102-2: performing a first round of iterative compression; reassigning message extension registers V0-V3 to V0, V5, V6, V7, V3, V8; executing the message expansion function to obtain 4 32-bit words, and storing the 4 32-bit words into a designated neon register; performing two rounds of iterative compression; copying 3 32-bit word messages from the neon registers to a designated general purpose register;
s102-3: three rounds of iterative compression are performed; copying three 32-bit words from the neon registers to a designated general purpose register; executing the message expansion function to obtain 4 new 32-bit words, and storing the 4 new 32-bit words into an execution neon register;
s102-4: performing message expansion like S102-3 three times;
s102-5: performing a round of iterative compression; copy 0xcec53d43 into w30 register; performing two rounds of iterative compression; copying 3 32-bit words from the neon registers to a designated general purpose register; executing the message expansion function to obtain 4 new 32-bit words, and storing the 4 new 32-bit words into a designated neon register;
s102-6: three rounds of iterative compression are performed; copying 3 32-bit words from the neon registers to a designated general purpose register; executing the message expansion function to obtain 4 new 32-bit words, and storing the 4 new 32-bit words into a designated neon register;
S102-7: performing a message extension similar to S102-6 ten times;
s102-8: three rounds of iterative compression are performed; copying 3 32-bit words from the neon registers to a designated general purpose register; three rounds of iterative compression are performed; copying 3 32-bit words from the neon registers to a designated general purpose register; three rounds of iterative compression are performed; copying 1 32-bit word from the neon register to a designated general purpose register; performing a round of iterative compression; updating the values of the w 19-w 26 registers;
s102-9: judging whether the value of the x16 register is equal to the value of the x7 register, if so, entering S102-10; if not, returning to S102-1;
s102-10: popping to the x9 register; outputting the w 19-w 26 registers to the 32-byte memory addresses corresponding to the x9 registers; stacking to R19-R30; the stack space is freed.
Further, the S102-1: copying the values of the w 19-w 26 registers into the w 8-w 15 registers specifically comprises the following steps: the value of the w19 register is copied into the w8 register, the value of the w20 register is copied into the w9 register, the value of the w21 register is copied into the w10 register, the value of the w22 register is copied into the w11 register, the value of the w23 register is copied into the w12 register, the value of the w24 register is copied into the w13 register, the value of the w25 register is copied into the w14 register, and the value of the w26 register is copied into the w15 register.
Further, the S102-1: copying the first 7 32-bit word messages from the neon register to w 0-w 6 registers, specifically comprising:
copying the 0 th 32-bit word of the V0 register into the w0 register; copying the 1 st 32-bit word of the V0 register into the w1 register; copying the 2 nd 32-bit word of the V0 register into the w2 register; copying the 3 rd 32-bit word of the V0 register into the w3 register; copying the 0 th 32-bit word of the V1 register into a w4 register; copying the 1 st 32-bit word of the V1 register into a w5 register; the 2 nd 32-bit word of the V1 register is copied into the w6 register.
Further, the step S102-2: performing a first round of iterative compression, comprising:
performing a second class of iterative compression functions RFA1: the first 8 parameters w19-w26 are word registers used for storing iterative compression; the latter two parameters w0, w4 are message expansion word registers, the iterative compression performs iterative compression operations on the registers, and updates the values of the iterative compression word registers w19-w 26:
RFA1 w19,w20,w21,w22,w23,w24,w25,w26,w0,w4；
the RFA1 instruction sequence completes the first round of iterative compression while reallocating the message extension neon registers.
Further, the step S102-2: reassigning message extension registers V0-V3 through V0, V5, V6, V7, V3, V8, comprising:
Executing a message expansion function, wherein the first 5 parameters are input neon registers; the last register is an output register, and the calculated extended message word is saved to an output calculator:
GalWj V0,V5,V6,V7,V3,V8
further, the step S102-2: executing the message expansion function to obtain 4 32-bit words, and storing the 4 32-bit words into a designated neon register, wherein the method specifically comprises the following steps:
the message expansion function is executed, the message expansion operation is executed on 5 input neon registers V0, V5, V6, V7 and V3, the calculation result is stored in a V8 register, and the V8 register stores new 4 32-bit expansion message words.
Further, the step S102-2: performing two rounds of iterative compression, including:
executing an iterative compression operation function, wherein the first 8 parameters are word registers used for storing iterative compression; the latter two parameters are message expansion word registers, the iterative compression is performed on the registers, and the values of the iterative compression word registers are updated:
RFA w22,w19,w20,w21,w26,w23,w24,w25,w1,w5；
RFA w21,w22,w19,w20,w25,w26,w23,w24,w2,w6。
further, the step S102-2: copying 3 32-bit word messages from the neon registers to a designated general purpose register, specifically includes:
copy the 3 rd 32-bit word of the V1 register to the w0 register;
copy the 0 th 32-bit word of the V2 register to the w1 register;
The 1 st 32-bit word of the V2 register is copied to the w2 register.
Further, the step S102-3: three rounds of iterative compression are performed, including:
executing an iterative compression operation function, wherein the first 8 parameters are word registers used for storing iterative compression; the latter two parameters are message expansion word registers, the iterative compression is performed on the registers, and the values of the iterative compression word registers are updated:
RFA w20,w21,w22,w19,w24,w25,w26,w23,w3,w0；
RFA w19,w20,w21,w22,w23,w24,w25,w26,w4,w1；
RFA w22,w19,w20,w21,w26,w23,w24,w25,w5,w2。
further, the step S102-3 copies three 32-bit words from the neon register to a specified general purpose register, and specifically includes:
copy the 2 nd 32-bit word of the V2 register to the w3 register;
copy the 3 rd 32-bit word of the V2 register to the w4 register;
the 0 th 32-bit word of the V3 register is copied to the w5 register.
Further, the step S102-3 of executing the message expansion function, obtaining 4 new 32-bit words, and storing the 4 new 32-bit words into the execution neon register specifically includes:
executing a message expansion function, wherein the first 5 parameters are input neon registers; the last register is an output register, and the calculated extended message word is saved to an output calculator:
GalWj V5,V6,V7,V3,V8,V9。
further, the step S102-4: the message expansion is performed three times, and specifically comprises the following steps:
The first time:
executing an iterative compression operation function, wherein the first 8 parameters are word registers used for storing iterative compression; the latter two parameters are message extended word registers, performing iterative compression operation on the registers, and updating the values of the iterative compressed word registers:
RFA w21,w22,w19,w20,w25,w26,w23,w24,w6,w3；
executing an iterative compression operation function, wherein the first 8 parameters are word registers used for storing iterative compression; the latter two parameters are message extended word registers, performing iterative compression operation on the registers, and updating the values of the iterative compressed word registers:
RFA w20,w21,w22,w19,w24,w25,w26,w23,w0,w4；
executing an iterative compression operation function, wherein the first 8 parameters are word registers used for storing iterative compression; the latter two parameters are message extended word registers, performing iterative compression operation on the registers, and updating the values of the iterative compressed word registers:
RFA w19,w20,w21,w22,w23,w24,w25,w26,w1,w5；
copy the 1 st 32-bit word of the V3 register to the w6 register;
copy the 2 nd 32-bit word of the V3 register to the w0 register;
copy the 3 rd 32-bit word of the V3 register to the w1 register;
GalWj V6,V7,V3,V8,V9,V10；
second time:
executing an iterative compression operation function, wherein the first 8 parameters are word registers used for storing iterative compression; the latter two parameters are message extended word registers, performing iterative compression operation on the registers, and updating the values of the iterative compressed word registers:
RFA w22,w19,w20,w21,w26,w23,w24,w25,w2,w6；
RFA w21,w22,w19,w20,w25,w26,w23,w24,w3,w0；
RFA w20,w21,w22,w19,w24,w25,w26,w23,w4,w1；
Copy the 1 st 32-bit word of the V8 register to the w2 register;
copy the 2 nd 32-bit word of the V8 register to the w3 register;
copy the 3 rd 32-bit word of the V8 register to the w4 register;
executing a message expansion function, wherein the first 5 parameters are input neon registers; the last register is an output register, and the calculated extended message word is saved to an output calculator:
GalWj V7,V3,V8,V9,V10,V11；
third time:
executing an iterative compression operation function, wherein the first 8 parameters are word registers used for storing iterative compression; the latter two parameters are message extended word registers, performing iterative compression operation on the registers, and updating the values of the iterative compressed word registers:
RFA w19,w20,w21,w22,w23,w24,w25,w26,w5,w2；
RFA w22,w19,w20,w21,w26,w23,w24,w25,w6,w3；
RFA w21,w22,w19,w20,w25,w26,w23,w24,w0,w4；
copy the 1 st 32-bit word of the V9 register to the w5 register;
copy the 2 nd 32-bit word of the V9 register to the w6 register;
copy the 3 rd 32-bit word of the V9 register to the w0 register;
executing a message expansion function, wherein the first 5 parameters are input neon registers; the last register is an output register, and the calculated extended message word is saved to an output calculator:
GalWj V3,V8,V9,V10,V11,V12。
further, S102-5: performing a round of iterative compression, comprising:
executing an iterative compression operation function, wherein the first 8 parameters are word registers used for storing iterative compression; the latter two parameters are message extended word registers, performing iterative compression operation on the registers, and updating the values of the iterative compressed word registers:
RFA w20,w21,w22,w19,w24,w25,w26,w23,w1,w5。
Further, S102-5: copying 0xcec53d43 into w30 register, specifically includes:
the 32-bit unsigned number 0xcec53d43 is copied to the w30 register.
Further, S102-5: performing two rounds of iterative compression, including:
executing an iterative compression operation function, wherein the first 8 parameters are word registers used for storing iterative compression; the latter two parameters are message extended word registers, performing iterative compression operation on the registers, and updating the values of the iterative compressed word registers:
RFB w19,w20,w21,w22,w23,w24,w25,w26,w2,w6；
RFB w22,w19,w20,w21,w26,w23,w24,w25,w3,w0。
further, the step S102-5: copying 3 32-bit words from the neon registers to a designated general purpose register specifically includes:
copy the 1 st 32-bit word of the V10 register to the w1 register;
copy the 2 nd 32-bit word of the V10 register to the w2 register;
the 3 rd 32-bit word of the V10 register is copied to the w3 register.
Further, the step S102-5: executing the message expansion function to obtain 4 new 32-bit words, and storing the 4 new 32-bit words into a designated neon register, wherein the method specifically comprises the following steps:
performing message expansion, wherein the first 5 parameters are input neon registers; the last register is an output register, and the calculated extended message word is saved to an output calculator:
GalWj V8,V9,V10,V11,V12,V0。
Further, the step S102-6: three rounds of iterative compression are performed, including:
performing iterative compression operation, wherein the first 8 parameters are word registers used for storing iterative compression; the latter two parameters are message extended word registers, performing iterative compression operation on the registers, and updating the values of the iterative compressed word registers:
RFB w21,w22,w19,w20,w25,w26,w23,w24,w4,w1；
RFB w20,w21,w22,w19,w24,w25,w26,w23,w5,w2；
RFB w19,w20,w21,w22,w23,w24,w25,w26,w6,w3。
further, the step S102-6: copying 3 32-bit words from the neon registers to a designated general purpose register specifically includes:
copy the 1 st 32-bit word of the V11 register to the w4 register;
copy the 2 nd 32-bit word of the V11 register to the w5 register;
copy the 3 rd 32-bit word of the V11 register to the w6 register;
further, the step S102-6: executing the message expansion function to obtain 4 new 32-bit words, and storing the 4 new 32-bit words into a designated neon register, wherein the method specifically comprises the following steps:
executing a message expansion function, wherein the first 5 parameters are input neon registers; the last register is an output register, and the calculated extended message word is saved to an output calculator:
GalWj V9,V10,V11,V12,V0,V1。
further, the step S102-7: the message expansion is executed for ten times, and specifically comprises the following steps:
the first time:
executing an iterative compression operation function, wherein the first 8 parameters are word registers used for storing iterative compression; the latter two parameters are message extended word registers, performing iterative compression operation on the registers, and updating the values of the iterative compressed word registers:
RFB w22,w19,w20,w21,w26,w23,w24,w25,w0,w4；
RFB w21,w22,w19,w20,w25,w26,w23,w24,w1,w5；
RFB w20,w21,w22,w19,w24,w25,w26,w23,w2,w6；
Copy the 1 st 32-bit word of the V12 register to the w0 register;
copy the 2 nd 32-bit word of the V12 register to the w1 register;
copy the 3 rd 32-bit word of the V12 register to the w2 register;
GalWj V10,V11,V12,V0,V1,V2；
second time:
executing an iterative compression operation function, wherein the first 8 parameters are word registers used for storing iterative compression; the latter two parameters are message extended word registers, performing iterative compression operation on the registers, and updating the values of the iterative compressed word registers:
RFB w19,w20,w21,w22,w23,w24,w25,w26,w3,w0；
RFB w22,w19,w20,w21,w26,w23,w24,w25,w4,w1；
RFB w21,w22,w19,w20,w25,w26,w23,w24,w5,w2；
copy the 1 st 32-bit word of the V0 register to the w3 register;
copy the 2 nd 32-bit word of the V0 register to the w4 register;
copy the 3 rd 32-bit word of the V0 register to the w5 register;
GalWj V11,V12,V0,V1,V2,V3；
third time:
performing iterative compression operation, wherein the first 8 parameters are word registers used for storing iterative compression; the latter two parameters are message extended word registers, performing iterative compression operation on the registers, and updating the values of the iterative compressed word registers:
RFB w20,w21,w22,w19,w24,w25,w26,w23,w6,w3；
RFB w19,w20,w21,w22,w23,w24,w25,w26,w0,w4；
RFB w22,w19,w20,w21,w26,w23,w24,w25,w1,w5；
copy the 1 st 32-bit word of the V1 register to the w6 register;
copy the 2 nd 32-bit word of the V1 register to the w0 register;
copy the 3 rd 32-bit word of the V1 register to the w1 register;
GalWj V12,V0,V1,V2,V3,V4；
fourth time:
executing an iterative compression operation function, wherein the first 8 parameters are word registers used for storing iterative compression; the latter two parameters are message extended word registers, performing iterative compression operation on the registers, and updating the values of the iterative compressed word registers:
RFB w21,w22,w19,w20,w25,w26,w23,w24,w2,w6；
RFB w20,w21,w22,w19,w24,w25,w26,w23,w3,w0；
RFB w19,w20,w21,w22,w23,w24,w25,w26,w4,w1；
Copy the 1 st 32-bit word of the V2 register to the w2 register;
copy the 2 nd 32-bit word of the V2 register to the w3 register;
copy the 3 rd 32-bit word of the V2 register to the w4 register;
GalWj V0,V1,V2,V3,V4,V8；
fifth time:
executing an iterative compression operation function RFB, wherein the first 8 parameters are word registers used for storing iterative compression; the latter two parameters are message extended word registers, performing iterative compression operation on the registers, and updating the values of the iterative compressed word registers:
RFB w22,w19,w20,w21,w26,w23,w24,w25,w5,w2；
RFB w21,w22,w19,w20,w25,w26,w23,w24,w6,w3；
RFB w20,w21,w22,w19,w24,w25,w26,w23,w0,w4；
copy the 1 st 32-bit word of the V3 register to the w5 register;
copy the 2 nd 32-bit word of the V3 register to the w6 register;
copy the 3 rd 32-bit word of the V3 register to the w0 register;
GalWj V1,V2,V3,V4,V8,V9；
sixth time:
executing an iterative compression operation function RFB, wherein the first 8 parameters are word registers used for storing iterative compression; the latter two parameters are message extended word registers, performing iterative compression operation on the registers, and updating the values of the iterative compressed word registers:
RFB w19,w20,w21,w22,w23,w24,w25,w26,w1,w5；
RFB w22,w19,w20,w21,w26,w23,w24,w25,w2,w6；
RFB w21,w22,w19,w20,w25,w26,w23,w24,w3,w0；
copy the 1 st 32-bit word of the V4 register to the w1 register;
copy the 2 nd 32-bit word of the V4 register to the w2 register;
copy the 3 rd 32-bit word of the V4 register to the w3 register;
GalWj V2,V3,V4,V8,V9,V10；
seventh time:
performing iterative compression operation RFB, wherein the first 8 parameters are word registers used for storing iterative compression; the latter two parameters are message extended word registers, performing iterative compression operation on the registers, and updating the values of the iterative compressed word registers:
RFB w20,w21,w22,w19,w24,w25,w26,w23,w4,w1；
RFB w19,w20,w21,w22,w23,w24,w25,w26,w5,w2；
RFB w22,w19,w20,w21,w26,w23,w24,w25,w6,w3；
Copy the 1 st 32-bit word of the V8 register to the w4 register;
copy the 2 nd 32-bit word of the V8 register to the w5 register;
copy the 3 rd 32-bit word of the V8 register to the w6 register;
GalWj V3,V4,V8,V9,V10,V11；
eighth time:
executing an iterative compression operation function RFB, wherein the first 8 parameters are word registers used for storing iterative compression; the latter two parameters are message extended word registers, performing iterative compression operation on the registers, and updating the values of the iterative compressed word registers:
RFB w21,w22,w19,w20,w25,w26,w23,w24,w0,w4；
RFB w20,w21,w22,w19,w24,w25,w26,w23,w1,w5；
RFB w19,w20,w21,w22,w23,w24,w25,w26,w2,w6；
copy the 1 st 32-bit word of the V9 register to the w0 register;
copy V9 register 2 nd 32-bit word to w1 register;
copy V9 register 3 rd 32-bit word to w2 register;
GalWj V4,V8,V9,V10,V11,V12；
ninth time:
executing an iterative compression operation function RFB, wherein the first 8 parameters are word registers used for storing iterative compression; the latter two parameters are message extended word registers, performing iterative compression operation on the registers, and updating the values of the iterative compressed word registers:
RFB w22,w19,w20,w21,w26,w23,w24,w25,w3,w0；
RFB w21,w22,w19,w20,w25,w26,w23,w24,w4,w1；
RFB w20,w21,w22,w19,w24,w25,w26,w23,w5,w2；
copy the 1 st 32-bit word of the V10 register to the w3 register;
copy the 2 nd 32-bit word of the V10 register to the w4 register;
copy the 3 rd 32-bit word of the V10 register to the w5 register;
executing a message expansion function GalWj, wherein the first 5 parameters are input neon registers; the last register is an output register, and the calculated extended message word is saved to an output calculator:
GalWj V8,V9,V10,V11,V12,V0；
Tenth time:
executing an iterative compression operation function RFB, wherein the first 8 parameters are word registers used for storing iterative compression; the latter two parameters are message extended word registers, performing iterative compression operation on the registers, and updating the values of the iterative compressed word registers:
RFB w19,w20,w21,w22,w23,w24,w25,w26,w6,w3；
RFB w22,w19,w20,w21,w26,w23,w24,w25,w0,w4；
RFB w21,w22,w19,w20,w25,w26,w23,w24,w1,w5；
copy the 1 st 32-bit word of the V11 register to the w6 register;
copy the 2 nd 32-bit word of the V11 register to the w0 register;
copy the 3 rd 32-bit word of the V11 register to the w1 register;
performing message expansion, wherein the first 5 parameters are input neon registers; the last register is an output register, and the calculated extended message word is saved to an output calculator:
GalWj V9,V10,V11,V12,V0,V1；
eleventh time:
executing an iterative compression operation function RFB, wherein the first 8 parameters are word registers used for storing iterative compression; the latter two parameters are message extended word registers, performing iterative compression operation on the registers, and updating the values of the iterative compressed word registers:
RFB w20,w21,w22,w19,w24,w25,w26,w23,w2,w6；
RFB w19,w20,w21,w22,w23,w24,w25,w26,w3,w0；
RFB w22,w19,w20,w21,w26,w23,w24,w25,w4,w1；
copy the 1 st 32-bit word of the V12 register to the w2 register;
copy the 2 nd 32-bit word of the V12 register to the w3 register;
copy the 3 rd 32-bit word of the V12 register to the w4 register;
performing message expansion, wherein the first 5 parameters are input neon registers; the last register is an output register, and the calculated extended message word is saved to an output calculator:
GalWj V10,V11,V12,V0,V1,V2。
Further, the step S102-8: performing three rounds of iterative compression, copying 3 32-bit words from the neon registers to a designated general purpose register; the method specifically comprises the following steps:
executing an iterative compression operation function, wherein the first 8 parameters are word registers used for storing iterative compression; the latter two parameters are message extended word registers, performing iterative compression operation on the registers, and updating the values of the iterative compressed word registers:
RFB w21,w22,w19,w20,w25,w26,w23,w24,w5,w2；
RFB w20,w21,w22,w19,w24,w25,w26,w23,w6,w3；
RFB w19,w20,w21,w22,w23,w24,w25,w26,w0,w4；
copy the 1 st 32-bit word of the V0 register to the w5 register;
copy the 2 nd 32-bit word of the V0 register to the w6 register;
the 3 rd 32-bit word of the V0 register is copied to the w0 register.
Further, the step S102-8: three rounds of iterative compression are performed; copying 3 32-bit words from the neon registers to a designated general purpose register specifically includes:
executing an iterative compression operation function, wherein the first 8 parameters are word registers used for storing iterative compression; the latter two parameters are message extended word registers, performing iterative compression operation on the registers, and updating the values of the iterative compressed word registers:
RFB w22,w19,w20,w21,w26,w23,w24,w25,w1,w5；
RFB w21,w22,w19,w20,w25,w26,w23,w24,w2,w6；
RFB w20,w21,w22,w19,w24,w25,w26,w23,w3,w0；
copy the 1 st 32-bit word of the V1 register to the w1 register;
copy the 2 nd 32-bit word of the V1 register to the w2 register;
the 3 rd 32-bit word of the V1 register is copied to the w3 register.
Further, the step S102-8: three rounds of iterative compression are performed; copying 1 32-bit words from the neon registers to a designated general purpose register specifically includes:
executing an iterative compression operation function RFB, wherein the first 8 parameters are word registers used for storing iterative compression; the latter two parameters are message extended word registers, performing iterative compression operation on the registers, and updating the values of the iterative compressed word registers:
RFB w19,w20,w21,w22,w23,w24,w25,w26,w4,w1；
RFB w22,w19,w20,w21,w26,w23,w24,w25,w5,w2；
RFB w21,w22,w19,w20,w25,w26,w23,w24,w6,w3；
the V2 register 1 st 32-bit word is copied to the w4 register.
Further, S102-8, performing a round of iterative compression; updating the values of the w 19-w 26 registers specifically includes:
executing an iterative compression operation function RFB, wherein the first 8 parameters are word registers used for storing iterative compression; the latter two parameters are message extended word registers, performing iterative compression operation on the registers, and updating the values of the iterative compressed word registers:
RFB w20,w21,w22,w19,w24,w25,w26,w23,w0,w4；
w19=w19 exclusive or w8; w20=w20 exclusive or w9; w21=w21 exclusive or w10; w22=w22 exclusive or w11; w23=w23 exclusive or w12; w24=w24 exclusive or w13; w25=w25 exclusive or w14; w26=w26 exclusive or w15.
Further, the step S102-10: popping to the x9 register; outputting the w 19-w 26 registers to the 32-byte memory addresses corresponding to the x9 registers; stacking to R19-R30; releasing stack space, comprising:
Loading a 64-bit shaped word from stack position 0 into the x9 register;
storing the w19 register and the w20 register to the memory address corresponding to the x9 register, and adding 8 to the value of the x9 register;
storing the w21 register and the w22 register to the memory address corresponding to the x9 register, and adding 8 to the value of the x9 register;
storing the w23 register and the w24 register to the memory address corresponding to the x9 register, and adding 8 to the value of the x9 register;
storing the w25 register and the w26 register to memory addresses corresponding to the x9 register;
the R19-R30 registers are restored from the 96 bytes space beginning with the 8 th byte of the stack to 12 general registers, the stack register value is added with 128, and the process is finished.
Further, defining RFA1 function parameters as A, B, C, D, E, F, G, H, w0 and w4;
a, B, C, D, E, F, G, H represent 8 32-bit word registers for storing the iteratively compressed words; w0,24 represents a 32-bit register for holding a message extension word;
w27=w27 cycles shift right by 20 bits; w17=e plus w27; w28=a exclusive or B; w29=e exclusive or F;
executing three ext instructions reassembles the words in the neon registers, the layout of the message words originally saved in the neon registers is:
the neon register numbered 0 holds the 0,1,2,3 th word;
the neon register number 1 holds the 4,5,6,7 th word;
The neon register number 2 holds words 8,9,10, 11;
the neon register number 3 holds words 12,13,14, 15;
after adjustment, the message is modified into 5 registers for storage, so that parallel message expansion is convenient to execute;
the neon register numbered 0 holds the 0,1,2,3 th word;
the neon register No. 5 holds the 3,4,5,6 words;
the neon register number 6 holds the 6 th, 7 th, 8 th, 9 th words;
the neon register number 7 holds words 9,10,11, 12;
the neon register number 3 holds words 12,13,14, 15;
the three ext instructions are executed to recombine the words in the neon register, comprising the following steps:
calling an ext instruction, cascading V0 and V1 into 256-bit registers, circularly moving the 256-bit registers to the left by 12 bytes, and taking the lower 128 bits of the 256-bit registers to V5;
calling an ext instruction, cascading V1 and V2 into 256-bit registers, circularly moving the 256-bit registers to the left by 8 bytes, and taking the lower 128 bits of the 256-bit registers to V6;
calling an ext instruction, cascading V2 and V3 into 256-bit registers, circularly moving the 256-bit registers to the left by 4 bytes, and taking the lower 128 bits of the 256-bit registers to V7;
h=h plus w0; w17=w17 plus w30; w28=w28 exclusive or C; w29=w29 exclusive or G;
w0=w0 exclusive or w4; w17=w17 cycles left 25 bits; w27=w17 exclusive or w27;
d=dxor w0; h=h plus w17; b=b cycles left 23 bits; d=d plus w28;
h=h plus w29; d=d plus w27; w28=h cyclically shifts left by 23 bits before exclusive or H;
h=hcyclically left-shifted by 15 bits exclusive or w28; f=f cycles left 13 bits.
Further, parameters defining macro RFA functions are a, B, C, D, E, F, G, H, w0, w4;
wherein A, B, C, D, E, F, G, H represent 8 32-bit word registers for storing the iteratively compressed words; w0,24 represents a 32-bit register for holding a message extension word;
w30=w30 cycles left 31 bits; w27=w27 cycles shift left by 20 bits;
w17=e plus w27; w28=a exclusive or B; w29=e exclusive or F;
h=h plus w0; w17=w17 plus w30; w28=w28 exclusive or C; w29=w29 exclusive or G;
w0=w0 exclusive or w4; w17=w17 cycles left 25 bits; w27=w17 exclusive or w27;
d=d plus w0; h=h plus w17; b=b cycles left 23 bits; d=d plus w28;
h=h plus w29; d=d plus w27; w28=h cyclically shifts left by 23 bits before exclusive or H;
h=hcyclically shifts left by 15 bits before exclusive or w28; f=f cycles left 13 bits.
Further, parameters defining the RFB function are a, B, C, D, E, F, G, H, w0, w4;
wherein A, B, C, D, E, F, G, H represent 8 32-bit word registers for storing the iteratively compressed words; w0,24 represents a 32-bit register for holding a message extension word;
w30=w30 cycles left 31 bits; w29=g is inverted and then taken from E; w28=e and F;
w27=a cycles left by 20 bits; w17=e plus w30; h=h plus w0;
w17=w17 plus w27; w28=w29 or w28; w29=a or B;
w0=w0 exclusive or w4; w17=w17 cycles left 25 bits; h=h plus w28;
d=d plus w0; h=h plus w17; w29=w29 and C; w28=a and B;
b=b cycles left 23 bits; w17=w17 exclusive or w27; w29=w29 or w28;
d=d plus w29; w28=h cyclically shifts left by 23 bits before exclusive or H; d=d plus w17;
h=hcyclically shifts left by 15 bits before exclusive or w28; f=f cycles left 13 bits.
Further, parameters defining the macro GalWj function are Wj0, wj3, wj6, wj9, wj12, wj15;
wj0 represents the first extended message word neon register, which is the input register;
wj3 represents a second extended message word neon register, which is an input register;
wj6 represents a third extended message word neon register, which is an input register;
wj9 represents a fourth extended message word neon register, which is an input register;
wj12 represents a fifth extended message word neon register, which is an input register;
wj15 is an output register for storing newly generated extended message words;
wj12 logically shifts left 15 bits according to 32-bit groups and stores the shifted left 15 bits in V22;
Wj12 logically shifts right by 17 bits per packet in 32-bit packets before inserting into V22;
calling an ext instruction, cascading Wj9 and Wj9 into a 256-bit register, circularly moving the 256-bit register to the left by 4 bytes, and taking the lower 128 bits of the 256-bit register to V23; wj6 exclusive-or V22 and then storing the exclusive-or to V22;
wj3 is stored in V21 after shifting 7 bits to the left according to the logic of each 32-bit packet;
wj3 is inserted into V21 after logically shifting to the right by 25 bits per packet in 32-bit packets;
calling an ext instruction, cascading V22 and Wj9 into a 256-bit register, circularly moving 4 bytes leftwards, and taking 128 bits low to V22; v21 exclusive or V23 and then storing the exclusive or to V23; wj0 is exclusive or to V22 and then is stored to V22;
v22 groups each group according to 32 bits, logically shifts left by 15 bits and stores the group to V21;
v22 is inserted into V21 after each group is logically shifted to the right by 17 bits according to 32-bit groups;
v22 exclusive or V23 and then storing the exclusive or to V23;
v22 groups each group according to 32 bits, logically shifts left by 23 bits and stores the group to V24;
v22 is inserted into V24 after each group is logically shifted to the right by 9 bits according to 32-bit groups;
v21 exclusive or V23 and then storing the exclusive or to V23; v24 exclusive or V23 and then storing the mixture into V23;
invoking an ext instruction, cascading Wj12 and V23 into a 256-bit register, circularly moving the 256-bit register to the left by 12 bytes, and taking the lower 128 bits of the 256-bit register to Wj15.
Example two
The embodiment provides a quick signature verification implementation system based on a national encryption algorithm;
a mobile device message compression rapid implementation system based on a cryptographic algorithm comprises: carrying out hash processing on the input message by adopting a national encryption algorithm to obtain a digital abstract;
wherein the hash processing includes:
carrying out message expansion and iterative compression on an input message, and outputting a hash value, wherein the hash value is a hash processing result;
wherein said performing message expansion and iterative compression on the input message, outputting a hash value, comprises:
defining a message extension function format: function name (output hash value memory address, input message length);
applying for a stack space, and storing a register into the stack space; reading N message words from the output hash value memory address, and storing the N message words into a designated general register of the aarch64 processor;
performing iterative compression, copying the bit words from the neon register of the aarch64 processor to a designated general register of the aarch64 processor, performing a message expansion function, saving the obtained new bit words to the neon register of the aarch64 processor, and finally outputting a hash value.
It should be noted that the above modules are the same as examples and application scenarios implemented by the corresponding steps, but are not limited to the disclosure of the above embodiment one. It should be noted that the modules described above may be implemented as part of a system in a computer system, such as a set of computer-executable instructions.
The foregoing embodiments are directed to various embodiments, and details of one embodiment may be found in the related description of another embodiment.
The proposed system may be implemented in other ways. For example, the system embodiments described above are merely illustrative, such as the division of the modules described above, are merely a logical function division, and may be implemented in other manners, such as multiple modules may be combined or integrated into another system, or some features may be omitted, or not performed.
Example III
The embodiment also provides an electronic device, including: one or more processors, one or more memories, and one or more computer programs; wherein the processor is coupled to the memory, the one or more computer programs being stored in the memory, the processor executing the one or more computer programs stored in the memory when the electronic device is running, to cause the electronic device to perform the method of the first embodiment.
It should be understood that in this embodiment, the processor may be a central processing unit CPU, and the processor may also be other general purpose processors, digital signal processors DSP, application specific integrated circuits ASIC, off-the-shelf programmable gate array FPGA or other programmable logic device, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The memory may include read only memory and random access memory and provide instructions and data to the processor, and a portion of the memory may also include non-volatile random access memory. For example, the memory may also store information of the device type.
In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in a processor or by instructions in the form of software.
The method in the first embodiment may be directly implemented as a hardware processor executing or implemented by a combination of hardware and software modules in the processor. The software modules may be located in a random access memory, flash memory, read only memory, programmable read only memory, or electrically erasable programmable memory, registers, etc. as well known in the art. The storage medium is located in a memory, and the processor reads the information in the memory and, in combination with its hardware, performs the steps of the above method. To avoid repetition, a detailed description is not provided herein.
Those of ordinary skill in the art will appreciate that the elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
Example IV
The present embodiment also provides a computer-readable storage medium storing computer instructions that, when executed by a processor, perform the method of embodiment one.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. The mobile equipment message compression quick implementation method based on the cryptographic algorithm is characterized by comprising the following steps:
carrying out hash processing on the input message by adopting a national encryption algorithm to obtain a digital abstract;
wherein the hash processing includes: carrying out message expansion and iterative compression on an input message, and outputting a hash value, wherein the hash value is a hash processing result;
wherein said performing message expansion and iterative compression on the input message, outputting a hash value, comprises:
defining a message extension function format: function name (output hash value memory address, input message length);
Applying for a stack space, and storing a register into the stack space; reading N message words from the output hash value memory address, and storing the N message words into a designated general register of the aarch64 processor;
performing iterative compression, copying the bit words from the neon register of the aarch64 processor to a designated general register of the aarch64 processor, performing a message expansion function, saving the obtained new bit words to the neon register of the aarch64 processor, and finally outputting a hash value.
2. The method for quickly implementing message compression of mobile device based on cryptographic algorithm of claim 1, wherein performing iterative compression copies a bit word from a neon register of aarch64 processor to a designated general register of aarch64 processor, performing message expansion function, saving the obtained new bit word to the neon register of aarch64 processor, and finally outputting hash value, comprising:
2-1: reading 64 bytes from the memory address corresponding to the x16 register to the V0-V3 register, and simultaneously, adding 64 to the value of the x16 register to update the result into the x16 register; for the V0-V3 registers, realizing the reverse order of 32-bit bytes; reading the 32-bit unsigned integer 0x79cc4519 to w30 register; copying the values of the w 19-w 26 registers into the w 8-w 15 registers; copying the first 7 32-bit word messages from the neon register to w 0-w 6 registers;
2-2: performing a first round of iterative compression; reassigning message extension registers V0-V3 to V0, V5, V6, V7, V3, V8; executing the message expansion function to obtain 4 32-bit words, and storing the 4 32-bit words into a designated neon register; performing two rounds of iterative compression; copying 3 32-bit word messages from the neon registers to a designated general purpose register;
2-3: three rounds of iterative compression are performed; copying three 32-bit words from the neon registers to a designated general purpose register; executing the message expansion function to obtain 4 new 32-bit words, and storing the 4 new 32-bit words into an execution neon register;
2-4: performing message expansion like 2-3 three times;
2-5: performing a round of iterative compression; copy 0xcec53d43 into w30 register; performing two rounds of iterative compression; copying 3 32-bit words from the neon registers to a designated general purpose register; executing the message expansion function to obtain 4 new 32-bit words, and storing the 4 new 32-bit words into a designated neon register;
2-6: three rounds of iterative compression are performed; copying 3 32-bit words from the neon registers to a designated general purpose register; executing the message expansion function to obtain 4 new 32-bit words, and storing the 4 new 32-bit words into a designated neon register;
2-7: performing message expansion similar to 2-6 ten times;
2-8: three rounds of iterative compression are performed; copying 3 32-bit words from the neon registers to a designated general purpose register; three rounds of iterative compression are performed; copying 3 32-bit words from the neon registers to a designated general purpose register; three rounds of iterative compression are performed; copying 1 32-bit word from the neon register to a designated general purpose register; performing a round of iterative compression; updating the values of the w19-w26 registers;
2-9: judging whether the value of the x16 register is equal to the value of the x7 register, if so, entering S102-10; if not, returning to 2-1;
2-10: popping to the x9 register; outputting the w19-w26 registers to the 32-byte memory addresses corresponding to the x9 registers; stacking to R19-R30; the stack space is freed.
3. The method for quickly implementing message compression of mobile equipment based on the cryptographic algorithm as in claim 2, wherein the method is characterized in that the method comprises the following steps: performing a first round of iterative compression, comprising:
performing a second class of iterative compression functions RFA1: the first 8 parameters w19-w26 are word registers used for storing iterative compression; the latter two parameters w0, w4 are message expansion word registers, the iterative compression performs iterative compression operations on the registers, and updates the values of the iterative compression word registers w19-w 26:
RFA1 w19,w20,w21,w22,w23,w24,w25,w26,w0,w4；
The RFA1 instruction sequence completes the first round of iterative compression and simultaneously reallocates a message expansion neon register;
defining RFA1 function parameters as A, B, C, D, E, F, G, H, w0 and w4;
a, B, C, D, E, F, G, H represent 8 32-bit word registers for storing the iteratively compressed words; w0,24 represents a 32-bit register for holding a message extension word;
w27=w27 cycles shift right by 20 bits; w17=e plus w27; w28=a exclusive or B; w29=e exclusive or F;
executing three ext instructions reassembles the words in the neon registers, the layout of the message words originally saved in the neon registers is:
the neon register numbered 0 holds the 0,1,2,3 th word; the neon register number 1 holds the 4,5,6,7 th word; the neon register number 2 holds words 8,9,10, 11; the neon register number 3 holds words 12,13,14, 15;
after adjustment, the message is modified into 5 registers for storage, so that parallel message expansion is convenient to execute;
the neon register numbered 0 holds the 0,1,2,3 th word; the neon register No. 5 holds the 3,4,5,6 words; the neon register number 6 holds the 6 th, 7 th, 8 th, 9 th words; the neon register number 7 holds words 9,10,11, 12; the neon register number 3 holds words 12,13,14, 15;
The three ext instructions are executed to recombine the words in the neon register, comprising the following steps:
calling an ext instruction, cascading V0 and V1 into 256-bit registers, circularly moving the 256-bit registers to the left by 12 bytes, and taking the lower 128 bits of the 256-bit registers to V5;
calling an ext instruction, cascading V1 and V2 into 256-bit registers, circularly moving the 256-bit registers to the left by 8 bytes, and taking the lower 128 bits of the 256-bit registers to V6;
calling an ext instruction, cascading V2 and V3 into 256-bit registers, circularly moving the 256-bit registers to the left by 4 bytes, and taking the lower 128 bits of the 256-bit registers to V7;
h=h plus w0; w17=w17 plus w30; w28=w28 exclusive or C; w29=w29 exclusive or G;
w0=w0 exclusive or w4; w17=w17 cycles left 25 bits; w27=w17 exclusive or w27;
d=dxor w0; h=h plus w17; b=b cycles left 23 bits; d=d plus w28;
h=h plus w29; d=d plus w27; w28=h cyclically shifts left by 23 bits before exclusive or H;
h=hcyclically left-shifted by 15 bits exclusive or w28; f=f cycles left 13 bits.
4. The method for quickly implementing message compression of mobile equipment based on the cryptographic algorithm as in claim 2, wherein the method is characterized in that the method comprises the following steps: reassigning message extension registers V0-V3 through V0, V5, V6, V7, V3, V8, comprising: executing a message expansion function, wherein the first 5 parameters are input neon registers; the last register is an output register, and the calculated extended message word is saved to an output calculator:
GalWj V0,V5,V6,V7,V3,V8；
The parameters defining the macro GalWj function are Wj0, wj3, wj6, wj9, wj12, wj15;
wj0 represents the first extended message word neon register, which is the input register; wj3 represents a second extended message word neon register, which is an input register; wj6 represents a third extended message word neon register, which is an input register; wj9 represents a fourth extended message word neon register, which is an input register; wj12 represents a fifth extended message word neon register, which is an input register; wj15 is an output register for storing newly generated extended message words; wj12 logically shifts left 15 bits according to 32-bit groups and stores the shifted left 15 bits in V22; wj12 logically shifts right by 17 bits per packet in 32-bit packets before inserting into V22;
calling an ext instruction, cascading Wj9 and Wj9 into a 256-bit register, circularly moving the 256-bit register to the left by 4 bytes, and taking the lower 128 bits of the 256-bit register to V23; wj6 exclusive-or V22 and then storing the exclusive-or to V22; wj3 is stored in V21 after shifting 7 bits to the left according to the logic of each 32-bit packet; wj3 is inserted into V21 after logically shifting to the right by 25 bits per packet in 32-bit packets;
calling an ext instruction, cascading V22 and Wj9 into a 256-bit register, circularly moving 4 bytes leftwards, and taking 128 bits low to V22; v21 exclusive or V23 and then storing the exclusive or to V23; wj0 is exclusive or to V22 and then is stored to V22;
V22 groups each group according to 32 bits, logically shifts left by 15 bits and stores the group to V21; v22 is inserted into V21 after each group is logically shifted to the right by 17 bits according to 32-bit groups; v22 exclusive or V23 and then storing the exclusive or to V23; v22 groups each group according to 32 bits, logically shifts left by 23 bits and stores the group to V24; v22 is inserted into V24 after each group is logically shifted to the right by 9 bits according to 32-bit groups; v21 exclusive or V23 and then storing the exclusive or to V23; v24 exclusive or V23 and then storing the mixture into V23; invoking an ext instruction, cascading Wj12 and V23 into a 256-bit register, circularly moving the 256-bit register to the left by 12 bytes, and taking the lower 128 bits of the 256-bit register to Wj15.
5. The method for quickly implementing message compression of mobile equipment based on the cryptographic algorithm as in claim 2, wherein the method is characterized in that the method comprises the following steps: performing two rounds of iterative compression, including:
executing an iterative compression operation function, wherein the first 8 parameters are word registers used for storing iterative compression; the latter two parameters are message expansion word registers, the iterative compression is performed on the registers, and the values of the iterative compression word registers are updated:
RFA w22,w19,w20,w21,w26,w23,w24,w25,w1,w5；
RFA w21,w22,w19,w20,w25,w26,w23,w24,w2,w6；
defining parameters of macro RFA function as A, B, C, D, E, F, G, H, w0 and w4;
wherein A, B, C, D, E, F, G, H represent 8 32-bit word registers for storing the iteratively compressed words; w0,24 represents a 32-bit register for holding a message extension word;
w30=w30 cycles left 31 bits; w27=w27 cycles shift left by 20 bits; w17=e plus w27; w28=a exclusive or B; w29=e exclusive or F; h=h plus w0; w17=w17 plus w30; w28=w28 exclusive or C; w29=w29 exclusive or G; w0=w0 exclusive or w4; w17=w17 cycles left 25 bits; w27=w17 exclusive or w27; d=d plus w0; h=h plus w17; b=b cycles left 23 bits; d=d plus w28; h=h plus w29; d=d plus w27; w28=h cyclically shifts left by 23 bits before exclusive or H; h=hcyclically shifts left by 15 bits before exclusive or w28; f=f cycles left 13 bits.
6. The method for quickly implementing message compression of mobile equipment based on the cryptographic algorithm as in claim 2, wherein 2-5: performing two rounds of iterative compression, including:
executing an iterative compression operation function, wherein the first 8 parameters are word registers used for storing iterative compression; the latter two parameters are message extended word registers, performing iterative compression operation on the registers, and updating the values of the iterative compressed word registers:
RFB w19,w20,w21,w22,w23,w24,w25,w26,w2,w6；
RFB w22,w19,w20,w21,w26,w23,w24,w25,w3,w0；
parameters defining the RFB function are A, B, C, D, E, F, G, H, w0 and w4;
wherein A, B, C, D, E, F, G, H represent 8 32-bit word registers for storing the iteratively compressed words; w0,24 represents a 32-bit register for holding a message extension word;
w30=w30 cycles left 31 bits; w29=g is inverted and then taken from E; w28=e and F; w27=a cycles left by 20 bits; w17=e plus w30; h=h plus w0; w17=w17 plus w27; w28=w29 or w28; w29=a or B; w0=w0 exclusive or w4; w17=w17 cycles left 25 bits; h=h plus w28; d=d plus w0; h=h plus w17; w29=w29 and C; w28=a and B; b=b cycles left 23 bits; w17=w17 exclusive or w27; w29=w29 or w28; d=d plus w29; w28=h cyclically shifts left by 23 bits before exclusive or H; d=d plus w17; h=hcyclically shifts left by 15 bits before exclusive or w28; f=f cycles left 13 bits.
7. The method for quickly implementing message compression of mobile equipment based on the cryptographic algorithm as in claim 2, wherein the steps of 2-5: copying 3 32-bit words from the neon registers to a designated general purpose register specifically includes: copy the 1 st 32-bit word of the V10 register to the w1 register; copy the 2 nd 32-bit word of the V10 register to the w2 register; the 3 rd 32-bit word of the V10 register is copied to the w3 register.
8. The mobile device message compression quick realizing system based on the national encryption algorithm is characterized by comprising the following components: carrying out hash processing on the input message by adopting a national encryption algorithm to obtain a digital abstract;
wherein the hash processing includes: carrying out message expansion and iterative compression on an input message, and outputting a hash value, wherein the hash value is a hash processing result;
wherein said performing message expansion and iterative compression on the input message, outputting a hash value, comprises:
defining a message extension function format: function name (output hash value memory address, input message length);
applying for a stack space, and storing a register into the stack space; reading N message words from the output hash value memory address, and storing the N message words into a designated general register of the aarch64 processor;
Performing iterative compression, copying the bit words from the neon register of the aarch64 processor to a designated general register of the aarch64 processor, performing a message expansion function, saving the obtained new bit words to the neon register of the aarch64 processor, and finally outputting a hash value.
9. An electronic device, comprising:
a memory for non-transitory storage of computer readable instructions; and
a processor for executing the computer-readable instructions,
wherein the computer readable instructions, when executed by the processor, perform the method of any of the preceding claims 1-7.
10. A storage medium, characterized by non-transitory storage of computer readable instructions, wherein the instructions of the method of any of claims 1-7 are performed when the non-transitory computer readable instructions are executed by a computer.
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