CN117578861A - Soft start control circuit, DC-DC voltage converter and soft start control method - Google Patents

Soft start control circuit, DC-DC voltage converter and soft start control method Download PDF

Info

Publication number
CN117578861A
CN117578861A CN202311369301.7A CN202311369301A CN117578861A CN 117578861 A CN117578861 A CN 117578861A CN 202311369301 A CN202311369301 A CN 202311369301A CN 117578861 A CN117578861 A CN 117578861A
Authority
CN
China
Prior art keywords
voltage
signal
switching tube
soft start
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202311369301.7A
Other languages
Chinese (zh)
Inventor
尹延洋
赵倡申
李海松
陶平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Suzhou Poweron IC Design Co Ltd
Original Assignee
Suzhou Poweron IC Design Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Suzhou Poweron IC Design Co Ltd filed Critical Suzhou Poweron IC Design Co Ltd
Priority to CN202311369301.7A priority Critical patent/CN117578861A/en
Publication of CN117578861A publication Critical patent/CN117578861A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/36—Means for starting or stopping converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0038—Circuits or arrangements for suppressing, e.g. by masking incorrect turn-on or turn-off signals, e.g. due to current spikes in current mode control
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/157—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load

Abstract

A soft start control circuit, a DC-DC voltage converter and a soft start control method are provided. The soft start control circuit includes: the soft start step length setting circuit is suitable for generating a soft start voltage signal with a fixed slope; and the soft start frequency control circuit is connected with the soft start step length setting circuit of the DC-DC voltage converter and is suitable for generating a first clock signal with self-adaptive frequency based on the switching state of a switching tube in the DC-DC voltage converter in the current switching period, wherein the first clock signal is used for adjusting the working frequency of the DC-DC voltage converter in the next switching period so that the working frequency of the DC-DC voltage converter in the soft start stage is matched with the change of the voltage difference value between the feedback voltage signal and the soft start voltage signal. By adopting the scheme, the output voltage starting process is smoother and has smaller ripple while the excessive current and the overshoot of the output voltage at the instant of power-on are prevented.

Description

Soft start control circuit, DC-DC voltage converter and soft start control method
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a soft start control circuit, a DC-DC voltage converter and a soft start control method.
Background
The DC-DC voltage converter is widely applied to portable electronic equipment by virtue of high efficiency, low power consumption and the like.
However, the output voltage of the DC-DC voltage converter is controlled by an output voltage feedback terminal. After the electronic equipment is started, the voltage of the output voltage feedback end instantaneously reaches the reference voltage value set by the system, and at the stage, the output voltage of the DC-DC voltage converter rapidly rises to generate instantaneous heavy current, so that the damage to internal devices of the electronic equipment can be caused, and the service life of the electronic equipment is seriously influenced. Therefore, a soft start control circuit applied to a DC-DC voltage converter is important.
At present, a common soft start control circuit generates a soft start slope voltage with a fixed slope, so that the voltage of an output voltage feedback end of a DC-DC voltage converter can change along with the change of the soft start slope voltage, and the problems of overlarge current and overshoot of the output voltage at the moment of power-on are prevented.
However, the soft start control circuit can prevent the problems of excessive current and overshoot of output voltage at the instant of power-on, but has the problems of unsmooth starting process of the output voltage and larger ripple wave, and is difficult to meet the requirements of modern electronic equipment.
Disclosure of Invention
The invention aims to solve the problems that: the starting process of the output voltage is smoother and has smaller ripple while the excessive current and the overshoot of the output voltage at the moment of power-on are prevented.
To solve the above problems, an embodiment of the present invention provides a soft start control circuit applied to a DC-DC voltage converter, the DC-DC voltage converter including: the switching tube and the output voltage feedback end are suitable for providing feedback voltage signals for feeding back the change of the output voltage; the soft start control circuit includes:
the soft start step length setting circuit is suitable for generating a soft start voltage signal with a fixed slope;
and the soft start frequency control circuit is connected with the soft start step length setting circuit of the DC-DC voltage converter and is suitable for generating a first clock signal with self-adaptive frequency based on the switching state of a switching tube in the DC-DC voltage converter in the current switching period, wherein the first clock signal is used for adjusting the working frequency of the DC-DC voltage converter in the next switching period so that the working frequency of the DC-DC voltage converter in the soft start stage is matched with the change of the voltage difference value between the feedback voltage signal and the soft start voltage signal.
Optionally, the soft start frequency control circuit includes:
the difference detection sub-circuit is suitable for detecting the voltage difference between the feedback voltage signal and the soft start voltage signal in the soft start stage of the DC-DC voltage converter to obtain a difference detection result signal;
the current follower circuit is connected with the difference detection circuit and is suitable for generating a current signal which changes along with the difference detection result signal;
and the self-adaptive clock generation sub-circuit is connected with the current following sub-circuit and is suitable for generating the first clock signal by using the current signal based on the switching state of a switching tube in the DC-DC voltage converter.
Optionally, the difference detection sub-circuit includes:
the error amplifier is provided with a first input end, a second input end and a third input end, wherein the first input end of the error amplifier is suitable for being connected with the soft start voltage signal, the second input end of the error amplifier is suitable for being connected with a first reference voltage signal, and the third input end of the error amplifier is suitable for being connected with a feedback voltage signal;
the error amplifier is suitable for comparing the voltage of the soft start voltage signal with the voltage of the first reference voltage signal, and amplifying the voltage difference between the soft start voltage signal and the feedback voltage signal when the voltage of the soft start voltage signal is smaller than the voltage of the first reference voltage signal to obtain an error amplified signal.
Optionally, the current follower sub-circuit includes:
the current following module is connected with the difference detection subcircuit and is suitable for generating the current signal and controlling the current signal to follow the change of the difference detection result signal;
and the current mirror module is suitable for carrying out mirror image processing on the current signal to obtain a mirror image current signal.
Optionally, the current follower module is adapted to control a change in the current signal inversely proportional to a change in the difference detection result signal.
Optionally, the current following module includes:
the first comparator is provided with a first input end and a second input end, the first input end of the first comparator is connected with the output end of the difference detection sub-circuit, and the second input end of the first comparator is suitable for being connected with a first threshold voltage signal;
the control end of the first switching tube is connected with the output end of the first comparator, the first end of the first switching tube is connected with the current following sub-circuit, and the second end of the first switching tube is connected with the difference value detection sub-circuit;
the first comparator is suitable for comparing the voltage of the difference detection result signal with a first threshold voltage provided by the first threshold voltage signal, controlling the first switching tube to be conducted when the voltage of the difference detection result signal is smaller than the first threshold voltage, and controlling the first switching tube to be conducted when the voltage of the difference detection result signal is larger than or equal to the first threshold voltage so as to generate the current signal and enable the current signal to follow the change of the difference detection result signal.
Optionally, the current mirror module includes: third switching tube, fourth switching tube, fifth switching tube, sixth switching tube, seventh switching tube, eighth switching tube, first current source, second current source, first resistance and second resistance, wherein:
the third switching tube is connected with the current following module, the fourth switching tube is connected with the third switching tube and the fifth switching tube, the fifth switching tube is connected with the first current source and the sixth switching tube, the sixth switching tube is connected with the first resistor and the second current source, and the seventh switching tube is connected with the sixth switching tube, the eighth switching tube and the second resistor.
Optionally, the first capacitor and the second capacitor are the same in size; the resistance value of the first resistor is K times of the resistance value of the second resistor R5; the channel lengths of the third switching tube to the eighth switching tube are the same and the width-to-length ratio is proportional; the current value provided by the first current source is K times of the current value provided by the second current source, and K is a positive number.
Optionally, the adaptive clock generation sub-circuit includes: the third comparator, the ninth switch tube, the first capacitor and the second capacitor, wherein:
The ninth switching tube and the first capacitor are connected with the second current source in parallel, and the second capacitor is connected with the second resistor in parallel;
the third comparator is provided with a first input end and a second input end; the first input end of the third comparator is connected with the sixth switching tube and the first resistor; and the second input end of the third comparator is connected with the seventh switching tube and the second resistor.
Optionally, the control terminal of the ninth switching tube is adapted to be connected to a dead zone signal representing a switching state of the switching tube in the DC-DC voltage converter in a current switching cycle, and the voltage of the first input terminal of the third comparator is adjusted based on the dead zone signal.
Optionally, the soft start step length setting circuit includes:
the fixed clock generation sub-circuit comprises a third current source, a second capacitor and a third clock generation sub-circuit, wherein the third current source predicts the third capacitor and is suitable for charging and discharging the third capacitor by utilizing the third current source to generate a second clock signal with fixed frequency;
the frequency divider circuit is suitable for carrying out frequency division processing on the second clock signal to obtain a frequency-divided second clock signal and an inverted signal of the frequency-divided second clock signal;
and the sampling and holding sub-circuit is connected with the fixed clock generation sub-circuit and the frequency division sub-circuit and is suitable for sampling and holding the voltage of the third capacitor under the control of the frequency-divided second clock signal and the inverted signal of the frequency-divided second clock signal.
Optionally, the fixed clock generation sub-circuit includes: the third current source, the fourth capacitor, the fourth comparator and the tenth switching tube; wherein;
the third current source is connected with the fourth capacitor in series, and the tenth switching tube is connected with the fourth capacitor in parallel; the control end of the tenth switching tube is connected with the output end of the fourth comparator;
the fourth comparator is provided with a first input end and a second input end; the first input end of the fourth comparator is connected with the third current source and the fourth capacitor; the second input end of the fourth comparator is suitable for being connected with a second reference voltage signal; the fourth comparator is adapted to compare the voltage of the fourth capacitor with a second reference voltage provided by the second reference voltage signal, so as to obtain the second clock signal.
Optionally, the sample-and-hold sub-circuit includes: an eleventh switching tube, a fifth capacitor, a twelfth switching tube, a thirteenth switching tube, a fourteenth switching tube, an operational amplifier, a sixth capacitor and a seventh capacitor; wherein:
the control end of the eleventh switching tube and the control end of the fourteenth switching tube are connected with the second clock signal after frequency division; the control end of the twelfth switching tube and the control end of the thirteenth switching tube are connected with the inverted signal of the second clock signal after frequency division;
The eleventh switching tube, the fifth capacitor and the twelfth switching tube are connected in series and are connected with the first input end of the operational amplifier; a second input end of the operational amplifier is grounded; the sixth capacitor is connected with the first input end of the operational amplifier and the output end of the operational amplifier; one end of the seventh capacitor is connected with the output end of the operational amplifier, and the other end of the seventh capacitor is grounded;
one end of the thirteenth switching tube is connected with the eleventh switching tube and the fifth capacitor, and the other end of the thirteenth switching tube is grounded;
one end of the fourteenth switching tube is connected with the twelfth switching tube and the fifth capacitor, and the other end of the fourteenth switching tube is grounded.
Embodiments of the present invention also provide a DC-DC voltage converter including:
the voltage conversion circuit comprises a switching tube and is suitable for carrying out voltage conversion on input voltage;
the feedback circuit is connected with the voltage conversion circuit and provided with an output voltage feedback end, and is suitable for generating a feedback voltage signal based on the output voltage of the voltage conversion circuit so as to control the output voltage of the voltage conversion circuit;
a soft start control circuit as in any one of the embodiments above; the soft start control circuit is connected with the voltage conversion circuit and the feedback circuit and is suitable for providing a first clock signal with self-adaptive frequency;
The logic control circuit is connected with the soft start control circuit and is suitable for acquiring the first clock signal and the turn-off control signal and carrying out logic control on a switching tube in the voltage conversion circuit based on the first clock signal and the turn-off control signal.
Optionally, the logic control circuit includes:
a selector having a first input terminal and a second input terminal; the first input end of the selector is connected with the soft start control circuit, and the second input end of the selector is suitable for being connected with a third clock signal with fixed frequency;
the second SR trigger is provided with a first input end and a second input end; the first input end of the second SR trigger is connected with the output end of the selector, and the second input end is suitable for being connected with the turn-off control signal;
and the logic driving sub-circuit is connected with the output end of the second SR trigger and is suitable for controlling the on-off of a switching tube in the voltage conversion circuit based on the output of the second SR trigger.
Optionally, the logic driving sub-circuit is connected to the soft start control circuit and adapted to provide a dead zone signal reflecting a switching state of a switching tube in the DC-DC voltage converter to the soft start control circuit to generate the first clock signal.
The embodiment of the invention also provides a soft start control method which is applied to the DC-DC voltage converter, wherein the DC-DC voltage converter comprises the following components: the switching tube and the output voltage feedback end are suitable for providing feedback voltage signals for feeding back the change of the output voltage; the method comprises the following steps:
generating a soft start voltage signal with a fixed slope;
and generating a first clock signal with self-adaptive frequency based on the switching state of a switching tube in the DC-DC voltage converter in the current switching period, wherein the first clock signal is used for adjusting the working frequency of the DC-DC voltage converter in the next switching period, so that the working frequency of the DC-DC voltage converter in the soft start stage is adaptive to the change of the voltage difference value between the feedback voltage signal and the soft start voltage signal.
Optionally, the generating the first clock signal with the adaptive frequency based on the switching state of the switching tube in the DC-DC voltage converter includes:
detecting a voltage difference value between the feedback voltage signal and the soft start voltage signal to obtain a difference value detection result signal;
generating a current signal that varies in response to the difference detection result signal;
And generating the first clock signal by using the current signal based on the switching state of a switching tube in the DC-DC voltage converter in the current switching period.
Optionally, the change in the current signal is inversely proportional to the change in the difference detection result signal.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
by adopting the scheme of the invention, the soft start step length setting circuit and the soft start frequency control circuit are arranged, and the soft start step length setting circuit can generate a soft start voltage signal with a fixed slope, so that the output voltage of the DC-DC voltage converter can stably and gently rise, and the surge current and the overshoot voltage of the DC-DC voltage converter in the soft start stage are effectively prevented. The soft start frequency control circuit can generate a first clock signal with self-adaptive frequency based on the switching state of a switching tube in the DC-DC voltage converter, and the first clock signal can adjust the working frequency of the DC-DC voltage converter, so that the working frequency of the DC-DC voltage converter in a soft start stage is adaptive to the change of a voltage difference value between the feedback voltage signal and the soft start voltage signal, and further the DC-DC voltage converter can be in a low-frequency intermittent mode in the first few periods of the soft start stage, and the output voltage of the DC-DC voltage converter can be smoother and has smaller ripple in the soft start stage.
Drawings
FIG. 1 is a schematic diagram of a soft start control circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a soft start frequency control circuit according to an embodiment of the present invention;
FIG. 3 is a timing diagram of related signals of a soft start frequency control circuit according to an embodiment of the present invention;
FIG. 4 is a schematic circuit diagram of a soft start step length setting circuit according to an embodiment of the present invention;
FIG. 5 is a timing diagram of related signals in a soft start step length setting process according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a DC-DC voltage converter according to an embodiment of the invention;
fig. 7 is a schematic circuit diagram of a DC-DC voltage converter according to an embodiment of the present invention;
FIG. 8 is a flow chart of a soft start control method in an embodiment of the invention;
fig. 9 is a timing diagram of signals associated with a DC-DC voltage converter during soft start control.
Detailed Description
The existing common soft start control circuit can enable the voltage of the output voltage feedback end of the DC-DC voltage converter to change along with the change of the soft start slope voltage by generating a soft start slope voltage with a fixed slope, thereby preventing the problems of overlarge current and overshoot of the output voltage in the instant of power-on. However, the soft start control circuit can prevent the problems of excessive current and overshoot of output voltage at the instant of power-on, but has the problems of unsmooth starting process of the output voltage and larger ripple wave, and is difficult to meet the requirements of modern electronic equipment.
In order to solve the problem, the invention provides a soft start control circuit which comprises a soft start step length setting circuit and a soft start frequency control circuit, wherein the soft start step length setting circuit can generate a soft start voltage signal with a fixed slope to prevent surge current and overshoot voltage of a DC-DC voltage converter in a soft start stage. The soft start frequency control circuit can generate a first clock signal with self-adaptive frequency based on the switching state of a switching tube in the DC-DC voltage converter, and the working frequency of the DC-DC voltage converter is adjusted through the first clock signal, so that the working frequency of the DC-DC voltage converter in a soft start stage is adaptive to the change of a voltage difference value between the feedback voltage signal and the soft start voltage signal, and the output voltage of the DC-DC voltage converter is smoother and has smaller ripple in the soft start stage.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Referring to fig. 1, an embodiment of the present invention provides a soft start control circuit. The soft start control circuit is applied to a DC-DC voltage converter including: the switching tube and the output voltage feedback end are suitable for providing feedback voltage signals for feeding back the change of the output voltage.
Specifically, the soft start control circuit may include: a soft start step length setting circuit 11 and a soft start frequency control circuit 12. Wherein:
the soft start step length setting circuit 11 is adapted to generate a soft start voltage signal with a fixed slope.
The soft start frequency control circuit 12 is connected with the soft start step length setting circuit 11 of the DC-DC voltage converter, and is adapted to generate a first clock signal with an adaptive frequency based on a switching state of a switching tube in the DC-DC voltage converter in a current switching period, where the first clock signal is used to adjust a working frequency of the DC-DC voltage converter in a next switching period, so that the working frequency of the DC-DC voltage converter in a soft start stage is adapted to a change of a voltage difference between the feedback voltage signal and the soft start voltage signal.
The soft-start frequency control circuit 12 uses the switching period of the switching tube in the DC-DC voltage converter as a frequency adjustment period, and adjusts the switching frequency of the switching tube in the DC-DC voltage converter in the next switching period based on the switching state of the switching tube in the DC-DC voltage converter in the current switching period, so as to adjust the working frequency of the DC-DC voltage converter, so that the working frequency of the DC-DC voltage converter in the soft-start stage can be adapted to the variation of the voltage difference between the feedback voltage signal and the soft-start voltage signal, and the output voltage of the DC-DC voltage converter can be smoother in the soft-start stage with smaller ripple.
The DC-DC voltage converter may be a DC-DC voltage converter with any circuit structure, as long as the DC-DC voltage converter includes a switching tube and an output voltage feedback terminal, and the circuit structure of the DC-DC voltage converter is not limited herein.
In a specific implementation, the soft-start frequency control circuit 12 may have various structures, which are not limited herein, so long as the first clock signal can be generated based on the switching state of the switching tube in the DC-DC voltage converter in the current switching period.
In one embodiment of the present invention, with continued reference to fig. 1, the soft start frequency control circuit 12 may include: a difference detection sub-circuit 121, a current follower sub-circuit 122, and an adaptive clock generation sub-circuit 123. Wherein:
the difference detection sub-circuit 121 is adapted to detect a voltage difference between the feedback voltage signal and the soft start voltage signal during a soft start phase of the DC-DC voltage converter, to obtain a difference detection result signal;
the current follower sub-circuit 122 is connected to the difference detection circuit 121 and is adapted to generate a current signal that changes along with the difference detection result signal;
the adaptive clock generation sub-circuit 123 is connected to the current follower sub-circuit 122 and is adapted to generate the first clock signal based on the switching state of the switching tubes in the DC-DC voltage converter using the current signal.
In an implementation, referring to fig. 2, the difference detection subcircuit 121 may be implemented with an error amplifier EA, and in particular, the error amplifier EA may have a first input, a second input, and a third input. The first input terminal of the error amplifier EA is adapted to be connected to the soft start voltage signal SS, the second input terminal of the error amplifier is adapted to be connected to the first reference voltage signal VREF1, and the third input terminal is adapted to be connected to the feedback voltage signal FB.
The error amplifier EA is adapted to compare the voltage levels of the soft start voltage signal SS and the first reference voltage signal VREF1, and amplify the voltage difference between the soft start voltage signal SS and the feedback voltage signal VREF1 when the voltage of the soft start voltage signal SS is smaller than the voltage of the first reference voltage signal VREF1, so as to obtain an error amplification signal ea_out.
In an embodiment, in the initial state, the voltage value of the error amplification signal ea_out is smaller, and along with the rising of the voltage of the soft start voltage signal SS, the voltage of the feedback voltage signal FB also rises, and the voltage value of the error amplification signal ea_out also gradually rises to a stable value.
In some embodiments, the difference detection sub-circuit 121 may further include a third resistor R3 and a seventh capacitor C7. The third resistor R3 is connected in series with the seventh capacitor C7, the other end of the third resistor R3 is connected with the error amplifier EA, and the other end of the seventh capacitor C7 is grounded. By providing the third resistor R3 and the seventh capacitor C7, stable operation of the entire voltage converter can be maintained.
In a specific implementation, the structure of the current follower sub-circuit 122 may be various, which is not limited herein.
In one embodiment, the current follower sub-circuit 122 may include: the current follower module and the current mirror module. Wherein:
the current following module is connected with the difference detection subcircuit 121, and is suitable for generating the current signal and controlling the current signal to follow the change of the difference detection result signal;
the current mirror module is suitable for carrying out mirror image processing on the current signal to obtain a mirror image current signal.
In a specific implementation, the current signal may follow the change of the difference detection result signal in a plurality of ways, which is not limited herein, as long as the current signal is controlled by the difference detection result signal. In particular, how the current signal follows the variation of the difference detection result signal is related to the circuit configuration of the current follower sub-circuit 122.
In an embodiment, the current follower module may control the change of the current signal to be inversely proportional to the change of the difference detection result signal, that is, the larger the voltage value of the difference detection result signal is, the smaller the current value of the current signal is.
Accordingly, referring to fig. 2, the current following module 1221 may include: the first comparator CMP1 and the first switching transistor Q1. Wherein:
the first comparator CMP1 has a first input end and a second input end, the first input end of the first comparator CMP1 is connected with the output end of the difference detection sub-circuit, and the second input end of the first comparator CMP1 is suitable for being connected with a first threshold voltage signal Vth1;
and a control end of the first switching tube Q1 is connected with the output end of the first comparator CMP1, a first end of the first switching tube Q1 is connected with the current follower sub-circuit, and a second end of the first switching tube Q1 is connected with the difference value detection sub-circuit.
The first comparator CMP1 is adapted to compare the voltage of the difference detection result signal ea_out with a first threshold voltage provided by the first threshold voltage signal Vth1, and to control the first switching tube Q1 to be turned on when the voltage of the difference detection result signal ea_out is smaller than the first threshold voltage Vth1, and to control the first switching tube Q1 to be turned off gradually from on to be turned off when the voltage of the difference detection result signal ea_out is greater than or equal to the first threshold voltage Vth1, so as to generate the current signal i_ea, and to cause the current signal i_ea to follow the change of the difference detection result signal ea_out.
In an implementation, the first switching tube Q1 may be an NMOS tube. At this time, the drain of the first switching tube Q1 may be connected to the current follower sub-circuit, and the source of the first switching tube Q1 may be connected to the output terminal of the error amplifier EA. When the first switching tube Q1 is turned on, a current loop is formed between the current follower sub-circuit and the current follower module and between the current follower sub-circuit and the error amplifier EA, so as to generate a current signal i_ea flowing through the drain electrode of the first switching tube Q1. When the first switching tube Q1 is turned off, a current loop formed between the current follower sub-circuit and the current follower module and the error amplifier EA is also turned off, and the current signal i_ea flowing through the drain of the first switching tube Q1 is gradually reduced.
In an implementation, the first threshold voltage provided by the first threshold voltage signal Vth1 is typically a fixed value. By setting the magnitude of the first threshold voltage, the specific timing at which the first switching transistor Q1 changes from the on state to the off state can be controlled.
FIG. 3 is a timing diagram of the related signals of the soft start frequency control circuit. Referring to fig. 3, in the initial state, the voltage of the difference detection result signal ea_out is generally equal to or less than the first threshold voltage provided by the first threshold voltage signal Vth 1. At this time, the first comparator CMP1 may output a high level signal to control the first switching transistor Q1 to be turned on. At this time, the current signal i_ea flowing through the drain of the first switching tube Q1 reaches a maximum value.
Along with the rising of the soft start voltage signal SS, the feedback voltage signal FB rises along with the rising of the soft start voltage signal SS, and the voltage of the difference detection result signal ea_out also gradually rises, when the voltage of the difference detection result signal ea_out is greater than the first threshold voltage, the gate-source voltage of the first switch tube Q1 is controlled to decrease, and at this time, the change of the current signal i_ea flowing through the drain electrode of the first switch tube Q1 is inversely proportional to the change of the difference detection result signal ea_out. The voltage of the difference detection result signal ea_out gradually increases from the first threshold voltage to a stable value, and the current value of the current signal i_ea gradually decreases from the maximum value to zero.
In an embodiment, the current follower module 122 may further include: the second comparator CMP2 and the second switching transistor Q2. The second comparator CMP2 has a first input and a second input. The first input terminal of the second comparator CMP2 is adapted to be connected to the second threshold voltage signal Vth2, and the second input terminal of the second comparator CMP2 is adapted to be connected to the difference detection result signal ea_out.
The second threshold voltage signal Vth2 is adapted to provide a second threshold voltage, and the second comparator CMP2 is adapted to compare the voltage of the difference detection result signal ea_out with the second threshold voltage, and control the on/off of the second switching tube Q2 according to the comparison result.
In a specific implementation, the second comparator CMP2 is configured to limit the upper limit of the difference detection result signal ea_out, and form a difference detection result signal of a current loop with the difference detection circuit 121 and the current mirror module, where the maximum voltage value of the difference detection result signal should be less than the second threshold voltage, so as to limit the upper limit of the inductor current in the soft start stage.
In a specific implementation, the current mirror module may have various circuit structures, which are not limited herein, so long as the current signal can be mirrored to obtain a mirrored current signal.
In one embodiment, referring to fig. 2, the current mirror module may include: the third switching tube Q3, the fourth switching tube Q4, the fifth switching tube Q5, the sixth switching tube Q6, the seventh switching tube Q7, the eighth switching tube Q8, the first current source I1, the second current source I2, the first resistor R1 and the second resistor R2, wherein:
the third switching tube Q3 is connected to the current follower module 1221, the fourth switching tube Q4 is connected to the third switching tube Q3 and the fifth switching tube Q5, the fifth switching tube Q5 is connected to the first current source I1 and the sixth switching tube Q6, the sixth switching tube Q6 is connected to the first resistor R1 and the second current source I2, and the seventh switching tube Q7 is connected to the sixth switching tube Q6, the eighth switching tube Q8 and the second resistor R2.
In a specific implementation, a control end of the fifth switching tube Q5 is connected to a control end of the sixth switching tube Q6 and a control end of the seventh switching tube Q7, a first end of the fifth switching tube Q5, a first end of the sixth switching tube Q6 and a first end of the seventh switching tube Q7 are all connected to the power supply voltage VCC, a second end of the fifth switching tube Q5 is grounded through the first current source I1, a second end of the sixth switching tube Q6 is grounded through the first resistor R1 and the second current source I2, and a second end of the seventh switching tube Q7 is grounded through the second resistor R2.
Therefore, the fifth switching tube Q5 forms a current mirror image with the sixth switching tube Q6 and the seventh switching tube Q7, and the current flowing through the fifth switching tube Q5 is equal to the current flowing through the sixth switching tube Q6 and the current flowing through the seventh switching tube Q7.
The first end of the third switching tube Q3, the first end of the fourth switching tube Q4 and the first end of the eighth switching tube Q8 are connected to the power supply voltage VCC. The control end of the third switching tube Q3 is connected with the control end of the fourth switching tube Q4 and the control end of the eighth switching tube Q8. The control end of the third switching tube Q3 is also connected with the second end of the third switching tube Q3 and the first end of the first switching tube Q1. The second end of the fourth switching tube Q4 is connected with the second end of the fifth switching tube Q5. A second end of the eighth switching tube Q8 is connected to a second end of the seventh switching tube Q7.
At this time, a current mirror image is formed among the third switching tube Q3, the fourth switching tube Q4 and the eighth switching tube Q8, and the current flowing through the third switching tube Q3 is equal to the current flowing through the fourth switching tube Q4 and the current flowing through the eighth switching tube Q8.
In an implementation, the third switching tube Q3 to the eighth switching tube Q8 may be PMOS tubes. At this time, among the third switching tube Q3 to the eighth switching tube Q8, the first end of any switching tube refers to the source end of the PMOS tube, the second end of any switching tube refers to the drain end of the PMOS tube, and the control end of any switching tube refers to the gate end of the PMOS tube.
In other embodiments, the third switching tube Q3 to the eighth switching tube Q8 may be other switching tubes, for example, NMOS tubes, and the structure of the current mirror module may be specifically adjusted according to the device of the actual switching tube.
In a preferred embodiment, the first capacitor C1 and the second capacitor C2 may be the same size, where the resistance of the first resistor R1 is K times the resistance of the second resistor R5, and K is a positive number. The channel lengths of the third to eighth switching transistors Q3 to Q8 are the same and the width to length ratio is proportional. The current value provided by the first current source 11 is K times the current value provided by the second current source I2.
Of course, in other embodiments, the first capacitor C1 and the second capacitor C2 may be different in size, the resistance of the first resistor R1 is a non-K-time relationship with the resistance of the second resistor R5, and the sizes of the third switching tube Q3 to the eighth switching tube Q8 are not proportional, and the current value provided by the first current source 11 is a non-K-time relationship with the current value provided by the second current source I2.
The current mirror module is used for mirror image processing of the current signal to obtain a mirror image current signal, so that the output of the self-adaptive clock generation sub-circuit can be regulated by the mirror image current signal, the output of the self-adaptive clock generation sub-circuit can be changed along with the change of the mirror image current signal, and the output of the self-adaptive clock generation sub-circuit can be changed along with the change of the difference detection result signal, thereby achieving the purpose of adaptively regulating the working frequency of the DC-DC voltage converter.
In a specific implementation, the adaptive clock generation sub-circuit may be implemented using a variety of circuit structures, which are not limited herein.
In one embodiment, referring to fig. 2, the adaptive clock generation sub-circuit may include: a third comparator CMP3, a ninth switching tube Q9, a first capacitor C1 and a second capacitor C2, wherein:
The ninth switching tube Q9 and the first capacitor C1 are both connected in parallel with the second current source I2, and the second capacitor C2 is connected in parallel with the second resistor R2;
the third comparator CMP3 has a first input VP and a second input VN; a first input terminal VP of the third comparator CMP3 is connected to the sixth switching tube Q6 and the first resistor R1; the second input VN of the third comparator CMP3 is connected to the seventh switching tube Q7 and to the second resistor R2.
In an implementation, the ninth switching transistor Q9 may be an NMOS transistor. The switching state of the switching tube in the current switching period in the DC-DC voltage converter is obtained through a ninth switching tube Q9. For example, the DC-DC voltage converter may generate a dead-band signal pwm_dt that may characterize the switching state of the switching tube in the DC-DC voltage converter at the current switching cycle. Specifically, the dead zone signal pwm_dt is low when the switching transistors in the DC-DC voltage converter are all off, otherwise, the dead zone signal pwm_dt may be high. The dead zone signal pwm_dt is used to control the on/off of the ninth switching tube Q9, and further control the charge and discharge of the first capacitor C1, so that the voltage of the first input end VP of the third comparator CMP3 can be adjusted, and finally the output of the third comparator CMP3, that is, the inversion of the first clock signal ss_pwm, is changed.
Assuming that the current value provided by the current signal i_ea is i_ea ', the current value provided by the first current source I1 is I1', the current value provided by the second current source I2 is I2', the ratio of the resistance values of the first resistor R1 and the second resistor R2 is 2:1, the ratio of the magnitudes of the first capacitor C1 and the second capacitor C2 is 1:1, referring to fig. 2, when the current signal i_ea exists, the magnitudes of the currents flowing through the fifth switching tube Q5, the sixth switching tube Q6 and the seventh switching tube Q7 are (I1 ' -i_ea '), and the current for charging the first capacitor C1 is (I1 ' -i_ea ' -I2 '), and the voltage across the second capacitor C2 is I1' ×r2.
The third comparator CMP3 takes the second input terminal VN as a reference, when the current of the first input terminal VP charges the first capacitor C1 to be higher than the reference I1' R2 of the second input terminal VN, the first clock signal ss_pwm output by the third comparator CMP3 is at a high level, and then the first clock signal ss_pwm controls the operating frequency of the DC-DC voltage converter, so as to control the on and off of the power tube.
When the dead zone signal pwm_dt is at a high level, the ninth switching tube Q9 is turned on to discharge the first capacitor C1, and the first input terminal VP of the third comparator CMP3 is lower than the second input terminal VN, and the first clock signal ss_pwm is at a low level. When the dead zone signal pwm_dt signal is low, the current flowing through the sixth switching tube Q6 charges the first capacitor C1 with a current value (I1 '-i_ea' -I2 ') until the reference value I1' R2 is reached.
As the soft start voltage signal SS continues to rise, the error amplifier EA output voltage also rises, and the current signal i_ea will gradually decrease to zero current. In this process, the current flowing through the fifth switching tube Q5, the sixth switching tube Q6, and the seventh switching tube Q7 gradually increases. Since the reference of the second input terminal VN of the third comparator CMP3 is unchanged and the current of the sixth switching tube Q6 gradually increases, the inversion frequency of the first clock signal ss_pwm output by the third comparator CMP3 will also be increased, and finally the current flowing through the fifth switching tube Q5, the sixth switching tube Q6 and the seventh switching tube Q7 is I1', and at this time, the DC-DC voltage converter will gradually change from the discontinuous mode to the continuous mode.
Since the resistance of the first resistor R1 is greater than that of the second resistor R2, the voltage of the first input terminal VP of the third comparator CMP3 will be constantly greater than that of the second input terminal VN, the first clock signal ss_pwm will always be at a high level, the DC-DC voltage converter will exit the frequency modulation mode and will continue to operate at a fixed switching frequency, thereby realizing that the operating frequency of the soft start stage varies with the output voltage of the error amplifier, so that the first few periods of the soft start are in the low-frequency intermittent mode, and therefore the whole soft start process is stable and smooth and has small ripple.
As shown in FIG. 3, after the DC-DC voltage converter starts to power up, the output EA_OUT of the error amplifier is equal to the first threshold voltage Vth1, the current signal I_EA reaches a maximum value, the feedback voltage signal rises along with the rising of the soft start voltage signal SS, the output EA_OUT of the error amplifier also rises to a stable value, and the current signal I_EA is reduced to zero. The first clock signal ss_pwm output from the third comparator CMP3 is the operating frequency of the system at this stage, and increases in frequency with the decrease of the current signal i_ea, and finally ends the adaptive frequency modulation stage to continue to operate at a fixed frequency.
In particular, referring to fig. 1, the soft start step length setting circuit 11 may have various circuit structures, which are not limited herein, as long as the step length of the soft start stage ramp voltage can be set.
In an embodiment of the present invention, referring to fig. 1, the soft start step length setting circuit 11 may include: a fixed clock generation sub-circuit 111, a frequency division sub-circuit 112, and a sample-and-hold sub-circuit 113. Wherein:
the fixed clock generation sub-circuit 111 includes a third current source for predicting a third capacitor, and is adapted to generate a second clock signal with a fixed frequency by charging and discharging the third capacitor by using the third current source;
The frequency divider circuit 112 is adapted to perform frequency division processing on the second clock signal to obtain a frequency-divided second clock signal and an inverted signal of the frequency-divided second clock signal;
the sample-hold sub-circuit 113 is connected to the fixed clock generation sub-circuit 111 and the frequency divider sub-circuit 112, and is adapted to sample and hold the voltage of the third capacitor under the control of the divided second clock signal and the inverted signal of the divided second clock signal.
Fig. 4 is a schematic circuit diagram of a soft start step length setting circuit according to an embodiment of the invention.
Referring to fig. 4, in an embodiment of the present invention, the fixed clock generating sub-circuit 111 may include: a third current source I3, a fourth capacitor C4, a fourth comparator CMP4, and a tenth switching tube Q10; wherein;
the third current source I3 is connected in series with the fourth capacitor C4, and the tenth switching tube Q10 is connected in parallel with the fourth capacitor C4; the control end of the tenth switching tube Q10 is connected with the output end of the fourth comparator CMP 4;
the fourth comparator CMP4 has a first input terminal and a second input terminal; a first input end of the fourth comparator CMP4 is connected with the third current source I3 and the fourth capacitor C4; a second input end of the fourth comparator CMP4 is suitable for being connected with a second reference voltage signal VREF2; the fourth comparator CMP4 is adapted to compare the voltage of the fourth capacitor C4 with the second reference voltage provided by the second reference voltage signal VREF2, so as to obtain the second clock signal ss_clk.
In an implementation, the third current source I3 charges the fourth capacitor C4 to generate the triangular wave signal STEP1. When the charging voltage is equal to the second reference voltage provided by the second reference voltage signal VREF2, the second clock signal ss_clk output by the fourth comparator CMP4 is at a high level, and at the same time, the second clock signal ss_clk is output to the control terminal of the tenth switching transistor Q10, so that the tenth switching transistor Q10 is turned on. At this time, the voltage of the fourth capacitor C4 is discharged through the tenth switching tube Q10, so that the second clock signal ss_clk output by the fourth comparator CMP4 is at a low level. By repeating this, the second clock signal ss_clk with a fixed frequency can be obtained.
In an implementation, the tenth switching tube Q10 may be an NMOS tube, a PMOS tube, or other types of switching tubes, which is not limited herein.
In one embodiment of the present invention, referring to fig. 4, the frequency divider circuit 112 may include: d flip-flop DFF1 and first SR flip-flop SR1. Wherein:
the output of the fourth comparator CMP4 is connected to the CLK terminal of the D flip-flop DFF1, and the second clock signal ss_clk is divided by the D flip-flop DFF 1. The first output terminal Q of the D flip-flop DFF1 is connected to the S terminal of the first SR flip-flop SR1, and at this time, the first output terminal Q and the second output terminal QN of the first SR flip-flop SR1 output the divided second clock signal CLK and the inverted signal clk_b of the divided second clock signal CLK, respectively. The frequency of the divided second clock signal CLK and the inverse signal CLK_B of the divided second clock signal CLK is 1/2 of the frequency of the second clock signal SS_CLK, and the pulse width is 50% of the frequency of the second clock signal SS_CLK.
In an embodiment of the present invention, the sample-and-hold sub-circuit 113 may include: an eleventh switching tube Q11, a fifth capacitor C5, a twelfth switching tube Q12, a thirteenth switching tube Q13, a fourteenth switching tube Q14, an operational amplifier A1, a sixth capacitor C6 and a seventh capacitor C7; wherein:
the control end of the eleventh switching tube Q11 and the control end of the fourteenth switching tube Q14 are connected with the second clock signal CLK after frequency division; the control end of the twelfth switching tube Q12 and the control end of the thirteenth switching tube Q13 are connected with an inversion signal CLK_B of the frequency-divided second clock signal CLK;
the eleventh switching tube Q11, the fifth capacitor C5 and the twelfth switching tube Q12 are connected in series and connected with the first input end of the operational amplifier A1; a second input end of the operational amplifier A1 is grounded; the sixth capacitor C6 is connected to the first input end of the operational amplifier A1 and the output end of the operational amplifier A1; one end of the seventh capacitor C7 is connected to the output end of the operational amplifier A1, and the other end is grounded.
One end of the thirteenth switching tube Q13 is connected to the eleventh switching tube Q11 and the fifth capacitor C5, and the other end is grounded. One end of the fourteenth switching tube Q14 is connected to the twelfth switching tube Q12 and the fifth capacitor C5, and the other end is grounded.
In a specific implementation, the eleventh switching tube Q11, the twelfth switching tube Q12, the thirteenth switching tube Q13, and the fourteenth switching tube Q14 may be NMOS tubes. At this time, the drain terminal of the thirteenth switching transistor Q13 is connected to the source terminal of the eleventh switching transistor Q11 and the fifth capacitor C5, and the source terminal of the thirteenth switching transistor Q13 is grounded. The drain terminal of the fourteenth switching tube Q14 is connected to the drain terminal of the twelfth switching tube Q12 and the fifth capacitor C5, and the source terminal of the fourteenth switching tube Q14 is grounded.
In other embodiments, the eleventh switch tube Q11, the twelfth switch tube Q12, the thirteenth switch tube Q13, and the fourteenth switch tube Q14 may be PMOS tubes or other switch devices, which are not limited herein, and the circuit structure of the sample-hold sub-circuit 113 may be adjusted according to the specific switch device type.
In a specific implementation, when the divided second clock signal CLK is at a high level and the inverted signal clk_b of the divided second clock signal CLK is at a low level, the eleventh switch Q11 and the fourteenth switch Q14 are turned on, the thirteenth switch Q13 and the twelfth switch Q12 are turned off, and at this time, the fifth capacitor C5 samples the fourth capacitor C4.
When the divided second clock signal CLK is at a low level and the inverted signal clk_b of the divided second clock signal CLK is at a high level, the thirteenth and twelfth switching transistors Q13 and Q12 are turned on, the eleventh and fourteenth switching transistors Q11 and Q14 are turned off, and the fifth capacitor C5 holds the sampling voltage, thereby generating a soft start step voltage.
Since the first input terminal and the second input terminal of the operational amplifier A1 have a characteristic of being virtually short, the second input terminal of the operational amplifier A1 is grounded, and thus the voltage of the first input terminal of the operational amplifier A1 can be kept at a low potential. In addition, since the voltage across the sixth capacitor C6 does not suddenly change, the soft start step voltage is transmitted to the output terminal of the operational amplifier A1 through the sixth capacitor C6. Since the sixth capacitor C6 has no discharging path, the soft start voltage signal SS at the output end of the operational amplifier A1 gradually rises along with the frequency of the divided second clock signal CLK, and rises by one step voltage (step) per switching period, so as to finally generate the soft start voltage signal SS with a fixed slope.
Fig. 5 is a schematic waveform diagram of each signal in the soft start step length setting circuit. Referring to fig. 4 and 5, in the embodiment, the third current source I3 charges the fourth capacitor C4 to generate the triangular wave signal STEP1 until the charging voltage of the fourth capacitor C4 is equal to the second reference voltage, and the fourth comparator CMP4 generates the second clock signal ss_clk with a fixed frequency.
Subsequently, the frequency divider circuit 112 divides the second clock signal ss_clk to generate a divided second clock signal CLK and an inverted signal clk_b thereof. At this time, the frequency of the divided second clock signal CLK is 2 times that of the second clock signal ss_clk, and the divided second clock signal CLK controls the on/off of the eleventh switching transistor Q11 and generates the signal STEP2.
The signal STEP2 samples the voltage of the triangular wave signal STEP1 when the frequency-divided second clock signal CLK is at a high level, and is at zero voltage when the frequency-divided second clock signal CLK is at a low level. The fifth capacitor C5 holds to generate a soft start STEP voltage, the waveform of which is shown as signal STEP 3.
The soft start step voltage is then transferred to the output of the operational amplifier A1 through the sixth capacitor C6. Since the voltage across the sixth capacitor C6 will not be abrupt and the sixth capacitor C6 has no discharging path, the soft start step voltage will be periodically transferred to the output terminal of the operational amplifier A1 along with the divided second clock signal CLK to generate the soft start voltage signal SS.
By adopting the soft start control circuit in the embodiment of the invention, the soft start voltage signal with a fixed slope can be generated by the soft start step length setting circuit, and the soft start voltage signal can lead the output voltage of the system to stably and gently rise, thereby effectively preventing the surge current and the overcharge voltage in the soft start stage. Through the soft start frequency control circuit, the working frequency of the DC-DC voltage converter can be changed along with the change of the output voltage of the error amplifier, so that the DC-DC voltage converter can be in a low-frequency intermittent mode in the first few periods of soft start of the DC-DC voltage converter, and the whole soft start process is smoother and has smaller ripple waves.
In addition, by adopting the soft start control circuit in the embodiment of the invention, the working frequency of the system is indirectly controlled by the error amplifier EA no-load or full-load state, so that the DC-DC voltage converter is started in no-load or full-load state, and the required soft start time is consistent, thereby better meeting the requirements of electronic equipment.
Referring to fig. 6, an embodiment of the present invention also provides a DC-DC voltage converter, which may include: a voltage conversion circuit 61, a feedback circuit 62, a soft start control circuit 63, and a logic control circuit 64. Wherein:
the voltage conversion circuit 61 includes a switching tube adapted to perform voltage conversion on an input voltage;
the feedback circuit 62 is connected to the voltage conversion circuit 61 and has an output voltage feedback terminal adapted to generate a feedback voltage signal based on the output voltage of the voltage conversion circuit to control the output voltage of the voltage conversion circuit;
the soft start control circuit 63 is connected to the voltage conversion circuit 61 and the feedback circuit 62, and is adapted to provide a first clock signal having an adaptive frequency;
the logic control circuit 64 is connected to the soft start control circuit 63, and is adapted to obtain the first clock signal and the turn-off control signal, and to perform logic control on the switching tube in the voltage conversion circuit based on the first clock signal and the turn-off control signal.
In a specific implementation, the first clock signal may be a frequency adjustment period of a switching tube in the DC-DC voltage converter, and based on a switching state of the switching tube in the DC-DC voltage converter in a current switching period, a switching frequency of the switching tube in the DC-DC voltage converter in a next switching period is adjusted, so as to adjust a working frequency of the DC-DC voltage converter, so that the working frequency of the DC-DC voltage converter in a soft start stage can be adapted to a variation of a voltage difference between the feedback voltage signal and the soft start voltage signal, and therefore an output voltage of the DC-DC voltage converter can be smoother in the soft start stage with smaller ripple.
In a specific implementation, the DC-DC voltage converter may be a buck converter or a boost converter, which is not limited herein.
In one embodiment of the present invention, the logic control circuit 14 may include: a selector, a second SR flip-flop, and a logic drive sub-circuit. Wherein:
the selector is provided with a first input end and a second input end; the first input end of the selector is connected with the soft start control circuit, and the second input end of the selector is suitable for being connected with a third clock signal with fixed frequency;
The second SR trigger is provided with a first input end and a second input end; the first input end of the second SR trigger is connected with the output end of the selector, and the second input end is suitable for being connected with the turn-off control signal;
the logic driving sub-circuit is connected with the output end of the second SR trigger and is suitable for controlling the on-off of a switching tube in the voltage conversion circuit 61 based on the output of the second SR trigger.
Taking the DC-DC voltage converter as a DC-DC buck converter as an example, in an embodiment of the present invention, a circuit structure of the DC-DC voltage converter may be as shown in fig. 2.
Referring to fig. 7, in the DC-DC buck converter, the voltage converting circuit 61 may include: fifteenth switching transistor Q15, sixteenth switching transistor Q16, and inductor L. The fifteenth switching tube Q15 and the sixteenth switching tube Q16 may be NMOS tubes.
Specifically, the drain terminal of the fifteenth switching transistor Q15 is connected to the voltage input terminal VIN. The source end of the fifteenth switching tube Q15 and the drain end of the sixteenth switching tube Q16 are connected with one end of the inductor L, and the connection point is a bridge arm midpoint SW. The source terminal of the sixteenth switching transistor Q16 is grounded. The other end of the inductor L is used as the voltage output terminal VOUT.
In one embodiment of the present invention, referring to fig. 7, the feedback circuit 62 may include: the third resistor R3, the fourth resistor R4, the output capacitor C0 and the load resistor RL. One end of the third resistor R3 is connected to the inductor L, and the other end is connected to the fourth resistor R4. The other end of the fourth resistor R4 is grounded. One end of the output capacitor C0 is connected with the inductor L, and the other end of the output capacitor C0 is connected with the grounding end of the fourth resistor R4. The load resistor RL is connected in parallel with the output capacitor C0.
The connection point of the third resistor R3 and the fourth resistor R4 is used as an output voltage feedback end of the feedback circuit 62, and outputs a feedback voltage signal FB. When the output voltage of the output terminal VOUT of the DC-DC voltage converter changes, the feedback voltage signal FB changes accordingly, so that the feedback voltage signal FB is output to the soft start control circuit 63, so that the soft start control circuit 63 can determine the change of the output voltage of the output terminal VOUT of the DC-DC voltage converter based on the change of the feedback voltage signal FB, thereby adjusting the operating frequency.
In a specific implementation, the soft start control circuit 63 may include: the soft start step length setting circuit 631 and the soft start frequency control circuit 632. The soft start step length setting circuit 631 may generate the soft start voltage signal SS with a fixed slope. The soft-start frequency control circuit 632 can generate a first clock signal ss_pwm with an adaptive frequency based on the switching states of the fifteenth switching tube Q15 and the sixteenth switching tube Q16 in the DC-DC voltage converter in the current switching period, where the first clock signal ss_pwm can adjust the working frequency of the DC-DC voltage converter in the next switching period, so that the working frequency of the DC-DC voltage converter in the soft-start stage is adapted to the variation of the voltage difference between the feedback voltage signal FB and the soft-start voltage signal SS.
The soft start control circuit 63 may be specifically described in the above embodiments, and will not be described herein.
In an implementation, referring to fig. 7, the logic control circuit may include: a selector 641, a second SR flip-flop 642, and a logic drive sub-circuit 643. Wherein:
the selector 641 has a first input and a second input; the first input terminal of the selector 641 is connected to the soft start control circuit, and the second input terminal is adapted to be connected to a third clock signal CLK3 of a fixed frequency.
The second SR flip-flop 642 has a first input and a second input. The first input terminal of the second SR flip-flop 642 is connected to the output terminal of the selector 641, and the second input terminal is adapted to be coupled to the shutdown control signal hs_close.
The logic driving sub-circuit 643 is connected to the output end of the second SR flip-flop 642, and is adapted to control the on/off of the switching tube in the voltage conversion circuit based on the output of the second SR flip-flop 642.
Specifically, the first clock signal ss_pwm output from the soft start control circuit 63 is output to the first input terminal of the selector 641. A second input terminal of the selector 641 is coupled to a third clock signal CLK3. When there is a valid first clock signal ss_pwm (i.e., the first clock signal ss_pwm is not fixed high), the selector 641 selects the first clock signal ss_pwm as the output signal. When the active first clock signal ss_pwm does not exist, the selector 641 selects the third clock signal CLK3 as the output signal.
An output of the selector 641 is connected to a first input terminal of the second SR flip-flop 642, and an output of the selector 641 is used as a turn-on control signal of the fifteenth switching transistor Q15. The other input of the second SR flip-flop 642 turns off the control signal hs_close as the turn-off control signal of the fifteenth switching transistor Q15.
The output of the second SR flip-flop 642 is connected to the logic driving sub-circuit 643, and the logic driving sub-circuit 643 is connected to the control terminals of the fifteenth switching transistor Q15 and the sixteenth switching transistor Q16, so that the switching on/off of the fifteenth switching transistor Q15 and the sixteenth switching transistor Q16 can be controlled based on the output of the second SR flip-flop 642.
In an embodiment, the logic driving sub-circuit 643 is connected to the soft start control circuit 63 and adapted to provide a dead zone signal pwm_dt reflecting the switching state of the switching transistors in the DC-DC voltage converter to the soft start control circuit 63 to generate the first clock signal ss_pwm.
In the upper DC-DC voltage converter, the voltage input at the voltage input terminal VIN is converted into an output voltage, and the output voltage generates a feedback voltage through the feedback circuit 62. In the soft start control circuit 63, the soft start step length setting circuit may generate a soft start voltage signal SS with a fixed slope to prevent the output voltage from overshooting. The soft start frequency control circuit may receive the soft start voltage signal SS, the feedback voltage signal FB, and the dead zone signal pwm_dt, and generate the first clock signal ss_pwm having the adaptive frequency in the soft start stage according to the above three signals.
In the soft start phase, the alternative selector 641 selects the first clock signal ss_pwm to output to the second SR flip-flop 642, and the second SR flip-flop 642 receives the first clock signal ss_pwm and the off control signal hs_close to generate the logic switch signal PWM. The waveform of the logic switching signal PWM may be as shown in fig. 3.
The logic switching signal PWM generated by the second SR flip-flop 642 passes through the logic driving sub-circuit 643 to control the on/off of the fifteenth switching transistor Q15 and the sixteenth switching transistor Q16 for synchronous rectification, so that the DC-DC voltage converter works at the adaptive soft-start switching frequency, and the feedback voltage signal FB can smoothly and stably rise along with the soft-start voltage signal SS.
Referring to fig. 8, an embodiment of the present invention further provides a soft start control method applied to a DC-DC voltage converter including: the switching tube and the output voltage feedback end are suitable for providing feedback voltage signals for feeding back the change of the output voltage. The method may comprise the steps of:
step 81, generating a soft start voltage signal with a fixed slope.
In a specific implementation, the soft start voltage signal is a ramp voltage signal.
Step 82, generating a first clock signal with an adaptive frequency based on a switching state of a switching tube in the DC-DC voltage converter in a current switching cycle.
The first clock signal is used for adjusting the working frequency of the DC-DC voltage converter in the next switching period, so that the working frequency of the DC-DC voltage converter in the soft start stage is matched with the change of the voltage difference between the feedback voltage signal and the soft start voltage signal.
In an implementation, generating the first clock signal with the adaptive frequency based on a switching state of a switching tube in the DC-DC voltage converter in a current switching cycle may include: detecting a voltage difference value between the feedback voltage signal and the soft start voltage signal to obtain a difference value detection result signal; generating a current signal that varies in response to the difference detection result signal; and generating the first clock signal using the current signal based on a switching state of a switching tube in the DC-DC voltage converter.
In specific implementation, the soft start control circuit in the embodiment of the invention can be adopted to carry out soft start control on the DC-DC voltage converter.
Specifically, referring to fig. 2, the soft start control circuit may first determine whether the voltage of the output signal ea_out of the error amplifier EA is greater than the first threshold voltage provided by the first threshold voltage signal Vth1 and less than the stable value of the error amplifier EA.
When the voltage of the output signal ea_out of the error amplifier EA is greater than the first threshold voltage provided by the first threshold voltage signal Vth1 and less than the stable value of the error amplifier EA, a first clock signal with an adaptive frequency is generated.
When the voltage of the output signal ea_out of the error amplifier EA is equal to the stable value, the output voltage ea_out of the error amplifier EA is far greater than the first threshold voltage, the output of the third comparator CMP3 is constantly at a high level, and at this time, the DC-DC voltage converter will be in a continuous operation mode with a fixed frequency, i.e. the switching on of the switching tube in the voltage conversion circuit is controlled with a fixed clock frequency.
In the process of generating the first clock signal, first, a current signal i_ea is generated, the current value of the current signal i_ea is greater than zero, and then the current controlled by the current signal i_ea charges the first capacitor C1, so as to provide the voltage to the first input terminal VP of the third comparator CMP3, and the voltage of the second input terminal VN of the third comparator CMP3 is fixed.
When the voltage of the first input terminal VP of the third comparator CMP3 is greater than the voltage of the second input terminal VN, the first clock signal ss_pwm is at a high level, and the first clock signal ss_pwm at the high level controls the fifteenth switching transistor Q15 to be turned on to raise the potential of the node SW. The output of the error amplifier EA is determined in real time, and the first clock signal ss_pwm is continuously output until the first clock signal ss_pwm in one switching period is obtained.
After the fifteenth switching transistor Q15 is switched for one period, the output of the error amplifier EA will rise, the voltage of the feedback voltage signal will also rise, and the rising speed of the error amplifier EA is controlled by the voltage of the feedback voltage signal, which follows the change of the soft start voltage signal SS. Then, the voltage of the soft start signal SS is determined, if the voltage of the soft start signal SS is greater than the voltage value of the first reference voltage signal VREF1, the soft start is ended, otherwise, the output of the error amplifier EA is continuously determined, and then the corresponding operating frequency is selected.
In an embodiment, the change in the current signal is inversely proportional to the change in the difference detection result signal.
Fig. 9 is a waveform diagram of relevant signals in a DC-DC voltage converter. Referring to fig. 9, after the DC-DC voltage converter is powered on, the output voltage of the error amplifier is compared with the first threshold voltage, and a current signal i_ea inversely related to the output signal ea_out of the error amplifier is generated to control the operating frequency of the soft start stage, so as to control the frequency of the node SW switch wave, the feedback voltage signal FB will rise along with the rising of the soft start voltage signal SS, and the feedback voltage signal FB will rise by one step size every time a SW switch wave occurs.
As the voltage of the output signal ea_out of the error amplifier increases, the current value of the current signal i_ea gradually decreases, and the frequency of the node SW switch wave also increases, so that the DC-DC voltage converter gradually changes from adaptive frequency modulation to a fixed clock frequency. As shown in fig. 9, in the adaptive frequency modulation stage, the soft start process is smooth and linear, and the ripple is small, until the soft start voltage signal SS reaches the first reference voltage VREF1 (as shown in tss), and then the soft start process is ended, and the feedback voltage will continue to work along with the first reference voltage VREF 1. At this time, the frequency of the current IL flowing through the inductor (shown as the inductor L in fig. 7) remains substantially fixed.
By adopting the DC-DC voltage converter in the embodiment of the invention, the problems of overlarge current and overshoot of output voltage at the moment of power-on can be prevented, and the output voltage can be smoother and has smaller ripple wave in the starting process. In addition, the time required for soft start in the idle or full state can be kept consistent.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (19)

1. A soft start control circuit for use in a DC-DC voltage converter, the DC-DC voltage converter comprising: the switching tube and the output voltage feedback end are suitable for providing feedback voltage signals for feeding back the change of the output voltage; the soft start control circuit is characterized by comprising:
the soft start step length setting circuit is suitable for generating a soft start voltage signal with a fixed slope;
and the soft start frequency control circuit is connected with the soft start step length setting circuit of the DC-DC voltage converter and is suitable for generating a first clock signal with self-adaptive frequency based on the switching state of a switching tube in the DC-DC voltage converter in the current switching period, wherein the first clock signal is used for adjusting the working frequency of the DC-DC voltage converter in the next switching period so that the working frequency of the DC-DC voltage converter in the soft start stage is matched with the change of the voltage difference value between the feedback voltage signal and the soft start voltage signal.
2. The soft start control circuit of claim 1, wherein the soft start frequency control circuit comprises:
the difference detection sub-circuit is suitable for detecting the voltage difference between the feedback voltage signal and the soft start voltage signal in the soft start stage of the DC-DC voltage converter to obtain a difference detection result signal; the current follower circuit is connected with the difference detection circuit and is suitable for generating a current signal which changes along with the difference detection result signal;
And the self-adaptive clock generation sub-circuit is connected with the current following sub-circuit and is suitable for generating the first clock signal by using the current signal based on the switching state of a switching tube in the DC-DC voltage converter.
3. The soft start control circuit of claim 2, wherein the difference detection subcircuit comprises:
the error amplifier is provided with a first input end, a second input end and a third input end, wherein the first input end of the error amplifier is suitable for being connected with the soft start voltage signal, the second input end of the error amplifier is suitable for being connected with a first reference voltage signal, and the third input end of the error amplifier is suitable for being connected with a feedback voltage signal; the error amplifier is suitable for comparing the voltage of the soft start voltage signal with the voltage of the first reference voltage signal, and amplifying the voltage difference between the soft start voltage signal and the feedback voltage signal when the voltage of the soft start voltage signal is smaller than the voltage of the first reference voltage signal to obtain an error amplified signal.
4. The soft-start control circuit of claim 2, wherein the current follower sub-circuit comprises:
The current following module is connected with the difference detection subcircuit and is suitable for generating the current signal and controlling the current signal to follow the change of the difference detection result signal;
and the current mirror module is suitable for carrying out mirror image processing on the current signal to obtain a mirror image current signal.
5. The soft start control circuit of claim 4, wherein the current follower module is adapted to control a change in the current signal inversely proportional to a change in the difference detection result signal.
6. The soft start control circuit of claim 4, wherein the current follower module comprises:
the first comparator is provided with a first input end and a second input end, the first input end of the first comparator is connected with the output end of the difference detection sub-circuit, and the second input end of the first comparator is suitable for being connected with a first threshold voltage signal;
the control end of the first switching tube is connected with the output end of the first comparator, the first end of the first switching tube is connected with the current following sub-circuit, and the second end of the first switching tube is connected with the difference value detection sub-circuit;
the first comparator is suitable for comparing the voltage of the difference detection result signal with a first threshold voltage provided by the first threshold voltage signal, controlling the first switching tube to be conducted when the voltage of the difference detection result signal is smaller than the first threshold voltage, and controlling the first switching tube to be conducted when the voltage of the difference detection result signal is larger than or equal to the first threshold voltage so as to generate the current signal and enable the current signal to follow the change of the difference detection result signal.
7. The soft-start control circuit of claim 4, wherein the current mirror module comprises: third switching tube, fourth switching tube, fifth switching tube, sixth switching tube, seventh switching tube, eighth switching tube, first current source, second current source, first resistance and second resistance, wherein:
the third switching tube is connected with the current following module, the fourth switching tube is connected with the third switching tube and the fifth switching tube, the fifth switching tube is connected with the first current source and the sixth switching tube, the sixth switching tube is connected with the first resistor and the second current source, and the seventh switching tube is connected with the sixth switching tube, the eighth switching tube and the second resistor.
8. The soft-start control circuit of claim 7, wherein the first capacitor is the same size as the second capacitor; the resistance value of the first resistor is K times of the resistance value of the second resistor R5; the channel lengths of the third switching tube to the eighth switching tube are the same and the width-to-length ratio is proportional; the current value provided by the first current source is K times of the current value provided by the second current source, and K is a positive number.
9. The soft-start control circuit of claim 7, wherein the adaptive clock generation sub-circuit comprises: the third comparator, the ninth switch tube, the first capacitor and the second capacitor, wherein: the ninth switching tube and the first capacitor are connected with the second current source in parallel, and the second capacitor is connected with the second resistor in parallel;
the third comparator is provided with a first input end and a second input end; the first input end of the third comparator is connected with the sixth switching tube and the first resistor; and the second input end of the third comparator is connected with the seventh switching tube and the second resistor.
10. The soft start control circuit of claim 9, wherein the control terminal of the ninth switching tube is adapted to receive a dead band signal indicative of a switching state of the switching tube in the DC-DC voltage converter at a current switching cycle, the voltage at the first input terminal of the third comparator being adjusted based on the dead band signal.
11. The soft start control circuit of claim 1, wherein the soft start step length setting circuit comprises:
the fixed clock generation sub-circuit comprises a third current source, a second capacitor and a third clock generation sub-circuit, wherein the third current source predicts the third capacitor and is suitable for charging and discharging the third capacitor by utilizing the third current source to generate a second clock signal with fixed frequency;
The frequency divider circuit is suitable for carrying out frequency division processing on the second clock signal to obtain a frequency-divided second clock signal and an inverted signal of the frequency-divided second clock signal;
and the sampling and holding sub-circuit is connected with the fixed clock generation sub-circuit and the frequency division sub-circuit and is suitable for sampling and holding the voltage of the third capacitor under the control of the frequency-divided second clock signal and the inverted signal of the frequency-divided second clock signal.
12. The soft start control circuit of claim 11, wherein the fixed clock generation sub-circuit comprises: the third current source, the fourth capacitor, the fourth comparator and the tenth switching tube; wherein; the third current source is connected with the fourth capacitor in series, and the tenth switching tube is connected with the fourth capacitor in parallel; the control end of the tenth switching tube is connected with the output end of the fourth comparator; the fourth comparator is provided with a first input end and a second input end; the first input end of the fourth comparator is connected with the third current source and the fourth capacitor; the second input end of the fourth comparator is suitable for being connected with a second reference voltage signal; the fourth comparator is adapted to compare the voltage of the fourth capacitor with a second reference voltage provided by the second reference voltage signal, so as to obtain the second clock signal.
13. The soft-start control circuit of claim 11, wherein the sample-and-hold sub-circuit comprises: an eleventh switching tube, a fifth capacitor, a twelfth switching tube, a thirteenth switching tube, a fourteenth switching tube, an operational amplifier, a sixth capacitor and a seventh capacitor; wherein:
the control end of the eleventh switching tube and the control end of the fourteenth switching tube are connected with the second clock signal after frequency division; the control end of the twelfth switching tube and the control end of the thirteenth switching tube are connected with the inverted signal of the second clock signal after frequency division;
the eleventh switching tube, the fifth capacitor and the twelfth switching tube are connected in series and are connected with the first input end of the operational amplifier; a second input end of the operational amplifier is grounded; the sixth capacitor is connected with the first input end of the operational amplifier and the output end of the operational amplifier; one end of the seventh capacitor is connected with the output end of the operational amplifier, and the other end of the seventh capacitor is grounded; one end of the thirteenth switching tube is connected with the eleventh switching tube and the fifth capacitor, and the other end of the thirteenth switching tube is grounded;
one end of the fourteenth switching tube is connected with the twelfth switching tube and the fifth capacitor, and the other end of the fourteenth switching tube is grounded.
14. A DC-DC voltage converter, comprising:
the voltage conversion circuit comprises a switching tube and is suitable for carrying out voltage conversion on input voltage;
the feedback circuit is connected with the voltage conversion circuit and provided with an output voltage feedback end, and is suitable for generating a feedback voltage signal based on the output voltage of the voltage conversion circuit so as to control the output voltage of the voltage conversion circuit;
soft start control circuit according to any one of claims 1 to 13; the soft start control circuit is connected with the voltage conversion circuit and the feedback circuit and is suitable for providing a first clock signal with self-adaptive frequency;
the logic control circuit is connected with the soft start control circuit and is suitable for acquiring the first clock signal and the turn-off control signal and carrying out logic control on a switching tube in the voltage conversion circuit based on the first clock signal and the turn-off control signal.
15. The DC-DC voltage converter of claim 14, wherein the logic control circuit comprises:
a selector having a first input terminal and a second input terminal; the first input end of the selector is connected with the soft start control circuit, and the second input end of the selector is suitable for being connected with a third clock signal with fixed frequency;
The second SR trigger is provided with a first input end and a second input end; the first input end of the second SR trigger is connected with the output end of the selector, and the second input end is suitable for being connected with the turn-off control signal;
and the logic driving sub-circuit is connected with the output end of the second SR trigger and is suitable for controlling the on-off of a switching tube in the voltage conversion circuit based on the output of the second SR trigger.
16. A DC-DC voltage converter as recited in claim 15, wherein the logic drive subcircuit is coupled to the soft-start control circuit and adapted to provide a dead band signal reflecting a switching state of a switching tube in the DC-DC voltage converter to the soft-start control circuit to generate the first clock signal.
17. A soft start control method applied to a DC-DC voltage converter, the DC-DC voltage converter comprising: the switching tube and the output voltage feedback end are suitable for providing feedback voltage signals for feeding back the change of the output voltage; characterized in that the method comprises:
generating a soft start voltage signal with a fixed slope;
and generating a first clock signal with self-adaptive frequency based on the switching state of a switching tube in the DC-DC voltage converter in the current switching period, wherein the first clock signal is used for adjusting the working frequency of the DC-DC voltage converter in the next switching period, so that the working frequency of the DC-DC voltage converter in the soft start stage is adaptive to the change of the voltage difference value between the feedback voltage signal and the soft start voltage signal.
18. The soft start control method of claim 17, wherein the generating a first clock signal having an adaptive frequency based on a switching state of a switching tube in the DC-DC voltage converter at a current switching cycle comprises:
detecting a voltage difference value between the feedback voltage signal and the soft start voltage signal to obtain a difference value detection result signal;
generating a current signal that varies in response to the difference detection result signal;
and generating the first clock signal by using the current signal based on the switching state of a switching tube in the DC-DC voltage converter in the current switching period.
19. The soft start control method of claim 18, wherein the change in the current signal is inversely proportional to the change in the difference detection result signal.
CN202311369301.7A 2023-10-20 2023-10-20 Soft start control circuit, DC-DC voltage converter and soft start control method Pending CN117578861A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311369301.7A CN117578861A (en) 2023-10-20 2023-10-20 Soft start control circuit, DC-DC voltage converter and soft start control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311369301.7A CN117578861A (en) 2023-10-20 2023-10-20 Soft start control circuit, DC-DC voltage converter and soft start control method

Publications (1)

Publication Number Publication Date
CN117578861A true CN117578861A (en) 2024-02-20

Family

ID=89892513

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311369301.7A Pending CN117578861A (en) 2023-10-20 2023-10-20 Soft start control circuit, DC-DC voltage converter and soft start control method

Country Status (1)

Country Link
CN (1) CN117578861A (en)

Similar Documents

Publication Publication Date Title
US7202644B2 (en) DC—DC converting method and apparatus
US9647557B2 (en) Three phases controller for buck-boost regulators
US8669748B2 (en) Device for synchronous DC-DC conversion and synchronous DC-DC converter
US8044642B2 (en) Power supply device capable of stably supplying output voltage with increased responsiveness
US7928715B2 (en) Switching regulator
US7279869B2 (en) PFM control circuit for DC regulator
US7804285B2 (en) Control of operation of switching regulator to select PWM control or PFM control based on phase comparison
US7498793B2 (en) Current-mode DC-to-DC-converter
US8004263B2 (en) Switching regulator
US9774255B2 (en) Synchronous buck DC-DC converter and method thereof
US8179113B2 (en) Buck-Boost switching regulator and method thereof for DC/DC conversion
US20090174384A1 (en) Switching regulator and method of controlling the same
US7723967B2 (en) Step-up converter having an improved dynamic response
CN108306489B (en) Drive circuit, control circuit and drive method of buck-boost switching converter
US20110101946A1 (en) Voltage converters
US8350541B2 (en) Control circuit and method for a soft-start scheme of a switch mode power supply for a power amplifier
TW201351861A (en) Method of controlling a power converting device and related circuit
JP2004096982A (en) Dc-dc converter
JP2005295795A (en) Current mode switching regulator having predetermined conduction period
TW201444254A (en) Efficient control circuit for buck-boost converters and control method thereof
CN112688538B (en) Quasi-constant on-time control circuit and switch converter and method thereof
EP4046266A1 (en) Method and system for buck converter current re-use
CN110875686B (en) Electronic converter and method of operating an electronic converter
US10128757B2 (en) Buck-boost converter with small disturbance at mode transitions
CN113765373A (en) Control circuit of voltage conversion circuit

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination