CN117578519A - Capacitor bank automatic leveling method and device, electronic equipment and storage medium - Google Patents
Capacitor bank automatic leveling method and device, electronic equipment and storage medium Download PDFInfo
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
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- H02J3/18—Arrangements for adjusting, eliminating or compensating reactive power in networks
- H02J3/1821—Arrangements for adjusting, eliminating or compensating reactive power in networks using shunt compensators
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- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J2203/00—Indexing scheme relating to details of circuit arrangements for AC mains or AC distribution networks
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Abstract
The embodiment of the invention discloses a capacitor bank automatic leveling method, a capacitor bank automatic leveling device, electronic equipment and a storage medium. The capacitor bank automatic leveling method comprises the following steps: constructing a calculation model of a capacitor bank leveling boundary condition; judging whether the nameplate deviation rate and/or the unbalance rate of the capacitor bank meet preset requirements or not based on a calculation model; if the preset requirement is not met, the capacitors in the capacitor bank are replaced. According to the invention, the capacitor bank is leveled without manual calculation, so that a large amount of time is saved, the calculated leveling result is accurate, and the existing leveling scheme is optimized.
Description
Technical Field
The embodiment of the invention relates to the technical field of power systems and automation thereof, in particular to a capacitor bank automatic leveling method, a device, electronic equipment and a storage medium.
Background
With the increase of the power load, the demand for reactive power support of the circuit is stricter, the short circuit work of the external fuse wire of the capacitor bank is gradually developed in recent times, the replacement work of the capacitor is also gradually increased, the capacitor bank is leveled, but the capacitor bank is manually calculated at present, the consumed time is relatively long, and the calculated leveling result is not accurate enough.
Disclosure of Invention
The invention provides an automatic leveling method, an automatic leveling device, electronic equipment and a storage medium for a capacitor bank, which do not need manual calculation to level the capacitor bank, save a great deal of time, have accurate calculated leveling results and optimize the existing leveling scheme.
According to an aspect of the present invention, there is provided a capacitor bank auto-leveling method including:
constructing a calculation model of a capacitor bank leveling boundary condition;
judging whether the nameplate deviation rate and/or the unbalance rate of the capacitor bank meet preset requirements or not based on the calculation model;
and if the preset requirement is not met, replacing the capacitors in the capacitor bank.
Optionally, the capacitor bank includes a double Y-capacitor bank and a single Y-capacitor bank.
Optionally, the constructing a calculation model of the capacitor bank leveling boundary condition includes:
and constructing a calculation model of the leveling boundary condition of the double Y-shaped capacitor bank and a calculation model of the leveling boundary condition of the single Y-shaped capacitor bank.
Optionally, the expression of the calculation model of the double Y-type capacitor bank leveling boundary condition is as follows:
wherein U is 1 Is the maximum unbalance rate between the two Y-shaped capacitor banks, U 2 Is the maximum unbalance rate between the arms of the double Y-type capacitor bank, C 1 Is the sum of the measured capacitance values of the upper arm and the lower arm of the phase A, C 2 Is the sum of the measured capacitance values of the upper arm and the lower arm of the phase B, C 3 Is the sum of the measured capacitance values of the upper arm and the lower arm of the C phase, U n1 Is the standard value of the phase-to-phase unbalance rate of the double Y-type capacitor bank, U n2 Is the standard value of unbalance rate between arms of the double Y-shaped capacitor bank, P is the maximum nameplate deviation rate, and P n Is the standard value of nameplate deviation, m is the number of capacitors, d 1 For the first capacitance actual measurement value, d m Is the measured value of the mth capacitance, D 1 For the first capacitor nameplate value, D 2 For the second capacitor nameplate value, D m Is the mth capacitor nameplate value.
Optionally, the expression of the sum of the measured capacitance values of the upper arm and the lower arm of the phase a, the sum of the measured capacitance values of the upper arm and the lower arm of the phase B, and the sum of the measured capacitance values of the upper arm and the lower arm of the phase C is as follows:
C 1 ＝{C a1 ,C a2 }，C 2 ＝{C b1 ,C b2 }，C 3 ＝{C c1 ,C c2 }
wherein C is a1 Is the sum of the measured capacitance values of the A phase upper arm and C phase upper arm a2 Is the sum of the measured capacitance values of the lower arm of the phase A, C b1 Is the sum of the measured capacitance values of the upper arm of the phase B, C b2 Is the sum of the measured capacitance values of the lower arm of the phase B, C c1 Is the sum of the measured capacitance values of the upper arm of the C phase and C c2 Is the sum of the measured capacitance values of the lower arm of the C phase.
Optionally, the expression of the calculation model of the single Y-type capacitor bank leveling boundary condition is as follows:
C 22 ＝{C a ,C b ,C c }
wherein U is the maximum unbalance rate among single Y-type capacitor groups and U n Is the standard value of the phase-to-phase unbalance rate of a single Y-type capacitor bank、C 22 Is the sum of three-phase measured capacitance values C a Is the sum of the measured compatibility values of phase A, C b Is the sum of the measured capacitance values of phase B, C c Is the sum of the measured compatibility values of phase C.
Optionally, the determining whether the nameplate deviation rate and/or the unbalance rate of the capacitor bank meets the preset requirement based on the calculation model includes:
judging whether the nameplate deviation rate and/or the unbalance rate of the single Y-shaped capacitor bank meet preset requirements or not based on the calculation model;
and judging whether the nameplate deviation rate and/or the unbalance rate of the double Y-shaped capacitor bank meet preset requirements or not based on the calculation model.
According to another aspect of the present invention, there is provided a capacitor bank auto-leveling device including:
the calculation model construction module is used for constructing a calculation model of the capacitor bank leveling boundary condition;
the preset requirement judging module is used for judging whether the nameplate deviation rate and/or the unbalance rate of the capacitor bank meet preset requirements or not based on the calculation model;
and the preset requirement determining module is used for replacing the capacitors in the capacitor bank if the preset requirement is not met.
According to another aspect of the present invention, there is also provided an electronic apparatus including:
one or more processors;
a memory for storing one or more programs;
the one or more programs, when executed by the one or more processors, cause the one or more processors to implement the methods described in embodiments of the present invention.
According to another aspect of the present invention, there is also provided a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements a method according to an embodiment of the present invention.
According to the technical scheme, a calculation model of the capacitor bank leveling boundary condition is constructed; judging whether the nameplate deviation rate and/or the unbalance rate of the capacitor bank meet preset requirements or not based on a calculation model; if the preset requirement is not met, the capacitors in the capacitor bank are replaced. And (3) providing an optimized leveling scheme by taking the unbalance rate and the nameplate deviation rate as boundary conditions, and intelligently adapting to the actual conditions of all substations. Compared with the prior art, the capacitor bank is leveled without manual calculation, a large amount of time is saved, the calculated leveling result is accurate, and the existing leveling scheme is optimized. In summary, the invention solves the problems of time consumption, inaccurate leveling result, and non-optimal leveling scheme in the prior art.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a capacitor bank auto-leveling method provided according to an embodiment of the present invention;
fig. 2 is a schematic structural view of a capacitor bank automatic leveling device according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Fig. 1 is a flowchart of a capacitor bank auto-leveling method provided according to an embodiment of the present invention, and referring to fig. 1, an embodiment of the present invention provides a capacitor bank auto-leveling method that may be performed by a capacitor bank auto-leveling device that may be integrated in an electronic apparatus, and that may be implemented by software and/or hardware. The capacitor bank automatic leveling method comprises the following steps:
s110, constructing a calculation model of the capacitor bank leveling boundary condition.
Optionally, the capacitor bank includes a double Y-capacitor bank and a single Y-capacitor bank.
Optionally, the constructing a calculation model of the capacitor bank leveling boundary condition includes:
and constructing a calculation model of the leveling boundary condition of the double Y-shaped capacitor bank and a calculation model of the leveling boundary condition of the single Y-shaped capacitor bank.
Optionally, the expression of the calculation model of the double Y-type capacitor bank leveling boundary condition is as follows:
wherein U is 1 Is the maximum unbalance rate between phases of the double Y-shaped capacitor bank, U 2 Maximum unbalance rate between arms of double Y-type capacitor group, C 1 Is the sum of the measured capacitance values of the upper arm and the lower arm of the phase A, C 2 Is the sum of the measured capacitance values of the upper arm and the lower arm of the phase B, C 3 Is the sum of the measured capacitance values of the upper arm and the lower arm of the C phase, U n1 Is the standard value of the phase-to-phase unbalance rate of the double Y-type capacitor bank, U n2 Is the standard value of unbalance rate between arms of the double Y-shaped capacitor bank, P is the maximum nameplate deviation rate, and P n Is the standard value of nameplate deviation, m is the number of capacitors, d 1 For the first capacitance actual measurement value, d m Is the measured value of the mth capacitance, D 1 For the first capacitor nameplate value, D 2 For the second capacitor nameplate value, D m Is the mth capacitor nameplate value.
Optionally, the expression of the sum of the measured capacitance values of the upper arm and the lower arm of the phase a, the sum of the measured capacitance values of the upper arm and the lower arm of the phase B, and the sum of the measured capacitance values of the upper arm and the lower arm of the phase C is as follows:
C 1 ＝{C a1 ,C a2 }，C 2 ＝{C b1 ,C b2 }，C 3 ＝{C c1 ,C c2 }
wherein C is a1 Is the sum of the measured capacitance values of the A phase upper arm and C phase upper arm a2 Is the sum of the measured capacitance values of the lower arm of the phase A, C b1 Is the sum of the measured capacitance values of the upper arm of the phase B, C b2 Is the sum of the measured capacitance values of the lower arm of the phase B, C c1 Is the sum of the measured capacitance values of the upper arm of the C phase and C c2 Is the sum of the measured capacitance values of the lower arm of the C phase.
Optionally, the expression of the calculation model of the single Y-type capacitor bank leveling boundary condition is as follows:
C 22 ＝{C a ,C b ,C c }
wherein U is the maximum unbalance rate among single Y-type capacitor groups and U n Is the standard value and C of the phase-to-phase unbalance rate of a single Y-type capacitor bank 22 Is the sum of three-phase measured capacitance values C a Is the sum of the measured compatibility values of phase A, C b Is the sum of the measured capacitance values of phase B, C c Is the sum of the measured compatibility values of phase C.
Specifically, because the leveling needs to meet the requirements of unbalance rate and nameplate deviation rate, a calculation model for leveling the double-Y-shaped capacitor bank and a calculation model for leveling the single-Y-shaped capacitor bank are constructed by taking the unbalance rate and the nameplate deviation rate as boundary conditions.
S120, judging whether the nameplate deviation rate and/or the unbalance rate of the capacitor bank meet preset requirements or not based on the calculation model.
Optionally, the determining whether the nameplate deviation rate and/or the unbalance rate of the capacitor bank meets the preset requirement based on the calculation model includes:
judging whether the nameplate deviation rate and/or the unbalance rate of the single Y-shaped capacitor bank meet preset requirements or not based on the calculation model;
and judging whether the nameplate deviation rate and/or the unbalance rate of the double Y-shaped capacitor bank meet preset requirements or not based on the calculation model.
Specifically, whether the nameplate deviation rate of the capacitor bank meets the requirement is judged according to the expression of the calculation model of the double Y-shaped capacitor bank leveling boundary condition and the expression of the calculation model of the single Y-shaped capacitor bank leveling boundary condition, the capacitors are not required to be replaced if the nameplate deviation rate meets the requirement, the original capacitance value is replaced by a new capacitance value, and corresponding replacement times are increased according to the positions (upper layers and lower layers) where the capacitors are located.
S130, if the preset requirement is not met, replacing the capacitor in the capacitor bank.
Specifically, for a single Y-type capacitor bank, a capacitor C with the largest three-phase capacitance value is found max Then, the capacitor C with the smallest volume value is determined in the other two phases min And exchanging the positions of the two capacitors, calculating whether the boundary condition is met according to the expression of the calculation model of the single Y-type capacitor bank leveling boundary condition, if not, continuing the steps until the boundary condition is met, and if so, recording the replacement condition of the capacitor bank and outputting a replacement result.
For a double Y-type capacitor bank, the requirement of the phase-to-phase unbalance rate is met through a switching capacitor. Find capacitor C with maximum three-phase capacitance max Then, the capacitor C with the smallest volume value is determined in the other two phases min And exchanging the positions of the two capacitors, calculating whether the inter-phase unbalance rate is met according to the boundary conditions in the expression of the calculation model of the double Y-type capacitor bank leveling boundary conditions, if not, continuing the steps until the inter-phase unbalance rate is met, and if so, further meeting the requirement of the inter-arm unbalance rate.
Finding one phase with the largest unbalance rate among the three phases, and further finding the capacitor C with the largest capacity value in that phase max Then, a capacitor C with the smallest capacitance value is determined in the other arm of the phase min And exchanging the positions of the two capacitors, calculating whether the unbalance rate between the arms is met according to the boundary conditions in the expression of the calculation model of the double Y-shaped capacitor bank leveling boundary conditions, if not, continuing the steps until the unbalance rate is met, and if so, recording the replacement condition of the capacitor bank and outputting a replacement result.
The automatic leveling method of the capacitor bank takes the requirements for the unbalance rate of the capacitance value of the capacitor bank and the deviation rate of the measured value and the nameplate value of the single capacitance as boundary conditions, considers the variables of the capacitor bank of each transformer substation, including a double-Y/single-Y wiring mode, the single double-layer of the capacitor bank, the number of the capacitor bank, whether the capacitor needs to be replaced or not, and provides an optimized leveling scheme. The practical leveling strategy is adopted, and the situations that the capacitor chamber comprises upper and lower layers, the number of capacitor banks of different stations is inconsistent, the capacity is inconsistent and the like are considered, so that the intelligent adaptation to the practical situation of each transformer substation can be realized.
According to the technical scheme, a calculation model of the capacitor bank leveling boundary condition is constructed; judging whether the nameplate deviation rate and/or the unbalance rate of the capacitor bank meet preset requirements or not based on a calculation model; if the preset requirement is not met, the capacitors in the capacitor bank are replaced. And (3) providing an optimized leveling scheme by taking the unbalance rate and the nameplate deviation rate as boundary conditions, and intelligently adapting to the actual conditions of all substations. Compared with the prior art, the capacitor bank is leveled without manual calculation, a large amount of time is saved, the calculated leveling result is accurate, and the existing leveling scheme is optimized. In summary, the invention solves the problems of time consumption, inaccurate leveling result, and non-optimal leveling scheme in the prior art.
Fig. 2 is a schematic structural diagram of a capacitor bank automatic leveling device according to an embodiment of the present invention, and referring to fig. 2, the embodiment of the present invention further provides a capacitor bank automatic leveling device, which includes:
a calculation model construction module 201, configured to construct a calculation model of the capacitor bank leveling boundary condition;
a preset requirement judging module 202, configured to judge whether a nameplate deviation rate and/or an unbalance rate of the capacitor bank meet preset requirements based on the calculation model;
the preset requirement determining module 203 is configured to replace the capacitor in the capacitor bank if the preset requirement is not met.
Optionally, the constructing a calculation model of the capacitor bank leveling boundary condition includes:
and constructing a calculation model of the leveling boundary condition of the double Y-shaped capacitor bank and a calculation model of the leveling boundary condition of the single Y-shaped capacitor bank.
Optionally, the expression of the calculation model of the double Y-type capacitor bank leveling boundary condition is as follows:
wherein U is 1 Is the maximum unbalance rate between the two Y-shaped capacitor banks, U 2 Is a double Y-shaped electric deviceMaximum unbalance rate between arms of container group, C 1 Is the sum of the measured capacitance values of the upper arm and the lower arm of the phase A, C 2 Is the sum of the measured capacitance values of the upper arm and the lower arm of the phase B, C 3 Is the sum of the measured capacitance values of the upper arm and the lower arm of the C phase, U n1 Is the standard value of the phase-to-phase unbalance rate of the double Y-type capacitor bank, U n2 Is the standard value of unbalance rate between arms of the double Y-shaped capacitor bank, P is the maximum nameplate deviation rate, and P n Is the standard value of nameplate deviation, m is the number of capacitors, d 1 For the first capacitance actual measurement value, d m Is the measured value of the mth capacitance, D 1 For the first capacitor nameplate value, D 2 For the second capacitor nameplate value, D m Is the mth capacitor nameplate value.
Optionally, the expression of the sum of the measured capacitance values of the upper arm and the lower arm of the phase a, the sum of the measured capacitance values of the upper arm and the lower arm of the phase B, and the sum of the measured capacitance values of the upper arm and the lower arm of the phase C is as follows:
C 1 ＝{C a1 ,C a2 }，C 2 ＝{C b1 ,C b2 }，C 3 ＝{C c1 ,C c2 }
wherein C is a1 Is the sum of the measured capacitance values of the A phase upper arm and C phase upper arm a2 Is the sum of the measured capacitance values of the lower arm of the phase A, C b1 Is the sum of the measured capacitance values of the upper arm of the phase B, C b2 Is the sum of the measured capacitance values of the lower arm of the phase B, C c1 Is the sum of the measured capacitance values of the upper arm of the C phase and C c2 Is the sum of the measured capacitance values of the lower arm of the C phase.
Optionally, the expression of the calculation model of the single Y-type capacitor bank leveling boundary condition is as follows:
C 22 ＝{C a ,C b ,C c }
wherein U is the maximum unbalance rate among single Y-type capacitor groups and U n Is the standard value and C of the phase-to-phase unbalance rate of a single Y-type capacitor bank 22 Is the sum of three-phase measured capacitance values C a Is the sum of the measured compatibility values of phase A, C b Is the sum of measured capacitance values of phase B、C c Is the sum of the measured compatibility values of phase C.
Optionally, the determining whether the nameplate deviation rate and/or the unbalance rate of the capacitor bank meets the preset requirement based on the calculation model includes:
judging whether the nameplate deviation rate and/or the unbalance rate of the single Y-shaped capacitor bank meet preset requirements or not based on the calculation model;
and judging whether the nameplate deviation rate and/or the unbalance rate of the double Y-shaped capacitor bank meet preset requirements or not based on the calculation model.
Fig. 3 shows a schematic diagram of the structure of an electronic device 10 that may be used to implement an embodiment of the invention. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. Electronic equipment may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the inventions described and/or claimed herein.
As shown in fig. 3, the electronic device 10 includes at least one processor 11, and a memory, such as a Read Only Memory (ROM) 12, a Random Access Memory (RAM) 13, etc., communicatively connected to the at least one processor 11, in which the memory stores a computer program executable by the at least one processor, and the processor 11 may perform various appropriate actions and processes according to the computer program stored in the Read Only Memory (ROM) 12 or the computer program loaded from the storage unit 18 into the Random Access Memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 may also be stored. The processor 11, the ROM 12 and the RAM 13 are connected to each other via a bus 14. An input/output (I/O) interface 15 is also connected to bus 14.
Various components in the electronic device 10 are connected to the I/O interface 15, including: an input unit 16 such as a keyboard, a mouse, etc.; an output unit 17 such as various types of displays, speakers, and the like; a storage unit 18 such as a magnetic disk, an optical disk, or the like; and a communication unit 19 such as a network card, modem, wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunication networks.
The processor 11 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various processors running machine learning model algorithms, digital Signal Processors (DSPs), and any suitable processor, controller, microcontroller, etc. The processor 11 performs the various methods and processes described above, for example, the capacitor bank auto leveling method.
In some embodiments, the capacitor bank auto-leveling method may be implemented as a computer program tangibly embodied on a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and/or installed onto the electronic device 10 via the ROM 12 and/or the communication unit 19. When a computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the capacitor bank auto-leveling method described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to perform the capacitor bank auto-leveling method in any other suitable manner (e.g., by means of firmware).
Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.
A computer program for carrying out methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions/acts specified in the flowchart and/or block diagram block or blocks to be implemented. The computer program may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.
In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, the computer readable storage medium may be a machine readable signal medium. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) through which a user can provide input to the electronic device. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.
The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), blockchain networks, and the internet.
The computing system may include clients and servers. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also called a cloud computing server or a cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical hosts and VPS service are overcome.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.
The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.
Claims (10)
1. A method for automatically leveling a capacitor bank, comprising:
constructing a calculation model of a capacitor bank leveling boundary condition;
judging whether the nameplate deviation rate and/or the unbalance rate of the capacitor bank meet preset requirements or not based on the calculation model;
and if the preset requirement is not met, replacing the capacitors in the capacitor bank.
2. The method of claim 1, wherein the capacitor bank comprises a double Y-capacitor bank and a single Y-capacitor bank.
3. The method of claim 1, wherein constructing a computational model of capacitor bank leveling boundary conditions comprises:
and constructing a calculation model of the leveling boundary condition of the double Y-shaped capacitor bank and a calculation model of the leveling boundary condition of the single Y-shaped capacitor bank.
4. A method according to claim 3, characterized in that the expression of the calculation model of the double Y-capacitor bank leveling boundary conditions is as follows:
wherein U is 1 Is the maximum unbalance rate between the two Y-shaped capacitor banks, U 2 Is the maximum unbalance rate between the arms of the double Y-type capacitor bank, C 1 Is the sum of the measured capacitance values of the upper arm and the lower arm of the phase A, C 2 Is the sum of the measured capacitance values of the upper arm and the lower arm of the phase B, C 3 Is the sum of the measured capacitance values of the upper arm and the lower arm of the C phase, U n1 Is the standard value of the phase-to-phase unbalance rate of the double Y-type capacitor bank, U n2 Is the standard value of unbalance rate between arms of the double Y-shaped capacitor bank, P is the maximum nameplate deviation rate, and P n Is the standard value of nameplate deviation, m is the number of capacitors, d 1 For the first capacitance actual measurement value, d m Is the measured value of the mth capacitance, D 1 For the first capacitor nameplate value, D 2 For the second capacitor nameplate value, D m Is the mth capacitor nameplate value.
5. The method of claim 4, wherein the expression for the sum of the measured capacities of the a-phase upper and lower arms, the sum of the measured capacities of the B-phase upper and lower arms, and the sum of the measured capacities of the C-phase upper and lower arms is as follows:
C 1 ＝{C a1 ,C a2 }，C 2 ＝{C b1 ,C b2 }，C 3 ＝{C c1 ,C c2 }
wherein C is a1 Is the sum of the measured capacitance values of the A phase upper arm and C phase upper arm a2 Is the sum of the measured capacitance values of the lower arm of the phase A, C b1 Is the sum of the measured capacitance values of the upper arm of the phase B, C b2 Is the sum of the measured capacitance values of the lower arm of the phase B, C c1 Is the sum of the measured capacitance values of the upper arm of the C phase and C c2 Is the sum of the measured capacitance values of the lower arm of the C phase.
6. A method according to claim 3, characterized in that the expression of the calculation model of the single Y-capacitor bank leveling boundary conditions is as follows:
C 22 ＝{C a ,C b ,C c }
wherein U is the maximum unbalance rate among single Y-type capacitor groups and U n Is the standard value and C of the phase-to-phase unbalance rate of a single Y-type capacitor bank 22 Is the sum of three-phase measured capacitance values C a Is the sum of the measured compatibility values of phase A, C b Is the sum of the measured capacitance values of phase B, C c Is the sum of the measured compatibility values of phase C.
7. The method of claim 2, wherein determining whether the nameplate deviation and/or unbalance rate of the capacitor bank meets a preset requirement based on the computational model comprises:
judging whether the nameplate deviation rate and/or the unbalance rate of the single Y-shaped capacitor bank meet preset requirements or not based on the calculation model;
and judging whether the nameplate deviation rate and/or the unbalance rate of the double Y-shaped capacitor bank meet preset requirements or not based on the calculation model.
8. An automatic leveling device for a capacitor bank, comprising:
the calculation model construction module is used for constructing a calculation model of the capacitor bank leveling boundary condition;
the preset requirement judging module is used for judging whether the nameplate deviation rate and/or the unbalance rate of the capacitor bank meet preset requirements or not based on the calculation model;
and the preset requirement determining module is used for replacing the capacitors in the capacitor bank if the preset requirement is not met.
9. An electronic device, comprising:
one or more processors;
a memory for storing one or more programs;
when executed by the one or more processors, causes the one or more processors to implement the method of any of claims 1-7.
10. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the method according to any of claims 1-7.
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| CN202311526009.1A CN117578519A (en) | 2023-11-15 | 2023-11-15 | Capacitor bank automatic leveling method and device, electronic equipment and storage medium |
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| CN202311526009.1A CN117578519A (en) | 2023-11-15 | 2023-11-15 | Capacitor bank automatic leveling method and device, electronic equipment and storage medium |
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