CN117577671A - Super-junction IGBT device - Google Patents

Super-junction IGBT device Download PDF

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Publication number
CN117577671A
CN117577671A CN202311578709.5A CN202311578709A CN117577671A CN 117577671 A CN117577671 A CN 117577671A CN 202311578709 A CN202311578709 A CN 202311578709A CN 117577671 A CN117577671 A CN 117577671A
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region
epitaxial layer
gate
conductivity type
layer
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曾大杰
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Shenzhen Shangyangtong Technology Co ltd
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Shenzhen Shangyangtong Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention discloses a super-junction IGBT device, which comprises: the device comprises a super junction structure and a first epitaxial layer positioned at the bottom of the super junction structure, wherein the bottom surface of a second conductive type column of the super junction structure is positioned below the top surface of the first epitaxial layer, a first bottom doping region of a second conductive type is formed at the bottom of the second conductive type column, the first bottom doping region is contacted with an extension part of the second conductive type column extending into the first epitaxial layer and overlapped to form a second bottom doping region, and when the device is reversely biased, each second bottom doping region depletes the first epitaxial layer and forms a bottom pressure-resistant layer; the front side structure of the superjunction IGBT device includes a channel region doped with the second conductivity type. A first top doped region doped with a first conductivity type is arranged between the channel region and the second conductivity type column, and the first top doped region enables the second conductivity type column to be in a floating structure. The invention can improve the breakdown voltage of the device and reduce the process difficulty at the same time, and can lead the breakdown voltage of the device to be more than 1200V.

Description

Super-junction IGBT device
Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a Super Junction (SJ) Insulated Gate Bipolar Transistor (IGBT) device.
Background
As shown in fig. 1, the structure of the existing super-junction IGBT device (SJ-IGBT) is schematically shown; the existing superjunction IGBT device includes:
the collector region 101 is formed by back injection, taking an N-type device as an example, the collector region 101 is doped P-type, and is formed by P-type back injection; implanted impuritiesTypically Boron (Boron), but also BF2, at an energy of between 15 and 100keV, at a dose of typically 1e12/cm 2 ～1e14/cm 2 Between them. Generally, the higher the dose of the back side implant, the lower the on-voltage drop when the device is on, but the larger the current tail when the device is off, the higher the turn-off loss. The dose of the backside implant is therefore typically higher for IGBT devices for low speed applications, and lower for high speed applications.
The N-type epitaxial layer 102 constitutes the N-type drift region of the device. Unlike the conventional IGBT, the SJ-IGBT further includes P pillars 105 formed in the N-type epitaxial layer 102, and the N pillars formed by the N-type epitaxial layer 102 between the P pillars 105 and the P pillars 105 are alternately arranged to form a superjunction structure, where the thickness t101 of the superjunction structure is the thickness of the P-type 105. The P-pillar 105 is usually implemented in two ways, namely, trench etching and P-type silicon filling, and the method has the advantages of less process steps, but high depth-to-width ratio of the trench etching and high process difficulty; and when P-type silicon is filled, defects are easily introduced, so that the electric leakage of the device is large, and more importantly, the inclination angle of the groove etching is difficult to Monitor (Monitor), so that great difficulty is brought to process control. The other is based on multiple epitaxy and ion implantation, which has the advantages of simple process implementation, but more process steps and high cost. The breakdown voltage of the SJ-IGBT is reduced by the lateral depletion of the P-pillar 105 and the N-type drift region between the P-pillars 105, so that the doping concentration of the drift region can be greatly increased without reducing the breakdown voltage. Taking 650V IGBT as an example, the doping concentration of the drift region is usually 2e14/cm 3 The doping concentration of the drift region of the SJ-IGBT can be 2e15/cm 3 Above, even up to 1e16/cm 3 The above. The depth of the P column 105 is deep, so that the rapid extraction of charges can be realized when the IGBT is turned off, and dv/dt in the turn-off process is improved. But in order to increase the conductance modulation effect of the IGBT, the P pillars 105 are typically floating. This may be achieved by epitaxy above the process, or by high energy N-type ion implantation, i.e. forming N-doped regions 112 on top of the P-pillars 105.
The gate structure in fig. 1 is a trench gate, and includes a gate dielectric layer 103 formed on an inner surface of a gate trench and a polysilicon gate 104 filled in the gate trench. The gate dielectric layer 103 is typically a gate oxide layer, and the thickness of the gate oxide layer is typically equal toNearby.
A P-type channel region 106 is formed on top of the super junction structure, and the IGBT is used for reducing Latch-Up (Latch-Up), the doping concentration of the channel region 106 is usually higher, the channel region 106 is formed by ion implantation, and the implantation dose is usually 1e13/cm 2 ～1e14/cm 2 Between them.
An emitter region 107, which is an N+ doped source region, is formed on the surface of the channel region 106, the emitter region 107 is typically implanted with Arsenic (arsenical) at a dose of typically 1e15/cm 2 ～1e16/cm 2 Between them. Emitter region 107 is connected to a source electrode formed by front side metal layer 110 through metal via 108. The metal vias 108 are typically formed with Tungsten (tunesten) fill. In order to form a good ohmic contact between the metal via 108 and the channel region 106, a via implant is used to form the channel drain region 109, typically using a BF2 implant with an energy of typically between 15 and 100keV, and a dose of typically 1e14/cm 2 ～5e15/cm 2 Between them.
The doping concentration of the N-type epitaxial layer 102 corresponding to the drift region of the SJ-IGBT is more than 5 times that of the traditional IGBT, and the breakdown voltage is mainly realized by the lateral depletion of an N column and a P column 5 formed by the N-type epitaxial layer 102, so that the equivalent doping concentration of the drift region is reduced, and the corresponding Breakdown Voltage (BV) is realized; therefore, the breakdown voltage thereof mainly depends on the depth t101 of the P pillar 5; typically for a 650V SJ-IGBT, its depth t101 needs to be greater than 40 μm; whereas if a 1200V SJ-IGBT is to be implemented, its depth t101 needs to be greater than 80 μm; this presents a significant difficulty in the implementation of the process.
Disclosure of Invention
The technical problem to be solved by the invention is to provide the super-junction IGBT device, which can improve the breakdown voltage of the device and reduce the process difficulty at the same time, and can enable the breakdown voltage of the device to reach more than 1200V.
In order to solve the above technical problems, the super-junction IGBT device provided by the invention includes: a first epitaxial layer doped with a first conductivity type and a second epitaxial layer doped with the first conductivity type formed on a top surface of the first epitaxial layer.
Forming a plurality of second conductive type pillars in the second epitaxial layer, the first conductive type pillars being composed of the second epitaxial layer between the second conductive type pillars; the first conductive type columns and the second conductive type columns are alternately arranged to form a super junction structure.
The doping concentration of the second conductive type column is matched with the doping concentration of the second epitaxial layer, so that the charges of the first conductive type column and the second conductive type column are matched, and when the device is reversely biased, the super junction structure is exhausted and a top pressure-resistant layer is formed.
The bottom surface of the second conductivity type pillars is below the top surface of the first epitaxial layer, and a first bottom doped region of a second conductivity type is formed in the first epitaxial layer below the bottom surface of each of the second conductivity type pillars.
The first bottom doping region and the extension part of the second conductive type column extending into the first epitaxial layer are contacted and overlapped to form second bottom doping regions, and when the device is reversely biased, the first epitaxial layer is depleted by each second bottom doping region and a bottom pressure-resistant layer is formed; the doping concentration of the second conductive type column has fluctuation generated by the process, and the doping concentration of the first bottom doping region meets the requirement of fully exhausting the first epitaxial layer required by voltage withstanding when the device is reversely biased when the doping concentration of the second conductive type column is at the lowest value of the fluctuation.
The front side structure of the superjunction IGBT device includes a channel region doped with the second conductivity type.
A first top doped region of a first conductivity type doping is provided between the channel region and the second conductivity type pillar, the first top doped region spacing the second conductivity type pillar from the channel region and thereby rendering the second conductivity type pillar a floating structure.
The back structure of the super-junction IGBT device is formed on the back of the first epitaxial layer.
In a further improvement, the composition structure of the second conductive type column comprises a third epitaxial layer of the second conductive type filled in the super junction trench.
A further improvement is that a bottom surface of the second conductivity type pillar is defined by a bottom surface of the superjunction trench, the bottom surface of the superjunction trench being located below a top surface of the first epitaxial layer.
The first bottom doped region is an ion implantation region of a second conductivity type formed at the bottom of the superjunction trench in a self-aligned manner.
The ion implantation energy of the first bottom doped region is 50 keV-200 keV, and the implantation dosage is 5e11cm -2 ～2e12cm -2 。
In a further improvement, the resistivity of the first epitaxial layer is 5 times or more the resistivity of the second epitaxial layer.
In a further improvement, the resistivity of the first epitaxial layer is 10 times or more the resistivity of the second epitaxial layer.
Further improvement is that the front structure further comprises: a gate structure, a heavily doped emitter region of a first conductivity type, an interlayer film, a via hole passing through the interlayer film, and an emitter and a gate electrode patterned from a front side metal layer.
The gate structure comprises a gate dielectric layer and a gate conductive material layer.
The emitter region is formed on a surface of the channel region and is self-aligned to the gate structure.
The emitting region is connected with the emitting electrode through the through hole corresponding to the top.
The gate conductive material layer is connected with the gate through the through hole corresponding to the top.
A further improvement is that the through hole corresponding to the emitting region also passes through the emitting region and is in contact with the channel region; and a channel leading-out region which is heavily doped with the second conduction type is formed at the bottom of the through hole corresponding to the emission region, ohmic contact is formed between the channel leading-out region and the through hole at the top of the channel leading-out region, and the channel region is contacted with the through hole through the channel leading-out region.
The gate structure is further improved by adopting a trench gate, the trench gate further comprises a gate trench, the gate dielectric layer is formed on the inner side surface of the gate trench, and the gate trench is filled with the gate conductive material layer.
The drift region includes the first top doped region at the bottom of the channel region, the first conductivity type pillar, and the first epitaxial layer.
The gate trench extends longitudinally through the channel region, and sides of the channel region covered by the trench gate sides are used to form a conductive channel connecting the emitter region and the drift region.
A further improvement is that the gate structure employs a planar gate.
A fourth epitaxial layer doped with the first conductivity type is formed on top of the superjunction structure, the first top doped region is composed of the fourth epitaxial layer, and the channel region is formed in a selected region of the fourth epitaxial layer.
The drift region comprises a first top doped region at the bottom of the channel region, the fourth epitaxial layer between the channel regions, and the first conductivity type pillars and the first epitaxial layer at the bottom.
The planar gate is formed on the front surface of the channel region and extends to the surface of the drift region, and the surface of the channel region covered by the front surface of the planar gate is used for forming a conductive channel for connecting the emission region and the drift region.
A further improvement is that the step of the superjunction structure is the sum of the width of the first conductivity type pillars and the width of the second conductivity type pillars.
The step of the trench gate is the sum of the width of the gate trench and the pitch of the gate trench.
The step of the trench gate is independent of the step of the superjunction structure, so that the step of the trench gate is smaller than or equal to or larger than the step of the superjunction structure.
A further improvement is that more than one emitter trench is also provided between at least part of the gate trenches.
And a second dielectric layer and an emitter conductive material layer are formed on the inner side surface of the emitter groove, and the emitter conductive material layer is connected with the emitter through the through hole corresponding to the top.
Further improvement is that the front structure further comprises: a carrier storage layer of a first conductivity type heavily doped, the carrier storage layer disposed between the channel region and the first top doped region.
Further improvement is that the back structure includes:
a heavily doped collector region of the second conductivity type.
A back metal layer is formed on the back surface of the collector region and a collector is drawn out from the back metal layer.
Further improvement is that the back structure includes:
and the buffer layer is positioned between the top surface of the first epitaxial layer and the top surface of the collector region, the doping concentration of the buffer layer is larger than that of the first epitaxial layer, and the first epitaxial layer is prevented from being completely consumed when the device is reversely biased, so that device punch-through is prevented.
The buffer layer is formed on the back surface of the first epitaxial layer by back surface ion implantation, the implantation energy of the back surface ion implantation of the buffer layer is 100 keV-2 MeV, and the implantation dosage is 1e12cm -2 ～3e13cm -2 。
The super-junction IGBT device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or the super-junction IGBT device is a P-type device, the first conduction type is P-type, and the second conduction type is N-type.
The super-junction IGBT device adopts the top voltage-resistant layer formed by depletion of the super-junction structure and the bottom voltage-resistant layer formed by depletion of the first epitaxial layer at the bottom of the super-junction structure to realize voltage resistance together during reverse bias, so that the breakdown voltage of the device can be improved, and the defect of increased process difficulty caused by increasing the voltage resistance by independently increasing the thickness of the super-junction structure is avoided, so that the breakdown voltage of the device can be improved, the process difficulty can be reduced, and the breakdown voltage of the device can be more than 1200V.
In the invention, the depletion of the first epitaxial layer is realized by adopting the extension part of the second conductive type column extending downwards into the first epitaxial layer, and the doping concentration of the second conductive type column needs to be ensured to meet the requirement of charge matching with the first conductive type column, so that the doping concentration of the second conductive type column cannot be regulated according to the depletion requirement of the first epitaxial layer, and in order to ensure the full depletion of the first epitaxial layer, the first bottom doping region is added at the bottom of the second conductive type column, and the first bottom doping region can compensate the depletion deficiency of the first epitaxial layer when the doping concentration of the second conductive type column fluctuates, thereby ensuring that the full depletion of the first epitaxial layer can be realized even when the doping concentration of the second conductive type column is the lowest value of fluctuation, and ensuring that the breakdown voltage reaches the required value; in addition, the first bottom doped region can be formed at the bottom of the second conductive type column in a self-aligned manner through ion implantation, so that the method has the advantage of simple process.
According to the invention, the first bottom doping region is arranged to easily realize sufficient depletion of the first epitaxial layer, meanwhile, in order to avoid the problem of device punch-through caused by complete depletion of the first epitaxial layer, the buffer layer with doping concentration larger than that of the first epitaxial layer is additionally arranged at the bottom of the first epitaxial layer, the buffer layer can prevent the device from punch-through, and meanwhile, the arrangement of the first epitaxial layer and the first bottom doping region is facilitated in turn, so that the process of the device is simpler.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
fig. 1 is a schematic structural diagram of a conventional superjunction IGBT device;
fig. 2A is a schematic structural diagram of the IGBT device according to the first embodiment of the present invention before diffusion after implantation of the first bottom doped region;
fig. 2B is a schematic structural view of an IGBT device according to the first embodiment of the invention;
fig. 3 is a schematic structural view of an IGBT device according to a second embodiment of the invention;
fig. 4 is a schematic structural diagram of an IGBT device according to a third embodiment of the invention.
Detailed Description
As shown in fig. 2B, a schematic structural diagram of an IGBT device according to a first embodiment of the invention; fig. 2A is a schematic structural diagram of the IGBT device according to the first embodiment of the present invention, after implantation, before diffusion of the first bottom doped region 12; the super-junction IGBT device of the first embodiment of the invention comprises: a first epitaxial layer 11 doped with a first conductivity type and a second epitaxial layer 2 doped with the first conductivity type formed on a top surface of the first epitaxial layer 11.
A plurality of second conductive type pillars 5 are formed in the second epitaxial layer 2, the first conductive type pillars being composed of the second epitaxial layer 2 between the second conductive type pillars 5; the first conductive type pillars and the second conductive type pillars 5 are alternately arranged to form a superjunction structure.
The doping concentration of the second conductivity type pillars 5 is matched with the doping concentration of the second epitaxial layer 2 so that the charges of the first conductivity type pillars and the second conductivity type pillars 5 are matched, and when the device is reversely biased, the super junction structure is depleted and a top voltage-resistant layer is formed. The charge matching of the first conductive type column and the second conductive type column 5 means that the first conductive type column and the second conductive type column 5 can be mutually and laterally depleted when the device is reversely biased.
The bottom surface of the second conductivity type pillars 5 is located below the top surface of the first epitaxial layer 11, and a first bottom doped region 12 of the second conductivity type is formed in the first epitaxial layer 11 below the bottom surface of each second conductivity type pillar 5. In fig. 2B, the thickness t is the thickness of the second conductivity type pillar 5, and the effective thickness of the superjunction structure is equal to the thickness of the second conductivity type pillar 5 on the top surface of the first epitaxial layer 11.
The first bottom doping region 12 is contacted with an extension part of the second conductive type column 5 extending into the first epitaxial layer 11 and overlapped to form second bottom doping regions, and when the device is reversely biased, each second bottom doping region depletes the first epitaxial layer 11 and forms a bottom pressure-resistant layer; the doping concentration of the second conductivity type pillars 5 has process-induced fluctuations, and the doping concentration of the first bottom doped region 12 is such that sufficient depletion required for withstand voltage of the first epitaxial layer 11 upon reverse bias of the device is still ensured when the doping concentration of the second conductivity type pillars 5 is at the lowest value of the fluctuations. According to the common general knowledge of the person skilled in the art, in the prior art, a super junction structure and the first epitaxial layer 11 at the bottom are often directly overlapped to form a voltage-resistant layer, and the disadvantage of this structure is that the depletion of the first epitaxial layer 11 is not easy to perform good control, because the first epitaxial layer 11 is completely depleted through the extension portion of the second conductivity type pillar 5, which can limit the doping concentration and thickness of the first epitaxial layer 11, so that the doping concentration and thickness of the first epitaxial layer 11 are not well set; meanwhile, even if the doping concentration and thickness of the first epitaxial layer 11 are set to be depleted by the extension portion of the second conductivity type pillar 5, after the actual process, parameters tend to fluctuate, for example, the doping concentration of the second conductivity type pillar 5 fluctuates up and down at a design value, and when the fluctuation of the doping concentration of the second conductivity type pillar 5 reaches a lower value, the required depletion of the first epitaxial layer 11 is not achieved, so that the depletion control of the first epitaxial layer 11 in the prior art is difficult. In the first embodiment of the present invention, by separately providing the first bottom doped region 12, the first bottom doped region 12 is easily set according to the depletion requirement of the first epitaxial layer 11, so as to ensure that the first epitaxial layer 11 can be fully depleted, and ensure the withstand voltage of the first epitaxial layer 11.
The front side structure of the superjunction IGBT device comprises a channel region 6 doped with the second conductivity type.
A first top doped region 15 of the first conductivity type doping is provided between the channel region 6 and the second conductivity type pillar 5, the first top doped region 15 spacing the second conductivity type pillar 5 from the channel region 6 and thereby providing the second conductivity type pillar 5 with a floating structure. In some embodiments, the first top doped region 15 is formed by a first conductivity type doped epitaxial layer. In some embodiments, it can also be: the first top doped region 15 is formed by ion implantation of a first conductivity type doping on the basis of the epitaxial layer.
The back side structure of the super junction IGBT device is formed on the back side of the first epitaxial layer 11.
In the first embodiment of the present invention, the composition structure of the second conductivity type pillar 5 includes the third epitaxial layer of the second conductivity type filled in the superjunction trench.
The bottom surface of the second conductivity type pillars 5 is defined by the bottom surface of the superjunction trench, which is located below the top surface of the first epitaxial layer 11.
The first bottom doped region 12 is an ion implanted region of the second conductivity type formed in the bottom of the superjunction trench in a self-aligned manner. As shown in fig. 2A, the ion implantation region 12A is an ion implantation region of the second conductivity type formed at the bottom of the superjunction trench in a self-aligned manner corresponding to the first bottom doping region 12. Typically, the ion implantation region 12a is smaller in area after implantation, such as a width generally close to the bottom width of the superjunction trench. However, due to the low doping concentration of the first epitaxial layer 11, the ion implantation region 12a is subjected to a thermal process and then is diffused greatly, and the diffused ion implantation region 12a forms the first bottom doped region 12.
In some embodiments, the ion implantation energy of the first bottom doped region 12 is 50 keV-200 keV, the implantation dose is 5e11cm -2 ～2e12cm -2 。
In some embodiments, the resistivity of the first epitaxial layer 11 is more than 5 times the resistivity of the second epitaxial layer 2; the resistivity corresponds to the doping concentration, from the doping concentration point of view can be described as: the doping concentration of the first epitaxial layer 11 is 1/5 or less of the doping concentration of the second epitaxial layer 2. In some preferred embodiments, the resistivity of the first epitaxial layer 11 is more than 10 times the resistivity of the second epitaxial layer 2.
In a first embodiment of the present invention, the front structure further includes: a gate structure, a heavily doped emitter region 7 of the first conductivity type, an interlayer film 14, a via 8 passing through the interlayer film 14, and an emitter and a gate (not shown) patterned from the front side metal layer 10. The front metal layer 10 corresponding to the emitter electrode shown in fig. 2B is not shown.
The gate structure comprises a gate dielectric layer 3 and a gate conductive material layer 4. In some embodiments, the gate dielectric layer 3 is a gate oxide layer. The gate conductive material layer 4 adopts a polysilicon gate.
An emitter region 7 is formed on the surface of the channel region 6 and is self-aligned to the gate structure.
The emitter region 7 is connected to the emitter via a top corresponding via 8.
The layer of gate conductive material 4 is connected to the gate through a top corresponding via 8.
The corresponding through holes 8 of the emitter region 7 also pass through the emitter region 7 and are in contact with the channel region 6; a channel extraction region 9 heavily doped with the second conductivity type is also formed at the bottom of the through hole 8 corresponding to the emitter region 7, ohmic contact is formed between the channel extraction region 9 and the top through hole 8, and the channel region 6 is contacted with the through hole 8 through the channel extraction region 9.
In the first embodiment of the invention, the gate structure adopts a trench gate, the trench gate further comprises a gate trench, the gate dielectric layer 3 is formed on the inner side surface of the gate trench, and the gate trench is filled with the gate conductive material layer 4.
The components of the drift region include a first top doped region 15 at the bottom of the channel region 6, a column of the first conductivity type and a first epitaxial layer 11.
The gate trench runs longitudinally through the channel region 6, the sides of the channel region 6 covered by the trench gate sides being used to form a conductive channel connecting the emitter region 7 and the drift region.
In other embodiments, it can also be: the grid structure adopts a plane grid. A fourth epitaxial layer doped with the first conductivity type is formed on top of the superjunction structure, the first top doped region 15 being composed of the fourth epitaxial layer, and the channel region 6 being formed in a selected region of the fourth epitaxial layer. The components of the drift region include a first top doped region 15 at the bottom of the channel region 6, a fourth epitaxial layer between the channel regions 6, and a bottom first conductivity type pillar and first epitaxial layer 11. A planar gate is formed on the front side of the channel region 6 and extends to the drift region surface, the surface of the channel region 6 covered by the front side of the planar gate being used to form a conductive channel connecting the emitter region 7 and the drift region.
In the first embodiment of the present invention, the step of the superjunction structure is the sum of the width of the first conductivity type pillar and the width of the second conductivity type pillar 5.
The step of the trench gate is the sum of the width of the gate trench and the pitch of the gate trench.
The step of the trench gate is independent of the step of the superjunction structure, so that the step of the trench gate is smaller than or equal to or larger than the step of the superjunction structure.
In the first embodiment of the present invention shown in fig. 2B, the step of the trench gate is set equal to the step of the superjunction structure, and the trench gate is generally disposed directly above the first conductivity type pillar. At this time, the thickness of the first top doping region 15 may be thinner, and the bottom of the gate trench may enter the top region of the first conductive type column.
In other embodiments, the step of the trench gate can also be set to be smaller than the step of the superjunction structure; or the step of the trench gate is set to be larger than that of the superjunction structure. And how to set can be flexibly selected according to actual needs.
In a first embodiment of the present invention, a back structure includes:
the collector region 1 is heavily doped of the second conductivity type.
A back metal layer (not shown) is formed on the back surface of the collector region 1 and the collector is drawn out of the back metal layer.
A buffer layer 13 doped with the first conductivity type, the buffer layer 13 being located between the top surface of the first epitaxial layer 11 and the top surface of the collector region 1, the buffer layer 13 having a doping concentration greater than that of the first epitaxial layer 11, preventing device punch-through when the first epitaxial layer 11 is fully depleted when the device is reverse biased. By providing the buffer layer 13, device punch-through is prevented, thereby improving device performance; the arrangement of the first bottom doped region 12 and the first epitaxial layer 11 can be further simplified in turn, for example, the first bottom doped region 12 can be increased to ensure that the first epitaxial layer 11 can be fully depleted in reverse bias, and the thickness of the first epitaxial layer 11 is fixed when the first epitaxial layer 11 is fully depleted, so that the voltage withstand capability of the first epitaxial layer 11 is also fixed. In contrast, if the buffer layer 13 is not provided, the doping of the first bottom doping 12 needs to control the depletion of the first epitaxial layer 11 to prevent device punch-through. The device is penetrated between the emitter region 7 and collector region 1 by a depletion region.
In some embodiments, the buffer layer 13 is formed on the back surface of the first epitaxial layer 11 by back surface ion implantation, the implantation energy of the back surface ion implantation of the buffer layer 13 is 100 keV-2 MeV, and the implantation dose is 1e12cm -2 ～3e13cm -2 。
In the first embodiment of the invention, the super-junction IGBT device is an N-type device, the first conductive type is N-type, and the second conductive type is P-type. In other embodiments are also: the super-junction IGBT device is a P-type device, the first conduction type is P-type, and the second conduction type is N-type.
The super-junction IGBT device of the first embodiment of the invention realizes voltage resistance by adopting the top voltage-resistant layer formed by depletion of the super-junction structure and the bottom voltage-resistant layer formed by depletion of the first epitaxial layer 11 at the bottom of the super-junction structure together in reverse bias, so that the breakdown voltage of the device can be improved, and the defect of increased process difficulty caused by increasing the voltage resistance by independently increasing the thickness of the super-junction structure is avoided, so that the first embodiment of the invention can improve the breakdown voltage of the device, reduce the process difficulty and enable the breakdown voltage of the device to be more than 1200V.
In the first embodiment of the present invention, the depletion of the first epitaxial layer 11 is achieved by adopting the extension portion of the second conductive type column 5 extending downward into the first epitaxial layer 11, and since the doping concentration of the second conductive type column 5 needs to be guaranteed to meet the requirement of matching with the charge of the first conductive type column, the doping concentration of the second conductive type column 5 cannot be adjusted according to the depletion requirement of the first epitaxial layer 11, in order to guarantee the sufficient depletion of the first epitaxial layer 11, the first bottom doping region 12 is added at the bottom of the second conductive type column 5, and the first bottom doping region 12 can compensate the depletion deficiency of the first epitaxial layer 11 when the doping concentration of the second conductive type column 5 fluctuates, so that the sufficient depletion of the first epitaxial layer 11 can be still achieved even when the doping concentration of the second conductive type column 5 is at the lowest value of fluctuation, and the breakdown voltage can be guaranteed to reach the required value; in addition, the first bottom doping region 12 can be self-aligned to the bottom of the second conductive type column 5 by ion implantation, so that there is an advantage in that the process is simple.
In the first embodiment of the present invention, the first bottom doped region 12 is disposed to easily realize sufficient depletion of the first epitaxial layer 11, and in order to avoid the problem of device punch-through caused by complete depletion of the first epitaxial layer 11, the first embodiment of the present invention further adds the buffer layer 13 with a doping concentration greater than that of the first epitaxial layer 11 at the bottom of the first epitaxial layer 11, where the buffer layer 13 can prevent device punch-through, and is in turn beneficial to the disposition of the first epitaxial layer 11 and the first bottom doped region 12, so that the device process is simpler.
The following further describes relevant parameters of the device according to the first embodiment of the present invention, taking a 1200V superjunction IGBT as an example:
the thickness of the second epitaxial layer 2, i.e. the length of the drift region of the second epitaxial layer 2, is 50 microns, the corresponding doping concentration is 2Ω×cm (here resistivity is used to denote doping concentration), and the lateral depletion of the first and second conductivity type pillars 5 formed by the second epitaxial layer 2 is used to withstand approximately half the breakdown voltage.
The other half is realized by the first epitaxial layer 11; the doping concentration of the first epitaxial layer 11 is 110Ω×cm, with a corresponding thickness of 55 μm.
Because the doping concentration of the second conductivity type pillar 5 is somewhat fluctuating, this may result in a lower electric field strength at the bottom of the second conductivity type pillar 5, as shown at a location a in fig. 2B, if the P-type doping concentration is lower than ideal; this may result in a weakening of the depletion capability of the drift region formed by the first epitaxial layer 11, resulting in a reduction of the breakdown voltage. To solve this problem, there is a P-type ion implantation at the bottom of the second conductivity type pillar 5, which is aimed at ensuring that the first epitaxial layer 11 is sufficiently depleted even in the case of a change in the doping concentration of the second conductivity type pillar 5, thereby ensuring that the device has a sufficient withstand voltage; the first bottom doped region 12 is typically implanted at an energy of between 50 and 200keVThe dosage is usually 5e11/cm 2 To 2e12/cm 2 Between them. The first bottom doped region 12 and the second conductivity type pillar 5 are formed as a P-type entity. The location of the P-type ion implantation in the body must be at the location of the first epitaxial layer 11, as shown in fig. 2A. Because of the large difference in doping concentrations of the first epitaxial layer 11 and the second epitaxial layer 2, the width of the P-type region formed in the body of the first bottom doped region 12 is increased, as shown in fig. 2B.
In the prior SJ-IGBT, the drift region directly consists of the second epitaxial layer 2 with high doping concentration, so that the problem of punch-through is not needed to be worried. However, in the first embodiment of the present invention, the doping concentration of the first epitaxial layer 11 is low, and if it is depleted, the device is easily penetrated, and in order to solve this problem, a buffer layer 13 may be added between the first epitaxial layer 11 and the collector region 1, the first epitaxial layer 1 is typically formed on the surface of a semiconductor substrate such as a silicon wafer, and this buffer layer 13 is typically formed by backside ion implantation after the silicon wafer is thinned. The usual implant impurity for ion implantation of the buffer layer 13 is Phosphorus (Phosphorus), the implant energy is typically between 100keV and 2MeV, and the implant dose is typically 1e12/cm 2 ～3e13/cm 2 Between them. To reduce the Spike (Spike) during turn-off, proton implantation may also be used, which can implant a deeper junction depth.
In the first embodiment of the present invention, the step (Pitch) of the superjunction structure is mainly limited by the second conductivity type pillars 5 and the distance between the second conductivity type pillars 5. Taking a typical silicon 1200V super-junction IGBT (SJ-IGBT) as an example, the width of the second conductivity type pillar 5, which is a typical P pillar, is 4 μm, the distance between the P pillar and the P pillar is 5 μm, and the depth of the P pillar is 45 μm; the corresponding Pitch is 9 μm.
In the first embodiment of the present invention, the step of the trench gate is equal to the step of the superjunction structure, so that the trench gate is 9 μm. In other embodiments, the trench gate step can also be: 3 μm, 1.8 μm, 2 μm, etc. The flexibility of Pitch of the trench gate is not lost by Pitch pinning of the P-pillars. This is different from the SJ MOSFET because electrons and holes are injected into the entire drift region when the SJ-IGBT is turned on.
As shown in fig. 3, a schematic structural diagram of an IGBT device according to a second embodiment of the invention; the IGBT device according to the second embodiment of the invention differs from the IGBT device according to the first embodiment of the invention in that the IGBT device according to the second embodiment of the invention further includes:
more than one emitter trench is also provided between at least some of the gate trenches.
A second dielectric layer 3a and an emitter conductive material layer 4a are formed on the inner side surface of the emitter trench, the emitter conductive material layer 4a is filled, and the emitter conductive material layer 4a is connected with the emitter through a through hole 8 corresponding to the top.
The emitter trench and the gate trench are formed in the same process structure and simultaneously, the second dielectric layer 3a and the gate dielectric layer 3 are formed in the same process structure and simultaneously, and the emitter conductive material layer 4a is formed in the same process structure and simultaneously.
The gate conductive material layer 4 and the emitter conductive material layer 4a are respectively formed such that the emitter region 7 is not formed at the side of the emitter conductive material layer 4a and the top of the emitter conductive material layer 4a is connected to the emitter. In this way no conductive channel is formed in the channel region 6 at the side of the emitter trench.
Meanwhile, the top of the emitter electrode conductive material layer 4a is connected with the emitter electrode, so that parasitic capacitance between the grid electrode and the collector electrode can be reduced, and the parasitic capacitance between the grid electrode and the collector electrode is reduced, wherein the parasitic capacitance between the grid electrode and the collector electrode is related to the depletion region of the drift region by the grid electrode conductive material layer 4; after the emitter conductive material layer 4a is added, the depletion region of the drift region by the gate conductive material layer 4 is reduced, so Cgc can be reduced. Depletion of the drift region by the emitter conductive material layer 4a forms Cec, cgc being the parasitic capacitance between the emitter and collector. Since Cgc is the miller capacitance of the device, the effect on the switching speed is large, so by reducing Cgc, the switching speed of the device is increased.
In addition, if more than two emitter trenches are included between two adjacent gate trenches, the channel region 6 between the emitter trenches will not be connected to the emitter and to other electrodes, and thus will be in a floating, i.e., floating state, and in fig. 3, the channel region in a floating state is denoted by reference numeral 6a alone. The floating channel region 6a increases the charge carrier injection storage effect, the on-voltage decreases, but the corresponding off-loss increases. The floating channel region 6a needs to be provided according to actual needs.
As shown in fig. 4, a schematic structural diagram of an IGBT device according to a third embodiment of the invention; the IGBT device according to the third embodiment of the present invention is different from the IGBT device according to the second embodiment of the present invention in that the IGBT device according to the third embodiment of the present invention further includes:
the front structure further includes: a carrier storage layer 16 of the first conductivity type heavily doped, the carrier storage layer 16 being arranged between the channel region 6 and the first top doped region 15.
The carrier storage layer 16 can be realized by ion implantation. In some preferred embodiments, the first top doped region 15 is realized by ion implantation. The specific implementation process can be performed using any of the presently disclosed processes.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.

Claims (17)

1. A superjunction IGBT device, comprising: a first epitaxial layer doped with a first conductivity type and a second epitaxial layer doped with the first conductivity type formed on a top surface of the first epitaxial layer;
forming a plurality of second conductive type pillars in the second epitaxial layer, the first conductive type pillars being composed of the second epitaxial layer between the second conductive type pillars; the first conductive type columns and the second conductive type columns are alternately arranged to form a super junction structure;
the doping concentration of the second conductive type column is matched with the doping concentration of the second epitaxial layer so that the charges of the first conductive type column and the second conductive type column are matched, and when the device is reversely biased, the super junction structure is exhausted and a top pressure-resistant layer is formed;
the bottom surface of the second conductive type column is located below the top surface of the first epitaxial layer, and a first bottom doping region of the second conductive type is formed in the first epitaxial layer below the bottom surface of each second conductive type column;
the first bottom doping region and the extension part of the second conductive type column extending into the first epitaxial layer are contacted and overlapped to form second bottom doping regions, and when the device is reversely biased, the first epitaxial layer is depleted by each second bottom doping region and a bottom pressure-resistant layer is formed; the doping concentration of the second conductive type column has fluctuation generated by a process, and the doping concentration of the first bottom doping region meets the requirement of fully exhausting required for withstand voltage of the first epitaxial layer when the doping concentration of the second conductive type column is the lowest value of fluctuation;
the front surface structure of the super-junction IGBT device comprises a channel region doped with a second conductive type;
a first top doped region of a first conductivity type doping between the channel region and the second conductivity type pillar, the first top doped region spacing the second conductivity type pillar from the channel region and thereby rendering the second conductivity type pillar a floating structure;
the back structure of the super-junction IGBT device is formed on the back of the first epitaxial layer.
2. The superjunction IGBT device of claim 1, wherein: the composition structure of the second conductive type column comprises a third epitaxial layer of the second conductive type filled in the super junction groove.
3. The superjunction IGBT device of claim 2, wherein: a bottom surface of the second conductivity type pillar is defined by a bottom surface of the superjunction trench, the bottom surface of the superjunction trench being below a top surface of the first epitaxial layer;
the first bottom doped region is an ion implantation region of a second conductivity type formed at the bottom of the superjunction trench in a self-aligned manner.
4. The superjunction IGBT device of claim 3 wherein: the ion implantation energy of the first bottom doping region is 50 keV-200 keV, and the implantation dosage is 5e11cm -2 ～2e12cm -2 。
5. The superjunction IGBT device of claim 1, wherein: the resistivity of the first epitaxial layer is more than 5 times that of the second epitaxial layer.
6. The superjunction IGBT device of claim 5 wherein: the resistivity of the first epitaxial layer is 10 times or more the resistivity of the second epitaxial layer.
7. The superjunction IGBT device of claim 1, wherein: the facade further comprises: a gate structure, a heavily doped emitter region of a first conductivity type, an interlayer film, a via hole passing through the interlayer film, and an emitter and a gate formed by patterning a front side metal layer;
the grid structure comprises a grid dielectric layer and a grid conductive material layer;
the emitter region is formed on the surface of the channel region and is self-aligned with the gate structure;
the emitting region is connected with the emitting electrode through the through hole corresponding to the top;
the gate conductive material layer is connected with the gate through the through hole corresponding to the top.
8. The superjunction IGBT device of claim 7, wherein: the through holes corresponding to the emitting areas also pass through the emitting areas and are in contact with the channel areas; and a channel leading-out region which is heavily doped with the second conduction type is formed at the bottom of the through hole corresponding to the emission region, ohmic contact is formed between the channel leading-out region and the through hole at the top of the channel leading-out region, and the channel region is contacted with the through hole through the channel leading-out region.
9. The superjunction IGBT device of claim 7, wherein: the gate structure adopts a trench gate, the trench gate further comprises a gate trench, the gate dielectric layer is formed on the inner side surface of the gate trench, and the gate conductive material layer fills the gate trench;
the drift region comprises a first top doped region at the bottom of the channel region, the first conductivity type column and the first epitaxial layer;
the gate trench extends longitudinally through the channel region, and sides of the channel region covered by the trench gate sides are used to form a conductive channel connecting the emitter region and the drift region.
10. The superjunction IGBT device of claim 7, wherein: the grid structure adopts a planar grid;
forming a fourth epitaxial layer doped with a first conductive type on top of the superjunction structure, wherein the first top doped region consists of the fourth epitaxial layer, and the channel region is formed in a selected region of the fourth epitaxial layer;
the drift region comprises a first top doped region at the bottom of the channel region, a fourth epitaxial layer between the channel regions, and a first conductivity type pillar and a first epitaxial layer at the bottom;
the planar gate is formed on the front surface of the channel region and extends to the surface of the drift region, and the surface of the channel region covered by the front surface of the planar gate is used for forming a conductive channel for connecting the emission region and the drift region.
11. The superjunction IGBT device of claim 10 wherein: the step of the superjunction structure is the sum of the width of the first conductivity type pillar and the width of the second conductivity type pillar;
the step of the trench gate is the sum of the width of the gate trench and the pitch of the gate trench;
the step of the trench gate is independent of the step of the superjunction structure, so that the step of the trench gate is smaller than or equal to or larger than the step of the superjunction structure.
12. The superjunction IGBT device of claim 11 wherein: more than one emitter groove is arranged between at least part of the grid grooves;
and a second dielectric layer and an emitter conductive material layer are formed on the inner side surface of the emitter groove, and the emitter conductive material layer is connected with the emitter through the through hole corresponding to the top.
13. The superjunction IGBT device of claim 7, wherein: the facade further comprises: a carrier storage layer of a first conductivity type heavily doped, the carrier storage layer disposed between the channel region and the first top doped region.
14. The superjunction IGBT device of claim 1, wherein: the back structure includes:
a collector region heavily doped with the second conductivity type;
a back metal layer is formed on the back surface of the collector region and a collector is drawn out from the back metal layer.
15. The superjunction IGBT device of claim 14 wherein: the back structure includes:
and the buffer layer is positioned between the top surface of the first epitaxial layer and the top surface of the collector region, the doping concentration of the buffer layer is larger than that of the first epitaxial layer, and the first epitaxial layer is prevented from being completely consumed when the device is reversely biased, so that device punch-through is prevented.
16. The superjunction IGBT device of claim 15, wherein: the buffer layer is formed on the back surface of the first epitaxial layer by back surface ion implantation, and the implantation energy of the back surface ion implantation of the buffer layer is 100 keV-2 MeV with an implantation dose of 1e12cm -2 ～3e13cm -2 。
17. The superjunction IGBT device of claim 15, wherein: the super-junction IGBT device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or the super-junction IGBT device is a P-type device, the first conduction type is P-type, and the second conduction type is N-type.
CN202311578709.5A 2023-11-24 2023-11-24 Super-junction IGBT device Pending CN117577671A (en)

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