CN117577550A - Method and device for analyzing defect of semiconductor device, readable medium and electronic equipment - Google Patents
Method and device for analyzing defect of semiconductor device, readable medium and electronic equipment Download PDFInfo
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Abstract
The embodiment of the application provides a defect analysis method and device of a semiconductor device, a readable medium and electronic equipment. The defect analysis method comprises the following steps: obtaining a plurality of defect scanning results obtained by scanning the semiconductor device through a plurality of scanning sizes by a defect scanning program, wherein one scanning size corresponds to one defect scanning result; acquiring regions of the semiconductor device, which are scanned by the defect scanning program through the plurality of scanning sizes, so as to obtain scanning regions corresponding to the scanning sizes; according to the scanning areas corresponding to the scanning sizes, calculating overlapped scanning areas corresponding to the scanning sizes; and carrying out defect source analysis on the semiconductor device according to the defect data respectively located in the overlapped scanning areas in the defect scanning results. The technical scheme of the embodiment of the application can accurately position the defect position in the semiconductor device, and effectively improves the accuracy of defect analysis of the semiconductor device.
Description
Technical Field
The present invention relates to the field of semiconductor chip technologies, and in particular, to a method and apparatus for analyzing defects of a semiconductor device, a readable medium, and an electronic device.
Background
The performance of semiconductor devices, which are the core of modern electronic devices, directly affects the efficiency and stability of the electronic device. However, various factors may cause defects in the device from the manufacturing process of the semiconductor device to the operation process thereof, and the defects may originate from problems of materials, environments, processes and the like in the manufacturing process, or aging, overload and the like in the operation process. Therefore, the detection and identification of defects of a semiconductor device are key to improving the performance and reliability of the device, and the defect source analysis (Defect Source Analysis, abbreviated as DSA) is a method for detecting and analyzing defects in the semiconductor device, and the source and formation mechanism of the defects can be deeply known through the DSA, so that corresponding measures are taken to improve the performance and reliability of the device.
However, the DSA scheme proposed in the related art cannot accurately analyze the newly added defects in the semiconductor device, affecting the accuracy of defect analysis of the semiconductor device.
Disclosure of Invention
The embodiment of the application provides a defect analysis method and device for a semiconductor device, a readable medium and electronic equipment, which can accurately position the defect position in the semiconductor device and effectively improve the accuracy of defect analysis of the semiconductor device.
Other features and advantages of the present application will be apparent from the following detailed description, or may be learned in part by the practice of the application.
According to a first aspect of embodiments of the present application, there is provided a defect analysis method of a semiconductor device, including: obtaining a plurality of defect scanning results obtained by scanning the semiconductor device through a plurality of scanning sizes by a defect scanning program, wherein one scanning size corresponds to one defect scanning result; acquiring regions of the semiconductor device, which are scanned by the defect scanning program through the plurality of scanning sizes, so as to obtain scanning regions corresponding to the scanning sizes; according to the scanning areas corresponding to the scanning sizes, calculating overlapped scanning areas corresponding to the scanning sizes; and carrying out defect source analysis on the semiconductor device according to the defect data respectively located in the overlapped scanning areas in the defect scanning results.
In some embodiments of the present application, based on the foregoing solution, performing defect source analysis on the semiconductor device according to defect data in the overlapping scan areas in the plurality of defect scan results, where the defect source analysis includes: respectively acquiring defect point information in the overlapped scanning area from the defect scanning results; and determining the new situation of the defect points of the plurality of defect scanning results in the overlapped scanning area according to the defect point information in the overlapped scanning area, which is respectively acquired from the plurality of defect scanning results.
In some embodiments of the present application, based on the foregoing solution, determining, according to defect point information in the overlapping scan area obtained from the plurality of defect scan results, a defect point new situation of the plurality of defect scan results in the overlapping scan area includes: and if the number of the overlapped scanning areas corresponding to the plurality of scanning sizes is multiple, determining the defect point newly-increased situation of the plurality of defect scanning results in each overlapped scanning area according to the defect point information in each overlapped scanning area, which is respectively acquired from the plurality of defect scanning results.
In some embodiments of the present application, based on the foregoing aspect, the plurality of scan sizes includes two scan sizes, the plurality of defect scan results includes a first defect scan result corresponding to a first scan size, and a second defect scan result corresponding to a second scan size;
performing defect source analysis on the semiconductor device according to defect data respectively located in the overlapped scanning areas in the defect scanning results, wherein the defect source analysis comprises the following steps: acquiring position information of a first defect point in the overlapped scanning area from the first defect scanning result, and acquiring position information of a second defect point in the overlapped scanning area from the second defect scanning result; comparing the position information of the first defect point with the position information of the second defect point to determine a target defect point which is different from the position information of the first defect point in the second defect point; and comparing the second defect scanning result with the first defect scanning result, and taking the target defect point as a defect point which is newly added in the overlapped scanning area.
In some embodiments of the present application, based on the foregoing solution, obtaining the regions of the semiconductor device scanned by the defect scanning program through the plurality of scanning dimensions, to obtain the scanning regions corresponding to the respective scanning dimensions, includes: and recording the scanned area of the semiconductor device by the defect scanning program when the defect scanning program scans the semiconductor device through each scanning size so as to generate a scanning area corresponding to each scanning size.
In some embodiments of the present application, based on the foregoing solution, obtaining a plurality of defect scan results obtained by scanning a semiconductor device by a defect scan program through a plurality of scan sizes includes: and acquiring a plurality of defect scanning results obtained by scanning the semiconductor device when different pixel sizes are adopted as scanning parameters by a defect scanning program, wherein one pixel size corresponds to one scanning size.
In some embodiments of the present application, based on the foregoing solutions, when the defect scanning program scans the semiconductor device through the plurality of scan sizes, a scanning process corresponding to at least a portion of the scan sizes adopts a scanning manner that does not entirely cover the semiconductor device.
In some embodiments of the present application, based on the foregoing solution, the defect analysis method further includes: and discarding defect data which are not in the overlapped scanning area in the defect scanning results when performing defect source analysis on the semiconductor device.
According to a second aspect of the embodiments of the present application, there is provided a defect analysis apparatus of a semiconductor device, including: an acquisition unit configured to acquire a plurality of defect scan results obtained by scanning the semiconductor device by a plurality of scan sizes, wherein one scan size corresponds to one defect scan result; the defect scanning program is used for obtaining the areas of the semiconductor device, which are scanned by the plurality of scanning sizes, respectively, so as to obtain the scanning areas corresponding to the scanning sizes; a calculating unit configured to calculate overlapping scan areas corresponding to the plurality of scan sizes according to the scan areas corresponding to the respective scan sizes; and the processing unit is configured to analyze the source of the defect of the semiconductor device according to the defect conditions respectively located in the overlapped scanning areas in the defect scanning results.
According to a third aspect of the embodiments of the present application, there is provided a computer readable medium having stored thereon a computer program which, when executed by a processor, implements a defect analysis method of a semiconductor device as described in the above embodiments.
According to a fourth aspect of embodiments of the present application, there is provided an electronic device, including: one or more processors; and storage means for storing one or more computer programs which, when executed by the one or more processors, cause the electronic device to implement the method of defect analysis for a semiconductor device as described in the above embodiments.
According to a fifth aspect of embodiments of the present application, there is provided a computer program product comprising a computer program stored in a computer readable storage medium. The processor of the electronic device reads and executes the computer program from the computer-readable storage medium, so that the electronic device performs the defect analysis method of the semiconductor device provided in the above-described various alternative embodiments.
In some embodiments of the present application, a plurality of defect scan results obtained by scanning a semiconductor device by a defect scan program through a plurality of scan sizes and scan areas corresponding to the respective scan sizes may be obtained, and then, according to the scan areas corresponding to the respective scan sizes, overlapping scan areas corresponding to the plurality of scan sizes are calculated, and further, defect source analysis is performed on the semiconductor device according to defect data in the overlapping scan areas respectively in the plurality of defect scan results. Therefore, in the technical scheme of the embodiment of the application, the scanning area corresponding to the multiple scanning processes of the defect scanning program can be analyzed to determine the overlapped scanning area of the multiple scanning processes, and then the defect data in the overlapped scanning area is compared and analyzed, so that inaccuracy of defect source analysis caused by incomplete scanning areas of the multiple scanning processes can be avoided, further, the defect position in the semiconductor device can be accurately positioned, and the accuracy of defect analysis of the semiconductor device is effectively improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
Fig. 1 shows a schematic diagram of defect source analysis of a semiconductor device;
FIG. 2 shows a schematic diagram of a defect source analysis process;
fig. 3 illustrates a flow chart of a method of defect analysis of a semiconductor device according to one embodiment of the present application;
fig. 4 shows a flowchart of a defect analysis method of a semiconductor device according to an embodiment of the present application;
FIG. 5 illustrates a schematic diagram of a recording process of a scanned area according to one embodiment of the present application;
FIG. 6 is a comparative diagram showing defect source analysis of the technical solution of the embodiment of the present application and the technical solution in the related art;
fig. 7 shows a block diagram of a defect analysis apparatus of a semiconductor device according to an embodiment of the present application;
fig. 8 shows a schematic diagram of a computer system suitable for use in implementing the electronic device of the embodiments of the present application.
Detailed Description
Example embodiments are now described in a more complete manner with reference being made to the figures. However, the illustrated embodiments may be embodied in various forms and should not be construed as limited to only these examples; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art.
Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the present application. However, it will be recognized by one skilled in the art that the present application may be practiced without all of the specific details of the embodiments, that one or more specific details may be omitted, or that other methods, components, devices, steps, etc. may be used.
In the present embodiment, the term "module" or "unit" refers to a computer program or a part of a computer program having a predetermined function, and works together with other relevant parts to achieve a predetermined object, and may be implemented in whole or in part by using software, hardware (such as a processing circuit or a memory), or a combination thereof. Also, a processor (or multiple processors or memories) may be used to implement one or more modules or units. Furthermore, each module or unit may be part of an overall module or unit that incorporates the functionality of the module or unit.
The block diagrams depicted in the figures are merely functional entities and do not necessarily correspond to physically separate entities. That is, the functional entities may be implemented in software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.
The flow diagrams depicted in the figures are exemplary only, and do not necessarily include all of the elements and operations/steps, nor must they be performed in the order described. For example, some operations/steps may be decomposed, and some operations/steps may be combined or partially combined, so that the order of actual execution may be changed according to actual situations.
It should be noted that: references herein to "a plurality" means two or more. "and/or" describes an association relationship of an association object, meaning that there may be three relationships, e.g., a and/or B may represent: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.
The technical solution of the embodiments of the present application mainly relates to defect analysis of a semiconductor device, and in particular, to performing defect source analysis (i.e., DSA) on the semiconductor device, when performing defect source analysis on the semiconductor device, a defect scanning program (flip) is required to scan the semiconductor device, and then comparing and analyzing the results of multiple scans.
When a defect scanning program is used to perform a defect scan on a semiconductor device, the size (i.e., the scan size, specifically, the height of the scan) of one scan of the defect scanning program is determined by the pixel size (i.e., pixel size) set in the defect scanning program. And in order to increase the scanning speed, the defect scanning procedure may adopt a sampling mode with a scanning coverage of 50% (i.e. 50% COV), i.e. only 50% of the area is scanned in one scanning process. In this case, if the pixel sizes used in the two scanning processes of the defect scanning procedure are different, the actual scanning areas (i.e., scan size) are also different, and thus when DSA is used to analyze the newly added defect (i.e., the adder defect), the DSA analysis result is inaccurate due to inconsistent coverage of the two scanning processes.
Specifically, for example, in the DSA analysis process shown in fig. 1, in step 1, the semiconductor device is scanned in a manner of 90nm pixel size and 50% scan coverage, so that the regions a and B of the semiconductor device are scanned, and the regions C and D skip the scanning process. In the step 2, the semiconductor device is scanned in a mode of 45nm pixel size and 50% scanning coverage, so that the area A and the area C of the semiconductor device are scanned, and the area B and the area D skip the scanning process.
In the related art, when DSA analysis is performed on the scene shown in fig. 1, the defect point data obtained by the scanning in step 2 is directly used to compare with the defect point data obtained by the scanning in step 1, so as to determine whether there is a new defect point. However, this method is not accurate, because the scan data of the region C is not scanned in the step 1, the scan data of the region B is not scanned in the step 2, and the scan data of the region B is not scanned in the step 2, so if the defect point data obtained by the scan in the step 2 is directly used to compare with the defect point data obtained by the scan in the step 1, the accuracy of DSA analysis is low due to the difference of the scan regions.
In a specific example, as shown in fig. 2, it is assumed that after the scanning performed in step 1, 2 defect points are found in the area a, no defect point is found in the area B, and the scanning process is skipped for the areas C and D; after the scanning in step 2, 2 defect points are found in the area a, and these two defect points are the same as those found in the area a in step 1, while one defect point is found in the area C, and the scanning process is skipped for the areas B and D. Then if, according to the scheme in the related art, step 2 is a new 1 defect point (i.e., a defect point in the area C) compared to step 1, but in practice, step 1 is not performed on the area C, the scan data of step 1 for the area C is missing, so if it is directly determined that the conclusion that the defect point in the area C in step 2 is the new defect point is inaccurate, the accuracy of performing defect analysis on the semiconductor device is affected.
Based on the problems existing in the related art, the technical scheme of the embodiment of the application provides a new defect analysis scheme of the semiconductor device, wherein the scanning area corresponding to the multiple scanning processes of the defect scanning program can be analyzed to determine the overlapped scanning area of the multiple scanning processes, and then the defect data in the overlapped scanning area is compared and analyzed, so that inaccuracy of defect source analysis caused by incomplete scanning areas of the multiple scanning processes can be avoided, further, the defect position in the semiconductor device can be accurately positioned, and the accuracy of defect analysis on the semiconductor device is improved.
The implementation details of the technical solutions of the embodiments of the present application are described in detail below:
fig. 3 illustrates a flow chart of a method of defect analysis of a semiconductor device according to one embodiment of the present application, which may be performed by an electronic device, which may be an electronic device running a defect scanning program. Referring to fig. 3, the defect analysis method of the semiconductor device at least includes steps S310 to S330, and is described in detail as follows:
in step S310, a plurality of defect scan results obtained by scanning the semiconductor device by the defect scan program through a plurality of scan sizes, wherein one scan size corresponds to one defect scan result; and acquiring the regions of the semiconductor device, which are scanned respectively by the defect scanning program through a plurality of scanning sizes, so as to obtain the scanning regions corresponding to the scanning sizes.
It should be noted that, the semiconductor device in the embodiments of the present application may be a product chip, and generally, the product chip refers to a chip product formed by different types of integrated circuits or a single type of integrated circuit, and the chip product after being packaged may be used in various electronic devices, such as a computer, a mobile phone, a television, and so on. Product pieces can be divided into two major categories, analog chips and digital chips. The analog chip is a chip for processing analog signals, and is commonly provided with an integrated operational amplifier, a digital-to-analog converter, a multiplier, an integrated voltage stabilizer, a timer, a signal generator, a comparator and the like. Digital chips are chips that process digital signals and can be classified into general-purpose digital ICs (Integrated Circuit, integrated circuits) and application-specific digital ICs. The general digital IC refers to circuits such as memories, micro-elements (e.g., microprocessors, microcontrollers, digital processors, etc.), logic circuits (e.g., gate arrays, display drivers, etc.), which are widely used and standard. An application specific digital IC refers to a circuit designed for a particular user, specific or special purpose.
Alternatively, the semiconductor device in the embodiments of the present application may be a wafer, which is a wafer used for manufacturing a silicon semiconductor, and various circuit element structures may be manufactured on the wafer, so as to be an integrated circuit product with a specific function. The semiconductor device may also be a die (i.e., die), which is a small piece cut from a wafer with a laser, that is, a die before the chip has not been packaged. Or may be other types of semiconductor devices.
In the embodiment of the present application, the defect scanning program scans the semiconductor device by setting the scanning parameters, for example, different pixel sizes may be set for the defect scanning program, and then the defect scanning program scans the semiconductor device by adopting the corresponding scanning size (specifically, the scanning height) according to the set pixel size, that is, the pixel size set for the defect scanning program affects the scanning size of the defect scanning program.
In some alternative embodiments, the semiconductor device may be scanned using a defect scanning program with different scanning dimensions (i.e., different pixel sizes for the defect scanning program), and then each scanning dimension may result in a single defect scan result, so that the defect scanning program may obtain multiple defect scan results for scanning the semiconductor device with multiple scanning dimensions. Optionally, the defect scanning result may include information such as shape, size, location, number, etc. of the defect points.
In some alternative embodiments, when the defect scanning program scans the semiconductor device through a plurality of scanning sizes, at least a part of scanning processes corresponding to the scanning sizes adopt a scanning mode of non-total coverage, so that the scanning speed of the defect scanning program can be increased. Wherein, the scanning process corresponding to at least part of the scanning size adopts a scanning mode which is not fully covered, which means that a part of the scanning process adopts a scanning mode which is not fully covered, or all the scanning processes adopt a scanning mode which is fully covered. For example, if the defect scanning program scans the semiconductor device with 2 scan sizes, then a non-full coverage scanning scheme may be used when scanning the semiconductor device with these 2 scan sizes, or a non-full coverage scanning scheme may be used when scanning the semiconductor device with 1 scan size.
It should be noted that, the scanning mode of non-complete coverage refers to that one scanning process of the defect scanning procedure does not completely cover the set scanning size, i.e. one scanning process covers only a partial area of the set scanning size. For example, if the scanning mode of the non-total coverage is the 50% scanning coverage mode, only 50% of the area (the area is the area size indicated by the set scanning size) is scanned in one scanning process.
In some alternative embodiments, when the defect scanning program scans the semiconductor device through each scanning size, the area scanned by the defect scanning program may be recorded to obtain a scanning area corresponding to each scanning size. For example, when the defect scanning program scans a semiconductor device by one scanning size, if the actual scanning area is the area a and the area B, the scanning area corresponding to the scanning size may be recorded as the area a and the area B.
It can be seen that, in step S310 shown in fig. 3, after the semiconductor device is scanned by the defect scanning program through a plurality of scanning sizes, a defect scanning result corresponding to each scanning size may be obtained, and a scanning area corresponding to each scanning size may also be obtained, so that defect data (such as the number of defect points, defect point position information, etc.) included in the scanning area corresponding to each scanning size may be obtained according to the defect scanning result.
With continued reference to fig. 3, in step S320, overlapping scan areas corresponding to a plurality of scan sizes are calculated from the scan areas corresponding to the respective scan sizes.
In some alternative embodiments, according to the scan areas corresponding to the respective scan sizes, the overlapping scan areas corresponding to the plurality of scan sizes are calculated, that is, the areas commonly scanned during the process of finding the defect scanning program to scan the semiconductor device through the plurality of scan sizes. For example, the region scanned by the defect scanning program when scanning the semiconductor device by scanning the size 1 (i.e., the scanning region corresponding to the scanning size 1) is the region a and the region B; the region scanned by the defect scanning program when the semiconductor device is scanned by the scanning size 2 (i.e. the scanning region corresponding to the scanning size 2) is the region a and the region C, and then the overlapping scanning region corresponding to the scanning size 1 and the scanning size 2 is the region a.
In step S330, a defect source analysis is performed on the semiconductor device according to the defect data in the overlapping scan region among the plurality of defect scan results.
In some alternative embodiments, the process of performing defect source analysis on the semiconductor device may be to obtain defect point information (such as the number of defect points, position information of the defect points, etc.) in the overlapping scan area from the plurality of defect scan results, and then determine the defect point new situation of the plurality of defect scan results in the overlapping scan area according to the defect point information in the overlapping scan area obtained from the plurality of defect scan results.
For example, continuing with the above example, assuming that the scan area corresponding to scan size 1 is area a and area B, when the defect scanning program scans the semiconductor device by scan size 1, 2 defect points are found in area a, and no defect point is found in area B; when the scanning area corresponding to the scanning size 2 is the area a and the area C, and the defect scanning program scans the semiconductor device by the scanning size 2, 3 defect points are found in the area a (2 defect points among the 3 defect points are the same as the defect points found in the area a by the scanning size 1), and 2 defect points are found in the area C, since the overlapping scanning area corresponding to the scanning size 1 and the scanning size 2 is the area a, it can be determined that 1 defect point is newly added in the area a compared with the scanning size 1 when the defect scanning program scans the semiconductor device by the scanning size 2.
Alternatively, in performing defect source analysis on the semiconductor device, defect data that is not within the overlapping scan area among the plurality of defect scan results may be discarded. For example, in the above example, when the defect scanning program scans the semiconductor device by the scanning size 1, the area C is not scanned, and when the defect scanning program scans the semiconductor device by the scanning size 2, the area B is not scanned, so that the defect data in the area B obtained by scanning the semiconductor device by the defect scanning program by the scanning size 1 can be discarded, and the defect data in the area C obtained by scanning the semiconductor device by the defect scanning program by the scanning size 2 can be discarded, so that the problem that the conclusion of the newly added defect point is inaccurate due to the analysis of the defect data in different scanning areas in the multiple scanning processes can be avoided. Note that discarding defect data that is not in the overlapping scan area in the plurality of defect scan results means that the defect source analysis is performed without using the defect data.
In some optional embodiments, if the number of overlapping scan areas corresponding to the plurality of scan sizes is multiple, then the defect point newly-increased situation of the plurality of defect scan results in each overlapping scan area may be determined according to defect point information in each overlapping scan area, which is acquired from the plurality of defect scan results, so that accuracy of defect source analysis may be ensured.
For example, when the scanning area corresponding to the scanning size 1 is an area a, an area B, an area C, and an area D, and the defect scanning program scans the semiconductor device by the scanning size 1, 2 defect points are found in the area a, no defect point is found in the area B, 1 defect point is found in the area C, and 1 defect point is found in the area D; when the scanning area corresponding to the scanning size 2 is the area a, the area C and the area E, and when the defect scanning program scans the semiconductor device by the scanning size 2, 3 defect points are found in the area a (2 defect points among the 3 defect points are the same as the defect points found by the scanning size 1, for example, the position information of 2 defect points among the 3 defect points is the same as the position information of the defect points found by the scanning size 1 in the area a), 3 defect points are found in the area C (1 defect point among the 3 defect points is the same as the defect point found by the scanning size 1 in the area C, for example, the position information of 1 defect point among the 3 defect points is the same as the position information of the defect point found by the scanning size 1 in the area C), and no defect point is found in the area E, then since the overlapping scanning areas corresponding to the scanning size 1 and the scanning size 2 are the area a and the area C, that is, a plurality of overlapping scanning areas exist, then the defect source analysis is performed for the area a and the area C, respectively, that is, when the defect scanning is performed by the scanning size 2, the defect point is increased by the new defect point in the area a compared with the new defect point in the scanning area C by the scanning size 1 compared with the new defect point found by the scanning size 1 in the area C.
In a specific application scenario of the present application, the defect scanning procedure may scan the semiconductor device through 2 scan sizes, and then the obtained defect scanning result includes a first defect scanning result corresponding to the first scan size and a second defect scanning result corresponding to the second scan size. In this case, the process of performing defect source analysis on the semiconductor device may be: acquiring position information of a first defect point in an overlapped scanning area from a first defect scanning result, acquiring position information of a second defect point in the overlapped scanning area from a second defect scanning result, comparing the position information of the first defect point with the position information of the second defect point to determine a target defect point which is different from the position information of the first defect point in the second defect point, and comparing the target defect point with the first defect scanning result as a second defect scanning result to newly increase the defect points in the overlapped scanning area.
For example, when the scanning area corresponding to the first scanning size is an area a, an area B, and an area C, and the defect scanning program scans the semiconductor device by the first scanning size, 2 defect points are found in the area a, no defect point is found in the area B, and 2 defect points are found in the area C; the scanning areas corresponding to the second scanning size are an area A, an area C and an area E, when the defect scanning program scans the semiconductor device through the second scanning size, 3 defect points are found in the area A, 1 defect point is found in the area C, and no defect point is found in the area E. Since the overlapping scanning areas corresponding to the first scanning size and the second scanning size are the area a and the area C, if the position information of 1 defect point among the 3 defect points found in the area a by the second scanning size is not the same as the position information of the defect point found in the area a by the first scanning size, it is indicated that one defect point is newly found in the area a by the second scanning size, that is, it is possible to determine that the number of defect points newly added in the overlapping scanning area a is 1 compared with the first defect scanning result by the second defect scanning result; if the position information of 1 defect point found in the area C by the second scan size is the same as the position information of a certain defect point found in the area C by the first scan size, it is explained that no new defect point is found in the area C by the second scan size, i.e., it is possible to determine that the second defect scan result has no new defect point in the overlapped scan area C compared to the first defect scan result.
In the above embodiment of the present application, if the position information of the 3 defect points found in the area a by the second scanning size is different from the position information of the defect points found in the area a by the first scanning size, it is explained that the 3 defect points are newly found in the area a by the second scanning size, and therefore it is possible to determine that the number of defect points newly added in the overlapped scanning area a is 3 as compared with the first defect scanning result. That is, in the embodiment of the present application, it is determined whether a defect point is newly added in the same overlapping scanning area, mainly depending on the position information of the defect point scanned by the multiple scanning processes, and thus it is determined whether a defect point not scanned by the previous scanning process is found in the subsequent scanning process.
Meanwhile, it should be noted that in the above embodiment of the present application, the defect points are considered to be the same defect points when the position information of the defect points are the same, and in other embodiments of the present application, the determination may be performed according to more attribute information of the defect points, for example, whether the defect points are the same defect points may be determined according to the position information and the shape information of the defect points, that is, the position information and the shape information of the defect points scanned by the multiple scanning processes are the same, and then the defect points are considered to be the same defect points.
Therefore, the technical scheme of the embodiment of the application mainly records the scanned area when the defect scanning program scans the semiconductor device, further analyzes the scanning area corresponding to the multiple scanning processes of the defect scanning program to determine the overlapped scanning area of the multiple scanning processes, and then performs contrast analysis on the defect data in the overlapped scanning area, so that inaccuracy of defect source analysis caused by incomplete scanning areas of the multiple scanning processes can be avoided, and further the defect position in the semiconductor device can be accurately positioned.
Taking a defect scanning program to scan a semiconductor device by 2 scan sizes as an example, implementation details of the technical scheme in the embodiment of the application will be described again:
as shown in fig. 4, assuming that the defect scanning procedure scans the semiconductor device with different scanning sizes through steps 1 and 2, respectively, a specific defect analysis method may include:
s401, recording the scanning area when the defect scanning program scans the semiconductor device through step 1, and then, after the scanning is completed, maintaining the defect scanning result in the database. Optionally, the defect scanning result may include information such as the shape, size, location (e.g. the scanning area, etc.) and number of the defect points.
S402, when the defect scanning program scans the semiconductor device through step 2, the scanning area is recorded, and then after the scanning is completed, the defect scanning result is held in the database. Similarly, the defect scanning result may also include information such as the shape, size, location (e.g., the scanning area, etc.), number, etc. of the defect points.
S403, when DSA analysis is performed based on the defect scan results of step 1 and step 2, it is necessary to use the result of processing the data of the scan area. The processing of the data of the scan area is to find the overlapping scan area in the step 1 and the step 2, so as to exclude the influence of the non-overlapping area, and further, when DSA analysis (for example, performing overlay analysis on the defect scan results in the step 1 and the step 2 through analysis software) is performed, the defect point condition in the overlapping scan area can be accurately analyzed.
In some alternative embodiments, the process of recording the scan area may be as shown in fig. 5, where recording data corresponding to Layer1 is used to represent scan area information (i.e., information obtained by scanning respective die in the semiconductor device) of the step 1 for scanning the semiconductor device, and recording data corresponding to Layer2 is used to represent scan area information of the step 2 for scanning the semiconductor device. These recorded data are formed into a file (e.g. a KLARF file, which is a text format for storing the results) and then stored in a database, from which the DSA analysis is performed, to obtain the scanning areas of step 1 and step 2.
Specifically, as shown in fig. 6, when the semiconductor device is scanned in the pixel size of 90nm and the scanning coverage of 50%, the area a (assuming that 4 defect points are scanned) and the area B (assuming that 4 defect points are scanned) of the semiconductor device are scanned, and the area C and the area D skip the scanning process. In the step 2, the semiconductor device is scanned in a manner that the pixel size is 45nm and the scanning coverage is 50%, then the area a of the semiconductor device (assuming that 13 defect points are scanned, and the position information of 4 defect points is the same as the position information of 4 defect points scanned in the area a in the step 1, that is, 4 defect points in the 13 defect points scanned in the area a in the step 2 are consistent with the defect points scanned in the area a in the step 1) and the area C (assuming that 5 defect points are scanned) are scanned, and the scanning process is skipped in the areas B and D.
In this case, in the DSA analysis, the related art directly uses the defect point obtained by the scan in step 2 to compare with the defect point obtained by the scan in step 1 to determine whether there are new defect points, that is, step 2 is newly increased by 9 (13-4 more regions a) +5 (5-0 more regions C) =14 defect points compared with step 1. However, this method is not accurate, because the region C is not scanned in the step 1, and the scan data of the region C in the step 1 is missing, so if the defect point data obtained by the step 2 scan is directly used to compare with the defect point data obtained by the step 1 scan, the accuracy of DSA analysis is low due to the difference of the scan regions.
In the technical solution of the embodiment of the present application, the areas scanned in the step 1 and the step 2 are analyzed first to determine the area (i.e. the overlapping scanning area) scanned in the step 1 and the step 2 together, that is, the area a, and the data of the area not overlapping scanning area are discarded without DSA analysis, so after the technical solution of the embodiment of the present application is adopted, 9 defect points are newly added in the step 2 compared with the step 1 (i.e. 13-4 defect data in the area a are newly added and defect data in the area C are discarded).
In summary, the technical scheme of the embodiment of the application can analyze the scanning area corresponding to the multiple scanning processes of the defect scanning program to determine the overlapping scanning area of the multiple scanning processes, so that the defect data in the overlapping scanning area can be compared and analyzed, and the accuracy of defect analysis of the semiconductor device is improved.
The following describes an apparatus embodiment of the present application that may be used to perform the defect analysis method of the semiconductor device in the above-described embodiments of the present application. For details not disclosed in the embodiments of the apparatus of the present application, please refer to the embodiments of the defect analysis method of the semiconductor device described in the present application.
Fig. 7 shows a block diagram of a defect analysis apparatus of a semiconductor device according to an embodiment of the present application.
Referring to fig. 7, a defect analysis apparatus 700 of a semiconductor device according to an embodiment of the present application includes: an acquisition unit 702, a calculation unit 704 and a processing unit 706.
Wherein the obtaining unit 702 is configured to obtain a plurality of defect scan results obtained by scanning the semiconductor device by a defect scanning program through a plurality of scan sizes, wherein one scan size corresponds to one defect scan result; the defect scanning program is used for obtaining the areas of the semiconductor device, which are scanned by the plurality of scanning sizes, respectively, so as to obtain the scanning areas corresponding to the scanning sizes; the calculating unit 704 is configured to calculate overlapping scan areas corresponding to the plurality of scan sizes according to the scan areas corresponding to the respective scan sizes; the processing unit 706 is configured to perform defect source analysis on the semiconductor device according to defect situations in the overlapping scan areas respectively in the plurality of defect scan results.
In some embodiments of the present application, based on the foregoing scheme, the processing unit 706 is configured to: respectively acquiring defect point information in the overlapped scanning area from the defect scanning results; and determining the new situation of the defect points of the plurality of defect scanning results in the overlapped scanning area according to the defect point information in the overlapped scanning area, which is respectively acquired from the plurality of defect scanning results.
In some embodiments of the present application, based on the foregoing scheme, the processing unit 706 is configured to: and if the number of the overlapped scanning areas corresponding to the plurality of scanning sizes is multiple, determining the defect point newly-increased situation of the plurality of defect scanning results in each overlapped scanning area according to the defect point information in each overlapped scanning area, which is respectively acquired from the plurality of defect scanning results.
In some embodiments of the present application, based on the foregoing aspect, the plurality of scan sizes includes two scan sizes, the plurality of defect scan results includes a first defect scan result corresponding to a first scan size, and a second defect scan result corresponding to a second scan size;
the processing unit 706 is configured to: acquiring position information of a first defect point in the overlapped scanning area from the first defect scanning result, and acquiring position information of a second defect point in the overlapped scanning area from the second defect scanning result; comparing the position information of the first defect point with the position information of the second defect point to determine a target defect point which is different from the position information of the first defect point in the second defect point; and comparing the second defect scanning result with the first defect scanning result, and taking the target defect point as a defect point which is newly added in the overlapped scanning area.
In some embodiments of the present application, based on the foregoing scheme, the obtaining unit 702 is configured to: and recording the scanned area of the semiconductor device by the defect scanning program when the defect scanning program scans the semiconductor device through each scanning size so as to generate a scanning area corresponding to each scanning size.
In some embodiments of the present application, based on the foregoing scheme, the obtaining unit 702 is configured to: and acquiring a plurality of defect scanning results obtained by scanning the semiconductor device when different pixel sizes are adopted as scanning parameters by a defect scanning program, wherein one pixel size corresponds to one scanning size.
In some embodiments of the present application, based on the foregoing solutions, when the defect scanning program scans the semiconductor device through the plurality of scan sizes, a scanning process corresponding to at least a portion of the scan sizes adopts a scanning manner that does not entirely cover the semiconductor device.
In some embodiments of the present application, based on the foregoing scheme, the processing unit 706 is further configured to: and discarding defect data which are not in the overlapped scanning area in the defect scanning results when performing defect source analysis on the semiconductor device.
Fig. 8 shows a schematic diagram of a computer system suitable for implementing an electronic device according to an embodiment of the present application, which may be the electronic device for performing the defect analysis method for a semiconductor device in the foregoing embodiment.
It should be noted that, the computer system 800 of the electronic device shown in fig. 8 is only an example, and should not impose any limitation on the functions and the application scope of the embodiments of the present application.
As shown in fig. 8, the computer system 800 may include a central processing unit (Central Processing Unit, CPU) 801 that may perform various appropriate actions and processes according to a program stored in a Read-Only Memory (ROM) 802 or a program loaded from a storage section 808 into a random access Memory (Random Access Memory, RAM) 803, for example, performing the methods described in the above embodiments. In the RAM 803, various programs and data required for system operation are also stored. The CPU 801, ROM 802, and RAM 803 are connected to each other by a bus 804. An Input/Output (I/O) interface 805 is also connected to bus 804.
The following components may be connected to the I/O interface 805: an input portion 806 including a keyboard, mouse, etc.; an output portion 807 including a Cathode Ray Tube (CRT), a liquid crystal display (Liquid Crystal Display, LCD), and the like, and a speaker, and the like; a storage section 808 including a hard disk or the like; and a communication section 809 including a network interface card such as a LAN (Local Area Network ) card, modem, or the like. The communication section 809 performs communication processing via a network such as the internet. The drive 810 is also connected to the I/O interface 805 as needed. A removable medium 811 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is mounted on the drive 810 as needed so that a computer program read out therefrom is mounted into the storage section 808 as needed.
In particular, according to embodiments of the present application, the processes described above with reference to flowcharts may be implemented as computer software programs. For example, embodiments of the present application include a computer program product comprising a computer program embodied on a computer readable medium for performing the method shown in the flowchart. In such an embodiment, the computer program may be downloaded and installed from a network via the communication section 809, and/or installed from the removable media 811. When executed by a Central Processing Unit (CPU) 801, the computer program performs the various functions defined in the system of the present application.
It should be noted that, the computer readable medium shown in the embodiments of the present application may be a computer readable signal medium or a computer readable storage medium, or any combination of the two. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-Only Memory (ROM), an erasable programmable read-Only Memory (Erasable Programmable Read Only Memory, EPROM), flash Memory, an optical fiber, a portable compact disc read-Only Memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. In the present application, however, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, with a computer-readable computer program embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. A computer program embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wired, etc., or any suitable combination of the foregoing.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present application. Where each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams or flowchart illustration, and combinations of blocks in the block diagrams or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer programs.
The units involved in the embodiments of the present application may be implemented by means of software, or may be implemented by means of hardware, and the described units may also be provided in a processor. Wherein the names of the units do not constitute a limitation of the units themselves in some cases.
As another aspect, the present application also provides a computer-readable medium that may be contained in the electronic device described in the above embodiment; or may exist alone without being incorporated into the electronic device. The computer readable medium carries one or more computer programs which, when executed by the electronic device, cause the electronic device to implement the methods described in the above embodiments.
It should be noted that although in the above detailed description several modules or units of a device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functions of two or more modules or units described above may be embodied in one module or unit, in accordance with embodiments of the present application. Conversely, the features and functions of one module or unit described above may be further divided into a plurality of modules or units to be embodied.
From the above description of embodiments, those skilled in the art will readily appreciate that the example embodiments described herein may be implemented in software, or may be implemented in software in combination with the necessary hardware. Thus, the technical solution according to the embodiments of the present application may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (which may be a CD-ROM, a usb disk, a mobile hard disk, etc.) or on a network, comprising several instructions to cause an electronic device to perform the method according to the embodiments of the present application.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the embodiments disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains.
It is to be understood that the present application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.
Claims (11)
1. A defect analysis method of a semiconductor device, comprising:
obtaining a plurality of defect scanning results obtained by scanning the semiconductor device through a plurality of scanning sizes by a defect scanning program, wherein one scanning size corresponds to one defect scanning result;
acquiring regions of the semiconductor device, which are scanned by the defect scanning program through the plurality of scanning sizes, so as to obtain scanning regions corresponding to the scanning sizes;
according to the scanning areas corresponding to the scanning sizes, calculating overlapped scanning areas corresponding to the scanning sizes;
And carrying out defect source analysis on the semiconductor device according to the defect data respectively located in the overlapped scanning areas in the defect scanning results.
2. The defect analysis method of the semiconductor device according to claim 1, wherein performing defect source analysis on the semiconductor device based on defect data in the overlapping scan areas, respectively, among the plurality of defect scan results, comprises:
respectively acquiring defect point information in the overlapped scanning area from the defect scanning results;
and determining the new situation of the defect points of the plurality of defect scanning results in the overlapped scanning area according to the defect point information in the overlapped scanning area, which is respectively acquired from the plurality of defect scanning results.
3. The defect analysis method of the semiconductor device according to claim 2, wherein determining a defect point newly added condition of the plurality of defect scan results in the overlapping scan area based on defect point information in the overlapping scan area acquired from the plurality of defect scan results, respectively, comprises:
and if the number of the overlapped scanning areas corresponding to the plurality of scanning sizes is multiple, determining the defect point newly-increased situation of the plurality of defect scanning results in each overlapped scanning area according to the defect point information in each overlapped scanning area, which is respectively acquired from the plurality of defect scanning results.
4. The defect analysis method of the semiconductor device according to claim 1, wherein the plurality of scan sizes includes two scan sizes, the plurality of defect scan results includes a first defect scan result corresponding to a first scan size, and a second defect scan result corresponding to a second scan size;
performing defect source analysis on the semiconductor device according to defect data respectively located in the overlapped scanning areas in the defect scanning results, wherein the defect source analysis comprises the following steps:
acquiring position information of a first defect point in the overlapped scanning area from the first defect scanning result, and acquiring position information of a second defect point in the overlapped scanning area from the second defect scanning result;
comparing the position information of the first defect point with the position information of the second defect point to determine a target defect point which is different from the position information of the first defect point in the second defect point;
and comparing the second defect scanning result with the first defect scanning result, and taking the target defect point as a defect point which is newly added in the overlapped scanning area.
5. The method according to claim 1, wherein acquiring the regions of the semiconductor device scanned by the defect scanning program through the plurality of scanning dimensions, respectively, to obtain the scanned regions corresponding to the respective scanning dimensions, comprises:
and recording the scanned area of the semiconductor device by the defect scanning program when the defect scanning program scans the semiconductor device through each scanning size so as to generate a scanning area corresponding to each scanning size.
6. The method of analyzing defects of a semiconductor device according to claim 1, wherein obtaining a plurality of defect scan results obtained by scanning the semiconductor device through a plurality of scan sizes by a defect scan program, comprises:
and acquiring a plurality of defect scanning results obtained by scanning the semiconductor device when different pixel sizes are adopted as scanning parameters by a defect scanning program, wherein one pixel size corresponds to one scanning size.
7. The method according to any one of claims 1 to 6, wherein the defect scanning program is configured such that, when the semiconductor device is scanned by the plurality of scanning dimensions, at least a part of scanning processes corresponding to the scanning dimensions adopt a scanning method that does not entirely cover the semiconductor device.
8. The defect analysis method of the semiconductor device according to any one of claims 1 to 6, characterized in that the defect analysis method further comprises:
and discarding defect data which are not in the overlapped scanning area in the defect scanning results when performing defect source analysis on the semiconductor device.
9. A defect analysis apparatus of a semiconductor device, comprising:
an acquisition unit configured to acquire a plurality of defect scan results obtained by scanning the semiconductor device by a plurality of scan sizes, wherein one scan size corresponds to one defect scan result; the defect scanning program is used for obtaining the areas of the semiconductor device, which are scanned by the plurality of scanning sizes, respectively, so as to obtain the scanning areas corresponding to the scanning sizes;
a calculating unit configured to calculate overlapping scan areas corresponding to the plurality of scan sizes according to the scan areas corresponding to the respective scan sizes;
and the processing unit is configured to analyze the source of the defect of the semiconductor device according to the defect conditions respectively located in the overlapped scanning areas in the defect scanning results.
10. A computer readable medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the method of defect analysis of a semiconductor device according to any one of claims 1 to 8.
11. An electronic device, comprising:
one or more processors;
a memory for storing one or more computer programs that, when executed by the one or more processors, cause the electronic device to implement the method of defect analysis of a semiconductor device of any of claims 1-8.
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