CN117577165A - Self-checking processing method and device and resistive random access memory - Google Patents
Self-checking processing method and device and resistive random access memory Download PDFInfo
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Abstract
The invention provides a self-checking processing method and device and a resistance random access memory, and relates to the technical field of data processing. The method comprises the following steps: decomposing the self-checking parameters based on the redundant remainder system and the target system number to obtain a decomposition result; programming the decomposition result onto a resistive memory array; obtaining a calculation result obtained by the operation of the resistance random access memory array; and checking the calculation result to determine whether the operation of the resistance change memory array has errors. The method solves the problem that the error rate of the calculation result of the current resistance random access memory is high.
Description
Technical Field
The present invention relates to the field of data processing technologies, and in particular, to a self-checking processing method and apparatus, and a resistive random access memory.
Background
The computation and storage in existing von neumann architecture computers are separate, done by a Central Processing Unit (CPU) and memory, respectively. In the past, the clock frequency and performance of the processor develop rapidly, and the access speed of the memory is improved more slowly, so that a memory wall and a power consumption wall are formed between the clock frequency and the performance of the processor, and the improvement of the system computing power and energy efficiency is severely restricted. The memory-computing integrated architecture is expected to solve the problem, and the core idea is to transfer part or all of computation to storage, complete the operation by using a storage unit, and the extremely close approach greatly reduces the delay and the power consumption of data movement and solves the problem of a storage wall.
The resistive random access memory is a novel nonvolatile memory, and has important prospect in the aspect of realizing an integrated system for high-energy-efficiency memory because of the advantages of simple structure, low power consumption, good size contractibility, high memory access speed and the like. However, the resistive random access memory stores data by modulating the resistance value, and the resistance value cannot be precisely controlled because of the working mechanism of the conductive filament. In addition, resistive random access memories have a relaxation effect, and their resistance values drift over time over a small range. In summary, the error rate of the calculation result obtained by the integrated system based on the resistive random access memory is generally high.
Disclosure of Invention
The invention aims to provide a self-checking processing method, a self-checking processing device and a resistance random access memory, so as to solve the problem of high error rate of a calculation result.
To achieve the above object, an embodiment of the present invention provides a self-checking processing method, including:
decomposing the self-checking parameters based on the redundant remainder system and the target system number to obtain a decomposition result;
programming the decomposition result onto a resistive memory array;
obtaining a calculation result obtained by the operation of the resistance random access memory array;
and checking the calculation result to determine whether the operation of the resistance change memory array has errors.
Optionally, the decomposing the self-checking parameter based on the redundant remainder system and the target number system includes:
determining a remainder base used by the redundant remainder system according to the calculated magnitude of the target number;
determining a redundancy base according to the target error rate of the resistance random access memory array;
and determining the target number according to the resistance states which can be represented by the resistance change memory units in the resistance change memory array.
Optionally, the decomposing the self-checking parameter based on the redundant remainder system and the target number to obtain a decomposition result includes:
decomposing the self-checking parameter according to the remainder base and the redundancy base to obtain a target component of the self-checking parameter; wherein the target component includes a remainder component and a redundancy component;
and decomposing the target component according to the target system number to obtain the decomposition result.
Optionally, after the decomposition result is programmed, mapping sequentially based on different target bases in a first direction of the resistive random access memory array, and mapping sequentially based on high and low bits expanded by a system in a second direction of the resistive random access memory array; the target groups include a remainder group and a redundancy group.
Optionally, the verifying the calculation result, determining whether the operation of the resistive random access memory array has an error includes:
accumulating the calculation result according to the target system number to obtain first check information;
obtaining second check information according to the target base and the first check information;
and comparing the result of the second check information for the redundancy basic modulus with the first check information to determine whether the operation of the resistance random access memory array has errors.
Optionally, the accumulating the calculation result according to the target number to obtain first check information includes:
by the formula y i ＝y i [0]·n 0 +y i [1]·n 1 + …, calculate y i The method comprises the steps of carrying out a first treatment on the surface of the Wherein y is i Representing first check information corresponding to the ith target base, n represents the target number, y i [0]Representing the first calculation result, y, corresponding to the ith target base i [1]Representing a second calculation result corresponding to the target base i; the target base comprises a residual base and a redundant base; i is an integer greater than or equal to 1.
Optionally, the obtaining second verification information according to the target base and the first verification information includes:
by the formula y= (Σy) i ·M i ·[(M i ) -1 mod m i ])mod(∏m i ) Calculating second verification information y; wherein M is i ＝(∏m i )/m i ，m i Representing the i-th target group.
Optionally, the comparing the result of the second parity check on the redundancy base modulus with the first parity check information determines whether an operation of the resistive random access memory array has an error, including:
by checking the formula y mod m i ＝y i And p+1 is less than or equal to i and less than or equal to q, determining that no error exists in the operation of the resistive random access memory array when the check formula is established, and determining that the error exists in the operation of the resistive random access memory array when the check formula is not established;
where p is equal to the number of remainder groups and q is equal to Yu Shuji and the total number of redundancy groups.
To achieve the above object, an embodiment of the present invention provides a self-test processing apparatus, including:
the first processing module is used for decomposing the self-checking parameters based on the redundant remainder system and the target system number to obtain a decomposition result;
a second processing module for programming the decomposition result onto a resistive memory array;
the third processing module is used for obtaining a calculation result obtained by the operation of the resistance random access memory array;
and the first determining module is used for checking the calculation result and determining whether the operation of the resistance random access memory array has errors.
Optionally, the apparatus further comprises:
the second determining module is used for determining a remainder base used by the redundant remainder system according to the calculation magnitude of the target number;
the third determining module is used for determining a redundancy base according to the target error rate of the resistance random access memory array;
and the fourth determining module is used for determining the target number according to the resistance states which can be represented by the resistance change memory units in the resistance change memory array.
Optionally, the first processing module includes:
the first processing unit is used for decomposing the self-checking parameters according to the remainder base and the redundancy base to obtain target components of the self-checking parameters; wherein the target component includes a remainder component and a redundancy component;
and the second processing unit is used for decomposing the target component according to the target system number to obtain the decomposition result.
Optionally, after the decomposition result is programmed, mapping sequentially based on different target bases in a first direction of the resistive random access memory array, and mapping sequentially based on high and low bits expanded by a system in a second direction of the resistive random access memory array; the target groups include a remainder group and a redundancy group.
Optionally, the first determining module includes:
the third processing unit is used for accumulating the calculation result according to the target system number to obtain first check information;
the fourth processing unit is used for obtaining second verification information according to the target base and the first verification information;
and the determining unit is used for comparing the result of the second check information on the redundancy basic modulus with the first check information and determining whether the operation of the resistance random access memory array has errors.
Optionally, the third processing unit is further configured to:
by the formula y i ＝y i [0]·n 0 +y i [1]·n 1 + …, calculate y i The method comprises the steps of carrying out a first treatment on the surface of the Wherein y is i Representing first check information corresponding to the ith target base, n represents the target number, y i [0]Representing the first calculation result, y, corresponding to the ith target base i [1]Representing a second calculation result corresponding to the target base i; the target base comprises a residual base and a redundant base; i is an integer greater than or equal to 1.
Optionally, the fourth processing unit is further configured to:
by the formula y= (Σy) i ·M i ·[(M i ) -1 mod m i ])mod(∏m i ) Calculating second verification information y; wherein M is i ＝(∏m i )/m i ，m i Representing the i-th target group.
Optionally, the determining unit is further configured to:
by checking the formula y mod m i ＝y i And p+1 is less than or equal to i and less than or equal to q, determining that no error exists in the operation of the resistive random access memory array when the check formula is established, and determining that the error exists in the operation of the resistive random access memory array when the check formula is not established;
where p is equal to the number of remainder groups and q is equal to Yu Shuji and the total number of redundancy groups.
To achieve the above object, an embodiment of the present invention provides a resistance change memory device, including a transceiver, a processor, a memory, and a program or instructions stored on the memory and executable on the processor; according to the instructions transmitted by the transceiver, the processor executes the program or the instructions to realize the self-checking processing method.
To achieve the above object, an embodiment of the present invention provides a readable storage medium having stored thereon a program or instructions which, when executed by a processor, implement the steps in the self-checking processing method as described above.
The technical scheme of the invention has the following beneficial effects:
according to the method provided by the embodiment of the invention, the self-checking parameters can be decomposed based on the redundant remainder system and the target number, after a decomposition result is obtained, the decomposition result is programmed on the resistive random access memory array, then the calculation result obtained through the resistive random access memory array operation is obtained, and the calculation result is checked to determine whether the resistive random access memory array operation has errors or not, so that the errors are corrected in time, and the error rate of the self-calculation result is reduced.
Drawings
FIG. 1 is a flow chart of a self-checking processing method according to an embodiment of the invention;
FIG. 2 is an exploded view of RRNS;
FIG. 3 is a diagram of a mapping of decomposition results;
FIG. 4 is a schematic diagram of the sequence of operations performed in the calculation of a resistive memory array;
FIG. 5 is a diagram of the target error rate and the total calculated error rate;
FIG. 6 is a block diagram of an apparatus module according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a resistive memory device according to an embodiment of the present invention.
Detailed Description
In order to make the technical problems, technical solutions and advantages to be solved more apparent, the following detailed description will be given with reference to the accompanying drawings and specific embodiments.
It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
In various embodiments of the present invention, it should be understood that the sequence numbers of the following processes do not mean the order of execution, and the order of execution of the processes should be determined by the functions and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.
In addition, the terms "system" and "network" are often used interchangeably herein.
In the examples provided herein, it should be understood that "B corresponding to a" means that B is associated with a from which B may be determined. It should also be understood that determining B from a does not mean determining B from a alone, but may also determine B from a and/or other information.
For ease of understanding, some of the matters related to the embodiments of the present application are described below:
in a computationally integrated system, the input signal is multiplied by a storage weight equal to the output signal, where the weights are mapped in a storage array. In most application scenarios, the required weights, inputs and outputs are relatively large numbers, but the conductance states that a resistive memory cell can distinguish between are limited, i.e. the number that a cell can store is limited, and for representing and calculating larger numbers, a number needs to be represented by multiple memory cells. The mapping schemes of the current weight are two, one is expanded according to a binary system, for example, the range of the original number is 0-7, the original number is 6, and the mapping scheme is expanded according to the binary system to 110; the second is to spread by number, and the same is to spread by 0111111 for number 6.
However, for the binary expansion method, the weight of each bit after expansion according to the binary is different, namely, the high bit weight is large, and the low bit weight is small, if the calculation result corresponding to the high bit has a small error, the calculation result of the low bit is completely submerged, so the calculation accuracy according to the binary expansion method is low, and the error is large. For the number-wise expansion method, the weight of each bit is as small as possible, so any one-bit calculation error only has a small influence on the overall calculation accuracy, but if the operand is large, the number of bits after the number expansion is too large, for example, for numbers in the range of 0 to 1000, if one device has four conductivity states, 334 bits after expansion (if the number is only 5 bits according to the binary expansion method), so large array requirements are unacceptable and have no expansion.
As shown in fig. 2, the self-checking processing method in the embodiment of the invention includes:
step 201, decomposing the self-checking parameters based on the redundant remainder system and the target number to obtain a decomposition result;
step 202, programming the decomposition result to a resistive random access memory array;
step 203, obtaining a calculation result obtained by the operation of the resistive random access memory array;
and 204, checking the calculation result to determine whether the operation of the resistive random access memory array has errors.
Thus, the resistive random access memory applying the method of the embodiment of the present invention, according to the steps 201 to 204, can decompose the self-checking parameter based on the redundancy remainder system and the target number, obtain the decomposition result, program the decomposition result on the resistive random access memory array, then verify the calculation result by obtaining the calculation result obtained by the operation of the resistive random access memory array, and determine whether the operation of the resistive random access memory array has errors, thereby correcting the errors in time, and reducing the error rate of the self-calculation result.
It should be appreciated that in this embodiment, a self-test process according to steps 201-204 described above is performed on the target number (i.e., the number to be calculated). That is, the calculation of the target number by the resistive random access memory array is accompanied by a self-check, and if it is determined that there is an error in the operation of the resistive random access memory array, it is considered that the operation of the resistive random access memory array corresponding to the target number is also an error, and the calculation of the target number by the resistive random access memory array and a new self-check can be performed again until it is determined that there is no error in the operation of the resistive random access memory array.
The remainder system (Residue Number System, RNS) is a non-weighted digital representation system, the RNS represents the original number by using the remainder of the data, and each remainder component can be completely independently operated when multiplication, addition and the like are operated, so that the traditional multi-digit complex operation can be realized by a plurality of parallel simple operations with fewer digits, and the high parallelism can greatly improve the calculation speed.
The redundant remainder system (Redundant Residue Number System, RRNS) makes each component independent and redundant by introducing redundant remainder base into the remainder system, when partial remainder components have errors, the errors cannot be spread among the components, and at the moment, correct operation results can be obtained through the redundancy relation among the remainder components and a certain error correction algorithm, namely the system has the self-checking and self-correcting capabilities.
Therefore, in the method of the embodiment of the invention, before the self-checking parameters are decomposed based on the redundant remainder system and the target number to obtain the decomposition result, the remainder base and the redundant base used by the redundant remainder system need to be determined. Of course, to perform step 101, the target number is also determined.
Optionally, the decomposing the self-checking parameter based on the redundant remainder system and the target number system includes:
determining a remainder base used by the redundant remainder system according to the calculated magnitude of the target number;
determining a redundancy base according to the target error rate of the resistance random access memory array;
and determining the target number according to the resistance states which can be represented by the resistance change memory units in the resistance change memory array.
That is, for the number to be calculated accompanying the self-test, determining a remainder base used by the redundant remainder system according to the calculation order; determining a redundancy base according to the target error rate of the resistive random access memory array; and determining the target number according to the resistance states which can be represented by the resistance change memory units in the resistance change memory array.
Here, the calculation orders may be divided in advance, for example, 0 to 1000 are one calculation order, and 1001 to 10000 are one calculation order. Of course, the partitioning may also be based on other means.
As one embodiment, the redundant remainder system is provided with remainder bases for use with different computational magnitudes. Therefore, after the calculation magnitude based on the target number, the applicable residual number base can be directly found through setting.
As one embodiment, the redundancy remainder system is provided with redundancy groups that differ in target error rates for the resistive memory array. And selecting a proper number and a proper size of redundant bases according to the target error rate of the resistive random access memory array. The selection mode can be random, large to small, small to large, etc. Here, the target error rate may be understood as the maximum error rate allowed after the operation of the resistive memory array.
As one embodiment, the different resistance states that can be represented by the resistive memory cells in the resistive memory array are provided with corresponding binary numbers. Therefore, based on the resistance states that can be represented by the resistive memory cells in the resistive memory array, the applicable resistance states can be directly found by setting.
After determining the applicable remainder, redundancy, and target decimal number, step 101 includes:
decomposing the self-checking parameter according to the remainder base and the redundancy base to obtain a target component of the self-checking parameter;
and decomposing the target component according to the target system number to obtain the decomposition result.
In this embodiment, p remainder bases used by the redundant remainder system can be denoted as m 1 ～m p (q-p) redundancy groups are denoted as m p+1 ～m q The target number is noted as k.
For the self-checking parameter x, the target component obtained by RRNS decomposition is marked as (x 1 |x 2 |…|x q ) RNS(m1|m2|…|mq) The method comprises the steps of carrying out a first treatment on the surface of the Wherein x is 1 To correspond to m 1 Component x of (2) 2 To correspond to m 2 Component (…), x q To correspond to m q Is a component of (a). The target component is spread in k scale, and the decomposition result can be expressed as (x 1 [0]，x 1 [1]…|x 2 [0]，x 2 [1]…|…|x q [0]，x q [1]…) RNS(m1|m2|…|mq) . The method comprises the steps of carrying out a first treatment on the surface of the Wherein x is 1 [0]，x 1 [1]… is corresponding to x 1 Is a result of the expansion of (a); x is x 2 [0]，x 2 [1]… is corresponding to x 2 Is a result of the expansion of (a); x is x q [0]，x q [1]… is corresponding to x q Is a result of the expansion of (a).
For example, the self-test parameter x=64, 4 remainder bases m 1 ＝8、m 2 ＝7、m 3 ＝5、m 4 =3, 1 redundancy group m 5 =11, the target number is binary (k=2), and as shown in fig. 2, 64 is taken as a decomposition source number, and is decomposed by RRNS, and is expressed as 0, 1, 4, 1, 9 in RRNS, so as to obtain a target component: 0. 1, 4, 1, 9, wherein 0, 1, 4, 1 are remainder components and 9 are redundant components. And expanding each target component according to binary system to obtain a decomposition result 0000 0011 0001 1001, wherein the total number of the target components is 16, and the last four bits are redundant bits. Here, the target component 0 is a component of the remainder base 8, the target component 1 is a component of the remainder base 7, the target component 4 is a component of the remainder base 5, the target component 1 is a component of the remainder base 3, and the target component 9 is a component of the remainder base 11. Of the 16-bit decomposition results, 0000 is the expansion result of the target component 0, 001 is the expansion result of the target component 1, 100 is the expansion result of the target component 4, 01 is the expansion result of the target component 1, and 1001 is the expansion result of the target component 9.
Optionally, after the decomposition result is programmed, mapping sequentially based on different target bases in a first direction of the resistive random access memory array, and mapping sequentially based on high and low bits expanded by a system in a second direction of the resistive random access memory array; the target groups include a remainder group and a redundancy group.
Here, the first direction and the second direction of the resistive memory array are different directions. Taking a rectangular resistive random access memory array as an example, assuming that the first direction is a column direction and the second direction is a row direction, the resulting decomposition result is mapped to the position of the resistive random access memory array (RRAM array) as shown in fig. 3. Wherein an expansion component of the target components corresponding to a target base can be expressed as a matrix D, such as x 1 [0]. The operation sequence in the calculation is shown in FIG. 4, in which the picture is drawnThe shaded part is the current open operation array, the matrix array corresponding to different RNS components is required to be opened in a time-sharing way, and all columns can be read simultaneously so as to complete multiply-add operation on different remainder components.
In this embodiment, all matrices D may be regarded as weight matrices.
Thus, the calculation result obtained by the operation of the resistive random access memory array can be recorded as y 1 [0]，y 1 [1]…，y q [0]，y q [1]…。
Optionally, the verifying the calculation result, determining whether the operation of the resistive random access memory array has an error includes:
accumulating the calculation result according to the target system number to obtain first check information;
obtaining second check information according to the target base and the first check information;
and comparing the result of the second check information for the redundancy basic modulus with the first check information to determine whether the operation of the resistance random access memory array has errors.
Optionally, the accumulating the calculation result according to the target number to obtain first check information includes:
by the formula y i ＝y i [0]·n 0 +y i [1]·n 1 + …, calculate y i The method comprises the steps of carrying out a first treatment on the surface of the Wherein y is i Representing first check information corresponding to the ith target base, n represents the target number, y i [0]Representing the first calculation result, y, corresponding to the ith target base i [1]Representing a second calculation result corresponding to the target base i; i is an integer greater than or equal to 1.
Where i is less than or equal to q, which is equal to Yu Shuji and the total number of redundancy groups. The remainder base and the redundancy base are used for redundancy remainder system decomposition.
Optionally, the obtaining second verification information according to the target base and the first verification information includes:
by the formula y= (Σy) i ·M i ·[(M i ) -1 mod m i ])mod(∏m i ) Calculating second verification information y; wherein M is i ＝(∏m i )/m i ，m i Representing the i-th target group.
Optionally, the comparing the result of the second parity check on the redundancy base modulus with the first parity check information determines whether an operation of the resistive random access memory array has an error, including:
by checking the formula y mod m i ＝y i And p+1 is less than or equal to i and less than or equal to q, determining that no error exists in the operation of the resistive random access memory array when the check formula is established, and determining that the error exists in the operation of the resistive random access memory array when the check formula is not established;
where p is equal to the number of remainder groups and q is equal to Yu Shuji and the total number of redundancy groups.
In this way, the method of the embodiment of the invention adds up the calculation results of the resistive random access memory array according to the system and calculates y by using the target base, and then determines whether the operation of the resistive random access memory array has errors or not by checking whether the formula is established, thus completing the self-checking.
If the current calculation error is detected, the calculation is performed again, and the total calculation error rate of the self-checking method and the self-checking-free calculation error rate of the method in the embodiment of the invention under the same target error rate is compared in fig. 5, wherein the redundancy bases are 11 and 13, and the total calculation error rate after the self-checking of the method in the embodiment of the invention can be reduced by two orders of magnitude.
In summary, in the method of the embodiment of the present invention, RRNS decomposition is performed on the self-checking parameters and the self-checking parameters are expanded according to the system, and the redundancy base may be used to perform self-checking. The method can ensure that the high calculation accuracy is maintained while the expansion bit number is smaller, so that the large operand operation based on the integral calculation of the resistance random access memory is possible. Furthermore, RRNS-based mapping schemes have high parallelism, require fewer input pulses, have shorter computation times, and improve significantly for larger operands than traditional binary-based mapping schemes.
As shown in fig. 6, an embodiment of the present application provides a self-checking processing device, including:
a first processing module 610, configured to decompose the self-checking parameter based on the redundant remainder system and the target number, to obtain a decomposition result;
a second processing module 620 for programming the decomposition result onto a resistive memory array;
a third processing module 630, configured to obtain a calculation result obtained by the resistive random access memory array operation;
the first determining module 640 is configured to verify the calculation result, and determine whether an operation of the resistive random access memory array has an error.
Optionally, the apparatus further comprises:
the second determining module is used for determining a remainder base used by the redundant remainder system according to the calculation magnitude of the target number;
the third determining module is used for determining a redundancy base according to the target error rate of the resistance random access memory array;
and the fourth determining module is used for determining the target number according to the resistance states which can be represented by the resistance change memory units in the resistance change memory array.
Optionally, the first processing module includes:
the first processing unit is used for decomposing the self-checking parameters according to the remainder base and the redundancy base to obtain target components of the self-checking parameters; wherein the target component includes a remainder component and a redundancy component;
and the second processing unit is used for decomposing the target component according to the target system number to obtain the decomposition result.
Optionally, after the decomposition result is programmed, mapping sequentially based on different target bases in a first direction of the resistive random access memory array, and mapping sequentially based on high and low bits expanded by a system in a second direction of the resistive random access memory array; the target groups include a remainder group and a redundancy group.
Optionally, the first determining module includes:
the third processing unit is used for accumulating the calculation result according to the target system number to obtain first check information;
the fourth processing unit is used for obtaining second verification information according to the target base and the first verification information;
and the determining unit is used for comparing the result of the second check information on the redundancy basic modulus with the first check information and determining whether the operation of the resistance random access memory array has errors.
Optionally, the third processing unit is further configured to:
by the formula y i ＝y i [0]·n 0 +y i [1]·n 1 + …, calculate y i The method comprises the steps of carrying out a first treatment on the surface of the Wherein y is i Representing first check information corresponding to the ith target base, n represents the target number, y i [0]Representing the first calculation result, y, corresponding to the ith target base i [1]Representing a second calculation result corresponding to the target base i; the target base comprises a residual base and a redundant base; i is an integer greater than or equal to 1.
Optionally, the fourth processing unit is further configured to:
by the formula y= (Σy) i ·M i ·[(M i ) -1 mod m i ])mod(∏m i ) Calculating second verification information y; wherein M is i ＝(∏m i )/m i ，m i Representing the i-th target group.
Optionally, the determining unit is further configured to:
by checking the formula y mod m i ＝y i And p+1 is less than or equal to i and less than or equal to q, determining that no error exists in the operation of the resistive random access memory array when the check formula is established, and determining that the error exists in the operation of the resistive random access memory array when the check formula is not established;
where p is equal to the number of remainder groups and q is equal to Yu Shuji and the total number of redundancy groups.
The device of the embodiment can decompose the self-checking parameters based on the redundant remainder system and the target number, program the decomposition result on the resistive random access memory array after obtaining the decomposition result, and then verify the calculation result by obtaining the calculation result obtained by the resistive random access memory array operation to determine whether the operation of the resistive random access memory array has errors or not, thereby correcting the errors in time so as to reduce the error rate of the self-calculation result.
The device is a device applying the method, and the implementation mode of the embodiment of the method is suitable for the device and can achieve the same technical effect.
A resistive random access memory device according to an embodiment of the present invention, as shown in fig. 7, includes a transceiver 710, a processor 700, a memory 720, and a program or instructions stored on the memory 720 and executable on the processor 700; the processor 700 implements the self-test processing method described above when executing the program or instructions.
The transceiver 710 is configured to receive and transmit data under the control of the processor 700.
Wherein in fig. 7, a bus architecture may comprise any number of interconnected buses and bridges, and in particular one or more processors represented by processor 700 and various circuits of memory represented by memory 720, linked together. The bus architecture may also link together various other circuits such as peripheral devices, voltage regulators, power management circuits, etc., which are well known in the art and, therefore, will not be described further herein. The bus interface provides an interface. The transceiver 710 may be a number of elements, i.e. comprising a transmitter and a receiver, providing a unit for communicating with various other apparatus over a transmission medium.
The processor 700 is responsible for managing the bus architecture and general processing, and the memory 720 may store data used by the processor 700 in performing operations.
The readable storage medium of the embodiment of the present invention stores a program or an instruction, which when executed by a processor, implements the steps in the self-checking processing method described above, and can achieve the same technical effects, and is not repeated here.
The processor is a processor in the external network incoming controller described in the above embodiment. The readable storage medium includes a computer readable storage medium such as a Read-Only Memory (ROM), a random access Memory (Random Access Memory RAM), a magnetic disk or an optical disk.
It is further noted that many of the functional units described in this specification have been referred to as modules, in order to more particularly emphasize their implementation independence.
In an embodiment of the invention, the modules may be implemented in software for execution by various types of processors. An identified module of executable code may, for instance, comprise one or more physical or logical blocks of computer instructions which may, for instance, be organized as an object, procedure, or function. Nevertheless, the executables of an identified module need not be physically located together, but may comprise disparate instructions stored in different bits which, when joined logically together, comprise the module and achieve the stated purpose for the module.
Indeed, a module of executable code may be a single instruction, or many instructions, and may even be distributed over several different code segments, among different programs, and across several memory devices. Likewise, operational data may be identified within modules and may be embodied in any suitable form and organized within any suitable type of data structure. The operational data may be collected as a single data set, or may be distributed over different locations including over different storage devices.
Where a module may be implemented in software, taking into account the level of existing hardware technology, a module may be implemented in software, and one skilled in the art may, without regard to cost, build corresponding hardware circuitry, including conventional Very Large Scale Integration (VLSI) circuits or gate arrays, and existing semiconductors such as logic chips, transistors, or other discrete components, to achieve the corresponding functions. A module may also be implemented in programmable hardware devices such as field programmable gate arrays, programmable array logic, programmable logic devices or the like.
The exemplary embodiments described above are described with reference to the drawings, many different forms and embodiments are possible without departing from the spirit and teachings of the present invention, and therefore, the present invention should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will convey the scope of the invention to those skilled in the art. In the drawings, the size of the elements and relative sizes may be exaggerated for clarity. The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Unless otherwise indicated, a range of values includes the upper and lower limits of the range and any subranges therebetween.
While the foregoing is directed to the preferred embodiments of the present invention, it will be appreciated by those skilled in the art that various modifications and adaptations can be made without departing from the principles of the present invention, and such modifications and adaptations are intended to be comprehended within the scope of the present invention.
Claims (18)
1. A self-test processing method, comprising:
decomposing the self-checking parameters based on the redundant remainder system and the target system number to obtain a decomposition result;
programming the decomposition result onto a resistive memory array;
obtaining a calculation result obtained by the operation of the resistance random access memory array;
and checking the calculation result to determine whether the operation of the resistance change memory array has errors.
2. The method of claim 1, wherein the decomposing the self-test parameter based on the redundant remainder system and the target number comprises, before obtaining the decomposition result:
determining a remainder base used by the redundant remainder system according to the calculated magnitude of the target number;
determining a redundancy base according to the target error rate of the resistance random access memory array;
and determining the target number according to the resistance states which can be represented by the resistance change memory units in the resistance change memory array.
3. The method of claim 2, wherein the decomposing the self-test parameter based on the redundant remainder system and the target number to obtain a decomposition result comprises:
decomposing the self-checking parameter according to the remainder base and the redundancy base to obtain a target component of the self-checking parameter; wherein the target component includes a remainder component and a redundancy component;
and decomposing the target component according to the target system number to obtain the decomposition result.
4. The method of claim 1, wherein the decomposition results are programmed to map sequentially based on different target bases in a first direction of the resistive memory array and to map sequentially based on binary expansion of high and low bits in a second direction of the resistive memory array; the target groups include a remainder group and a redundancy group.
5. The method of claim 2, wherein verifying the calculation results to determine whether an operation of the resistive memory array is erroneous comprises:
accumulating the calculation result according to the target system number to obtain first check information;
obtaining second check information according to the target base and the first check information;
and comparing the result of the second check information for the redundancy basic modulus with the first check information to determine whether the operation of the resistance random access memory array has errors.
6. The method of claim 5, wherein accumulating the calculation result according to the target number to obtain the first check information includes:
by the formula y i ＝y i [0]·n 0 +y i [1]·n 1 + …, calculate y i The method comprises the steps of carrying out a first treatment on the surface of the Wherein y is i Representing first check information corresponding to the ith target base, n represents the target number, y i [0]Representing the first calculation result, y, corresponding to the ith target base i [1]Representing a second calculation result corresponding to the target base i; i is an integer greater than or equal to 1.
7. The method of claim 6, wherein the obtaining second verification information based on the target base and the first verification information comprises:
by the formula y= (Σy) i ·M i ·[(M i ) -1 mod m i ])mod(∏m i ) Calculating second verification information y; wherein M is i ＝(∏m i )/m i ，m i Representing the i-th target group.
8. The method of claim 7, wherein comparing the result of the second parity check against the redundancy base modulus with the first parity check information determines whether an operation of the resistive memory array is erroneous, comprising:
by checking the formula y mod m i ＝y i And p+1 is less than or equal to i is less than or equal to q, when the checking formula is established, determining that the operation of the resistive random access memory array has no error,determining that an operation of the resistive random access memory array is in error when the check formula is not established;
where p is equal to the number of remainder groups and q is equal to Yu Shuji and the total number of redundancy groups.
9. A self-test processing device, comprising:
the first processing module is used for decomposing the self-checking parameters based on the redundant remainder system and the target system number to obtain a decomposition result;
a second processing module for programming the decomposition result onto a resistive memory array;
the third processing module is used for obtaining a calculation result obtained by the operation of the resistance random access memory array;
and the first determining module is used for checking the calculation result and determining whether the operation of the resistance random access memory array has errors.
10. The apparatus as recited in claim 9, further comprising:
the second determining module is used for determining a remainder base used by the redundant remainder system according to the calculation magnitude of the target number;
the third determining module is used for determining a redundancy base according to the target error rate of the resistance random access memory array;
and the fourth determining module is used for determining the target number according to the resistance states which can be represented by the resistance change memory units in the resistance change memory array.
11. The apparatus of claim 10, wherein the first processing module comprises:
the first processing unit is used for decomposing the self-checking parameters according to the remainder base and the redundancy base to obtain target components of the self-checking parameters; wherein the target component includes a remainder component and a redundancy component;
and the second processing unit is used for decomposing the target component according to the target system number to obtain the decomposition result.
12. The apparatus of claim 9, wherein the decomposition results, after being programmed, are mapped sequentially based on different target bases in a first direction of the resistive memory array and mapped sequentially based on binary expansion of high and low bits in a second direction of the resistive memory array; the target groups include a remainder group and a redundancy group.
13. The apparatus of claim 10, wherein the first determining module comprises:
the third processing unit is used for accumulating the calculation result according to the target system number to obtain first check information;
the fourth processing unit is used for obtaining second verification information according to the target base and the first verification information;
and the determining unit is used for comparing the result of the second check information on the redundancy basic modulus with the first check information and determining whether the operation of the resistance random access memory array has errors.
14. The apparatus of claim 13, wherein the third processing unit is further configured to:
by the formula y i ＝y i [0]·n 0 +y i [1]·n 1 + …, calculate y i The method comprises the steps of carrying out a first treatment on the surface of the Wherein y is i Representing first check information corresponding to the ith target base, n represents the target number, y i [0]Representing the first calculation result, y, corresponding to the ith target base i [1]Representing a second calculation result corresponding to the target base i; the target base comprises a residual base and a redundant base; i is an integer greater than or equal to 1.
15. The apparatus of claim 14, wherein the fourth processing unit is further configured to:
by the formula y= (Σy) i ·M i ·[(M i ) -1 mod m i ])mod(∏m i ) Calculating second verification information y; wherein M is i ＝(∏m i )/m i ，m i Representing the i-th target group.
16. The apparatus of claim 15, wherein the determining unit is further configured to:
by checking the formula y mod m i ＝y i And p+1 is less than or equal to i and less than or equal to q, determining that no error exists in the operation of the resistive random access memory array when the check formula is established, and determining that the error exists in the operation of the resistive random access memory array when the check formula is not established;
where p is equal to the number of remainder groups and q is equal to Yu Shuji and the total number of redundancy groups.
17. A resistive random access memory comprising: a transceiver, a processor, a memory, and a program or instructions stored on the memory and executable on the processor; a self-test processing method according to any one of claims 1-8, wherein said processor, when executing said program or instructions, is implemented in accordance with instructions delivered by said transceiver.
18. A readable storage medium having stored thereon a program or instructions which when executed by a processor performs the steps in the self-test processing method according to any of claims 1-8.
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