CN117573556A - Software assertion verification method, system and equipment based on incremental SMT problem solving - Google Patents
Software assertion verification method, system and equipment based on incremental SMT problem solving Download PDFInfo
- Publication number
- CN117573556A CN117573556A CN202311656869.7A CN202311656869A CN117573556A CN 117573556 A CN117573556 A CN 117573556A CN 202311656869 A CN202311656869 A CN 202311656869A CN 117573556 A CN117573556 A CN 117573556A
- Authority
- CN
- China
- Prior art keywords
- bit vector
- target
- smt
- variable
- solving
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 71
- 238000012795 verification Methods 0.000 title claims abstract description 44
- 238000004422 calculation algorithm Methods 0.000 claims abstract description 34
- 230000014509 gene expression Effects 0.000 claims abstract description 31
- 238000004590 computer program Methods 0.000 claims description 17
- 230000008569 process Effects 0.000 claims description 17
- 238000006243 chemical reaction Methods 0.000 claims description 12
- 238000012545 processing Methods 0.000 claims description 6
- 230000003068 static effect Effects 0.000 claims description 5
- 238000009825 accumulation Methods 0.000 abstract description 3
- 238000005516 engineering process Methods 0.000 description 8
- 230000008901 benefit Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000009795 derivation Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000012217 deletion Methods 0.000 description 1
- 230000037430 deletion Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 238000009472 formulation Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000007781 pre-processing Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000001131 transforming effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/3668—Software testing
- G06F11/3672—Test management
- G06F11/3688—Test management for test execution, e.g. scheduling of test suites
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
Abstract
The invention provides a software assertion verification method, a system and equipment based on incremental SMT problem solving, wherein the method comprises the following steps: converting assertion to be verified in the software source code into a bit vector SMT formula; selecting a basic bit vector SMT formula, and dividing incremental expression parts of other bit vector SMT formulas relative to the basic bit vector SMT formula into multiple layers of contexts; converting a bit vector SMT formula to be solved into a CNF conjunctive normal form; pre-solving the CNF conjunctive normal form, and recording variable labels included in clauses belonging to a target context, wherein the target context is the context of an increment part of the target bit vector SMT formula compared with the bit vector SMT formula solved last time; if the pre-solving fails, deleting clauses containing corresponding variable labels; and solving the CNF conjunctive normal form by adopting a complete SAT solving algorithm. The invention can avoid redundant information generated in the information accumulation process and effectively improve the efficiency of the software assertion verification system.
Description
Technical Field
The invention relates to the technical field of computer software verification, in particular to a software assertion verification method, system and equipment based on incremental SMT problem solving.
Background
In a software verification process, a large number of assertions often need to be verified. These assertions act as key checkpoints in programming to ensure that software is functioning properly and accurately under all conditions. To verify assertions, the software execution path associated with each assertion needs to be encoded into a bit vector SMT formula and then solved using a bit vector SMT solver. However, the solution complexity of the bit vector SMT problem is very high, and when the number of assertions that software needs to verify is large, the limitation of the solution time will be a significant challenge. Since multiple assertions often originate from the same software program, there are typically a large number of shared parts in their SMT formulas, using SMT delta solution techniques is an effective way to improve time efficiency.
However, on the incremental solution problem of the bit vector SMT problem, the SAT solver needs to be called multiple times to get the solution for each query, so the overall solution performance depends on the efficiency of the SAT solution. If the SAT solving efficiency is not high, the incremental solving efficiency of the bit vector SMT problem is greatly affected.
Disclosure of Invention
The present invention has been made in view of the above problems, and is directed to providing a software assertion verification method, system, and apparatus that overcomes or at least partially solves the above problems based on incremental SMT problem solutions.
In one aspect of the invention, a software assertion verification method based on incremental SMT problem solving is provided, the method comprising:
acquiring a software source code to be verified, and converting each code assertion to be verified in the software source code into a corresponding bit vector SMT formula according to a code execution path to obtain a bit vector SMT formula set;
selecting a basic bit vector SMT formula from a bit vector SMT formula set, and dividing incremental expression parts, which are expanded by other bit vector SMT formulas in the bit vector SMT formula set relative to the basic bit vector SMT formula, into multi-layer contexts according to similarity relations among expressions included in each bit vector SMT formula in the bit vector SMT formula set;
carrying out formula simplification on a target bit vector SMT formula to be solved currently, and converting the simplified target bit vector SMT formula into a target CNF conjunctive normal form;
pre-solving a target CNF conjunctive normal form by adopting a preset simplified SAT solving algorithm, and recording variable labels of variables included in clauses belonging to a target context in the target CNF conjunctive normal form in a pre-solving process, wherein the target context is the context of an increment part of a target bit vector SMT formula compared with a bit vector SMT formula solved last time;
if the pre-solving fails, deleting each clause containing the corresponding variable label as a redundant clause according to the variable labels of the variables included in the clauses of the recorded target context;
and solving the target CNF conjunctive normal form by adopting a preset complete SAT solving algorithm.
Optionally, the pre-solving the target CNF conjunctive normal form by using a preset simplified SAT solving algorithm includes:
setting a scope variable l for each layer of context included in the target bit vector SMT formula i Setting a scope variable l for an i-th layer context i In the method, the variable labels of the new variables related to all clauses belonging to the ith layer context in the target CNF conjunctive form are increased by taking the labels of the scope variables corresponding to the ith layer context as references, and each clause c belonging to the ith layer context is converted into l i The method comprises the steps of U < c >, and taking a scope variable corresponding to each layer of context included in a target bit vector SMT formula as an assumption of a solving algorithm;
and pre-solving the converted CNF clauses and hypotheses by adopting a preset simplified SAT solving algorithm.
Optionally, the recording, in the pre-solving process, variable labels of variables included in clauses belonging to the target context in the target CNF conjunctive normal form includes:
identifying each target context included in the target bit vector SMT formula;
when a scope variable is set for the target context, recording the label of the scope variable corresponding to the target context and the maximum value of the variable label of the variable related to each clause belonging to the target context in the target CNF conjunctive normal form;
and adding the label of each target context corresponding to the scope variable and the corresponding maximum value of the label of the variable as a pair of data combinations to a preset redundant variable array.
Optionally, the deleting each clause including the corresponding variable label as a redundant clause according to the variable label of the variable included in the clause of the recorded target context includes:
and for any clause, if the clause comprises a variable of which the variable label belongs to a variable range corresponding to any data combination in the redundant variable array, deleting the clause as a redundant clause.
Optionally, the context corresponding to each scope variable is defined by a preset push statement and pop statement.
Optionally, the method sets a scope variable l for each layer of context included in the target bit vector SMT formula i Comprising the following steps:
setting scope variable array scope_lite= { l 1 ,l 2 ,…,l k Recording a scope variable corresponding to each layer context in the target bit vector SMT formula, wherein k is the layer number of the contexts included in the target bit vector SMT formula, when a push sentence is input, a new scope variable is added to the array, and when a pop sentence is executed, a scope variable corresponding to the push sentence with the nearest gap between the pop sentences is deleted from the scope_lite array.
Optionally, the transforming each code assertion to be verified in the software source code into a corresponding bit vector SMT formula according to the code execution path includes:
and converting the software source code into a static univariate assignment SSA form code, and respectively converting each code assertion to be verified into a corresponding bit vector SMT formula according to a code execution path.
Optionally, the formulating the SMT formula of the target bit vector to be solved includes:
and identifying bit vector operation existing in the bit vector SMT formula, and simplifying the bit vector SMT formula according to operation rules satisfied by the identified various bit vector operations.
In a second aspect, the present invention also provides a software assertion verification system based on incremental SMT problem solving, the system comprising:
the first conversion module is used for acquiring a software source code to be verified, and converting each code assertion to be verified in the software source code into a corresponding bit vector SMT formula according to a code execution path to obtain a bit vector SMT formula set;
the configuration module is used for selecting a basic bit vector SMT formula from the bit vector SMT formula set, and dividing incremental expression parts, which are expanded by other bit vector SMT formulas relative to the basic bit vector SMT formula in the bit vector SMT formula set, into multi-layer contexts according to the similarity relation among expressions included in each bit vector SMT formula in the bit vector SMT formula set;
the second conversion module is used for carrying out formula simplification on the current target bit vector SMT formula to be solved and converting the simplified target bit vector SMT formula into a target CNF conjunctive normal form;
the SAT pre-solving module is used for pre-solving the target CNF conjunctive normal form by adopting a preset simplified SAT solving algorithm, and recording variable labels of variables included in clauses belonging to target contexts in the target CNF conjunctive normal form in a pre-solving process, wherein the target contexts are contexts of increment parts of the target bit vector SMT formula compared with the last solved bit vector SMT formula;
the processing module is used for deleting each clause containing the corresponding variable label as a redundant clause according to the variable label of the variable contained in the clause of the recorded target context when the pre-solving fails;
and the SAT solving module is used for solving the target CNF conjunctive normal form by adopting a preset complete SAT solving algorithm.
In a third aspect, the present invention also provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the software assertion verification method as described above based on incremental SMT problem solution.
In a fourth aspect, the present invention also provides a computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the software assertion verification method based on incremental SMT problem solution as above when executing the computer program.
According to the software assertion verification method, system and equipment based on incremental SMT problem solving, the used bit vector SMT incremental solving technology can effectively utilize the characteristic that a large number of shared expressions exist among bit vector SMT formulas corresponding to all assertions, can effectively use derivation information accumulated by multiple assertion verification, and improves software assertion verification efficiency.
The foregoing description is only an overview of the present invention, and is intended to be implemented in accordance with the teachings of the present invention in order that the same may be more clearly understood and to make the same and other objects, features and advantages of the present invention more readily apparent.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:
FIG. 1 is a schematic diagram of an implementation of a software assertion verification method based on incremental SMT problem solution provided by an embodiment of the present invention;
FIG. 2 is a flowchart of a software assertion verification method based on incremental SMT problem solving provided by an embodiment of the invention;
FIG. 3 is a block diagram of a software assertion verification system that provides incremental SMT problem solution based according to an embodiment of the invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless expressly stated otherwise, as understood by those skilled in the art. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be understood by those skilled in the art that all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs unless defined otherwise. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Assertion (Assertion): an assertion is a program instruction that accepts a condition as a parameter. If the condition calculation is false, it will report an error and terminate the procedure. Assertions are often used to describe certain properties that a program needs to satisfy. Assertion verification (Assertion Checking): assertion verification means proving that the condition of the assertion is true for all inputs. SAT is a satisfiability problem, which refers to determining whether a set of variables are assigned to be satisfied for any propositional logic formula. SMT can satisfy the modulus theory, and the satisfaction judgment problem of the predicate logic formula of explaining the finger function and the relation symbol in the background theory. A Bit vector (Bit-vector) is a vector composed of boolean variables, and is a compact array data structure for storing bits (bits). The value of each bit may be 0 or 1. The Bit vector satisfaction modulus theory (Bit-vector SMT) is that under the Bit vector background theory, whether a group of variable assignment exists or not is judged to be satisfied by any predicate logic formula.
In software assertion verification systems, there are two main types of existing technologies: (1) Each assertion is solved as an independent bit vector SMT formula. (2) And directly solving by using a bit vector SMT solving technology supporting incremental solving. The first method does not utilize the continuity of the bit vector SMT formulas, and each assertion verification needs to recall the SMT solver for solving, so that a serious efficiency problem exists. The second approach uses incremental solution techniques, but is not optimized for the portion of the SAT solution, and therefore takes a long time when a large number of assertions need to be verified.
Aiming at the problems, the invention provides the software assertion verification method based on the incremental SMT problem solving, which can effectively verify accumulated deduction information by using multiple assertions, and avoid redundant information generated in the information accumulation process, thereby effectively improving the efficiency of the software assertion verification system.
Fig. 1 schematically illustrates an implementation schematic diagram of a software assertion verification method based on incremental SMT problem solving according to an embodiment of the present invention. The overall implementation principle of the scheme is shown in fig. 1, a user inputs a software source code to be verified, the system converts each code assertion to be verified in the source code into a static univariate assignment SSA form, further encodes a corresponding bit vector SMT increment formula, then uses an improved increment solving algorithm to carry out increment solving on the bit vector SMT increment formula to obtain a satisfaction solution of each assertion, and finally returns a result whether each assertion passes verification or not.
FIG. 2 schematically illustrates a flow chart of a software assertion verification method based on incremental SMT problem solution according to an embodiment of the invention. Referring to fig. 2, the software assertion verification method based on incremental SMT problem solving according to an embodiment of the present invention specifically includes the following steps:
s11, acquiring a software source code to be verified, and converting each code assertion to be verified in the software source code into a corresponding bit vector SMT formula according to a code execution path to obtain a bit vector SMT formula set.
Specifically, firstly, a software source code to be verified, which is input by a user, is acquired, and code assertion in the software source code is converted into a bit vector SMT formula. In step S11, each code assertion to be verified in the software source code is converted into a corresponding bit vector SMT formula according to the code execution path, which is specifically implemented as follows: and converting the software source code into a static univariate assignment SSA form code, and respectively converting each code assertion to be verified into a corresponding bit vector SMT formula according to a code execution path.
S12, selecting a basic bit vector SMT formula from a bit vector SMT formula set, and dividing incremental expression parts, which are expanded by other bit vector SMT formulas in the bit vector SMT formula set relative to the basic bit vector SMT formula, into multiple layers of contexts according to similarity relations among expressions included in each bit vector SMT formula in the bit vector SMT formula set.
In this embodiment, since multiple assertions often originate from the same software program, there are usually a large number of shared expression portions in the corresponding bit vector SMT formulas, and the present invention selects a simplest bit vector SMT formula as the base bit vector SMT formula, and divides the incremental expression portion of each bit vector SMT formula, which is extended with respect to the base bit vector SMT formula, into multiple layers of contexts. For example, the basic bit vector SMT formula includes N bit vector expressions, and the second bit vector SMT formula includes M other expressions in addition to the N bit vector expressions, and the M expressions are a layer context of the second bit vector SMT formula. For another example, the third bit vector SMT formula includes K other expressions in addition to the N bit vector expressions and the M expressions, where the M expressions are one layer of the third bit vector SMT formula and the K expressions are another layer of the third bit vector SMT formula.
It can be seen that other bit vector SMT formulas in each set of bit vector SMT formulas, except for the base bit vector SMT formulas, can be expressed as a combined expression of the base bit vector SMT formula and at least one layer of context.
S13, carrying out formula simplification on the current target bit vector SMT formula to be solved, and converting the simplified target bit vector SMT formula into a target CNF conjunctive normal form.
Specifically, before solving each satisfaction query (check-SAT) of the obtained bit vector SMT formula, the bit vector formula is preprocessed first, and then the bit vector SMT formula is converted into a SAT formula meeting the CNF paradigm by using tsetin coding.
In one embodiment of the present invention, the implementation manner of performing formula simplification on the current target bit vector SMT formula to be solved in step S13 may be: preprocessing the bit vector SMT formula, and realizing formula simplification by adopting constant propagation, gao Sixiao yuan and other modes.
In another embodiment of the present invention, the implementation manner of performing formula simplification on the current target bit vector SMT formula to be solved in step S13 may further be: and identifying bit vector operation existing in the bit vector SMT formula, and simplifying the bit vector SMT formula according to operation rules satisfied by the identified various bit vector operations.
S14, pre-solving the target CNF conjunctive normal form by adopting a preset simplified SAT solving algorithm, and recording variable labels of variables included in clauses belonging to target contexts in the target CNF conjunctive normal form in a pre-solving process, wherein the target contexts are contexts of increment parts of the target bit vector SMT formula compared with the last solved bit vector SMT formula.
It will be appreciated that it is necessary to record the variable labels that correspond to the SMT expression in the newly added context since the last solution, i.e. the context of the delta portion of the target bitvector SMT formula compared to the last solved bitvector SMT formula.
The technical scheme of the invention further comprises the step of accumulating the solving information of clauses belonging to other contexts except the target context in the target CNF conjunctive normal form, namely accumulating the solving information of a shared expression existing between a target bit vector SMT formula corresponding to the currently solved assertion and a bit vector SMT formula corresponding to the next assertion to be solved, so that the software assertion verification efficiency is improved by accumulating the solving information for the past time.
And S15, if the pre-solving fails, deleting each clause containing the corresponding variable label as a redundant clause according to the variable labels of the variables included in the clauses of the recorded target context.
S16, solving the target CNF conjunctive normal form by adopting a preset complete SAT solving algorithm.
In this embodiment, for the converted CNF formula, SAT pre-solution is first performed. If the pre-solving is successful, namely the pre-solving can determine the satisfaction of the SMT formula of the target bit vector, the algorithm returns a result and enters the next round of satisfaction inquiry so as to solve the SMT formula of the bit vector to be solved. If the pre-solving fails, deleting the redundant clause, avoiding redundant information generated in the information accumulation process, inputting the formula into a complete CDCL SAT solver for solving, returning the result by the algorithm after the solving is successful, and entering the next round of satisfiability query to solve the next bit vector SMT formula to be solved.
According to the software assertion verification method based on incremental SMT problem solving, the bit vector SMT incremental solving technology is used, the characteristic that a large number of shared expressions exist between bit vector SMT formulas corresponding to all assertions can be effectively utilized, accumulated deduction information can be effectively verified through multiple assertions, and software assertion verification efficiency is improved.
In the embodiment of the invention, the target CNF conjunctive normal form is pre-solved by adopting a preset simplified SAT solving algorithm, which specifically comprises the following steps:
setting a scope variable l for each layer of context included in the target bit vector SMT formula i Setting a scope variable l for an i-th layer context i When the target CNF is in a unified normal form by taking the reference number of the scope variable corresponding to the i-th layer context as a referenceThe variable labels of the new variables related to each clause belonging to the i-th layer context are incrementally set, and each clause c belonging to the i-th layer context is converted into l i The method comprises the steps of U < c >, and taking a scope variable corresponding to each layer of context included in a target bit vector SMT formula as an assumption of a solving algorithm; and pre-solving the converted CNF clauses and hypotheses by adopting a preset simplified SAT solving algorithm.
Specifically, the context corresponding to each scope variable is defined by a preset push statement and pop statement. Wherein, a scope variable l is respectively set for each layer of context included in the target bit vector SMT formula i The method specifically comprises the following steps: setting scope variable array scope_lite= { l 1 ,l 2 ,…,l k Recording a scope variable corresponding to each layer context in the target bit vector SMT formula, wherein k is the layer number of the contexts included in the target bit vector SMT formula, when a push sentence is input, a new scope variable is added to the array, and when a pop sentence is executed, a scope variable corresponding to the push sentence with the nearest gap between the pop sentences is deleted from the scope_lite array.
In one specific example, the delta solution algorithm maintains a scope variable l for each layer context (defined by push statement and pop statement) in the bit vector SMT formula i The scope variables are used to track the corresponding context. For each clause c belonging to the i-th layer context, it is converted into l i And adding the U-shaped C into the SAT solving algorithm. Meanwhile, the scope variables corresponding to all the active contexts at present are added into the SAT solving algorithm as an assumption (assumption). Active context i.e. the layer contexts comprised by the current target bit vector SMT formula. For the resulting CNF clauses and hypotheses, SAT pre-solutions are performed using a simplified CDCL algorithm. Compared with a complete SAT solving algorithm, the pre-solving process does not execute restarting operation, and performs equivalent variable detection, clause elimination and other formulated simplification operations only before entering a searching stage. In the SAT pre-solving process, if the number of clause conflicts reaches a preset number threshold, pre-solvingAnd (5) failing to enter a complete SAT solving process. Otherwise, the pre-solving is successful, the result is output, and the satisfaction query of a new round of formulas is entered.
Further, the recording the variable labels of the variables included in the clauses belonging to the target context in the target CNF conjunctive normal form in the pre-solving process specifically includes the following steps: identifying each target context included in the target bit vector SMT formula; when a scope variable is set for the target context, recording the label of the scope variable corresponding to the target context and the maximum value of the variable label of the variable related to each clause belonging to the target context in the target CNF conjunctive normal form; and adding the label of each target context corresponding to the scope variable and the corresponding maximum value of the variable label as a pair of data combinations to a preset redundant variable array to_remove.
Further, the deleting each clause including the corresponding variable label as a redundant clause according to the variable label of the variable included in the clause of the recorded target context specifically includes: and for any clause, if the clause comprises a variable of which the variable label belongs to a variable range corresponding to any data combination in the redundant variable array, deleting the clause as a redundant clause.
In one specific example, when the SAT pre-solution fails, redundancy clause deletion is first required.
In the incremental solving process, a plurality of groups scope_li= { l 1 ,l 2 ,…,l k Recording the scope variable of each context, adding a new scope variable to the array when a push statement is input, and ensuring that the label of the variable is minimal, i.e., any new variable later has a label greater than it. When executing pop statement, delete the scope variable from scope_li array, and record the largest variable label in current SAT formula. These two variables (l 1 ,l 2 ) Stored in the to remove array.
For any clause, if there is a label in it (l 1 ,l 2 ) The clause is redundant. Using a delay mechanism pairThe redundant clause is deleted, namely, corresponding two variables are added to the to_remove array every time the pop statement is executed in the whole incremental solving process, but the redundant clause deleting operation is not really executed until the SAT pre-solving fails.
After the redundant clauses are deleted, the formulas are solved using a complete CDCL SAT solver. And outputting the satisfaction query result corresponding to each assertion.
The software assertion verification method based on the incremental SMT problem solving provided by the embodiment of the invention has at least the following beneficial effects:
1) Compared with verifying each assertion as an independent bit vector SMT formula, the bit vector SMT incremental solving technology used by the invention can effectively utilize the characteristic that a large number of shared expressions exist between the SMT formulas corresponding to each assertion, and improves the software assertion verification efficiency by accumulating historical solving information.
2) Compared with a bit vector SMT incremental solver using only a complete CDCL SAT solving module, the invention uses the SAT pre-solving technology and the redundant clause deleting technology, can effectively avoid unnecessary complex solving process, and can quickly solve a large number of simple satisfiability examples, thereby improving the efficiency of software assertion verification.
For the purposes of simplicity of explanation, the methodologies are shown and described as a series of acts, it is to be understood and appreciated by one of ordinary skill in the art that the methodologies are not limited by the order of acts, as some acts may, in accordance with the methodologies, take place in other order or concurrently. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred embodiments, and that the acts are not necessarily required by the embodiments of the invention.
In addition, the embodiment of the invention also provides a software assertion verification system based on the incremental SMT problem solving. Referring to fig. 3, the software assertion verification system based on incremental SMT problem solution according to an embodiment of the present invention includes functional modules for implementing the software assertion verification method based on incremental SMT problem solution provided in any one of the embodiments above, specifically may include a first conversion module 301, a configuration module 302, a second conversion module 303, a SAT pre-solution module 304, a processing module 305, and a SAT solution module 306, where:
the first conversion module 301 is configured to obtain a software source code to be verified, convert each code assertion to be verified in the software source code into a corresponding bit vector SMT formula according to a code execution path, and obtain a set of bit vector SMT formulas;
a configuration module 302, configured to select a basic bit vector SMT formula from a set of bit vector SMT formulas, and divide an incremental expression portion of other bit vector SMT formulas in the set of bit vector SMT formulas, which is extended with respect to the basic bit vector SMT formula, into multiple layers of contexts according to a similarity relationship between expressions included in each bit vector SMT formula in the set of bit vector SMT formulas;
the second conversion module 303 is configured to perform formulation simplification on a target bit vector SMT formula to be solved currently, and convert the simplified target bit vector SMT formula into a target CNF conjunctive normal form;
the SAT pre-solving module 304 is configured to pre-solve the target CNF conjunctive normal form by using a pre-set simplified SAT solving algorithm, record, in the pre-solving process, variable labels of variables included in clauses belonging to a target context in the target CNF conjunctive normal form, where the target context is a context of an increment portion of the target bit vector SMT formula compared with a bit vector SMT formula solved last time;
the processing module 305 is configured to delete each clause including the corresponding variable label as a redundant clause according to the variable label of the variable included in the clause of the recorded target context when the pre-solution fails;
the SAT solving module 306 is configured to solve the target CNF conjunctive normal form by using a preset complete SAT solving algorithm.
In the embodiment of the present invention, the SAT pre-solving module 304 is specifically configured to set a scope variable l for each layer of context included in the target bit vector SMT formula i Setting a scope variable l for an i-th layer context i In the process, the effect corresponding to the i-th layer context is adoptedIncrementally setting the variable index of the new variable related to each clause belonging to the i-th layer context in the target CNF conjunctive formula by taking the index of the domain variable as a reference, and converting each clause c belonging to the i-th layer context into l i The method comprises the steps of U < c >, and taking a scope variable corresponding to each layer of context included in a target bit vector SMT formula as an assumption of a solving algorithm; and pre-solving the converted CNF clauses and hypotheses by adopting a preset simplified SAT solving algorithm.
Further, the SAT pre-solving module 304 is specifically configured to identify each target context included in the target bit vector SMT formula; when a scope variable is set for the target context, recording the label of the scope variable corresponding to the target context and the maximum value of the variable label of the variable related to each clause belonging to the target context in the target CNF conjunctive normal form; and adding the label of each target context corresponding to the scope variable and the corresponding maximum value of the label of the variable as a pair of data combinations to a preset redundant variable array.
Further, the processing module 305 is specifically configured to delete any clause as a redundant clause if the clause includes a variable whose variable number belongs to a variable range corresponding to any data combination in the redundant variable array.
In the embodiment of the invention, the context corresponding to each scope variable is defined by a preset push statement and pop statement.
Further, the SAT pre-solving module 304 is specifically configured to set a scope variable array scope_li= { l 1 ,l 2 ,…,l k Recording a scope variable corresponding to each layer context in the target bit vector SMT formula, wherein k is the layer number of the contexts included in the target bit vector SMT formula, when a push sentence is input, a new scope variable is added to the array, and when a pop sentence is executed, a scope variable corresponding to the push sentence with the nearest gap between the pop sentences is deleted from the scope_lite array.
In the embodiment of the present invention, the first conversion module 301 is specifically configured to convert a software source code into a code in the form of static univariate assignment SSA, and convert each code assertion to be verified into a corresponding bit vector SMT formula according to a code execution path.
In the embodiment of the present invention, the second conversion module 303 is specifically configured to identify a bit vector operation existing in the bit vector SMT formula, and simplify the bit vector SMT formula according to an operation rule satisfied by the identified various bit vector operations.
For the system embodiment, since the system embodiment is basically similar to the method embodiment, the description is relatively simple, and the relevant points refer to the part of the description of the method embodiment, and the corresponding technical effects are achieved.
In addition, the embodiment of the invention further provides a computer readable storage medium, on which a computer program is stored, the computer program realizing the steps of the software assertion verification method based on the incremental SMT problem solving when being executed by a processor.
In this embodiment, the software assertion verification method based on the incremental SMT problem solving may be stored in a computer readable storage medium if implemented in the form of a software functional unit and sold or used as a separate product. Based on such understanding, the present invention may implement all or part of the flow of the method of the above embodiment, or may be implemented by a computer program to instruct related hardware, where the computer program may be stored in a computer readable storage medium, and when the computer program is executed by a processor, the computer program may implement the steps of each of the method embodiments described above. Wherein the computer program comprises computer program code which may be in source code form, object code form, executable file or some intermediate form etc. The computer readable medium may include: any entity or device capable of carrying the computer program code, a recording medium, a U disk, a removable hard disk, a magnetic disk, an optical disk, a computer Memory, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), an electrical carrier signal, a telecommunications signal, a software distribution medium, and so forth. It should be noted that the computer readable medium contains content that can be appropriately scaled according to the requirements of jurisdictions in which such content is subject to legislation and patent practice, such as in certain jurisdictions in which such content is subject to legislation and patent practice, the computer readable medium does not include electrical carrier signals and telecommunication signals.
In addition, the embodiment of the invention also provides computer equipment, which comprises a memory, a processor and a computer program stored on the memory and capable of running on the processor, wherein the processor realizes the steps of the software assertion verification method based on the incremental SMT problem solving when executing the computer program. For example, steps S11 to S16 shown in fig. 2. Alternatively, the processor, when executing the computer program, implements the functions of the modules/units in the embodiment of the software assertion verification system based on incremental SMT problem solution, for example, the first conversion module 301, the configuration module 302, the second conversion module 303, the SAT pre-solution module 304, the processing module 305, and the SAT solution module 306 shown in fig. 3.
According to the software assertion verification method, system and equipment based on incremental SMT problem solving, the used bit vector SMT incremental solving technology can effectively utilize the characteristic that a large number of shared expressions exist among bit vector SMT formulas corresponding to all assertions, can effectively use derivation information accumulated by multiple assertion verification, and improves software assertion verification efficiency.
Furthermore, those skilled in the art will appreciate that while some embodiments herein include some features but not others included in other embodiments, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, any of the claimed embodiments can be used in any combination.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A software assertion verification method based on incremental SMT problem solving, the method comprising:
acquiring a software source code to be verified, and converting each code assertion to be verified in the software source code into a corresponding bit vector SMT formula according to a code execution path to obtain a bit vector SMT formula set;
selecting a basic bit vector SMT formula from a bit vector SMT formula set, and dividing incremental expression parts, which are expanded by other bit vector SMT formulas in the bit vector SMT formula set relative to the basic bit vector SMT formula, into multi-layer contexts according to similarity relations among expressions included in each bit vector SMT formula in the bit vector SMT formula set;
carrying out formula simplification on a target bit vector SMT formula to be solved currently, and converting the simplified target bit vector SMT formula into a target CNF conjunctive normal form;
pre-solving a target CNF conjunctive normal form by adopting a preset simplified SAT solving algorithm, and recording variable labels of variables included in clauses belonging to a target context in the target CNF conjunctive normal form in a pre-solving process, wherein the target context is the context of an increment part of a target bit vector SMT formula compared with a bit vector SMT formula solved last time;
if the pre-solving fails, deleting each clause containing the corresponding variable label as a redundant clause according to the variable labels of the variables included in the clauses of the recorded target context;
and solving the target CNF conjunctive normal form by adopting a preset complete SAT solving algorithm.
2. The method of claim 1, wherein pre-solving the target CNF conjunctive normal form using a pre-set reduced SAT solution algorithm, comprises:
setting a scope variable l for each layer of context included in the target bit vector SMT formula i Setting a scope variable l for an i-th layer context i In the method, the variable labels of the new variables related to all clauses belonging to the ith layer context in the target CNF conjunctive form are increased by taking the labels of the scope variables corresponding to the ith layer context as references, and each clause c belonging to the ith layer context is converted into l i The method comprises the steps of U < c >, and taking a scope variable corresponding to each layer of context included in a target bit vector SMT formula as an assumption of a solving algorithm;
and pre-solving the converted CNF clauses and hypotheses by adopting a preset simplified SAT solving algorithm.
3. The method according to claim 2, wherein recording, in the pre-solving process, variable labels of variables included in clauses belonging to the target context in the target CNF conjunctive form, includes:
identifying each target context included in the target bit vector SMT formula;
when a scope variable is set for the target context, recording the label of the scope variable corresponding to the target context and the maximum value of the variable label of the variable related to each clause belonging to the target context in the target CNF conjunctive normal form;
and adding the label of each target context corresponding to the scope variable and the corresponding maximum value of the label of the variable as a pair of data combinations to a preset redundant variable array.
4. A method according to claim 3, wherein said deleting each clause containing the corresponding variable label as a redundant clause according to the variable labels of the variables included in the clause of the target context of the record comprises:
and for any clause, if the clause comprises a variable of which the variable label belongs to a variable range corresponding to any data combination in the redundant variable array, deleting the clause as a redundant clause.
5. The method of claim 2, wherein the context for each scope variable is defined by a preset push statement and pop statement.
6. The method of claim 5, wherein the target bit vector SMT formula comprises setting a scope variable l for each layer of context i Comprising the following steps:
setting scope variable array scope_lite= { l 1 ,l 2 ,…,l k Recording a scope variable corresponding to each layer context in the target bit vector SMT formula, wherein k is the layer number of the contexts included in the target bit vector SMT formula, when a push sentence is input, a new scope variable is added to the array, and when a pop sentence is executed, a scope variable corresponding to the push sentence with the nearest gap between the pop sentences is deleted from the scope_lite array.
7. The method of any of claims 1-6, wherein translating each code predicate to be verified in the software source code into a corresponding bit vector SMT formula according to the code execution path comprises:
and converting the software source code into a static univariate assignment SSA form code, and respectively converting each code assertion to be verified into a corresponding bit vector SMT formula according to a code execution path.
8. A software assertion verification system based on incremental SMT problem solution, the system comprising:
the first conversion module is used for acquiring a software source code to be verified, and converting each code assertion to be verified in the software source code into a corresponding bit vector SMT formula according to a code execution path to obtain a bit vector SMT formula set;
the configuration module is used for selecting a basic bit vector SMT formula from the bit vector SMT formula set, and dividing incremental expression parts, which are expanded by other bit vector SMT formulas relative to the basic bit vector SMT formula in the bit vector SMT formula set, into multi-layer contexts according to the similarity relation among expressions included in each bit vector SMT formula in the bit vector SMT formula set;
the second conversion module is used for carrying out formula simplification on the current target bit vector SMT formula to be solved and converting the simplified target bit vector SMT formula into a target CNF conjunctive normal form;
the SAT pre-solving module is used for pre-solving the target CNF conjunctive normal form by adopting a preset simplified SAT solving algorithm, and recording variable labels of variables included in clauses belonging to target contexts in the target CNF conjunctive normal form in a pre-solving process, wherein the target contexts are contexts of increment parts of the target bit vector SMT formula compared with the last solved bit vector SMT formula;
the processing module is used for deleting each clause containing the corresponding variable label as a redundant clause according to the variable label of the variable contained in the clause of the recorded target context when the pre-solving fails;
and the SAT solving module is used for solving the target CNF conjunctive normal form by adopting a preset complete SAT solving algorithm.
9. The system of claim 8 wherein the SAT pre-solving module is configured to set a scope variable l for each layer of context included in the target bit vector SMT formula i Setting a scope variable l for an i-th layer context i In the method, the variable labels of the new variables related to all clauses belonging to the ith layer context in the target CNF conjunctive form are increased by taking the labels of the scope variables corresponding to the ith layer context as references, and each clause c belonging to the ith layer context is converted into l i The method comprises the steps of U < c >, and taking a scope variable corresponding to each layer of context included in a target bit vector SMT formula as an assumption of a solving algorithm; collectingAnd pre-solving the converted CNF clauses and hypotheses by using a preset simplified SAT solving algorithm.
10. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the method according to any one of claims 1-7 when the computer program is executed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311656869.7A CN117573556A (en) | 2023-12-05 | 2023-12-05 | Software assertion verification method, system and equipment based on incremental SMT problem solving |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311656869.7A CN117573556A (en) | 2023-12-05 | 2023-12-05 | Software assertion verification method, system and equipment based on incremental SMT problem solving |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117573556A true CN117573556A (en) | 2024-02-20 |
Family
ID=89893733
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311656869.7A Pending CN117573556A (en) | 2023-12-05 | 2023-12-05 | Software assertion verification method, system and equipment based on incremental SMT problem solving |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117573556A (en) |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6944849B1 (en) * | 2000-06-23 | 2005-09-13 | Microsoft Corporation | System and method for storing and reporting information associated with asserts |
| US20090222393A1 (en) * | 2008-03-03 | 2009-09-03 | Nec Laboratories America, Inc. | Efficient decision procedure for bounded integer non-linear operations using smt(lia) |
| JP2011013797A (en) * | 2009-06-30 | 2011-01-20 | Fujitsu Ltd | Program and device for determining record length |
| CN104123503A (en) * | 2014-06-25 | 2014-10-29 | 中国人民解放军国防科学技术大学 | CNF formula data protection method in SAT problem solving outsourcing process |
| US20160071012A1 (en) * | 2014-09-04 | 2016-03-10 | Fujitsu Limited | Test size reduction using don't care analysis |
| CN109146077A (en) * | 2018-08-01 | 2019-01-04 | 何安平 | A kind of SAT solver |
| US10650109B1 (en) * | 2018-06-20 | 2020-05-12 | Synopsys, Inc. | Boolean satisfiability (SAT) solver |
| CN112231205A (en) * | 2020-09-29 | 2021-01-15 | 安徽中科国创高可信软件有限公司 | First-order logic formula program verification method and system based on SMT solver |
| CN114024663A (en) * | 2021-11-24 | 2022-02-08 | 中国电子科技集团公司第三十研究所 | Linear diffusion layer branch number evaluation method, equipment and medium based on SMT |
| CN114564202A (en) * | 2022-01-13 | 2022-05-31 | 华东师范大学 | Symbol model detection method and system based on SAT solver and application thereof |
| CN115759065A (en) * | 2022-11-28 | 2023-03-07 | 长沙理工大学 | SAT preprocessing method based on digestion principle common clause elimination |
| CN116050311A (en) * | 2023-02-06 | 2023-05-02 | 中国科学院软件研究所 | Combined operation circuit equivalence verification method and system based on complete simulation |
| CN116089264A (en) * | 2022-11-30 | 2023-05-09 | 南京航空航天大学 | Synchronous language program multi-attribute incremental model detection method |
-
2023
- 2023-12-05 CN CN202311656869.7A patent/CN117573556A/en active Pending
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6944849B1 (en) * | 2000-06-23 | 2005-09-13 | Microsoft Corporation | System and method for storing and reporting information associated with asserts |
| US20090222393A1 (en) * | 2008-03-03 | 2009-09-03 | Nec Laboratories America, Inc. | Efficient decision procedure for bounded integer non-linear operations using smt(lia) |
| JP2011013797A (en) * | 2009-06-30 | 2011-01-20 | Fujitsu Ltd | Program and device for determining record length |
| CN104123503A (en) * | 2014-06-25 | 2014-10-29 | 中国人民解放军国防科学技术大学 | CNF formula data protection method in SAT problem solving outsourcing process |
| US20160071012A1 (en) * | 2014-09-04 | 2016-03-10 | Fujitsu Limited | Test size reduction using don't care analysis |
| US10650109B1 (en) * | 2018-06-20 | 2020-05-12 | Synopsys, Inc. | Boolean satisfiability (SAT) solver |
| CN109146077A (en) * | 2018-08-01 | 2019-01-04 | 何安平 | A kind of SAT solver |
| CN112231205A (en) * | 2020-09-29 | 2021-01-15 | 安徽中科国创高可信软件有限公司 | First-order logic formula program verification method and system based on SMT solver |
| CN114024663A (en) * | 2021-11-24 | 2022-02-08 | 中国电子科技集团公司第三十研究所 | Linear diffusion layer branch number evaluation method, equipment and medium based on SMT |
| CN114564202A (en) * | 2022-01-13 | 2022-05-31 | 华东师范大学 | Symbol model detection method and system based on SAT solver and application thereof |
| CN115759065A (en) * | 2022-11-28 | 2023-03-07 | 长沙理工大学 | SAT preprocessing method based on digestion principle common clause elimination |
| CN116089264A (en) * | 2022-11-30 | 2023-05-09 | 南京航空航天大学 | Synchronous language program multi-attribute incremental model detection method |
| CN116050311A (en) * | 2023-02-06 | 2023-05-02 | 中国科学院软件研究所 | Combined operation circuit equivalence verification method and system based on complete simulation |
Non-Patent Citations (4)
| Title |
|---|
| SHAOWEI CAI: "A Semi-exact Algorithm for Quickly Computing A Maximum Weight Clique in Large Sparse Graphs", Retrieved from the Internet <URL:https://www.jair.org/index.php/jair/article/view/12327/26716> * |
| SHAOWEI CAI: "Deep Cooperation of CDCL and Local Search for SAT", Retrieved from the Internet <URL:https://www.ijcai.org/proceedings/2022/0734.pdf> * |
| 张超;竺红卫;马琪;: "结合AIG和两变量观测策略的SAT满足性算法", 电路与系统学报, no. 01, 15 February 2013 (2013-02-15) * |
| 赵阳;吕涛;李华伟;李晓维;: "无界模型检验中融合电路信息的SAT算法研究", 计算机学报, no. 06, 15 June 2009 (2009-06-15) * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8442926B2 (en) | Information filtering system, information filtering method and information filtering program | |
| CN111400338B (en) | SQL optimization method, device, storage medium and computer equipment | |
| US8225060B2 (en) | Data de-duplication by predicting the locations of sub-blocks within the repository | |
| US11526608B2 (en) | Method and system for determining affiliation of software to software families | |
| US11388244B1 (en) | Method, device, and program product for managing computer system | |
| CN114722014B (en) | Batch data time sequence transmission method and system based on database log file | |
| Tang et al. | A comparative study of neural network techniques for automatic software vulnerability detection | |
| CN110806962B (en) | Log level prediction method, device and storage medium | |
| WO2016046233A1 (en) | Efficient conditional state mapping in a pattern matching automaton | |
| CN110618999A (en) | Data query method and device, computer storage medium and electronic equipment | |
| Van et al. | Cheap and good? simple and effective data augmentation for low resource machine reading | |
| Bshouty et al. | More efficient PAC-learning of DNF with membership queries under the uniform distribution | |
| US10747513B2 (en) | Utilizing created character index for switch statements | |
| CN117940894A (en) | System and method for detecting code clones | |
| CN117573556A (en) | Software assertion verification method, system and equipment based on incremental SMT problem solving | |
| CN111159022A (en) | Interrupt data access conflict detection method and device based on univariate access sequence mode | |
| CN116340137A (en) | Method, device, electronic equipment and medium for screening test cases by fuzzy test | |
| CN116527481A (en) | Network alarm association rule mining and fault positioning method and system based on statistics | |
| WO2016046232A1 (en) | Improved pattern matching | |
| CN113312619A (en) | Malicious process detection method and device based on small sample learning, electronic equipment and storage medium | |
| Wu et al. | Repoformer: Selective Retrieval for Repository-Level Code Completion | |
| US11144518B2 (en) | Detecting data mapping relationship within database system and optimizing data operation | |
| Chen | Reducing web page complexity to facilitate effective user navigation | |
| CN114880351B (en) | Recognition method and device of slow query statement, storage medium and electronic equipment | |
| WO2021245726A1 (en) | Information processing device, information processing method, and computer-readable recording medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB03 | Change of inventor or designer information | ||
| CB03 | Change of inventor or designer information |
Inventor after: Cai Shaowei Inventor after: Zhang Xindi Inventor before: Cai Shaowei |