CN117573515B - Programmable message parser verification method and platform - Google Patents
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Abstract
The application provides a programmable message parser verification method and a platform, wherein the method comprises the following steps: analyzing a message set to be tested based on a microcode configuration instruction set by adopting a pre-built simulator to obtain a simulation test result; translating the microcode configuration instruction set into a binary machine code instruction set; analyzing the message set to be tested based on the binary machine code instruction set by adopting a programmable message analyzer to obtain a target test result; and comparing the simulation test result with the target test result after the formats of the simulation test result and the target test result are unified to obtain a comparison result, so as to optimize the programmable message analyzer based on the comparison result. The application can effectively improve the adaptability and the cooperativity between the software and the hardware, and can effectively reduce the verification workload of the programmable message analyzer, thereby effectively improving the working efficiency.
Description
Technical Field
The present application relates to the field of message parsing, and in particular, to a method and platform for verifying a programmable message parser.
Background
At present, with the continuous expansion of internet scale and the rapid development of emerging network technologies, the expansion of network service application and the update of new network protocols put higher demands on the programmability of network equipment and the continuous evolution of protocols. Traditional core network equipment is designed and optimized for specific network protocols, and the processing process is efficient and concise, but the implementation is relatively solidified. With the development of programmable switches and intelligent network card driven programmable networks, these new devices may offer benefits over software defined network use cases and facilitate a transition to a fully programmable cloud. Programmable switches can be used for KV storage, load balancing, and congestion control. The intelligent network card can lighten the workload of a host CPU, and mainly focuses on the intelligent network card based on the FPGA, and the key of realizing the programmability is to be able to identify and process various data packet heads based on a programmable data packet analyzer.
In the verification method of the existing programmable message parser, the suitability and the cooperativity between software and hardware are poor, the verification workload is large, and the working efficiency is low.
Disclosure of Invention
In view of the foregoing, embodiments of the present application provide a programmable message parser verification method and platform to obviate or mitigate one or more disadvantages in the prior art.
A first aspect of the present application provides a method for verifying a programmable message parser, the method comprising:
Analyzing a message set to be tested based on a microcode configuration instruction set by adopting a pre-built simulator to obtain a simulation test result;
Translating the microcode configuration instruction set into a binary machine code instruction set; analyzing the message set to be tested based on the binary machine code instruction set by adopting a programmable message analyzer to obtain a target test result;
And comparing the simulation test result with the target test result after the formats of the simulation test result and the target test result are unified to obtain a comparison result, so as to optimize the programmable message analyzer based on the comparison result.
In some embodiments of the present application, before the analyzing the to-be-tested message set to obtain the simulation test result by adopting the pre-built simulator based on the microcode configuration instruction set, the method further includes:
Extracting header information corresponding to each of a plurality of network protocols; wherein the header information includes a domain value, next hop information, a length value and control information in the network protocol;
Each of the header information is translated into the microcode configuration instruction set.
In some embodiments of the application, said translating each of said header information into said microcode configuration instruction set comprises:
Obtaining a network protocol arrangement diagram according to each piece of next-hop information;
And translating the network protocol arrangement diagram based on a predefined instruction rule to obtain the microcode configuration instruction set.
In some embodiments of the present application, the analyzing the set of to-be-tested messages to obtain the simulation test result by using the pre-built simulator based on the microcode configuration instruction set includes:
And analyzing the message format and the field of each message data in the message set to be tested based on the microcode configuration instruction set, extracting the message information of each message data based on a data analysis algorithm, verifying, detecting and processing errors of each message data to obtain a detection result, and obtaining the simulation test result according to the message format, the field, the message information, the detection result and a preset target format of each message data.
In some embodiments of the application, translating the microcode configuration instruction set into a binary machine code instruction set includes:
And sequentially performing lexical analysis, grammar analysis and symbol analysis on the microcode configuration instruction set to obtain the binary machine code instruction set.
In some embodiments of the present application, the parsing the set of messages to be tested based on the binary machine code instruction set using a programmable message parser to obtain a target test result includes:
And analyzing each message data in the message set to be tested based on the binary machine code instruction set by adopting the programmable message analyzer to obtain message information corresponding to each message data, constructing a corresponding data structure based on each message information, and analyzing each data structure to obtain the target test result.
In some embodiments of the present application, the parsing each message data in the to-be-detected message set to obtain the message information corresponding to each message data includes:
and adopting the programmable message analyzer to divide data, extract fields and code and convert all message data in the message set to be tested based on the binary machine code instruction set to obtain message information corresponding to each message data.
A second aspect of the present application provides a programmable message parser verification platform, the platform comprising:
The software processing module is used for analyzing the message set to be tested based on the microcode configuration instruction set by adopting a pre-built simulator so as to obtain a simulation test result;
the hardware processing module is used for translating the microcode configuration instruction set into a binary machine code instruction set; analyzing the message set to be tested based on the binary machine code instruction set by adopting a programmable message analyzer to obtain a target test result;
And the test comparison module is used for comparing the simulation test result and the target test result after the formats of the simulation test result and the target test result are unified to obtain a comparison result so as to optimize the programmable message analyzer based on the comparison result.
A third aspect of the present application provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor, where the processor implements the programmable message parser verification method of the first aspect when the processor executes the computer program.
A fourth aspect of the present application provides a computer readable storage medium having stored thereon a computer program which when executed by a processor implements the programmable message parser verification method of the first aspect described above.
The application provides a programmable message parser verification method and a platform, wherein the method comprises the following steps: analyzing a message set to be tested based on a microcode configuration instruction set by adopting a pre-built simulator to obtain a simulation test result; translating the microcode configuration instruction set into a binary machine code instruction set; analyzing the message set to be tested based on the binary machine code instruction set by adopting a programmable message analyzer to obtain a target test result; and comparing the simulation test result with the target test result after the formats of the simulation test result and the target test result are unified to obtain a comparison result, so as to optimize the programmable message analyzer based on the comparison result. The application can effectively improve the adaptability and the cooperativity between the software and the hardware, and can effectively reduce the verification workload of the programmable message analyzer, thereby effectively improving the working efficiency.
Additional advantages, objects, and features of the application will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and drawings.
It will be appreciated by those skilled in the art that the objects and advantages that can be achieved with the present application are not limited to the above-described specific ones, and that the above and other objects that can be achieved with the present application will be more clearly understood from the following detailed description.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate and together with the description serve to explain the application. The components in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the application. Corresponding parts in the drawings may be exaggerated, i.e. made larger relative to other parts in an exemplary device actually manufactured according to the present application, for convenience in showing and describing some parts of the present application. In the drawings:
fig. 1 is a flowchart of a programmable message parser verification method according to an embodiment of the application.
Fig. 2 is a schematic structural diagram of a programmable message parser verification platform according to another embodiment of the application.
FIG. 3 is a system architecture diagram of a programmable message parser verification method in another embodiment of the application.
Fig. 4 is a network protocol arrangement diagram according to another embodiment of the present application.
FIG. 5 is a flow chart illustrating the generation of a microcode configuration instruction set according to another embodiment of the present application.
FIG. 6 is a flow chart illustrating the conversion of a microcode configuration instruction set to a binary machine code instruction set in another embodiment of the present application.
FIG. 7 is a flow chart illustrating the generation of a microcode configuration instruction set according to another embodiment of the present application.
Detailed Description
The present application will be described in further detail with reference to the following embodiments and the accompanying drawings, in order to make the objects, technical solutions and advantages of the present application more apparent. The exemplary embodiments of the present application and the descriptions thereof are used herein to explain the present application, but are not intended to limit the application.
It should be noted here that, in order to avoid obscuring the present application due to unnecessary details, only structures and/or processing steps closely related to the solution according to the present application are shown in the drawings, while other details not greatly related to the present application are omitted.
It should be emphasized that the term "comprises/comprising" when used herein is taken to specify the presence of stated features, elements, steps or components, but does not preclude the presence or addition of one or more other features, elements, steps or components.
It is also noted herein that the term "coupled" may refer to not only a direct connection, but also an indirect connection in which an intermediate is present, unless otherwise specified.
Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. In the drawings, the same reference numerals represent the same or similar components, or the same or similar steps.
The following examples are provided to illustrate the invention in more detail.
The embodiment of the application provides a programmable message parser verification method which can be executed by a programmable message parser verification platform, and referring to fig. 1, the programmable message parser verification method specifically comprises the following contents:
step 110: and analyzing the message set to be tested based on the microcode configuration instruction set by adopting a pre-constructed simulator so as to obtain a simulation test result.
Step 120: translating the microcode configuration instruction set into a binary machine code instruction set; and adopting a programmable message analyzer to analyze the message set to be tested based on the binary machine code instruction set so as to obtain a target test result.
Step 130: and comparing the simulation test result with the target test result after the formats of the simulation test result and the target test result are unified to obtain a comparison result, so as to optimize the programmable message analyzer based on the comparison result.
Specifically, the programmable message parser verification platform firstly adopts a pre-built simulator to parse a message set to be tested based on a microcode configuration instruction set so as to obtain a simulation test result; and then adopting a programmable message analyzer to analyze the message set to be tested based on the binary machine code instruction set so as to obtain a target test result. Finally, the simulation test result and the target test result are subjected to format unification and then are compared to obtain a comparison result, so that the programmable message analyzer is optimized based on the comparison result, the adaptability and the cooperativity between software and hardware can be effectively improved, meanwhile, the verification workload of the programmable message analyzer can be effectively reduced, and further, the working efficiency can be effectively improved.
In addition, after the comparison result is obtained, the comparison result is analyzed, so that a report and coverage rate data are generated, and the message parser is optimized.
To improve the suitability and cooperativity between the software and the hardware, before step 110, the method further includes:
step 90: extracting header information corresponding to each of a plurality of network protocols; wherein the header information includes a domain value, next hop information, a length value, and control information in the network protocol.
Step 100: each of the header information is translated into the microcode configuration instruction set.
Specifically, the programmable message parser verification platform extracts header information corresponding to each of a plurality of network protocols (the network protocols form a network model in fig. 3), and adopts a high-level programming language to describe the header information; referring to fig. 5, a compiler is used to translate each header information described in the high-level programming language into a microcode configuration instruction set, so as to improve the adaptability and cooperativity between the software and the hardware.
The header information includes a field value (extract key), next hop information (next type), a length value (length), and control signal information in a network protocol. Packet sequencer In FIG. 3 represents a message Wen Dingxu, PACKET DRIVER represents a message driver, monitor represents a controller, PACKET PARSER det represents a message parser, and In_agent represents an input agent. Out_agent represents the output agent, scoreboard represents the scoreboard, and Packet compare represents the message comparator.
To further promote the suitability and cooperativity between the software and the hardware, step 100 includes:
Obtaining a network protocol arrangement diagram according to each piece of next-hop information;
And translating the network protocol arrangement diagram based on a predefined instruction rule to obtain the microcode configuration instruction set.
Specifically, the programmable message parser verification platform obtains a network protocol arrangement chart according to each piece of next-hop information (see fig. 4); and then translating the network protocol arrangement diagram based on a predefined instruction rule to obtain a microcode configuration instruction set, so that the suitability and the cooperativity between the software and the hardware can be further improved.
In order to effectively reduce the verification workload of the programmable message parser, and further effectively improve the working efficiency, step 110 includes:
And analyzing the message format and the field of each message data in the message set to be tested based on the microcode configuration instruction set, extracting the message information of each message data based on a data analysis algorithm, verifying, detecting and processing errors of each message data to obtain a detection result, and obtaining the simulation test result according to the message format, the field, the message information, the detection result and a preset target format of each message data.
Specifically, referring to fig. 7, the verification platform of the programmable message parser adopts a simulator, analyzes the message format and the field of each message data in the message set to be tested based on a microcode configuration instruction set, extracts the message information of each message data based on a data analysis algorithm, verifies, detects and processes the error of each message data to obtain a detection result, and obtains a simulation test result according to the message format, the field, the message information, the detection result and a preset target format of each message data, thereby effectively reducing the verification workload of the programmable message parser and further effectively improving the working efficiency.
It should be noted that, the simulator is composed of a plurality of processing units, and the microcode configuration instruction set includes header information corresponding to each of a plurality of network protocols; and each processing unit in the simulator analyzes the message data according to the network protocol corresponding to the allocated microcode configuration instruction.
To effectively test the message parser, translating the microcode configuration instruction set into a binary machine code instruction set in step 120 includes:
And sequentially performing lexical analysis, grammar analysis and symbol analysis on the microcode configuration instruction set to obtain the binary machine code instruction set.
Specifically, referring to fig. 6, the programmable message parser verification platform sequentially performs lexical analysis, syntax analysis, and symbol analysis on the microcode configuration instruction set to obtain a binary machine code instruction set, so that the message parser can be effectively tested based on the binary machine code instruction set.
In order to effectively test the message parser, the step 120 of using a programmable message parser to parse the to-be-tested message set based on the binary machine code instruction set to obtain a target test result includes:
And analyzing each message data in the message set to be tested based on the binary machine code instruction set by adopting the programmable message analyzer to obtain message information corresponding to each message data, constructing a corresponding data structure based on each message information, and analyzing each data structure to obtain the target test result.
Specifically, the programmable message parser verification platform adopts a programmable message parser, parses each message data in the message set to be tested based on a binary machine code instruction set to obtain message information corresponding to each message data, constructs each corresponding data structure based on each message information, and analyzes each data structure to obtain a target test result, so that the message parser can be effectively tested.
It should be noted that, the parser is composed of a plurality of processing units, and the binary machine code instruction set includes header information corresponding to each of a plurality of network protocols; and each processing unit in the analyzer analyzes the message data according to the network protocol corresponding to the allocated binary machine code instruction.
In order to improve the integrity of the analysis of the message data, the analyzing each message data in the to-be-detected message set to obtain the message information corresponding to each message data, includes:
and adopting the programmable message analyzer to divide data, extract fields and code and convert all message data in the message set to be tested based on the binary machine code instruction set to obtain message information corresponding to each message data.
Specifically, the programmable message parser verification platform adopts a programmable message parser, and performs data segmentation, field extraction and code conversion on each message data in the message set to be tested based on a binary machine code instruction set to obtain the message information corresponding to each message data, so that the integrity of message data parsing can be effectively improved.
From the software aspect, the present application further provides a programmable message parser verification platform for executing all or part of the method for verifying a programmable message parser, referring to fig. 2, where the programmable message parser verification platform specifically includes the following contents:
The software processing module is used for analyzing the message set to be tested based on the microcode configuration instruction set by adopting a pre-built simulator so as to obtain a simulation test result;
the hardware processing module is used for translating the microcode configuration instruction set into a binary machine code instruction set; analyzing the message set to be tested based on the binary machine code instruction set by adopting a programmable message analyzer to obtain a target test result;
And the test comparison module is used for comparing the simulation test result and the target test result after the formats of the simulation test result and the target test result are unified to obtain a comparison result so as to optimize the programmable message analyzer based on the comparison result.
The embodiment of the programmable message parser verification platform provided by the application can be particularly used for executing the processing flow of the embodiment of the programmable message parser verification method in the embodiment, and the functions of the embodiment of the programmable message parser verification platform are not repeated herein, and reference can be made to the detailed description of the embodiment of the programmable message parser verification method.
The application provides a programmable message parser verification platform, which comprises the following steps: analyzing a message set to be tested based on a microcode configuration instruction set by adopting a pre-built simulator to obtain a simulation test result; translating the microcode configuration instruction set into a binary machine code instruction set; analyzing the message set to be tested based on the binary machine code instruction set by adopting a programmable message analyzer to obtain a target test result; and comparing the simulation test result with the target test result after the formats of the simulation test result and the target test result are unified to obtain a comparison result, so as to optimize the programmable message analyzer based on the comparison result. The application can effectively improve the adaptability and the cooperativity between the software and the hardware, and can effectively reduce the verification workload of the programmable message analyzer, thereby effectively improving the working efficiency.
The embodiment of the application also provides an electronic device, such as a central server, which may include a processor, a memory, a receiver and a transmitter, where the processor is configured to execute the method for verifying a programmable message parser as mentioned in the foregoing embodiment, and the processor and the memory may be connected by a bus or other manners, for example, through a bus connection. The receiver may be connected to the processor, memory, by wire or wirelessly.
The processor may be a central processing unit (Central Processing Unit, CPU). The Processor may also be other general purpose processors, digital Signal Processors (DSP), application SPECIFIC INTEGRATED Circuits (ASIC), field-Programmable gate arrays (Field-Programmable GATEARRAY, FPGA) or other Programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or a combination of the above.
The memory, as a non-transitory computer readable storage medium, may be used to store a non-transitory software program, a non-transitory computer executable program, and a module, such as program instructions/modules corresponding to the programmable message parser verification method in the embodiment of the present application. The processor executes various functional applications and data processing of the processor by running non-transitory software programs, instructions and modules stored in the memory, i.e., implementing the programmable message parser verification method in the method embodiments described above.
The memory may include a memory program area and a memory data area, wherein the memory program area may store an operating system, at least one application program required for a function; the storage data area may store data created by the processor, etc. In addition, the memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some embodiments, the memory may optionally include memory located remotely from the processor, the remote memory being connectable to the processor through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The one or more modules are stored in the memory that, when executed by the processor, perform the programmable message parser verification method of the embodiments.
In some embodiments of the present application, a user equipment may include a processor, a memory, and a transceiver unit, which may include a receiver and a transmitter, the processor, the memory, the receiver, and the transmitter may be connected by a bus system, the memory being configured to store computer instructions, the processor being configured to execute the computer instructions stored in the memory to control the transceiver unit to transmit and receive signals.
As an implementation manner, the functions of the receiver and the transmitter in the present application may be considered to be implemented by a transceiver circuit or a dedicated chip for transceiver, and the processor may be considered to be implemented by a dedicated processing chip, a processing circuit or a general-purpose chip.
As another implementation manner, a manner of using a general-purpose computer may be considered to implement the server provided by the embodiment of the present application. I.e. program code for implementing the functions of the processor, the receiver and the transmitter are stored in the memory, and the general purpose processor implements the functions of the processor, the receiver and the transmitter by executing the code in the memory.
The embodiment of the application also provides a computer readable storage medium, on which a computer program is stored, which when being executed by a processor, implements the steps of the programmable message parser verification method described above. The computer readable storage medium may be a tangible storage medium such as Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, floppy disks, hard disk, a removable memory disk, a CD-ROM, or any other form of storage medium known in the art.
Those of ordinary skill in the art will appreciate that the various illustrative components, systems, and methods described in connection with the embodiments disclosed herein can be implemented as hardware, software, or a combination of both. The particular implementation is hardware or software dependent on the specific application of the solution and the design constraints. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application. When implemented in hardware, it may be, for example, an electronic circuit, an Application Specific Integrated Circuit (ASIC), suitable firmware, a plug-in, a function card, or the like. When implemented in software, the elements of the application are the programs or code segments used to perform the required tasks. The program or code segments may be stored in a machine readable medium or transmitted over transmission media or communication links by a data signal carried in a carrier wave.
It should be understood that the application is not limited to the particular arrangements and instrumentality described above and shown in the drawings. For the sake of brevity, a detailed description of known methods is omitted here. In the above embodiments, several specific steps are described and shown as examples. The method processes of the present application are not limited to the specific steps described and shown, but various changes, modifications and additions, or the order between steps may be made by those skilled in the art after appreciating the spirit of the present application.
In this disclosure, features that are described and/or illustrated with respect to one embodiment may be used in the same way or in a similar way in one or more other embodiments and/or in combination with or instead of the features of the other embodiments.
The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, and various modifications and variations can be made to the embodiments of the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (8)
1. A method for verifying a programmable message parser, comprising:
Analyzing a message set to be tested based on a microcode configuration instruction set by adopting a pre-built simulator to obtain a simulation test result;
Translating the microcode configuration instruction set into a binary machine code instruction set; analyzing the message set to be tested based on the binary machine code instruction set by adopting a programmable message analyzer to obtain a target test result;
the simulation test result and the target test result are subjected to format unification and then are compared to obtain a comparison result, so that the programmable message analyzer is optimized based on the comparison result;
Before the simulator which is built in advance is adopted to analyze the message set to be tested based on the microcode configuration instruction set to obtain the simulation test result, the method further comprises the following steps:
Extracting header information corresponding to each of a plurality of network protocols; wherein the header information includes a domain value, next hop information, a length value and control information in the network protocol;
Translating each of said header information into said microcode configuration instruction set;
Said translating each of said header information into said microcode configuration instruction set, comprising:
Obtaining a network protocol arrangement diagram according to each piece of next-hop information;
And translating the network protocol arrangement diagram based on a predefined instruction rule to obtain the microcode configuration instruction set.
2. The method for verifying a programmable message parser as defined in claim 1, wherein the parsing the set of messages to be tested based on the microcode configuration instruction set using a pre-built simulator to obtain the simulation test result comprises:
And analyzing the message format and the field of each message data in the message set to be tested based on the microcode configuration instruction set, extracting the message information of each message data based on a data analysis algorithm, verifying, detecting and processing errors of each message data to obtain a detection result, and obtaining the simulation test result according to the message format, the field, the message information, the detection result and a preset target format of each message data.
3. The programmable message parser verification method of claim 1 wherein translating the microcode configuration instruction set into a binary machine code instruction set comprises:
And sequentially performing lexical analysis, grammar analysis and symbol analysis on the microcode configuration instruction set to obtain the binary machine code instruction set.
4. The method for verifying a programmable message parser as defined in claim 1, wherein the parsing the set of messages to be tested based on the binary machine code instruction set with the programmable message parser to obtain the target test result comprises:
And analyzing each message data in the message set to be tested based on the binary machine code instruction set by adopting the programmable message analyzer to obtain message information corresponding to each message data, constructing a corresponding data structure based on each message information, and analyzing each data structure to obtain the target test result.
5. The method for verifying a programmable message parser as defined in claim 4, wherein parsing each message data in the set of messages to be tested to obtain the message information corresponding to each message data, comprises:
and adopting the programmable message analyzer to divide data, extract fields and code and convert all message data in the message set to be tested based on the binary machine code instruction set to obtain message information corresponding to each message data.
6. A programmable message parser verification platform, comprising:
The software processing module is used for analyzing the message set to be tested based on the microcode configuration instruction set by adopting a pre-built simulator so as to obtain a simulation test result;
the hardware processing module is used for translating the microcode configuration instruction set into a binary machine code instruction set; analyzing the message set to be tested based on the binary machine code instruction set by adopting a programmable message analyzer to obtain a target test result;
The test comparison module is used for comparing the simulation test result and the target test result after the formats of the simulation test result and the target test result are unified to obtain a comparison result so as to optimize the programmable message analyzer based on the comparison result;
Before the simulator constructed in advance is adopted to analyze the message set to be tested based on the microcode configuration instruction set to obtain a simulation test result, the programmable message analyzer verification platform is further used for executing the following contents:
Extracting header information corresponding to each of a plurality of network protocols; wherein the header information includes a domain value, next hop information, a length value and control information in the network protocol;
Translating each of said header information into said microcode configuration instruction set;
Wherein said translating each of said header information into said microcode configuration instruction set comprises:
Obtaining a network protocol arrangement diagram according to each piece of next-hop information;
And translating the network protocol arrangement diagram based on a predefined instruction rule to obtain the microcode configuration instruction set.
7. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the programmable message parser verification method of any one of claims 1 to 5 when the computer program is executed by the processor.
8. A computer readable storage medium having stored thereon a computer program, which when executed by a processor implements the programmable message parser verification method of any one of claims 1 to 5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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