CN117573136A - Chip code text file processing method, electronic equipment and medium - Google Patents

Chip code text file processing method, electronic equipment and medium Download PDF

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CN117573136A
CN117573136A CN202311617397.4A CN202311617397A CN117573136A CN 117573136 A CN117573136 A CN 117573136A CN 202311617397 A CN202311617397 A CN 202311617397A CN 117573136 A CN117573136 A CN 117573136A
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code
file
chip
interpolation
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CN117573136B (en
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王定
请求不公布姓名
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Muxi Integrated Circuit Shanghai Co ltd
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
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    • G06F16/164—File meta data generation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/42—Syntactic analysis
    • G06F8/427—Parsing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The invention relates to the technical field of chips, in particular to a chip code text file processing method, electronic equipment and a medium, wherein the method comprises the following steps of S1, directly encoding non-repeated codes in a target code form, setting interpolation codes for the repeated codes in a preset interpolation code type encoding mode, and generating a chip code text file to be processed; s2, setting the file name of the chip code text file to be processed as XY.Z; s3, inputting the chip code text file to be processed into a preset file analyzer, and determining the type of the target code; and S4, analyzing the chip code text file to be processed based on a preset file analyzer to generate a corresponding repeated code in the form of a target code, replacing the corresponding interpolation code, and generating the target chip code file when all code analysis is completed. The invention improves the generation efficiency of the chip codes.

Description

Chip code text file processing method, electronic equipment and medium
Technical Field
The present invention relates to the field of chip technologies, and in particular, to a method for processing a chip code text file, an electronic device, and a medium.
Background
The existing chips are large in scale and have a large number of functional features (features), and some types of chips have the characteristics of high repetition and high stacking in the process of chip development, such as graphics processor (Graphics Processing Unit, GPU for short) chips. If the chip codes with the characteristics of high repetition and high stacking are directly encoded, a large number of repeated codes need to be written, a large amount of time is required to be consumed, the efficiency of generating the chip codes is low, and the text files of the chip codes generated by directly writing the chip codes with the characteristics of high repetition and high stacking are large, so that a large storage space is required to be occupied. Therefore, how to reduce the memory space occupied by the text file of the chip code and improve the generation efficiency of the chip code becomes a technical problem to be solved.
Disclosure of Invention
The invention aims to provide a chip code text file processing method, electronic equipment and medium, which reduce the storage space occupied by the chip code text file and improve the generation efficiency of the chip code.
The invention provides a method for processing a chip code text file, which comprises the following steps:
step S1, directly encoding a non-repeated code in a target code form, encoding the repeated code in a preset interpolation code type to set an interpolation code, setting a preset interpolation starting point identifier at the starting point of the interpolation code, setting a preset interpolation ending point identifier at the ending point of the interpolation code, and generating a chip code text file to be processed;
step S2, setting the file name of the chip code text file to be processed as XY.Z, wherein 'X' is a file identifier, 'Y' is target code type information, 'Z' is a preset file suffix, storing the chip code text file to be processed in a chip code text file storage area, and the file in the 'Z' format is a file which can be processed by a preset file analyzer;
s3, inputting the chip code text file to be processed into a preset file analyzer, analyzing the file name of the chip code text file to be processed by the file analyzer, and determining the type of the target code;
and S4, analyzing the text file of the chip code to be processed based on a preset file analyzer, for encoding in the form of an object code, when the code is analyzed to the interpolation code, extracting the interpolation code between the starting point identifier of the interpolation code and the key identifier of the corresponding interpolation code, analyzing the interpolation code, generating a repeated code in the form of the corresponding object code, replacing the corresponding interpolation code, and generating the object chip code file when all the code analysis is completed.
Compared with the prior art, the invention has obvious advantages and beneficial effects. By means of the technical scheme, the chip code text file processing method, the electronic equipment and the medium provided by the invention can achieve quite technical progress and practicality, have wide industrial utilization value, and have at least the following beneficial effects:
according to the method, the non-repeated codes are directly encoded in the form of the target codes, the repeated codes are encoded in the form of the preset interpolation codes, the interpolation codes are set, the chip code text file to be processed is generated, the chip code text file to be processed is stored in the chip code text file storage area, and the storage space occupied by the chip code text file is reduced. And then analyzing the text file of the chip code to be processed through a preset file analyzer to generate a target chip code file, so that the generation efficiency of the chip code is improved.
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In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a method for processing a chip code text file according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
The embodiment of the invention provides a chip code text file processing method, which is shown in fig. 1 and comprises the following steps:
and S1, directly encoding the non-repeated codes in the form of target codes, encoding the repeated codes in the form of preset interpolation code types, setting a preset interpolation starting point identifier at the starting point of the interpolation codes, setting a preset interpolation end point identifier at the end point of the interpolation codes, and generating a chip code text file to be processed.
It should be noted that the code space required for encoding the repeated code directly in the form of the object code is much larger than the space required for interpolating the code. The time required is also much longer than the time to generate the interpolated code.
As an embodiment, the object code types include C/c++, java, verilog, VHDL, and System Verilog languages, etc., and the preset interpolation code types include Python, perl, ruby, rust language, etc.
As one example, when the predetermined interpolation code type is python language, the corresponding predetermined interpolation start identifier is < PY >, and the corresponding predetermined interpolation end identifier is </PY >.
When the preset interpolation code type is perl language, the corresponding preset interpolation starting point identifier is < PL >, and the corresponding preset interpolation ending point identifier is </PL >.
When the preset interpolation code type is ruby language, the corresponding preset interpolation starting point identifier is < RB >, and the corresponding preset interpolation ending point identifier is < RB >.
When the preset interpolation code type is RUST language, the corresponding preset interpolation starting point identifier is < RT >, and the corresponding preset interpolation ending point identifier is </RT >.
And S2, setting the file name of the chip code text file to be processed as XY.Z, wherein 'X' is a file identifier, 'Y' is target code type information, 'Z' is a preset file suffix, storing the chip code text file to be processed in a chip code text file storage area, and the file in the 'Z' format is a file which can be processed by a preset file analyzer.
As an example, the file name of the chip code text file to be processed is set to a.cpp.xlog, where "a" is the file identification, "Cpp" is the object code type, and "Xlog" is the preset file suffix.
And S3, inputting the chip code text file to be processed into a preset file analyzer, analyzing the file name of the chip code text file to be processed by the file analyzer, and determining the type of the target code.
It should be noted that, a preset file parser needs to be written in advance, the input of the preset file parser is a chip code text file to be processed, and the output is a corresponding target chip code file.
And S4, analyzing the text file of the chip code to be processed based on a preset file analyzer, for encoding in the form of an object code, when the code is analyzed to the interpolation code, extracting the interpolation code between the starting point identifier of the interpolation code and the key identifier of the corresponding interpolation code, analyzing the interpolation code, generating a repeated code in the form of the corresponding object code, replacing the corresponding interpolation code, and generating the object chip code file when all the code analysis is completed.
The step S4 can automatically generate repeated codes in the form of target codes based on the analysis of the interpolation codes by the preset file analyzer, manual writing is not needed, and the generation efficiency of the target chip code file is improved.
As an embodiment, in the step S1, the setting of the interpolation code by the preset interpolation code type encoding of the repetition code includes:
and S11, directly setting the chip functional feature configuration information, or generating the chip functional feature configuration information based on analysis of the functional feature configuration file corresponding to the pre-generated chip composition module.
It should be noted that, the chip function feature configuration information may be set directly based on a specific application scenario.
And step S12, generating repeated code logic and repeated number according to the preset interpolation code type based on the chip functional characteristic configuration information.
It should be noted that, logic of the repetition code and the repetition number can be obtained based on the chip functional feature configuration information.
As an embodiment, in the step S11, generating the chip functional feature configuration information based on the analysis of the functional feature configuration file corresponding to the pre-generated chip composition module includes:
step S111, a functional feature configuration file corresponding to each chip component module is obtained, where the functional feature configuration file includes component module identification information, global functional feature configuration information, first sub-functional feature configuration information, second sub-functional feature configuration information, and third sub-functional feature configuration information, where the first sub-functional feature configuration information is configuration information for chip design and verification of a scene, the second sub-functional configuration information is configuration information only for verification of the scene, and the third sub-functional feature configuration information is configuration information for implementing a preset processing procedure.
The global feature configuration information is feature configuration information based on the whole project angle, such as process type, type information of a memory (memory), location information, and the like. The third sub-feature configuration information may specifically include feature configuration information for implementing a preprocessing procedure, feature configuration information related to Makefile variables, and the like.
Step S112, generating a design header file, a verification header file and a processing flow header file corresponding to the chip composition module based on the functional characteristic configuration files corresponding to the chip composition module and the functional characteristic configuration files corresponding to all descendant nodes of the chip composition module.
Step S113, generating chip function feature configuration information based on the design header file, the verification header file and the processing flow header file corresponding to the chip composition module.
In the chip development process, chip design, chip verification and various processing flows are involved, the processing flows comprise preprocessing and the like, and because the chip scale is huge and the functional characteristics are huge, if configuration information is generated based on the functional characteristics of the chip respectively aiming at each application scene, a great deal of cost is required to be consumed.
As one embodiment, the chip composition module list is { M } 1 ,M 2 ,…,M k ,…,M K M is }, where M k And K is the total number of the chip composition modules, and all the chip composition modules are arranged in a hierarchical manner to form a tree structure. The Chip generally includes an SOC (System-on-a-Chip) module, the SOC module includes a IP (Intellectual Property) module, the large-scale IP module may further include a small-scale IP module or subsystem (Sub System) module, the small-scale IP module may further include a Block module, it is understood that the SOC module is a top-level module, the non-top-level-follower module may be an SOC module, an IP module, a Sub System module, or a Block module, and the hierarchical relationship of each component module is known, that is, a parent-child module of each component module is known, and a sibling module is also known.
The step S111 includes:
step S1111, splitting each chip functional feature into a plurality of sub-functional features.
In step S1112, the plurality of sub-functional features of each chip functional feature are set in a plurality of chip constituent modules, wherein one of the sub-functional features is set in the top module, and if one of the sub-functional features is set in another constituent module other than the top module, one of the sub-functional features is necessarily set in the parent module of the constituent module.
Step S1113, obtaining a chip function feature list { F } 1 ,F 2 ,…,F n ,…,F N }, wherein F n The value range of N is 1 to N, and N is the total number of the functional features of the chip.
Step S1114, F n Splitting into g (n) sub-functional features { F 1 n ,F 2 n ,…,F x n ,…,F g(n) n }，F x n Is F n X has a value ranging from 1 to g (n), g (n) being F n The total number of sub-functional features of (C) and g (n) is more than or equal to 1.
It should be noted that when n takes different values, the value of g (n) may also be different, i.e. each F n The number of sub-functional features partitioned may not be the same. Each sub-feature is implemented by a corresponding chip composition module, if one F n Without resolution, g (n) =1.
Step S1115, build F 1 n And M is as follows 1 Corresponding relation of M 1 Is a top layer module.
The top-layer modules are constituent modules without father modules and with only child modules, and the non-top-layer modules are all provided with father modules.
Step S1116, is F y n Setting corresponding M i ,F y n Is F n Y has a value ranging from 2 to g (n), M i For the ith chip to form a module, the value of i ranges from 2 to K, each of which is equal to F y n M for setting corresponding relation i The parent module must be identical to one of F x n And establishing a corresponding relation.
It should be noted that each F needs to be implemented in the top module n Each F is a sub-functional feature of n In addition to the sub-features already implemented by the top-level module, may be distributed among other non-top-level modules, but one non-top-level module is provided with F n If the sub-functional feature of the module is not the top-level module, the parent module corresponding to the tree structure constructed by the chip composition module is also setPut F into n Is a sub-functional feature of (a). After the setting is completed, a plurality of different F's can be set in one chip composition module n Is a sub-functional feature of (c).
As an embodiment, the parameter information corresponding to the sub-functional feature includes fixed parameter information, first type variable parameter information and second type variable parameter information. The fixed parameter information is parameter information which always needs to exist and does not need to be changed, such as a functional characteristic identifier.
The first type of variable parameter information comprises a first identifier and a second identifier; when the first type variable parameter information is set as a first identifier, the corresponding sub-function feature is indicated to be valid; and when the first type variable parameter information is set as the second identifier, the corresponding sub-function feature is invalid, and the first type variable parameter information is set as the first identifier by default. By switching the first identifier and the second identifier of the first type variable parameter information, the setting of the corresponding sub-functional feature can be controlled, namely, when a certain sub-functional feature does not need to be realized, only the identifier information of the corresponding first type variable parameter information is changed in the configuration file.
The second type of variable parameter information comprises adjustable parameters, and parameters corresponding to the sub-functional features are set by adjusting the numerical value or the range of the adjustable parameters. It should be noted that, for one variable parameter, corresponding second type variable parameter information may be set.
The functional feature configuration file can be expanded, configured and reused by locally updating the functional feature configuration file, and the chip functional feature configuration information can be updated by updating the functional feature configuration file.
As an embodiment, when the functional feature needs to be deleted, the step S4 further includes:
a1, acquiring a to-be-closed function feature identifier, and if the to-be-closed function feature identifier is { F } 1 ,F 2 ,…,F n ,…,F N Elements in } based on F to be closed n Executing step A2, if the feature to be turned off is { F } 1 n ,F 2 n ,…,F x n ,…,F g(n) n Elements in } based on F to be closed x n Step A3 is performed.
Step SA2, when F is to be closed n M corresponding to each sub-functional feature of (C) k F to be closed in the corresponding functional characteristic configuration file n The first type variable parameter information corresponding to each sub-functional feature is set as the second identifier.
It will be appreciated that when a F needs to be deleted n When F is needed n All corresponding sub-functions are deleted.
Step SA3, to-be-closed F x n Corresponding F n Is set as to-be-processed F n To be closed F x n Corresponding M k Corresponding offspring node composition module and F to be processed n The composition module of the offspring node corresponding to the child function characteristics of the server is determined as the offspring node to be processed; at the position to be closed F x n Corresponding M k F to be closed in the corresponding functional characteristic configuration file x n Setting the corresponding first type variable parameter information as a second identifier; in the functional characteristic configuration file corresponding to the component modules of the offspring node to be processed, F to be processed n The first type of variable parameter information of the sub-functional feature of (a) is set to the second identification.
It can be understood that when a certain sub-functional feature needs to be deleted, the sub-functional feature and the constituent module of the descendant node corresponding to the sub-functional feature are also provided with F corresponding to the sub-functional feature n The same sub-feature is deleted together. In the tree structure, offspring nodes of a node refer to all child nodes of the node, and all child nodes of the node until leaf nodes, wherein each node corresponds to a composition module.
As can be seen from the step A1-the step A3, the deletion of the functional features or the sub-functional features can be flexibly controlled by controlling the identification of the first type of the third information.
As an embodiment, when the new functional feature is needed, the step S4 further includes:
step B1, obtaining the functional characteristic F to be added r ，r>N。
Step B2, F r Splitting into g (r) sub-functional features { F 1 r ,F 2 r ,…,F z r ,…,F g(r) r }，F z r Is F r The z-th sub-feature of (2), the value of z ranges from 1 to g (r), and g (r) is F r The total number of sub-functional features of the system, g (r) is more than or equal to 1.
Step B3, establishing F 1 r And M is as follows 1 Corresponding relation of F p r Setting corresponding M i ,F p r Is F r P-th sub-feature of (2) and p ranges from 2 to g (r), M i For the ith chip to form a module, the value of i ranges from 2 to K, each of which is equal to F p r M for setting corresponding relation i The parent module must be identical to one of F z r And establishing a corresponding relation.
Step B4, at each F z r Corresponding M k Adding F to the functional feature configuration file of (1) z r Is provided with sub-function feature identification and parameter information corresponding to the sub-function feature.
Adding a certain functional feature to the chip can be achieved through steps B1-B4.
As an embodiment, in addition to adding functional features corresponding to the chip, sub-functional features may be added to the existing functional features, and the step S4 further includes:
step C1, obtaining the sub-functional feature F to be added g(n)+1 n 。
Step C2, slave { M 1 ,M 2 ,…,M k ,…,M K Select F in } g(n)+1 n Corresponding M i 。
Step C3, at F g(n)+1 n Corresponding M i Adding F to corresponding functional feature configuration files g(n)+1 n Is a sub-feature identification of (a) and a sub-featureCorresponding parameter information.
It should be noted that the step C1 to the step C3 can realize the step of adding F to the existing F n When the newly added sub-functional features are needed, the steps C1-C3 can be respectively implemented for the newly added sub-functional features.
As an embodiment, when the sub-functional feature needs to be adjusted, the step S4 further includes:
step D1, obtaining the sub-functional characteristic F to be adjusted x n The corresponding target adjustment parameters.
Step D2, adjusting the sub-function characteristic F x n M corresponding to i In the corresponding functional feature configuration file, the corresponding adjustable parameter in the second type of variable parameter information is updated to be the target adjustment parameter.
It should be noted that, the values or ranges of the adjustable parameters of the sub-functional features to be adjusted can be adjusted through the steps D1-D2.
As an embodiment, the preset file parser is provided with logic for converting a preset interpolation code type into an object code type, and in step S4, the parsing the interpolation code to generate a repetition code of a corresponding object code type includes:
and S41, analyzing the interpolation code to obtain repeated code logic and repeated number.
Step S42, calling the conversion logic from the corresponding preset interpolation code type to the target code type based on the preset interpolation code type and the target code type corresponding to the interpolation code, and generating the target code with the repetition number based on the repetition code logic in the interpolation code.
In the step S4, the file name of the target chip code file is set to "x.y", and "Y" is the file name suffix of the target chip code file.
It should be noted that some exemplary embodiments are described as a process or a method depicted as a flowchart. Although a flowchart depicts steps as a sequential process, many of the steps may be implemented in parallel, concurrently, or with other steps. Furthermore, the order of the steps may be rearranged. The process may be terminated when its operations are completed, but may have additional steps not included in the figures. The processes may correspond to methods, functions, procedures, subroutines, and the like.
The embodiment of the invention also provides electronic equipment, which comprises: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to perform the methods of embodiments of the present invention.
The embodiment of the invention also provides a computer readable storage medium, which stores computer executable instructions for executing the method according to the embodiment of the invention.
According to the embodiment of the invention, the non-repeated codes are directly encoded in the form of the target codes, the repeated codes are encoded in the form of the preset interpolation code type, the interpolation codes are set, the chip code text file to be processed is generated, and the chip code text file to be processed is stored in the chip code text file storage area, so that the storage space occupied by the chip code text file is reduced. And then analyzing the text file of the chip code to be processed through a preset file analyzer to generate a target chip code file, so that the generation efficiency of the chip code is improved.
The present invention is not limited to the above-mentioned embodiments, but is intended to be limited to the following embodiments, and any modifications, equivalents and modifications can be made to the above-mentioned embodiments without departing from the scope of the invention.

Claims (9)

1. A method for processing a chip code text file, comprising:
step S1, directly encoding a non-repeated code in a target code form, encoding the repeated code in a preset interpolation code type to set an interpolation code, setting a preset interpolation starting point identifier at the starting point of the interpolation code, setting a preset interpolation ending point identifier at the ending point of the interpolation code, and generating a chip code text file to be processed;
step S2, setting the file name of the chip code text file to be processed as XY.Z, wherein 'X' is a file identifier, 'Y' is target code type information, 'Z' is a preset file suffix, storing the chip code text file to be processed in a chip code text file storage area, and the file in the 'Z' format is a file which can be processed by a preset file analyzer;
s3, inputting the chip code text file to be processed into a preset file analyzer, analyzing the file name of the chip code text file to be processed by the file analyzer, and determining the type of the target code;
and S4, analyzing the text file of the chip code to be processed based on a preset file analyzer, for encoding in the form of an object code, when the code is analyzed to the interpolation code, extracting the interpolation code between the starting point identifier of the interpolation code and the key identifier of the corresponding interpolation code, analyzing the interpolation code, generating a repeated code in the form of the corresponding object code, replacing the corresponding interpolation code, and generating the object chip code file when all the code analysis is completed.
2. The method of claim 1, wherein the step of determining the position of the substrate comprises,
in the step S1, setting the interpolation code by encoding the repetition code with a preset interpolation code type includes:
step S11, directly setting chip functional feature configuration information, or generating the chip functional feature configuration information based on analysis of a functional feature configuration file corresponding to a pre-generated chip composition module;
and step S12, generating repeated code logic and repeated number according to the preset interpolation code type based on the chip functional characteristic configuration information.
3. The method of claim 2, wherein the step of determining the position of the substrate comprises,
in the step S11, the generating of the chip function feature configuration information based on the function feature configuration file analysis corresponding to the pre-generated chip composition module includes:
step S111, a functional feature configuration file corresponding to each chip composition module is obtained, wherein the functional feature configuration file comprises composition module identification information, global functional feature configuration information, first sub-functional feature configuration information, second sub-functional feature configuration information and third sub-functional feature configuration information, the first sub-functional feature configuration information is configuration information for chip design and verification scenes, the second sub-functional configuration information is configuration information only for verification scenes, and the third sub-functional feature configuration information is configuration information for realizing preset processing flows;
step S112, generating a design header file, a verification header file and a processing flow header file corresponding to the chip composition module based on the functional characteristic configuration files corresponding to the chip composition module and the functional characteristic configuration files corresponding to all descendant nodes of the chip composition module;
step S113, generating chip function feature configuration information based on the design header file, the verification header file and the processing flow header file corresponding to the chip composition module.
4. The method of claim 2, wherein the step of determining the position of the substrate comprises,
the preset file parser is provided with a logic for converting a preset interpolation code type into an object code type, and in the step S4, the process of parsing the interpolation code to generate a repetition code of a corresponding object code type includes:
s41, analyzing the interpolation code to obtain repeated code logic and repeated number;
step S42, calling the conversion logic from the corresponding preset interpolation code type to the target code type based on the preset interpolation code type and the target code type corresponding to the interpolation code, and generating the target code with the repetition number based on the repetition code logic in the interpolation code.
5. The method of claim 1, wherein the step of determining the position of the substrate comprises,
in the step S4, the file name of the target chip code file is set to "x.y", and "Y" is the file name suffix of the target chip code file.
6. The method of claim 1, wherein the step of determining the position of the substrate comprises,
the object code types include C/C++, java, verilog, VHDL and System Verilog languages, and the preset interpolation code types include Python, perl, ruby and Rust languages.
7. The method of claim 6, wherein the step of providing the first layer comprises,
when the preset interpolation code type is python language, the corresponding preset interpolation starting point identifier is < PY >, and the corresponding preset interpolation ending point identifier is </PY >;
when the preset interpolation code type is perl language, the corresponding preset interpolation starting point identifier is < PL >, and the corresponding preset interpolation ending point identifier is </PL >;
when the preset interpolation code type is ruby language, the corresponding preset interpolation starting point identifier is < RB >, and the corresponding preset interpolation ending point identifier is < RB >;
when the preset interpolation code type is RUST language, the corresponding preset interpolation starting point identifier is < RT >, and the corresponding preset interpolation ending point identifier is </RT >.
8. An electronic device, comprising:
at least one processor;
and a memory communicatively coupled to the at least one processor;
wherein the memory stores instructions executable by the at least one processor, the instructions being arranged to perform the method of any of the preceding claims 1-7.
9. A computer readable storage medium, characterized in that computer executable instructions are stored for performing the method of any of the preceding claims 1-7.
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