CN117573065B - Multifunctional shift operation device and operation method for processor - Google Patents
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Abstract
The invention belongs to the field of computer data processing, and discloses a multifunctional shift operation device and an operation method of a processor, wherein the device comprises an instruction decoding and data distribution device, a source operand preprocessing device, a source operand multiplexing device, a 4 n-bit high-low bit turning device 1, a multiplexer MUX1, a shift amount generating device, a 4 n-bit multifunctional right shift shifter, a 4 n-bit high-low bit turning device 2, a multiplexer MUX2, a shift result post-processing device and an output shift result selecting device; the invention can support the shift calculation requirements of shift operation types such as different bit widths, logic right shift, logic left shift, arithmetic right shift, cyclic left shift, cyclic right shift and the like, greatly saves transistor resources, reduces the area and the power consumption, has smaller influence on time sequence path delay, improves the universality, the adaptability and the performance of a processor, and is suitable for application scenes such as microcontrollers, digital signal processors, CPUs and the like.
Description
Technical Field
The invention belongs to the field of computer data processing, and particularly relates to a multifunctional shift operation device and an operation method of a processor.
Background
Shift computation has wide application in a number of computer science and engineering fields, such as data compression, image processing, bit level manipulation, numerical computation, cryptography, programming, and optimization. The shift operation has a plurality of shift types such as arithmetic right shift, logic left shift, cyclic right shift and the like, the shift operation types have different roles in different application scenes, the logic left shift and the logic right shift are commonly used for bit level operation and data processing, the arithmetic right shift is commonly used for arithmetic operation with a signed number, the cyclic left shift and the cyclic right shift are commonly used for realizing a circular data structure such as a cyclic buffer area and a cyclic queue and the like, the shift calculation can improve the efficiency of an algorithm and a program, the shift calculation is very important for processing binary data, performance optimization and code compactness, and a shifter of a modern processor often needs to support the shift operation with a plurality of types and bit widths and is usually completed in one clock cycle. Modern processors typically integrate implementation shifters to support the implementation of multiple types of shift instructions.
Barrel shifter (Barrel Shifter) is a common implementation of shifter in modern processors, is a purely combinational logic circuit mode capable of performing shifting operation according to the change of shift quantity, and can realize quick shifting of multi-bit wide data. The barrel shifter is implemented by cascading a plurality of multiplexers, each of which is responsible for shifting by one binary bit, a bit of the shift determining the choice of shifting the source operand by the quadratic bit of the weight or the choice of not shifting. By means of the control signal, the shift direction and the shift number of bits can be selected, thereby realizing different types of shift operations. Although the barrel shifter can perform shifting operation of a plurality of bits simultaneously in one clock cycle, has high-speed shifting capability, it requires more logic gates and connection lines, occupies a larger chip area, and increases the size and complexity of the barrel shifter for shifting operation of a larger number of bits, possibly resulting in an increase in power consumption and delay.
If the shift operations of various types and various bit widths are implemented separately, a large amount of combinational logic circuits are required to be consumed, so that it is important to consider combinational logic multiplexing of the shift operations of various types and bit widths, which can effectively reduce the chip area and the consumption of transistor resources, and reduce the chip cost. Multiplexing implementation of various types and bit widths of shift operations in barrel-shaped shifters still faces challenges, and unreasonable multiplexing design not only can cause increase of chip area, power consumption and cost, but also can cause increase of complexity of the shifter and increase of time delay, and affects main frequency of chips. In practical processor designs, an appropriate shift operation method and hardware implementation are generally selected according to requirements and performance requirements.
Disclosure of Invention
In order to solve the technical problems, the invention provides a multifunctional shift operation device and an operation method of a processor, so as to achieve the purposes of realizing multi-type shift operation, saving transistor resources, reducing area and reducing power consumption.
In order to achieve the above purpose, the technical scheme of the invention is as follows:
A processor multifunctional shift operation device comprises an instruction decoding and data distribution device, a source operand preprocessing device, a source operand multiplexing device, a4 n-bit high-low bit turning device 1, a multiplexer MUX1, a shift amount generating device, a4 n-bit multifunctional right shift shifter, a4 n-bit high-low bit turning device 2, a multiplexer MUX2, a shift result post-processing device and an output shift result selecting device; wherein n is a natural number;
the instruction decoding and data distribution module is responsible for decoding an instruction fetched by a processor pipeline instruction fetching stage to obtain a shift operation type and a shift direction, wherein the shift operation type is distributed to a source operand multiplexing device and an output shift result selecting device, the shift direction is distributed to a multiplexer MUX1 and a multiplexer MUX2, and the operand fetching 1 and the operand 2 are respectively distributed to a source operand preprocessing device and a shift amount generating device;
The source operand preprocessing device is responsible for preprocessing an operand 1, converting the operand 1 into a plurality of data forms and obtaining a plurality of source operand preprocessing results;
the source operand multiplexing device is responsible for selecting a corresponding operand 1 preprocessing result from a plurality of source operand preprocessing results according to a shift operation type;
The 4 n-bit high-low bit turning device 1 is responsible for 4 n-bit high-low bit turning treatment on a source operand pretreatment result to obtain an intermediate operand;
The multiplexer MUX1 is responsible for selecting a preprocessing result of a source operand according to a shift direction;
the shift amount generating device is responsible for processing the operand 2 to obtain a right shift amount;
the 4 n-bit multifunctional right shift shifter is responsible for right shift operation of the intermediate operand output by the multiplexer MUX1 according to the right shift amount output by the shift amount generating device;
the 4 n-bit high-low bit turning device 2 is responsible for performing 4 n-bit high-low bit turning on a right shift result of the 4 n-bit multifunctional right shift shifter;
The multiplexer MUX2 is responsible for selecting a right shift result of the 4 n-bit multifunctional right shift shifter according to the shift direction;
The shift result post-processing device is responsible for post-processing the output shift result, converting the shift result into a plurality of data forms and obtaining a plurality of output shift results;
The output shift result selecting device is responsible for selecting a corresponding data representation form from a plurality of output shift results generated by the shift result post-processing device according to the shift operation type, so that a shift calculation result of the final processor multifunctional shift operation device is obtained.
In the above solution, the 4 n-bit multifunctional right shifter is composed of multiplexers and right shift modules, which are right shift 1-bit module, right shift 2-bit module, right shift 4-bit module, right shift 8-bit module, right shift 16-bit module, up to -bit module, right shift 1-bit module, right shift 2-bit module, right shift 4-bit module, right shift 8-bit module, right shift 16-bit module, up to -bit module, and up to right shift modules shift up to intermediate operands temp0, temp1, temp2, temp3, temp4, temp ( -1) by 1, 2-bit, 4-bit, 8-bit, 16-bit up to -bit shift amounts, and multiplexers are respectively, and are respectively, multiplexer SMUX0, multiplexer SMUX1, multiplexer SMUX2, multiplexer SMUX3, multiplexer SMUX4 up to multiplexer SMUX ( -1).
A processor multifunctional shift operation method adopts the processor multifunctional shift operation device, and comprises the following steps:
(1) The instruction decoding and data distribution device decodes the instruction fetched by the instruction fetching stage to obtain a shift operation type and a shift direction, the shift operation type is distributed to the source operand multiplexing device, the shift direction is distributed to the multiplexer MUX1 and the multiplexer MUX2, and the operand 1 and the operand 2 are respectively distributed to the source operand preprocessing device and the shift amount generating device;
(2) The source operand preprocessing device preprocesses the operand 1, converts the operand 1 into a plurality of data forms, obtains a plurality of source operand preprocessing results and outputs the source operand preprocessing results to the source operand multiplexing device;
(3) The source operand multiplexing device selects a corresponding operand preprocessing result from a plurality of data forms output by the source operand preprocessing device according to the relation between the shift operation type and the source operand preprocessing result, and outputs the operand preprocessing result to the 4 n-bit high-low bit turning device 1 and the multiplexer MUX1;
(4) The 4 n-bit high-low bit turnover device 1 performs 4 n-bit high-low bit turnover on the output result of the source operand multiplexing device; then, the multiplexer MUX1 selects the data form to be output to the 4 n-bit multi-functional right shift shifter according to the shift direction, if the shift direction is right shift, the result of the source operand multiplexing device is selected to be directly output to the 4 n-bit multi-functional right shift shifter, and if the shift direction is left shift, the result of the 4 n-bit high-low bit turning device 1 is selected to be output to the 4 n-bit multi-functional right shift shifter;
(5) The operand 2 sent by the instruction decoding and data distribution device obtains displacement bit quantity through a displacement quantity generating device and outputs the displacement quantity to a 4 n-bit multifunctional right-shift shifter; then, the selection result of the multiplexer MUX1 is subjected to right shift operation through a 4 n-bit multifunctional right shift shifter, and the right shift amount is shift bits obtained by a shift amount generating device;
(6) The shift result of the 4 n-bit multifunctional right shift shifter is output to the multiplexer MUX2 and the 4 n-bit high-low bit turning device 2; the 4 n-bit high-low bit turnover device 2 performs 4 n-bit high-low bit turnover on the output result of the 4 n-bit multifunctional right shift shifter; the multiplexer MUX2 selects the data form output to the shift result post-processing device according to the shift direction, if the shift direction is right shift, the result of the 4 n-bit multifunctional right shift shifter is directly output to the shift result post-processing device, and if the shift direction is left shift, the result of the 4 n-bit high-low bit turnover device 2 is selectively output to the shift result post-processing device;
(7) The shift result post-processing device performs post-processing on the output result of the multiplexer MUX2 to generate a plurality of data representation forms, and the plurality of post-processing results generated by the device are output to the output shift result selecting device;
(8) The output shift result selecting device selects a corresponding post-processing shift result from a plurality of data forms output by the shift result post-processing device according to the relation between the shift operation type and the output shift result, and outputs the shift calculation result of the last multifunctional shift operation device.
In the scheme, in the shifting process of the 4 n-bit multifunctional right shifting shifter, except that the 4 n-bit arithmetic right shifting operation type is shifted into the sign bit of the right shifting operand, the other shifting operations are shifted into zero positions;
the right shift operand is directly transmitted to a multiplexer SMUX0 and a right shift 1-bit module, when the lowest bit shamt [0] of the shift quantity is set, the multiplexer SMUX0 selects the shift result of the right shift 1-bit module to be output to the multiplexer SMUX1 and the right shift 2-bit module, otherwise, the right shift operand is directly selected to be output;
When bit shamt [1] of the shift quantity is set, the shift result of the shift 2-bit module is selected by the multiplexer SMUX1 to be output to the multiplexer SMUX2 and the shift 4-bit module, otherwise, the intermediate operand temp1 is selected to be output;
when bit shamt [2] of the shift quantity is set, the shift result of the shift 4-bit module is selected by the multiplexer SMUX2 to be output to the multiplexer SMUX3 and the shift 8-bit module, otherwise, the intermediate operand temp2 is selected to be output;
when bit shamt [3] of the shift quantity is set, the shift result of the shift 8-bit module is selected by the multiplexer SMUX3 to be output to the multiplexer SMUX4 and the shift 16-bit module, otherwise, the intermediate operand temp3 is selected to be output;
when bit 4 shamt [4] of the shift quantity is set, the multiplexer SMUX4 selects the shift result output shifted to the right by 16 bits, otherwise, selects the intermediate operand temp4 output; and so on, carrying out times of the operations, thereby obtaining a 4 n-bit right shift result.
Through the technical scheme, the multifunctional shift operation device and the operation method for the processor have the following beneficial effects:
1. The multifunctional shift operation device of the processor realizes shift operation of various shift bit widths and shift types and provides more flexible shift operation for the processor. The processor may need to process data with different bit widths under different application scenes, for example, 8-bit, 16-bit, 32-bit or 64-bit data, and the shifter with multiple functions and different bit widths can enable the processor to execute displacement operation in different data types and applications, so that the universality, adaptability and performance of the processor are improved, and the requirements of different data types and application scenes can be better met.
2. According to the invention, the 4 n-bit high-low bit turnover device 1 and the 4 n-bit high-low bit turnover device 2 are added before and after the 4 n-bit multifunctional right shift shifter, so that multiplexing of the left shift logic to the right shift logic is realized; through the source operand preprocessing device, the source operand multiplexing device, the shift result post-processing device and the output shift result selecting device, as shown in the following specific embodiment, multiplexing of the 4-bit shift logic, the 8-bit shift logic and the 16-bit shift logic to the 32-bit shift logic is realized according to the corresponding relations between different shift operation types, source operand preprocessing results and output shift results shown in the table 1. Benefits of multiplexing resources to implement a multifunctional shift operation device mainly include saving hardware resources, reducing power consumption, and reducing the cost of the system. Multiplexing resources means that the multifunctional shifter may share certain hardware units instead of assigning individual hardware for each possible shift operation. Thus, the required hardware elements such as logic gates, registers and the like can be reduced, and the chip area and the power consumption are reduced. The cost of chip design and manufacture can be reduced by multiplexing hardware resources, which reduces the required silicon area and the number of physical elements, thereby reducing the cost of chip manufacture.
3. The invention supports 4n shift operations of 4n arithmetic right shift, 4n logic left shift, 2n arithmetic right shift, 2n logic left shift, 2n cyclic right shift 2n shift operations, n arithmetic right shift, n logical right shift, n cyclic left shift, n cyclic right shift, n shift operations of n cyclic right shift, etc. various bit widths and types of shift operations (the supported data bit width can be equal to 4n bit, 2n bit, n/2 bit, n/4 bit, and can be as low as 4 bit).
In general, the present invention provides various benefits in hardware design, including resource conservation, efficiency improvement, cost reduction, and system performance improvement, by multiplexing resources to implement a multi-functional shift operation device. Such designs are common practice in modern computer architectures to meet ever-increasing functional and performance requirements.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below.
Fig. 1 is a schematic diagram of a multifunctional shift operation device of a processor according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of a 32-bit multifunctional right shift shifter according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.
The invention provides a multifunctional shift operation device of a processor, which comprises the following specific embodiments:
As shown in fig. 1, the device comprises an instruction decoding and data distribution device, a source operand preprocessing device, a source operand multiplexing device, a 32-bit high-low bit turning device 1, a multiplexer MUX1, a shift amount generating device, a 32-bit multifunctional right shift shifter, a 32-bit high-low bit turning device 2, a multiplexer MUX2, a shift result post-processing device and an output shift result selecting device; in this embodiment, n=8; the functions of the respective devices are as follows:
1. Instruction decoding and data distribution module
The instruction decoding and data distribution module is responsible for decoding an instruction fetched by the instruction fetching stage of the processor pipeline to obtain a shift operation type and a shift direction, wherein the shift operation type is distributed to the source operand multiplexing device and the output shift result selecting device, the shift direction is distributed to the multiplexer MUX1 and the multiplexer MUX2, and the operand fetching 1 and the operand 2 are respectively distributed to the source operand preprocessing device and the shift amount generating device.
2. Source operand preprocessing device
The source operand preprocessing device is responsible for preprocessing an operand 1, converting the operand 1 into a plurality of data forms shown in table 1, and obtaining a plurality of source operand preprocessing results.
Table 1 correspondence between shift operation type and source operand preprocessing result:
3. Source operand multiplexing device
The source operand multiplexing means is responsible for selecting a corresponding operand 1 pre-processing result from a plurality of source operand pre-processing results according to the type of shift operation shown in table 1.
4. 32-Bit high-low bit turning device 1
The 32-bit high-low bit turning device 1 is responsible for performing 32-bit high-low bit turning processing on a source operand pretreatment result to obtain an intermediate operand.
5. Multiplexer MUX1
The multiplexer MUX1 is responsible for selecting the preprocessing result of the source operand according to the shift direction; if the shift direction is right shift, the result of the source operand multiplexing device is selected to be directly output to the 32-bit multifunctional right shift shifter, and if the shift direction is left shift, the result of the 32-bit high-low bit turning device 1 is selected to be output to the 32-bit multifunctional right shift shifter.
6. Displacement generation device
The shift amount generating means is responsible for processing the operand 2 to obtain a right shift amount.
7. 32-Bit multifunctional right shift shifter
The 32-bit multifunctional right shift shifter is responsible for right shift operation of the intermediate operand output by the multiplexer MUX1 according to the right shift amount output by the shift amount generating device.
As shown in fig. 2, the 32-bit multifunctional right shifter is composed of 5 multiplexers, a right shift 1-bit module, a right shift 2-bit module, a right shift 4-bit module, a right shift 8-bit module, and a right shift 16-bit module, wherein the right shift 1-bit module, the right shift 2-bit module, the right shift 4-bit module, the right shift 8-bit module, and the right shift 16-bit module are respectively used for shifting the intermediate operands temp0, temp1, temp2, temp3, temp4 to the right by 1-bit, 2-bit, 4-bit, 8-bit, and 16-bit, and the 5 multiplexers are respectively a multiplexer SMUX0, a multiplexer SMUX1, a multiplexer SMUX2, a multiplexer SMUX3, and a multiplexer SMUX4.
8. 32-Bit high-low bit turning device 2
The 32-bit high-low bit turning device 2 is responsible for performing 32-bit high-low bit turning processing on a right shift result of the 32-bit multifunctional right shift shifter.
9. Multiplexer MUX2
The multiplexer MUX2 is responsible for selecting the right shift result of the 32-bit multi-functional right shift shifter according to the shift direction.
10. Shift result post-processing device
The shift result post-processing device is responsible for post-processing the output shift results, converting the shift results into a plurality of data forms shown in table 1, and obtaining a plurality of output shift results.
11. Output shift result selecting device
The output shift result selecting means is responsible for selecting a corresponding data representation form from a plurality of output shift results generated by the shift result post-processing means according to the shift operation type shown in table 1, thereby obtaining a shift calculation result of the final processor multifunction shift operation means.
A processor multifunctional shift operation method adopts the processor multifunctional shift operation device, and comprises the following steps:
(1) The instruction decoding and data distribution device decodes the instruction fetched by the instruction fetching stage to obtain a shift operation type and a shift direction, the shift operation type is distributed to the source operand multiplexing device and the output shift result selecting device, the shift direction is distributed to the multiplexer MUX1 and the multiplexer MUX2, and the operand fetching 1 and the operand 2 are respectively distributed to the source operand preprocessing device and the shift amount generating device.
(2) The source operand preprocessing device preprocesses the operand1, generates Operand1[31:0] and other various data representation forms according to the source operand preprocessing result shown in table 1, and outputs the plurality of operand preprocessing results generated by the device to the source operand multiplexing device.
(3) The source operand multiplexing device selects the corresponding operand preprocessing result from the plurality of data forms output by the source operand preprocessing device according to the relation between the shift operation type and the source operand preprocessing result shown in table 1, for example, if the shift operation type is 32-bit operand right-shift, 32-bit logic right-shift or 32-bit logic left-shift, then the corresponding Operand [31:0] is selected, the selection of the source operand preprocessing result of other shift operation types is not repeated, and the result is output to the 32-bit high-low bit flipping device 1 and the multiplexer MUX1.
(4) The 32-bit high-low bit turning device 1 turns the output result of the source operand multiplexing device into 32-bit high-low bit; then, the multiplexer MUX1 selects the data format to be output to the 32-bit multi-functional right shifter according to the shift direction, and if the shift direction is right shift, the result of the source operand multiplexing device is selected to be directly output to the 32-bit multi-functional right shifter, and if the shift direction is left shift, the result of the 32-bit high/low bit flipping device 1 is selected to be output to the 32-bit multi-functional right shifter.
(5) The operand 2 sent by the instruction decoding and data distribution device obtains five-bit shift amount shamt [4:0] through a shift amount generating device, and outputs the shift amount to a 32-bit multifunctional right shift shifter; then, the selection result of the multiplexer MUX1 is right shifted by a 32-bit multifunctional right shifter, and the right shift amount is five-bit shift amount shamt [4:0] obtained by the shift amount generating device.
As shown in fig. 2, in the shifting process of the 32-bit multifunctional right shifter, except that the type of the 32-bit arithmetic right shifting operation is shifted into the sign bit of the right shifting operand, the other shifting operations are shifted into zero bits;
the right shift operand is directly transmitted to a multiplexer SMUX0 and a right shift 1-bit module, when the lowest bit shamt [0] of the shift quantity is set, the multiplexer SMUX0 selects the shift result of the right shift 1-bit module to be output to the multiplexer SMUX1 and the right shift 2-bit module, otherwise, the right shift operand is directly selected to be output;
When bit shamt [1] of the shift quantity is set, the shift result of the shift 2-bit module is selected by the multiplexer SMUX1 to be output to the multiplexer SMUX2 and the shift 4-bit module, otherwise, the intermediate operand temp1 is selected to be output;
when bit shamt [2] of the shift quantity is set, the shift result of the shift 4-bit module is selected by the multiplexer SMUX2 to be output to the multiplexer SMUX3 and the shift 8-bit module, otherwise, the intermediate operand temp2 is selected to be output;
when bit shamt [3] of the shift quantity is set, the shift result of the shift 8-bit module is selected by the multiplexer SMUX3 to be output to the multiplexer SMUX4 and the shift 16-bit module, otherwise, the intermediate operand temp3 is selected to be output;
When bit 4 shamt [4] of the shift quantity is set, the multiplexer SMUX4 selects the shift result output shifted right by 16 bits, otherwise selects the intermediate operand temp4 output, thereby obtaining a 32-bit shift result.
(6) The shifting result of the 32-bit multifunctional right shifting shifter is output to the multiplexer MUX2 and the 32-bit high-low bit turning device 2; the 32-bit high-low bit turning device 2 turns the output result of the 32-bit multifunctional right shift shifter into 32-bit high-low bits; the multiplexer MUX2 selects the data form output to the shift result post-processing device according to the shift direction, if the shift direction is right shift, the result of the 32-bit multifunctional right shift shifter is directly output to the shift result post-processing device, and if the shift direction is left shift, the result of the 32-bit high-low bit turnover device 2 is output to the shift result post-processing device;
(7) The shift result post-processing device performs post-processing on the output result of the multiplexer MUX2, generates a plurality of data representation forms such as result [31:0] and the like according to the output shift result shown in table 1, and outputs a plurality of post-processing results generated by the device to the output shift result selecting device;
(8) The output shift result selecting device selects a corresponding post-processing shift result from a plurality of data forms output by the shift result post-processing device according to the relation between the shift operation type and the output shift result shown in table 1, for example, the shift operation type is 32-bit arithmetic right shift and 32-bit logic right shift, then a corresponding result [31:0] is selected, the shift operation type is 32-bit logic left shift, then a corresponding result [0:31] is selected, the selection of the post-processing shift result about other shift operation types is not repeated, and the output shift result selecting device outputs the shift calculation result of the final multifunctional shift operation device.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (3)
1. The processor multifunctional shift operation device is characterized by comprising an instruction decoding and data distribution device, a source operand preprocessing device, a source operand multiplexing device, a 4 n-bit high-low bit turning device 1, a multiplexer MUX1, a shift amount generating device, a 4 n-bit multifunctional right shift shifter, a 4 n-bit high-low bit turning device 2, a multiplexer MUX2, a shift result post-processing device and an output shift result selecting device; wherein n is a natural number;
the instruction decoding and data distribution module is responsible for decoding an instruction fetched by a processor pipeline instruction fetching stage to obtain a shift operation type and a shift direction, wherein the shift operation type is distributed to a source operand multiplexing device and an output shift result selecting device, the shift direction is distributed to a multiplexer MUX1 and a multiplexer MUX2, and the operand fetching 1 and the operand 2 are respectively distributed to a source operand preprocessing device and a shift amount generating device;
The source operand preprocessing device is responsible for preprocessing an operand 1, converting the operand 1 into a plurality of data forms and obtaining a plurality of source operand preprocessing results;
the source operand multiplexing device is responsible for selecting a corresponding operand 1 preprocessing result from a plurality of source operand preprocessing results according to a shift operation type;
The 4 n-bit high-low bit turning device 1 is responsible for 4 n-bit high-low bit turning treatment on a source operand pretreatment result to obtain an intermediate operand;
The multiplexer MUX1 is responsible for selecting a preprocessing result of a source operand according to a shift direction;
the shift amount generating device is responsible for processing the operand 2 to obtain a right shift amount;
the 4 n-bit multifunctional right shift shifter is responsible for right shift operation of the intermediate operand output by the multiplexer MUX1 according to the right shift amount output by the shift amount generating device;
the 4 n-bit high-low bit turning device 2 is responsible for performing 4 n-bit high-low bit turning on a right shift result of the 4 n-bit multifunctional right shift shifter;
The multiplexer MUX2 is responsible for selecting a right shift result of the 4 n-bit multifunctional right shift shifter according to the shift direction;
The shift result post-processing device is responsible for post-processing the output shift result, converting the shift result into a plurality of data forms and obtaining a plurality of output shift results;
the output shift result selecting device is responsible for selecting a corresponding data representation form from a plurality of output shift results generated by the shift result post-processing device according to the shift operation type, so as to obtain a shift calculation result of the final processor multifunctional shift operation device;
The 4 n-bit multifunctional right shifter consists of multiplexers and right shift 1-bit module, right shift 2-bit module, right shift 4-bit module, right shift 8-bit module, right shift 16-bit module, up to right shift/> -bit module, i.e./> right shift modules, right shift 1-bit module, right shift 2-bit module, right shift 4-bit module, right shift 8-bit module, right shift 16-bit module, up to right shift -bit module/> right shift module shifts temp0, temp1, temp2, temp3, temp4, temp (/ > -1) the/> intermediate operands to right shift 1-bit, 2-bit, 4-bit, 8-bit, 16-bit until/> -bit shift amounts, respectively, for the/ multiplexers, i.e. multiplexer SMUX0, multiplexer SMUX1, multiplexer SMUX2, multiplexer SMUX3, multiplexer SMUX4 until multiplexer (/ > -ux 1).
2. A method for performing a multi-functional shift operation on a processor, using a multi-functional shift operation device according to claim 1, comprising the steps of:
(1) The instruction decoding and data distribution device decodes the instruction fetched by the instruction fetching stage to obtain a shift operation type and a shift direction, the shift operation type is distributed to the source operand multiplexing device and the output shift result selecting device, the shift direction is distributed to the multiplexer MUX1 and the multiplexer MUX2, and the operand fetching 1 and the operand 2 are respectively distributed to the source operand preprocessing device and the shift amount generating device;
(2) The source operand preprocessing device preprocesses the operand 1, converts the operand 1 into a plurality of data forms, obtains a plurality of source operand preprocessing results and outputs the source operand preprocessing results to the source operand multiplexing device;
(3) The source operand multiplexing device selects a corresponding operand preprocessing result from a plurality of data forms output by the source operand preprocessing device according to the relation between the shift operation type and the source operand preprocessing result, and outputs the operand preprocessing result to the 4 n-bit high-low bit turning device 1 and the multiplexer MUX1;
(4) The 4 n-bit high-low bit turnover device 1 performs 4 n-bit high-low bit turnover on the output result of the source operand multiplexing device; then, the multiplexer MUX1 selects the data form to be output to the 4 n-bit multi-functional right shift shifter according to the shift direction, if the shift direction is right shift, the result of the source operand multiplexing device is selected to be directly output to the 4 n-bit multi-functional right shift shifter, and if the shift direction is left shift, the result of the 4 n-bit high-low bit turning device 1 is selected to be output to the 4 n-bit multi-functional right shift shifter;
(5) The operand 2 sent by the instruction decoding and data distribution device obtains displacement bit quantity through a displacement quantity generating device and outputs the displacement quantity to a 4 n-bit multifunctional right-shift shifter; then, the selection result of the multiplexer MUX1 is subjected to right shift operation through a 4 n-bit multifunctional right shift shifter, wherein the right shift amount is/> shift amount obtained by a shift amount generating device;
(6) The shift result of the 4 n-bit multifunctional right shift shifter is output to the multiplexer MUX2 and the 4 n-bit high-low bit turning device 2; the 4 n-bit high-low bit turnover device 2 performs 4 n-bit high-low bit turnover on the output result of the 4 n-bit multifunctional right shift shifter; the multiplexer MUX2 selects the data form output to the shift result post-processing device according to the shift direction, if the shift direction is right shift, the result of the 4 n-bit multifunctional right shift shifter is directly output to the shift result post-processing device, and if the shift direction is left shift, the result of the 4 n-bit high-low bit turnover device 2 is selectively output to the shift result post-processing device;
(7) The shift result post-processing device performs post-processing on the output result of the multiplexer MUX2 to generate a plurality of data representation forms, and the plurality of post-processing results generated by the device are output to the output shift result selecting device;
(8) The output shift result selecting device selects a corresponding post-processing shift result from a plurality of data forms output by the shift result post-processing device according to the relation between the shift operation type and the output shift result, and outputs the shift calculation result of the last multifunctional shift operation device.
3. The method of claim 2, wherein during the shifting of the 4 n-bit multi-functional right shifter, the other shifting operations are shifted into zero bits except that the 4 n-bit operand right shifting operation type is shifted into the sign bit of the right shifting operand;
the right shift operand is directly transmitted to a multiplexer SMUX0 and a right shift 1-bit module, when the lowest bit shamt [0] of the shift quantity is set, the multiplexer SMUX0 selects the shift result of the right shift 1-bit module to be output to the multiplexer SMUX1 and the right shift 2-bit module, otherwise, the right shift operand is directly selected to be output;
When bit shamt [1] of the shift quantity is set, the shift result of the shift 2-bit module is selected by the multiplexer SMUX1 to be output to the multiplexer SMUX2 and the shift 4-bit module, otherwise, the intermediate operand temp1 is selected to be output;
when bit shamt [2] of the shift quantity is set, the shift result of the shift 4-bit module is selected by the multiplexer SMUX2 to be output to the multiplexer SMUX3 and the shift 8-bit module, otherwise, the intermediate operand temp2 is selected to be output;
when bit shamt [3] of the shift quantity is set, the shift result of the shift 8-bit module is selected by the multiplexer SMUX3 to be output to the multiplexer SMUX4 and the shift 16-bit module, otherwise, the intermediate operand temp3 is selected to be output;
When bit 4 shamt [4] of the shift quantity is set, the multiplexer SMUX4 selects the shift result output shifted to the right by 16 bits, otherwise, selects the intermediate operand temp4 output; and so on, carrying out times of the operations, thereby obtaining a 4 n-bit right shift result. /(I)
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