CN117572932A - MMCM-based on-chip digital clock calibration method and system - Google Patents
MMCM-based on-chip digital clock calibration method and system Download PDFInfo
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- CN117572932A CN117572932A CN202311384840.8A CN202311384840A CN117572932A CN 117572932 A CN117572932 A CN 117572932A CN 202311384840 A CN202311384840 A CN 202311384840A CN 117572932 A CN117572932 A CN 117572932A
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- 238000000034 method Methods 0.000 title claims abstract description 21
- 230000010363 phase shift Effects 0.000 claims description 13
- 238000010586 diagram Methods 0.000 description 2
- 230000002457 bidirectional effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
Abstract
The invention discloses an on-chip digital clock calibration method and system based on an on-chip mixed clock manager (MMCM), and belongs to the technical field of time synchronization. The method comprises the following steps: determining the initial phase adjustment times and the initial phase adjustment direction of the MMCM according to the phase difference between the local clock and the target node clock and the phase difference between the calibration clock and the local clock; adjusting the MMCM phase according to the phase adjustment direction, the MMCM initial phase adjustment times and the set MMCM single adjustment steps to complete initial phase adjustment; calculating an MMCM phase adjustment period and a phase adjustment direction according to the frequency difference between the local clock and the clock of the destination node and the local clock period; the MMCM phase is adjusted according to the phase adjustment period and the phase adjustment direction. The invention occupies less hardware resources and can complete the clock frequency and phase calibration function without an external hardware circuit.
Description
Technical Field
The invention belongs to the technical field of time synchronization, and particularly relates to an on-chip digital clock calibration method and system based on an on-chip mixed clock manager (MMCM).
Background
In a distributed collaborative detection network, clock coherence between nodes is an important factor affecting system indexes. Due to space limitations and other factors, independent clock sources are often used as system clocks among multiple nodes. The frequency difference and the phase difference of the two sides can be obtained through the technologies of bidirectional time transfer and the like, however, how to calibrate the clock signal with the same frequency and the same phase as the destination node through the frequency difference and the phase difference is a technical difficulty.
The prior patent with the patent number of 202110584365.3 discloses a digital clock calibration method, and when the RTC timer is interrupted, a counter T16 is started; determining a first count value of the counter T16 in a first interrupt period of the RTC timer; determining a counting error value and a clock compensation type according to the first counting value and the calibrated second counting value; and performing timing calibration of the clock signal according to the second count value, the count error value and the clock compensation type. The method occupies more hardware resources, and can complete the clock frequency and phase calibration function only by an external hardware circuit.
Disclosure of Invention
The invention discloses an on-chip digital clock calibration method based on MMCM, which utilizes the accurate phase adjustment function of an on-chip mixed clock manager (MMCM) to realize the clock calibration function without an external clock generating device.
The technical scheme for realizing the purpose of the invention is as follows: an on-chip digital clock calibration method based on MMCM, comprising:
determining the initial phase adjustment times and the initial phase adjustment direction of the MMCM according to the phase difference between the local clock and the target node clock and the phase difference between the calibration clock and the local clock;
adjusting the MMCM phase according to the phase adjustment direction, the MMCM initial phase adjustment times and the set MMCM single adjustment steps to complete initial phase adjustment;
calculating an MMCM phase adjustment period and a phase adjustment direction according to the frequency difference between the local clock and the clock of the destination node and the local clock period;
the MMCM phase is adjusted according to the phase adjustment period and the phase adjustment direction.
Preferably, when the frequency difference or phase difference between the local clock and the destination node clock is updated, the MMCM initial phase and the MMCM phase adjustment are performed again.
Preferably, the initial phase adjustment times are specifically:
wherein Δp is the phase difference between the local clock and the target node clock, p0 is the phase difference between the calibration clock and the local clock, t0 is the set single adjustment step of the MMCM, and N is the initial phase adjustment times of the MMCM.
Preferably, the initial phase adjustment direction is determined based on the value of Δp-p0, and when Δp-p0 is greater than 0, the MMCM initial phase is adjusted forward, otherwise adjusted backward.
Preferably, the phase adjustment period is specifically:
in the formula, Δf is the frequency difference between the local clock and the destination node clock, T0 is the set MMCM single adjustment step, and T is the local clock period.
Preferably, if the frequency difference between the local clock and the destination node clock is greater than 0, the MMCM phase is adjusted forward, otherwise, the MMCM phase is adjusted backward.
Compared with the prior art, the invention has the remarkable advantages that: the invention occupies less hardware resources, and can complete the clock frequency and phase calibration function without an external hardware circuit; the invention has fast locking period, and clock locking can be completed by inputting the frequency difference and the phase difference result for a single time; the invention has the function of self-keeping time, and can keep the clock locking even if no frequency difference or phase difference input exists in a certain time.
Drawings
Fig. 1 is a schematic diagram of an MMCM-based digital clock calibration system on chip in accordance with the present invention.
Fig. 2 is a schematic diagram of an MMCM-based digital clock calibration system on chip in accordance with the present invention.
Fig. 3 is a flow chart of an MMCM-based on-chip digital clock calibration method in the present invention.
Detailed Description
The invention will now be described in detail with reference to the drawings and examples.
As shown in fig. 1 and 3, an on-chip digital clock calibration method based on MMCM includes the following steps:
step 1: determining the initial phase adjustment times and the initial phase adjustment direction of the MMCM according to the phase difference between the local clock and the target node clock and the phase difference between the calibration clock and the local clock;
in a further embodiment, the initial phase adjustment times are specifically:
wherein Δp is the phase difference between the local clock and the target node clock, p0 is the phase difference between the calibration clock and the local clock, t0 is the set single adjustment step of the MMCM, and N is the initial phase adjustment times of the MMCM.
And determining an initial phase adjustment direction according to the value of delta p-p0, when delta p-p0 is larger than 0, adjusting the initial phase of the MMCM forwards, increasing the phase by N x t0, changing the phase difference between the calibration clock and the local clock to p1=p0+N x t0, otherwise, adjusting backwards, reducing the phase by N x t0, and changing the phase difference between the calibration clock and the local clock to p1=p0-N x t0.
Step 2: adjusting the MMCM phase according to the phase adjustment direction, the MMCM initial phase adjustment times and the set MMCM single adjustment steps to complete initial phase adjustment;
in a further embodiment, the phase adjustment period is specifically:
in the formula, Δf is the frequency difference between the local clock and the destination node clock, T0 is the set MMCM single adjustment step, and T is the local clock period.
In a further embodiment, the phase adjustment direction is determined according to the frequency difference between the local clock and the destination node clock, if the frequency difference between the local clock and the destination node clock is greater than 0, the MMCM phase is adjusted forward, the phase is increased by t0, the phase difference between the calibration clock and the local clock becomes p2=p1+t0, otherwise, the MMCM phase is adjusted backward, the phase is reduced by t0, and the phase difference between the calibration clock and the local clock becomes p2=p1-t 0.
Step 3: calculating an MMCM phase adjustment period and a phase adjustment direction according to the frequency difference between the local clock and the clock of the destination node and the local clock period;
step 4: the MMCM phase is adjusted according to the phase adjustment period and the phase adjustment direction.
In a further embodiment, if the frequency difference or the phase difference between the local clock and the clock of the destination node is updated, the method returns to step 1 to perform calibration again, otherwise, the method of step 4 is continuously used for calibration.
As shown in fig. 2, an MMCM-based on-chip digital clock calibration system, comprising:
a phase shift parameter calculation circuit, a timing control circuit, a calibration clock phase calculation circuit and an MMCM; wherein:
the phase shift parameter calculation circuit is used for responding to the trigger signal and determining the MMCM initial phase adjustment times and the initial phase adjustment direction according to the phase difference between the local clock and the target node clock and the phase difference between the calibration clock and the local clock; the MMCM phase adjustment period and the phase adjustment direction are calculated according to the frequency difference between the local clock and the clock of the destination node and the local clock period;
the time sequence control circuit is used for carrying out initial phase adjustment and phase adjustment on the MMCM according to the MMCM initial phase adjustment times and the initial phase adjustment direction which are determined by the phase shift parameter calculation circuit, and the MMCM phase adjustment period and the phase adjustment direction;
MMCM, used for outputting the calibration clock after phase adjustment;
and the calibration clock phase calculation circuit is used for calculating the phase value of the calibration clock according to the phase adjustment value of the time sequence control circuit.
In a further embodiment, the on-chip digital clock calibration system based on the MMCM further includes a first timer, where the first timer value is set to an initial phase adjustment number, and the timer is decremented by one each time the MMCM completes the phase shift operation, and the initial phase adjustment is completed after the timer is cleared.
In a further embodiment, the MMCM-based on-chip digital clock calibration system further comprises a second timer, the second timer value being set to a phase adjustment period, the second timer value being decremented by one each clock period, and when the second timer value is 1, the phase shifting operation is completed once according to the phase adjustment direction and the second timer value is reset to the phase adjustment period.
The working process of the on-chip digital clock calibration system based on MMCM is as follows:
when the phase shift parameter calculation circuit receives an externally input trigger signal, determining MMCM initial phase adjustment times and initial phase adjustment directions according to the phase difference between an input local clock and a target node clock and the phase difference between a calibration clock and the local clock;
the initial phase adjustment times are specifically:
wherein Δp is the phase difference between the local clock and the target node clock, p0 is the phase difference between the calibration clock and the local clock, t0 is the set single adjustment step of the MMCM, and N is the initial phase adjustment times of the MMCM.
And determining an initial phase adjustment direction according to the value of delta p-p0, and adjusting the initial phase of the MMCM forwards when the delta p-p0 is larger than 0, otherwise, adjusting backwards.
The time sequence control circuit carries out initial phase adjustment on the MMCM according to the MMCM initial phase adjustment times and the initial phase adjustment direction determined by the phase shift parameter calculation circuit; setting the first timer value as the initial phase adjustment times, subtracting one timer from the MMCM every time the phase shifting operation is completed, and completing the initial phase adjustment after the timer is cleared.
The phase shift parameter calculation circuit calculates an MMCM phase adjustment period and a phase adjustment direction according to the frequency difference between the local clock and the target node clock and the local clock period, wherein the phase adjustment period is specifically as follows:
in the formula, Δf is the frequency difference between the local clock and the destination node clock, T0 is the set MMCM single adjustment step, and T is the local clock period.
If the frequency difference between the local clock and the destination node clock is greater than 0, the MMCM phase is adjusted forward, otherwise, the MMCM phase is adjusted backward.
The time sequence control circuit carries out phase adjustment on the MMCM according to the MMCM phase adjustment period and the phase adjustment direction determined by the phase shift parameter calculation circuit;
the MMCM outputs the phase-adjusted calibration clock.
Claims (10)
1. An on-chip digital clock calibration method based on MMCM, comprising:
determining the initial phase adjustment times and the initial phase adjustment direction of the MMCM according to the phase difference between the local clock and the target node clock and the phase difference between the calibration clock and the local clock;
adjusting the MMCM phase according to the phase adjustment direction, the MMCM initial phase adjustment times and the set MMCM single adjustment steps to complete initial phase adjustment;
calculating an MMCM phase adjustment period and a phase adjustment direction according to the frequency difference between the local clock and the clock of the destination node and the local clock period;
the MMCM phase is adjusted according to the phase adjustment period and the phase adjustment direction.
2. The MMCM-based on-chip digital clock calibration method of claim 1, wherein the MMCM initial phase and MMCM phase adjustment are performed again when the frequency difference or phase difference between the local clock and the destination node clock is updated.
3. The MMCM-based on-chip digital clock calibration method of claim 1, wherein the initial phase adjustment times are specifically:
wherein Δp is the phase difference between the local clock and the target node clock, p0 is the phase difference between the calibration clock and the local clock, t0 is the set single adjustment step of the MMCM, and N is the initial phase adjustment times of the MMCM.
4. The MMCM-based on-chip digital clock calibrating method according to claim 3, wherein the initial phase adjustment direction is determined according to a value of Δp-p0, and when Δp-p0 is greater than 0, the MMCM initial phase is adjusted forward, otherwise adjusted backward.
5. The MMCM-based on-chip digital clock calibration method of claim 3, wherein after the forward adjustment, the phase difference between the calibration clock and the local clock becomes p1=p0+n x t0, and after the backward adjustment, the phase difference between the calibration clock and the local clock becomes p1=p0-N x t0.
6. The MMCM-based on-chip digital clock calibration method of claim 1, wherein the phase adjustment period is specifically:
in the formula, Δf is the frequency difference between the local clock and the destination node clock, T0 is the set MMCM single adjustment step, and T is the local clock period.
7. The MMCM-based on-chip digital clock calibration method of claim 1, wherein the phase adjustment direction is specifically: if the frequency difference between the local clock and the destination node clock is greater than 0, the MMCM phase is adjusted forward, otherwise, the MMCM phase is adjusted backward.
8. An MMCM-based on-chip digital clock calibration system, comprising:
a phase shift parameter calculation circuit, a timing control circuit, a calibration clock phase calculation circuit and an MMCM; wherein:
the phase shift parameter calculation circuit is used for responding to the trigger signal and determining the MMCM initial phase adjustment times and the initial phase adjustment direction according to the phase difference between the local clock and the target node clock and the phase difference between the calibration clock and the local clock; the MMCM phase adjustment period and the phase adjustment direction are calculated according to the frequency difference between the local clock and the clock of the destination node and the local clock period;
the time sequence control circuit is used for carrying out initial phase adjustment and phase adjustment on the MMCM according to the MMCM initial phase adjustment times and the initial phase adjustment direction which are determined by the phase shift parameter calculation circuit, and the MMCM phase adjustment period and the phase adjustment direction;
MMCM, used for outputting the calibration clock after phase adjustment;
and the calibration clock phase calculation circuit is used for calculating the phase value of the calibration clock according to the phase adjustment value of the time sequence control circuit.
9. The MMCM-based on-chip digital clock calibration system of claim 8, further comprising a first timer, the first timer value being set to an initial number of phase adjustments, the MMCM completing the initial phase adjustment after zero clearing each time the MMCM completes a phase shift operation.
10. The MMCM based on-chip digital clock calibration system of claim 8, further comprising a second timer, the second timer value being set to a phase adjustment period, the second timer value being decremented by one for each clock period, and when the second timer value is 1, a phase shift operation is completed according to the phase adjustment direction and the second timer value is reset to the phase adjustment period.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202311384840.8A CN117572932A (en) | 2023-10-24 | 2023-10-24 | MMCM-based on-chip digital clock calibration method and system |
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| CN202311384840.8A CN117572932A (en) | 2023-10-24 | 2023-10-24 | MMCM-based on-chip digital clock calibration method and system |
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| CN117572932A true CN117572932A (en) | 2024-02-20 |
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- 2023-10-24 CN CN202311384840.8A patent/CN117572932A/en active Pending
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