CN117572930A - Digital circuit working voltage generating circuit, oscillator circuit and chip - Google Patents
Digital circuit working voltage generating circuit, oscillator circuit and chip Download PDFInfo
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- CN117572930A CN117572930A CN202311595719.XA CN202311595719A CN117572930A CN 117572930 A CN117572930 A CN 117572930A CN 202311595719 A CN202311595719 A CN 202311595719A CN 117572930 A CN117572930 A CN 117572930A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/02—Details
- H03B5/04—Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
- G05F3/262—Current mirrors using field-effect transistors only
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Abstract
The embodiment of the invention provides a digital circuit working voltage generating circuit, an oscillator circuit and a chip, which relate to the technical field of integrated circuits, wherein the digital circuit comprises a MOS device; the working voltage generating circuit comprises at least one first MOS device, and generates a first working voltage as the working voltage of the digital circuit based on the Vgs voltage when the first MOS device is conducted; the first working voltage is M Vgs, M is greater than 1, and M is less than the power voltage of the working voltage generating circuit. Based on the thought of the invention, no matter how the on voltage of the MOS device changes, the first working voltage can ensure the normal work of the digital circuit, and compared with the prior art that the power supply voltage is adopted as the working voltage of the digital circuit, the working voltage provided by the invention for the digital circuit can effectively reduce the power consumption of the digital circuit.
Description
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a digital circuit operating voltage generating circuit, an oscillator circuit, and a chip.
Background
Integrated circuit products typically include digital circuits composed of MOS devices such as and gates, or gates, not gates (inverters), and the like. At present, the working voltage of a digital circuit is generally the power supply voltage of the integrated circuit product, and the digital circuit is only used for outputting a level signal capable of representing logic '1' or logic '0', so that the working based on the power supply voltage easily causes higher power consumption and waste of power consumption. Based on this, some prior arts propose to use a fixed voltage lower than the power supply voltage as an operating voltage of the digital circuit to reduce the circuit power consumption.
However, parameters such as on-voltage of the MOS devices vary greatly between different chips on the same wafer and between chips on different batches of wafers due to process manufacturing, etc., which results in different on-speeds of the MOS devices. This phenomenon is known in the art as process corner, limiting the speed fluctuation range of NMOS and PMOS transistors to within a rectangle defined by four corners. The four angles are fast NFET and fast PFET, slow NFET and slow PFET, fast NFET and slow PFET, slow NFET and fast PFET, respectively. Based on this division criterion, the on-voltage (usually denoted by Vth) of the MOS devices in different chips will be in different ranges, even between different chips of the same type or different chips of the same lot. Meanwhile, the on-voltage of the MOS device is also changed by the influence of temperature. Therefore, in the same application, if a fixed voltage lower than the power supply voltage is only input into the integrated circuit product at a glance to serve as the working voltage in the integrated circuit product, the digital circuit in the integrated circuit product cannot work normally for the integrated circuit product in which the conduction threshold of the MOS transistor is greater than the fixed voltage, and the digital circuit in the integrated circuit product still has the problem of wasting power consumption for the integrated circuit product in which the conduction threshold of the MOS transistor is less than the fixed voltage.
Disclosure of Invention
The invention provides a digital circuit working voltage generating circuit, an oscillator circuit and a chip, which aim to provide a first working voltage for a digital circuit through the working voltage generating circuit, the first working voltage can ensure the normal working of the digital circuit no matter how the on voltage of an MOS device changes, and compared with the prior art that the power supply voltage is used as the working voltage of the digital circuit, the first working voltage provided for the digital circuit can effectively reduce the power consumption of the digital circuit.
In order to solve the above-described problems, from a first aspect, the present invention discloses a digital circuit operating voltage generating circuit, the digital circuit including a MOS device;
the working voltage generating circuit comprises at least one first MOS device, and generates a first working voltage as the working voltage of the digital circuit based on the Vgs voltage when the first MOS device is conducted;
the first working voltage is M Vgs, M is greater than 1, and M is less than the power voltage of the working voltage generating circuit.
In one possible embodiment of the present invention, the operating voltage generating circuit includes:
a current generation module generating a driving current based on a power supply voltage;
the first voltage generation module is used for generating driving voltage according to the driving current and N+1 first MOS devices which are sequentially connected in series, wherein N is more than or equal to 1 and less than M is less than N+1;
The second voltage generation module is used for generating a first working voltage according to the driving voltage.
In one possible embodiment of the present invention, the operating voltage generating circuit includes:
a current generation module generating a driving current based on a power supply voltage;
the first voltage generation module is used for generating a driving voltage according to the driving current and at least one first MOS device and resistor therein;
the second voltage generation module is used for generating a first working voltage according to the driving voltage.
In one possible embodiment of the present invention, the first MOS device is an NMOS device with a shorted gate drain.
In one possible embodiment of the present invention, the second voltage generating module includes: a first NMOS device and a capacitor; the first NMOS device and the capacitor are connected in series between the power supply voltage and the ground; the first NMOS device is conducted based on the driving voltage, so that the capacitor is charged to generate a first working voltage.
In a possible embodiment of the present invention, the second voltage generating module further includes: and the voltage-resistant element is connected between the first NMOS device and the power supply voltage so as to protect the first NMOS device.
In a possible embodiment of the present invention, the operating voltage generating circuit is further configured to adjust the operating voltage of the digital circuit from the first operating voltage to the second operating voltage when the power supply voltage is lower than the threshold voltage; the second working voltage is VDD-K, VDD is the power supply voltage, and K is a constant.
In one possible embodiment of the present invention, the operating voltage generating circuit further includes:
the detection module is used for detecting the driving current flowing through the first MOS device and generating a detection signal, wherein the driving current is generated based on the power supply voltage and is reduced along with the reduction of the power supply voltage, and the detection signal is used for representing that the power supply voltage is lower than the threshold voltage when the detection signal is effective;
the second voltage generating module is further configured to adjust the first operating voltage to a second operating voltage according to at least the power supply voltage when the detection signal is valid.
In one possible embodiment of the present invention, the current generating module includes a first PMOS device, a source terminal of the first PMOS device is connected to a power supply voltage, and a drain terminal of the first PMOS device is connected to the first voltage generating module;
the detection module comprises a second PMOS device and a second NMOS device which are mutually connected in series, the second PMOS device is connected with a power supply voltage, the second NMOS device is grounded, the second PMOS device and the first PMOS device form a current mirror, the second NMOS device and the first MOS device form a current mirror, and the first MOS device is an NMOS device with a short circuit of a grid drain end;
the node between the second PMOS device and the second NMOS device is used for generating a detection signal; when the detection signal is at a high level, the detection signal is valid.
In one possible embodiment of the present invention, the second voltage generating module includes a first NMOS device, a capacitor, and a switching tube; the first NMOS device and the capacitor are connected in series between the power supply voltage and the ground; the first NMOS device is conducted based on the driving voltage output by the first voltage generation module; the switch tube is used for being conducted when the detection signal is effective, so that the power supply voltage at least charges the capacitor through the switch tube to generate a second working voltage on the capacitor.
In a possible implementation manner of the present invention, the switching tube is a third PMOS device, and the working voltage generating circuit further includes an inverter; the source end of the third PMOS device is connected with the drain end of the first NMOS device, and the drain end of the third PMOS device is connected with the capacitor; the detection signal is input to the gate end of the third PMOS device through the inverter, so that the third PMOS device is turned on when the detection signal is effective.
Based on the same inventive concept, from a second aspect, the present invention also discloses an oscillator circuit comprising:
and a digital circuit operating voltage generating circuit according to the first aspect of the embodiment of the present invention;
the digital circuit is used for receiving the clock signal so as to shape the clock signal generated in the oscillator circuit based on the first working voltage with the magnitude of M Vgs provided by the working voltage generating circuit; m > 1 and M x Vgs < the supply voltage of the operating voltage generating circuit.
Further, the digital circuit is an inverter including a MOS device.
Based on the same inventive concept, from a third aspect, the invention also discloses a chip, which comprises the digital circuit operating voltage generating circuit according to the first aspect of the embodiment of the invention, or comprises the oscillator circuit according to the second aspect of the embodiment of the invention.
In a possible embodiment of the present invention, the chip is a lithium battery management chip.
The embodiment of the invention has the following advantages:
in the embodiment of the invention, the digital circuit and the working voltage generating circuit form the digital circuit working voltage generating circuit, namely, the digital circuit and the working voltage generating circuit are certainly in an integrated circuit product such as a chip, so that the MOS device in the digital circuit and the MOS device in the working voltage generating circuit are in the same process angle range, the conducting voltage of the MOS device in the digital circuit and the conducting voltage of the first MOS device in the working voltage generating circuit are considered to be in the same range (the same range depends on the chip or the PCB board, such as the same chip, the range is smaller), and on the basis, the first MOS device and the MOS device in the digital circuit have the same response to the change of the external environment and the change of the process angle, namely, when the conducting voltage of the MOS device in the digital circuit changes along with the process angle or along with the external temperature, the conducting voltage of the first MOS device in the working voltage generating circuit basically changes equivalently. Because the Vgs voltage of the present invention is a voltage that can turn on the first MOS device, it can be considered that the Vgs voltage is always greater than the on voltage Vth of the first MOS device regardless of the variation of the on voltage of the first MOS device. When the on voltage Vth of the first MOS device changes, the Vgs voltage also changes, and the first operating voltage M generated based on the Vgs also changes, so that the operating voltage generating circuit generates the first operating voltage based on the Vgs voltage when the first MOS device is turned on to serve as the operating voltage of the digital circuit, and the relationship between the operating voltage of the digital circuit and the Vgs voltage is established on the surface, and the relationship between the operating voltage and the on voltage of the MOS device in the digital circuit is substantially established, so that the MOS device in the digital circuit can be ensured to normally operate. Compared with the prior art that the power supply voltage is used as the working voltage of the digital circuit, the power consumption of the digital circuit can be effectively reduced by the working voltage provided by the invention to the digital circuit.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention.
FIG. 1 is a schematic diagram of a digital circuit operating voltage generating circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a digital circuit, a CMOS inverter;
FIG. 3 is a schematic diagram of the structure of two digital circuits, NMOS and PMOS;
FIG. 4 is a schematic diagram of the operating voltage generating circuit shown in FIG. 1;
FIG. 5 is another schematic diagram of the operating voltage generating circuit shown in FIG. 1;
FIG. 6 is a schematic diagram of another configuration of the operating voltage generating circuit shown in FIG. 1;
FIG. 7 is a block diagram of an alternative digital circuit operating voltage generating circuit according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of the operating voltage generating circuit shown in FIG. 7;
FIG. 9 is a block diagram of an oscillator circuit according to an embodiment of the present invention;
FIG. 10 is a block diagram of a chip according to an embodiment of the invention;
FIG. 11 is a block diagram of another chip according to an embodiment of the invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments.
The embodiment of the invention provides a digital circuit working voltage generating circuit, which comprises a MOS device; referring to fig. 1, the operating voltage generating circuit includes at least one first MOS device, and generates a first operating voltage as an operating voltage of the digital circuit based on Vgs voltages when the first MOS device is turned on; the first working voltage is M Vgs, M is greater than 1, and M is less than the power voltage VDD of the working voltage generating circuit.
In the embodiment of the invention, the digital circuit refers to a digital circuit including one or more MOS devices, and may specifically be an and gate, an or gate, a not gate, a nand gate, a nor gate, and the like. In other words, the digital circuits such as and gate, or gate, nor gate are all constituted by at least MOS devices.
The MOS device refers to a Metal Oxide Semiconductor (MOS) field effect transistor, or a metal insulator semiconductor (MOS) device, which may be simply referred to as a MOS transistor or a MOS transistor. In the embodiment of the invention, the MOS device can be an NMOS device or a PMOS device, and for a digital circuit, the MOS device can only comprise any one of the NMOS device and the PMOS device, or can also comprise the NMOS device and the PMOS device at the same time.
The inverter is one of the most basic gates in the digital circuit, and in order to facilitate understanding of the present solution, the following takes the digital circuit as a CMOS inverter as an example, to further describe the background technology and the inventive concept of the present invention:
as shown in fig. 2, the CMOS inverter is composed of an NMOS device and a PMOS device, the gate terminals of the NMOS device and the PMOS device are connected as input terminals, the drain terminal is connected as output terminals, the source terminal of the NMOS device is grounded, and the source terminal of the PMOS device is connected to its operating voltage (represented by the operating voltage Vx, which may be understood as the voltage that supplies power to the CMOS device) to form a series structure. In the drawings of the present invention, the power supply voltage is represented by VDD, and the ground voltage is represented by VSS.
In order to ensure that the CMOS inverter operates normally, the connected operating voltage Vx needs to be greater than the greater of the on-voltage Vth1 of the NMOS device and the on-voltage Vth2 of the PMOS device. The input and output signals of the inverter are digital signals, and the NMOS device and the PMOS device are respectively driven to be conducted through a low-level signal and a high-level signal. When the input end is a low-level signal of 0V, the NMOS device is turned off, the PMOS device is turned on, and the output end outputs a high-level signal with the voltage of Vx; when the input end is a high-level signal which is larger than the conduction voltage Vth1 of the NMOS device, the NMOS device is turned on, the PMOS device is turned off, and the output end outputs a low-level signal with the ground level (usually 0V), so that the logical NOT function is realized.
In a digital circuit, under the condition that an MOS device is conducted, the internal resistance of the MOS device is smaller, and the power consumption of the MOS device at the moment is directly related to the working voltage of the digital circuit. In the prior art, the power supply voltage of an integrated circuit product (the integrated circuit product may be a chip or an integrated circuit integrated on a PCB) is taken as the working voltage of the CMOS inverter therein, that is, vx=the power supply voltage in the prior art, based on the foregoing, it is known that Vx is only required to be greater than the larger one of the conduction voltage Vth1 of the NMOS device and the conduction voltage Vth2 of the PMOS device, in general, the conduction voltage Vth2 of the PMOS device will be greater than the conduction voltage Vth1 of the NMOS device, and obviously, the power supply voltage will be far greater than Vth2, thereby resulting in higher power consumption of the inverter and wasting power consumption. In the background art, on-voltage of the MOS device is different based on the process angle division, and the on-voltage of the MOS device varies with temperature, and if a fixed voltage lower than the supply voltage is used as the working voltage of the CMOS inverter just as in the prior art, the fixed voltage may be smaller than the on-voltage of the MOS device, so that the normal operation of the CMOS inverter cannot be ensured.
The working voltage generating circuit of the digital circuit provided by the embodiment of the invention can effectively solve the problem, and is used for providing the working voltage related to the conduction voltage of the MOS device for the digital circuit, so that the relation between the working voltage of the digital circuit and the conduction voltage of the MOS device is established, the working voltage of the digital circuit can be changed along with the change of the conduction voltage of the MOS device in the digital circuit, and the digital circuit can normally work on the basis of the working voltage no matter how the conduction voltage is changed.
Specifically: the digital circuit of the invention comprises MOS devices, and the working voltage generating circuit also comprises MOS devices, and because the working voltage generating circuit and the digital circuit are connected and positioned in the same integrated circuit product, such as the same chip, the fluctuation speed of the MOS devices in the working voltage generating circuit and the fluctuation speed of the MOS devices in the digital circuit can be limited in a rectangular frame defined by four corners, and the conducting voltage equivalent to the MOS devices in the same integrated circuit product can be limited in the same range. Obviously, the turn-on voltage of the MOS devices in the working voltage generating circuit and the turn-on voltage of the MOS devices in the digital circuit are in the same range, and the turn-on voltages of the NMOS devices in the two circuits can be considered to be basically the same, and the turn-on voltages of the PMOS devices are basically the same. On the basis, no matter how the on-voltage of the MOS device in the digital circuit changes along with the process angle or the outside temperature, the MOS device in the first MOS device and the digital circuit has the same response to the outside environment and the process angle. The same response means that when the turn-on voltage of the MOS device in the digital circuit increases due to temperature or process corner, the turn-on voltage of the first MOS device also increases accordingly, which is independent of the conductivity type of the MOS device. In other words, even if the MOS devices in the digital circuit are PMOS devices and the first MOS device is an NMOS device, both have the same response to, for example, temperature changes.
In the specific implementation means of the invention, the relation between the working voltage of the digital circuit and the on voltage of the MOS device is characterized by the voltage difference between the gate and source terminals of the MOS device, and the working voltage generating circuit generates a first working voltage with the size of M Vgs based on the Vgs voltage when the first MOS device is on. Lazavitamin current formula i=u (VGS-Vth) as known in the art 2 As shown, U is a constant, and when the difference VGS between the gate terminal voltage and the source terminal voltage of the MOS device is greater than the turn-on voltage Vth, the MOS device is turned on and is in a saturation region. The Vgs voltage of the present invention is a voltage that can turn on the first MOS device, and it can be considered that the Vgs voltage is always larger than the on voltage Vth of the first MOS device regardless of the variation of the on voltage of the MOS device, so that when the on voltage Vth of the first MOS device is varied, the Vgs voltage is also varied, and the first operating voltage m×vgs generated based on the Vgs is also varied. Based on the above, the first working voltage is used as the working voltage of the digital circuit, the relation between the working voltage of the digital circuit and the Vgs voltage is established on the surface, and the relation between the working voltage of the digital circuit and the conducting voltage of the MOS device in the digital circuit is essentially established, so that the MOS device in the digital circuit can be ensured to work normally.
It can be understood that no matter how the turn-on voltage of the MOS device in the digital circuit changes along with the process angle or along with the external temperature, since the turn-on voltage of the first MOS device in the working voltage generating circuit and the turn-on voltage of the MOS device in the digital circuit are in the same range, the MOS device in the first MOS device and the digital circuit can be considered to have the same response to the change of the external environment and the change of the process angle, and when the digital circuit is based on the first working voltage with the magnitude of M Vgs, no matter whether the conduction types of the MOS device in the digital circuit and the first MOS device are completely the same or not, the value of M can be reasonably designed according to the specific structure of the digital circuit to be powered, so that the digital circuit can work normally based on the first working voltage.
In some examples, for some digital circuits that include only one MOS device. As shown in fig. 3 (a), the NMOS inverter needs only one NMOS device and a resistor (in fig. 3, the resistor is denoted by R1) to be connected in series, the drain terminal of the NMOS device is connected to an operating voltage through the resistor, the source terminal is grounded, the gate terminal is an input terminal, and the drain terminal is an output terminal. In the structure, the first working voltage of M x Vgs is provided for the PMOS inverter, even if the first MOS device is an NMOS device, since M is greater than 1, M x Vgs can have a sufficient margin greater than the on voltage of the PMOS device, ensuring that the PMOS inverter works normally.
In another example, for a digital circuit having two MOS devices, such as a CMOS inverter, the on-voltages of the NMOS device and the PMOS device are different, but when M takes a value greater than 1, it is ensured that the first operating voltage is greater than the on-voltage of the PMOS device, so as to satisfy the normal operation of the CMOS inverter.
In the above two examples, after the MOS device in the digital circuit changes with the process corner or the temperature, although the turn-on voltage of the MOS device will change, since the first MOS device and the MOS device in the digital circuit will have the same response to the change of the external environment and the change of the process corner, the turn-on voltage of the first MOS device may be considered to be equally changed, and since the Vgs voltage is the voltage difference between the gate and source terminals that can turn on the first MOS device, the turn-on voltage of the first MOS device may be considered to be changed when the turn-on voltage of the first MOS device is changed, and then the first operating voltage m×vgs generated based on the Vgs may also be changed accordingly, and the digital circuit may ensure normal operation based on the first operating voltage.
It should be noted that, in various embodiments of the present invention, the power supply voltage of the working voltage generating circuit may be the power supply voltage of the integrated circuit product (such as a chip), or may be slightly less than the power supply voltage based on the power supply voltage generation of the integrated circuit product. Since the operating voltage generating circuit is a first operating voltage generated by operating at its supply voltage, the first operating voltage must be smaller than its supply voltage, i.e. M Vgs < the supply voltage of the operating voltage generating circuit. Compared with the prior art that the power supply voltage of the integrated circuit product is used as the working voltage of the digital circuit, the invention uses the first working voltage with the size of M Vgs as the working voltage of the digital circuit, thereby effectively reducing the power consumption while ensuring the normal operation of the digital circuit. The invention can reasonably design the M aiming at different digital circuits, and avoid waste caused by overhigh power consumption while ensuring the normal operation of the digital circuits. As shown in the inverter of FIG. 3, the value range of M can be designed to be 1 < M < 2; in principle, the CMOS inverter shown in FIG. 2 can be operated normally when the value range of M is larger than 1, and can be designed to ensure the stability of the operation of the whole inverter circuit without too high power consumption, so that M is within the range of 2 < M < 3.
Next, a description will be given of an achievable circuit configuration of the operating voltage generating circuit of the present invention.
In the embodiment of the invention, the first MOS device can be an NMOS device with a short circuit of a gate-drain terminal, or can be a PMOS device with a short circuit of the gate-drain terminal. The gate-drain short circuit refers to the gate-drain short circuit of the MOS device.
In an embodiment of the present invention, the working voltage generating circuit may generally include: the invention provides different embodiments based on the above modules, namely a current generation module, a first voltage generation module and a second voltage generation module:
in one embodiment of the present invention, the current generating module generates the driving current based on the power voltage; the first voltage generation module is used for generating driving voltage according to the driving current and N+1 first MOS devices which are sequentially connected in series, wherein N is more than or equal to 1 and less than M is less than N+1; the second voltage generation module is used for generating the first working voltage according to the driving voltage.
In this embodiment, taking the first MOS device as an example of an NMOS device with a shorted gate-drain, referring to fig. 4, n+1 NMOS devices with shorted gate-drain are connected in series between the current generating module and the ground, where a node between the first MOS device and the current generating module is used as an output node (Z1 point in the drawing) of the first voltage generating module. The current generation module provides driving current for the N+1 gate-drain shorted NMOS devices, each gate-drain shorted NMOS device generates voltage at a drain end and a source end of the gate-drain shorted NMOS device based on the driving current, and when a difference Vgs between a gate end voltage (Vg) and a source end voltage (Vs) is larger than a conduction voltage Vth, the gate-drain shorted NMOS device is conducted. In other words, when each NMOS device with the short-circuited gate-drain terminal is turned on, the voltage of the voltage difference between the gate and the source terminal is Vgs. Since the gate terminal and the drain terminal of the MOS device are connected, the gate terminal voltage (Vg) and the drain terminal voltage (Vd) of the MOS device are the same, so that the voltage drop Vds on each gate-drain terminal shorted NMOS device is Vgs when being conducted, and Vds > Vgs-Vth is certain, and the first MOS device conducted based on the Vgs voltage always works in a saturation region under the condition of normal driving current. Based on the above, n+1 NMOS devices with shorted gate drain ends are connected in series, and a driving voltage with a magnitude of (n+1) Vgs can be generated at the output node of the first voltage generating module. In the example shown in fig. 4, the NMOS devices with 3 shorted gate drain terminals are connected in series, and a driving voltage with 3 x vgs can be generated at the output node of the first voltage generating module.
In an embodiment, with continued reference to fig. 4, the second voltage generation module may include: a first NMOS device and a capacitor; wherein, the first NMOS device (in each drawing of the embodiment of the invention, the first NMOS device is marked by NM 1) and the capacitor are connected in series between the power supply voltage and the ground; the first NMOS device is conducted based on the driving voltage, so that the capacitor is charged to generate a first working voltage.
In the second voltage generating module, the gate terminal of the first NMOS device receives the driving voltage, and because the turn-on voltage of the first NMOS device as a switch is substantially the same as the turn-on voltage Vth of the NMOS device with the gate-drain terminal shorted, the first NMOS device can be very easily turned on based on the driving voltage. After the first NMOS device is conducted, the power supply voltage charges the capacitor through the first NMOS device, and the voltage generated on the capacitor is the working voltage provided by the second voltage generating module to the digital circuit. It will be appreciated that in this embodiment, the node between the capacitor and the source of the first NMOS device serves as the output node (point Z2 in the illustration) of the second voltage generation module. The second voltage generating module is connected with a power supply end of the digital circuit so as to provide a first working voltage for the digital circuit.
When the first NMOS device is conducted, the voltage difference between the gate and source ends of the first NMOS device is Vgs, after the first NMOS device is conducted, the voltage on the capacitor is gradually charged and increased to be larger than the difference value between the driving voltage ((N+1) Vgs) and the Vgs, at the moment, the conducting channel of the first NMOS device is gradually reduced to be turned off, and the capacitor is continuously charged in the process of gradually reducing to be turned off, so that the first working voltage with the voltage of M Vgs generated on the capacitor is the first working voltage, and N is larger than or equal to 1 and smaller than M and is smaller than N+1.
In the example shown in fig. 4, n+1 is 3, so the driving voltage is 3Vgs, and the first operating voltage is a voltage value greater than 2 Vgs. The first operating voltage generated under the structure can be suitable for the digital circuit of the CMOS inverter shown in fig. 2, and although the conduction voltages of the NMOS device and the PMOS device are different, the first operating voltage can be enough to meet the normal and stable operation of the digital circuit and ensure lower power consumption because M is more than 2 and less than 3. In this process, when the turn-on voltage of the MOS device in the digital circuit is changed by temperature, the Vgs voltage is correspondingly changed to ensure that the NMOS device capable of shorting the gate drain terminal is turned on, and on this basis, the driving voltage of (n+1) Vgs is correspondingly changed, and the first working voltage of M Vgs provided to the digital circuit by the second voltage generating module is correspondingly changed to ensure that the digital circuit can work normally with low power consumption.
In another embodiment of the present invention, the current generating module generates the driving current based on the power voltage; the first voltage generation module is used for generating a driving voltage according to the driving current and at least one first MOS device and resistor therein; the second voltage generation module is used for generating the first working voltage according to the driving voltage. Unlike the embodiment shown in fig. 4, in this embodiment, a resistor is used to replace a part of the first MOS devices, so that a driving voltage sufficient to turn on the first NMOS devices in the second voltage generating module can be generated, and finally, the second voltage generating module can generate a first working voltage with a magnitude of m×vgs according to the driving voltage, where M > 1. In this embodiment, the resistor may be specifically selected according to the digital circuit of the desired application, which essentially replaces a part of the first MOS device to generate the voltage, and the implementation principle is substantially the same as that of the embodiment shown in fig. 4, which is not repeated here.
The embodiment is applicable to an NMOS device with a short circuit of a gate-drain terminal of a first MOS device or a PMOS device with a short circuit of a gate-drain terminal of the first MOS device. Taking the structure shown in fig. 5 and fig. 6 as an example, in fig. 5, the first MOS device is an NMOS device with a shorted gate-drain terminal, the source terminal of the NMOS device with the shorted gate-drain terminal is grounded, and the drain terminal is connected to the current generating module through a resistor (the resistor is denoted by R2 in fig. 5 and fig. 6), where a node between the resistor and the current generating module is used as an output node of the first voltage generating module, and is used for outputting a driving voltage. In fig. 6, the first MOS device is a PMOS device with a shorted gate-drain terminal, where a source terminal of the PMOS device with a shorted gate-drain terminal is grounded through a resistor, and a drain terminal is connected to the current generating module, and a node between the drain terminal and the current generating module is used as an output node of the first voltage generating module for outputting a driving voltage.
In the above two embodiments, in an example, the current generation module may be implemented by the following structure: the current generation module may include a reference current generation unit for generating a reference current and a current mirror for copying the reference current to obtain the driving current. In some other examples, the current generation module may also be implemented by some existing current source, which is not limited herein.
Further, as shown in fig. 4, the second voltage generating module may further include: and the voltage-resistant element is connected between the first NMOS device and the power supply voltage so as to protect the first NMOS device. The voltage-resistant element may be a MOS device or a resistor, which is not limited in the present invention.
In some abnormal situations, the power supply voltage of the working voltage generating circuit is reduced relatively low, and the related circuit working based on the power supply voltage is affected, such as the second voltage generating circuit. Specifically, in the art, when the voltage difference between the gate and source terminals of the MOS device is greater than the turn-on voltage Vth thereof, the turn-on channel of the MOS device increases with the increase of the voltage difference between the gate and source terminals, and in the second voltage generating circuit shown in fig. 4-6, when the power supply voltage decreases, the target current decreases, the voltage difference between the gate and source terminals of the first MOS device also decreases, and the driving voltage output by the first voltage generating module decreases, so that the turn-on channel of the first NMOS device decreases gradually, at this time, the current flowing from the power supply voltage to the capacitor through the first NMOS device is relatively small, and the charging speed of the capacitor decreases, which results in that the stable first operating voltage cannot be provided to the digital circuit, and the operating efficiency of the digital circuit is affected. In view of this, the present invention also proposes the following solutions: as shown in fig. 7, the operating voltage generating circuit is further configured to adjust the operating voltage of the digital circuit from the first operating voltage to the second operating voltage when the power supply voltage is lower than the threshold voltage; the second working voltage is VDD-K, VDD is the power supply voltage, and K is a constant.
Whether the supply voltage is below its threshold voltage can be achieved in a number of ways. In some embodiments, a comparator circuit may be used to determine the power supply voltage and the threshold voltage. Of course, the determination may also be made using the structure as provided below in the present invention:
the operating voltage generating circuit further includes: the detection module is used for detecting the driving current flowing through the first MOS device and generating a detection signal, the driving current is generated based on the power supply voltage and is reduced along with the reduction of the power supply voltage, and the detection signal is used for representing that the power supply voltage is lower than the threshold voltage when the detection signal is effective; the second voltage generation module is further configured to adjust the first operating voltage to a second operating voltage according to at least the power supply voltage when the detection signal is valid. Referring to fig. 8, the current generation module includes a first PMOS device (denoted by PM1 in fig. 8), a source terminal of the first PMOS device being connected to a power supply voltage, and a drain terminal of the first PMOS device being connected to the first voltage generation module; the detection module comprises a second PMOS device (indicated as PM2 in the figure 8) and a second NMOS device (indicated as NM2 in the figure 8) which are connected in series, the second PMOS device is connected with a power supply voltage, the second NMOS device is grounded, the second PMOS device and the first PMOS device form a current mirror, the second NMOS device and the first MOS device form a current mirror, and in the figure 8, the first MOS device is an NMOS device with a short circuit of grid and drain ends; the node between the second PMOS device and the second NMOS device is used for generating a detection signal; when the detection signal is at a high level, the detection signal is valid.
In this embodiment, the first PMOS device is a current mirror portion of the current generating module, and is configured to copy the reference current, where the gate end of the second PMOS device and the gate end of the first PMOS device form a current mirror with the same potential, and the gate end of the second NMOS device and the gate end of the first MOS device (the NMOS device with the gate drain end being shorted) form a current mirror with the same potential, which may be specifically shown in fig. 8, where the second NMOS device and the first MOS device closest to the ground potential in the first voltage generating module form a current mirror. The driving capability of the second NMOS device is stronger than that of the second PMOS device (for example, the mirror ratio of the second NMOS device to the first MOS device is 2:1, and the mirror ratio of the second PMOS device to the first PMOS device is 1:2), so that the second NMOS device is turned on under the condition that the power supply voltage is normal, and the detection signal is pulled to a low level. When the power supply voltage is reduced, the pull-down capability of the second NMOS device to the potential where the detection signal is located is reduced, and in specific implementation, the driving capability of the second NMOS device and the second PMOS device can be designed according to the threshold voltage of the required power supply voltage, so that the pulling capability of the second NMOS device and the second PMOS device to the potential generation point where the detection signal is located is different, for example, the number of tubes connected in parallel with the second NMOS device is larger than that of tubes connected in parallel with the first PMOS device. When the pull-down capability of the second NMOS device to the potential of the detection signal is weakened to be capable of representing that the power supply voltage is lower than the threshold voltage, the potential of the detection signal is pulled up to be close to the potential of the power supply voltage by the second PMOS device, the detection signal is changed from low level to high level, and the detection signal is effective.
The present embodiment can also be understood from another angle: based on the foregoing, it is known that the driving current is generated based on the power supply voltage, and the gate-source voltage difference of the first MOS device is generated based on the driving current, so that when the power supply voltage is reduced, the driving current is reduced, and the gate-source voltage difference of the first MOS device is also reduced. The first MOS device is an NMOS device with a short circuit of a gate drain end, the second NMOS device and the first MOS device closest to the ground potential in the first voltage generation module form a current mirror, when the voltage difference of the gate source end of the first MOS device is just enabled to be conducted under the power supply voltage, the power supply voltage can be represented to be lower than the threshold voltage, at the moment, a conducting channel of the second NMOS device is reduced, the pull-down capability of the second NMOS device on the potential where the detection signal is located is weakened, the potential where the detection signal is pulled up to the potential close to the power supply voltage by the second PMOS device, the detection signal is changed from low level to high level, and the detection signal is effective.
In this embodiment, with continued reference to fig. 8, the second voltage generation module includes a first NMOS device (denoted by NM1 in fig. 8), a capacitor, and a switching tube; the first NMOS device and the capacitor are connected in series between the power supply voltage and the ground; the first NMOS device is conducted based on the driving voltage output by the first voltage generation module; the switch tube is used for being conducted when the detection signal is effective, so that the power supply voltage at least charges the capacitor through the switch tube to generate a second working voltage on the capacitor. When the power supply voltage is greater than the threshold voltage, the driving current flowing through the first MOS device is normal, the voltage generated by the second NMOS device copying the driving current can enable the driving current to be in a conducting state so as to pull the potential of the detection signal to a low level, the switch tube is kept to be turned off based on the detection signal which is the low level, the power supply voltage can charge the capacitor at a higher speed through the first NMOS device, and the output voltage provided by the second voltage generating module is a first working voltage of M Vgs, wherein M is greater than 1. When the power supply voltage starts to be reduced to be smaller than the threshold voltage, the driving current flowing through the first MOS device becomes smaller, the conducting channel of the driving current becomes smaller, the potential where the detection signal is located is pulled up to be close to the potential of the power supply voltage by the second PMOS device, the detection signal is changed from low level to high level, and the detection signal is effective. At this time, the switch tube is turned on, the power supply voltage charges the capacitor through the switch tube, in this process, the first NMOS device may not be completely turned off, and there is a small amount of current to charge the capacitor through the first NMOS device, and finally the voltage generated on the capacitor is the second working voltage of VDD-K, where VDD is the power supply voltage, and K is a constant.
The switching tube can be an NMOS device or a PMOS device. If the switching tube is an NMOS device, the switching tube is conducted based on a high level, and can be directly conducted based on a detection signal with the high level. In the example shown in this embodiment, with continued reference to fig. 8, the switching tube is a third PMOS device (denoted by PM3 in fig. 8), and the operating voltage generating circuit further includes an inverter; the source end of the third PMOS device is connected with the drain end of the first NMOS device, and the drain end of the third PMOS device is connected with the capacitor; the detection signal is input to the gate end of the third PMOS device through the inverter, so that the third PMOS device is turned on when the detection signal is effective. In this example, the number of inverters may be plural, and since the detection signal is active high and the PMOS device is turned on based on low, the number of inverters through which the detection signal passes may be specifically odd.
Based on the same inventive concept, the embodiment of the present invention also discloses an oscillator circuit, referring to fig. 9, comprising: the working voltage generating circuit of the digital circuit according to the embodiment of the invention; the digital circuit shapes a clock signal generated in the oscillator circuit based on a first working voltage with the size of M Vgs provided by the working voltage generating circuit; m > 1 and M x Vgs < the supply voltage of the operating voltage generating circuit.
In the embodiment of the present invention, as shown in fig. 9, the digital circuit may be a CMOS inverter, and in the oscillator circuit, there may be a plurality of CMOS inverters, where an operating voltage of each CMOS inverter is a first operating voltage provided by the operating voltage generating circuit and having a magnitude of m×vgs. In the process, when the on-voltage of the MOS device in the CMOS inverter is changed by temperature and the like, the Vgs voltage is correspondingly changed, and on the basis, the first working voltage with the size of M Vgs is correspondingly changed, so that the CMOS inverter can work normally with low power consumption. The explanation of the related structure and principle of the digital circuit operating voltage generating circuit can be referred to the foregoing, and will not be repeated herein.
Based on the same inventive concept, the embodiment of the invention also discloses a chip, and referring to fig. 10, the chip comprises the digital circuit working voltage generating circuit according to the embodiment of the invention. In the embodiment of the invention, the integrated circuit product disclosed by the invention is a chip, and particularly can be a lithium battery management chip. Because the working voltage generating circuit of the digital circuit is arranged in the chip, even if the on voltage of the MOS device in the digital circuit changes, the working voltage generating circuit generates the first working voltage based on the Vgs voltage when the first MOS device is on to be used as the working voltage of the digital circuit, the first working voltage is M Vgs, M is more than 1, and M is less than the power voltage of the working voltage generating circuit, and the working voltage generating circuit can ensure the normal working of the digital circuit. The explanation of the relevant structure and principle of the digital circuit operating voltage generating circuit can be referred to the foregoing, and will not be repeated here.
Based on the same inventive concept, the embodiment of the present invention also discloses a chip, and referring to fig. 11, the chip includes an oscillator circuit as in the embodiment of the present invention. In the embodiment of the invention, the chip may be a lithium battery management chip.
Even if the on voltage of the MOS device in the digital circuit changes, the oscillator circuit is internally provided with the digital circuit working voltage generating circuit according to the embodiment of the invention, namely the digital circuit and the working voltage generating circuit, the working voltage generating circuit can ensure the normal working of the digital circuit, and compared with the prior art that the power supply voltage is adopted as the working voltage of the digital circuit, the first working voltage provided by the invention to the digital circuit can effectively reduce the power consumption of the digital circuit. The specific circuit structure of the oscillator circuit and the explanation of the related principles can be referred to the foregoing description, and the present invention is not repeated here.
It should be noted that, in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described as different from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
The foregoing has outlined rather broadly the more detailed description of the invention in order that the detailed description of the invention that follows may be better understood, and in order that the present contribution to the art may be better appreciated. While various modifications of the embodiments and applications of the invention will occur to those skilled in the art, it is not necessary and not intended to be exhaustive of all embodiments, and obvious modifications or variations of the invention are within the scope of the invention.
Claims (15)
1. A digital circuit operating voltage generating circuit is characterized in that,
the digital circuit comprises a MOS device;
the working voltage generating circuit comprises at least one first MOS device, and generates a first working voltage as the working voltage of the digital circuit based on the Vgs voltage when the first MOS device is conducted;
the first working voltage is M-Vgs, M is greater than 1, and M-Vgs is less than the power supply voltage of the working voltage generating circuit.
2. The digital circuit operating voltage generating circuit according to claim 1, wherein,
the operating voltage generating circuit includes:
a current generation module that generates a driving current based on the power supply voltage;
the first voltage generation module is used for generating driving voltage according to the driving current and N+1 first MOS devices which are sequentially connected in series, wherein N is more than or equal to 1 and less than M is less than N+1;
and the second voltage generation module is used for generating the first working voltage according to the driving voltage.
3. The digital circuit operating voltage generating circuit according to claim 1, wherein,
the operating voltage generating circuit includes:
a current generation module that generates a driving current based on the power supply voltage;
The first voltage generation module is used for generating a driving voltage according to the driving current and at least one of the first MOS device and the resistor therein;
and the second voltage generation module is used for generating the first working voltage according to the driving voltage.
4. A digital circuit operating voltage generating circuit according to any of claims 1-3, wherein the first MOS device is a gate-drain shorted NMOS device.
5. A digital circuit operating voltage generating circuit according to any one of claims 1 to 3, wherein,
the second voltage generation module includes: a first NMOS device and a capacitor;
the first NMOS device and the capacitor are connected in series between the power supply voltage and the ground;
the first NMOS device is conducted based on the driving voltage so that the capacitor is charged to generate the first working voltage.
6. The digital circuit operating voltage generating circuit according to claim 5, wherein,
the second voltage generation module further includes:
and the voltage-resistant element is connected between the first NMOS device and the power supply voltage so as to protect the first NMOS device.
7. A digital circuit operating voltage generating circuit according to claim 2 or 3, wherein the operating voltage generating circuit is further configured to adjust the operating voltage of the digital circuit from the first operating voltage to a second operating voltage when the power supply voltage is lower than a threshold voltage; the second working voltage is VDD-K, VDD is the power supply voltage, and K is a constant.
8. The digital circuit operating voltage generating circuit according to claim 7, wherein,
the operating voltage generating circuit further includes:
a detection module for detecting a driving current flowing through the first MOS device and generating a detection signal, wherein the driving current is generated based on the power supply voltage and decreases with a decrease of the power supply voltage, and the detection signal is effective to indicate that the power supply voltage is lower than a threshold voltage;
the second voltage generating module is further configured to adjust the first operating voltage to the second operating voltage at least according to the power supply voltage when the detection signal is valid.
9. The digital circuit operating voltage generating circuit according to claim 8, wherein,
the current generation module comprises a first PMOS device, the source end of the first PMOS device is connected with the power supply voltage, and the drain end of the first PMOS device is connected with the first voltage generation module;
the detection module comprises a second PMOS device and a second NMOS device which are mutually connected in series, the second PMOS device is connected with the power supply voltage, the second NMOS device is grounded, the second PMOS device and the first PMOS device form a current mirror, the second NMOS device and the first MOS device form a current mirror, and the first MOS device is an NMOS device with a short circuit of grid and drain ends;
Wherein a node between the second PMOS device and the second NMOS device is configured to generate the detection signal; when the detection signal is at a high level, the detection signal is valid.
10. The digital circuit operating voltage generating circuit according to claim 9, wherein,
the second voltage generation module comprises a first NMOS device, a capacitor and a switching tube;
the first NMOS device and the capacitor are connected in series between a power supply voltage and ground;
the first NMOS device is conducted based on the driving voltage output by the first voltage generation module;
the switch tube is used for being conducted when the detection signal is effective, so that the power supply voltage at least charges the capacitor through the switch tube to generate the second working voltage on the capacitor.
11. The digital circuit operating voltage generating circuit according to claim 10, wherein,
the switching tube is a third PMOS device, and the working voltage generating circuit further comprises an inverter;
the source end of the third PMOS device is connected with the drain end of the first NMOS device, and the drain end of the third PMOS device is connected with the capacitor;
the detection signal is input to the gate end of the third PMOS device through the inverter, so that the third PMOS device is conducted when the detection signal is effective.
12. An oscillator circuit, comprising: a digital circuit operating voltage generating circuit according to any one of claims 1 to 11;
the digital circuit shapes a clock signal generated in the oscillator circuit based on a first working voltage with the magnitude of M-Vgs provided by the working voltage generating circuit; m > 1 and M x Vgs < the supply voltage of the operating voltage generating circuit.
13. The oscillator circuit of claim 12, wherein the digital circuit is an inverter comprising a MOS device.
14. A chip comprising a digital circuit operating voltage generating circuit according to any one of claims 1 to 11, or comprising an oscillator circuit according to any one of claims 12 to 13.
15. The chip of claim 14, wherein the chip is a lithium battery management chip.
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| CN202311595719.XA CN117572930A (en) | 2023-11-24 | 2023-11-24 | Digital circuit working voltage generating circuit, oscillator circuit and chip |
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| CN202311595719.XA CN117572930A (en) | 2023-11-24 | 2023-11-24 | Digital circuit working voltage generating circuit, oscillator circuit and chip |
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