CN117561513A

CN117561513A - Chip layout method and device

Info

Publication number: CN117561513A
Application number: CN202180099701.3A
Authority: CN
Inventors: 沈嘉华; 伍宏忠; 焦润; 黄宇; 张锐
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-06-24
Filing date: 2021-06-24
Publication date: 2024-02-13
Also published as: WO2022266956A1

Abstract

A chip layout method and device relate to the technical field of integrated circuit design. The method comprises the following steps: determining a first layout planning scheme of a plurality of target objects according to the first information; the first information comprises information for describing a plurality of target objects and connection relations among the target objects, and the first layout planning scheme is used for describing initial layout positions of the target objects in the chip; adjusting the first layout planning scheme according to at least one parameter to obtain a second layout planning scheme of the plurality of target objects, wherein the at least one parameter is used for representing the tightness degree of the plurality of target objects in the chip, and the second layout planning scheme is used for describing the target layout positions of the plurality of target objects in the chip; and outputting partition information corresponding to at least one group of the plurality of target objects on the chip according to a second layout planning scheme, wherein the partition information corresponding to each group on the chip is used for deploying the target objects belonging to the group on the chip. The scheme is beneficial to automatically realizing top-level layout planning and macro-module layout planning in VLSI physical design.

Description

Chip layout method and device

Technical Field

The present disclosure relates to the field of integrated circuit design, and in particular, to a chip layout method and apparatus.

Background

In very large scale integrated circuit (very large scale integrated circuit, VLSI) design, physical design is an important step. In general, large-scale chips describe circuit structures using netlists (netlists) hierarchically (hierarchy): one circuit structure is composed of an input/output port, a plurality of sub-modules (sub-modules), a macro module (macro module), a plurality of standard cells (ststandard cells) and connection relations between the sub-modules (macro modules) and the macro modules (macro modules). The sub-module is also a circuit structure (i.e. the sub-module may also include a sub-module), the macro-module is a sub-module that has been physically designed, and the standard cell is a minimum circuit structure that has a comparable size and has been physically designed. The physical design is to assign positions and positions of interconnection lines to macro blocks and standard cells in the netlist on the premise of given shapes and positions of input and output ports.

In physical design, layout planning (floor plan) and macro placement (macro placement) occupy irreplaceable positions. Layout planning includes giving the shape, location, and port location of the sub-modules; the macro block placement is to give the macro block position under the conditions of given placeable shape and port position. The layout planning and the placement of macro blocks directly influence the power consumption performance and various indexes of the area (power performance area, PPA) of the chip.

Along with the continuous evolution of design and manufacturing processes, the scale of integrated circuits is continuously increased, the hierarchical complexity of the design is continuously improved, and the complexity of top-level layout planning and macro-module placement is increased. For chips designed in a hierarchical manner, it is generally required that standard cells and macro blocks under the same logic level can be closely gathered in the same communication area, and for modules connected more closely, the modules are placed in adjacent areas, so as to obtain better area utilization rate and better performance.

In the current VLSI physical design, top-level layout planning and macro-block placement mainly depend on manual placement of engineers: the top layer layout planning is carried out by a back-end engineer with abundant experience, and the whole chip area is manually divided into a plurality of sub-areas according to modules according to the data flow guidance provided by the front end and the area requirement of the chip; the back-end engineer of the module design then plans the layout inside the module according to the shape planned by the top-level layout. The method has higher dependence on experience of engineers and understanding degree of the engineers on physical design, and has higher labor cost.

Disclosure of Invention

The application provides a chip layout method and device, which are beneficial to automatically realizing top layer layout planning and macro module layout planning in VLSI physical design.

In a first aspect, an embodiment of the present application provides a chip layout method, including: determining a first layout planning scheme of a plurality of target objects according to the first information; the first information comprises information for describing the plurality of target objects and the connection relation among the target objects, and the first layout planning scheme is used for describing the initial layout positions of the plurality of target objects in the chip; adjusting the first layout planning scheme according to at least one parameter to obtain a second layout planning scheme of the plurality of target objects, wherein the at least one parameter is used for representing the tightness degree of the plurality of target objects in the chip, and the second layout planning scheme is used for describing the target layout positions of the plurality of target objects in the chip; and outputting partition information corresponding to at least one group of the plurality of target objects on the chip according to the second layout planning scheme, wherein the partition information corresponding to each group on the chip is used for deploying the target objects belonging to the group on the chip.

By the scheme, the plurality of target objects can comprise macro modules and/or standard units and/or other objects which are required to be arranged on the chip, and the initial layout positions of the plurality of target objects are adjusted by utilizing at least one parameter so as to automatically obtain the target layout positions of the plurality of target objects on the chip, so that the top-level layout planning and the macro module layout planning in the VLSI physical design are automatically realized.

In one possible design, the adjusting the first layout plan according to at least one parameter, to obtain a second layout plan of the plurality of target objects includes: according to a target model, adopting a gradient descent method to carry out iterative adjustment on the first layout planning scheme to obtain the second layout planning scheme; inputting a layout planning scheme under a current gradient and the value of the at least one parameter into the target model in each iteration process to obtain the layout planning scheme under the next gradient and the value of the at least one parameter; the target model is used for representing the corresponding relation between a layout planning scheme under two adjacent gradients and the at least one parameter; when the set adjustment termination condition is reached, determining that the layout plan obtained in the last iteration is the second layout plan, wherein the adjustment termination condition comprises: candidate parameter values for a target parameter of the at least one parameter are less than or equal to the corresponding parameter threshold. Optionally, the at least one parameter includes one or more of: line length, cell distribution density, cohesive tightness.

According to the scheme, based on the target requirements of the chip physical design, the current layout positions of the plurality of target objects are subjected to iterative optimization by utilizing the target model, so that a layout planning scheme meeting the corresponding target requirements is obtained as much as possible, and good layout quality can be obtained while labor cost is reduced.

In one possible design, the target model is represented as:

f＝WL _r +λ _v *WL _v +λ _d *D+λ _g *G

wherein WL (WL) _r Representing the sum of the line lengths of the actual connecting lines between the plurality of target objects in each layout plan; WL (WL) _v Representing a sum of line lengths of virtual connection lines between the plurality of target objects in each layout plan; d represents the unit distribution density; g represents cohesive tightness of target objects belonging to the same group; lambda (lambda) _v 、λ _d 、λ _g Respectively the WL _v And D, G.

By the scheme, iterative optimization is performed by taking the line length of the actual connecting lines, the line length of the virtual connecting lines, the unit distribution density, the cohesion compactness of the groups and the like among a plurality of target objects as optimization parameters, so that each better layout planning scheme such as the line length, the density, the communication aggregation inside the groups and the like can be obtained from a plurality of candidate layout planning schemes for the plurality of target objects, and the quality of layout is ensured while the labor cost is reduced by realizing the physical design of an automatic chip.

In one possible design, when the first layout plan is iteratively adjusted using a gradient descent method, the method further includes: and adjusting the weight in the target model according to the Lagrangian relaxation method. Therefore, by adopting the Lagrange relaxation method, the optimization difficulty is reduced as much as possible, and the optimization progress is quickened.

In one possible design, the first information includes a feature value for describing at least one attribute feature of each target object; determining a first layout plan for the plurality of target objects according to the first information, including: grouping the plurality of target objects according to the target characteristics in the at least one attribute characteristic according to the first information to obtain at least one group; and carrying out position initialization based on the at least one group, and determining a first layout planning scheme of the plurality of target objects.

According to the scheme, the plurality of target objects are grouped according to the target characteristics, so that partition information corresponding to each group, such as the position and the shape of each group, can be obtained according to the at least one group after global layout, and the corresponding target objects belonging to each group can be deployed on the chip based on the partition information.

In one possible design, the plurality of target objects belong to a plurality of hierarchies, and the first information further includes information for describing a hierarchical relationship between the plurality of hierarchies; grouping the plurality of target objects according to target features in the at least one attribute feature according to the first information, including: and according to the hierarchical relationship of the multiple layers, logically dividing the target objects under each layer into corresponding groups based on at least one target characteristic value threshold. Optionally, the target feature is an area.

Through the scheme, in hierarchical chip physical design, the target objects of each level are grouped according to the size and logic depth requirements of each level, so that a finer layout planning result is obtained.

In one possible design, the plurality of target objects include macro blocks therein; the method further comprises the steps of: and splitting each macro module required to be arranged on the chip into at least one corresponding equivalent subunit according to the target utilization rate, wherein the area of each equivalent subunit is the same as the area of a preset standard unit serving as a splitting reference, or the difference value between the area of each equivalent subunit and the area of the standard unit is within a set error range.

Through the scheme, the macro module with the area larger than or far larger than that of the standard unit is logically segmented to obtain a plurality of equivalent sub-units equivalent to the standard unit in area, so that layout position optimization is uniformly performed with smaller granularity of the standard unit, and the optimization effect of a layout planning scheme is further improved.

It should be noted that, in the present application, the standard cells to be disposed on the chip are the minimum circuit structures that have realized the physical design, and therefore, when the related design file has already given the number of standard cells to be disposed on the chip, the sizes of the number of standard cells are known. The standard cell size is quite meant not to severely limit the size of the standard cell, but rather the size of the different standard cells is within a predetermined standard cell size range. When the macro block is logically split, the predetermined standard cell size can be used as a reference size, so that after the macro block is logically split based on the standard cell size, a plurality of equivalent subunits similar to the standard cell size can be obtained. The logic splitting is different from the actual splitting, i.e. the actual splitting operation is not executed, and is only used for logically splitting the whole macro module into equivalent subunits with the size similar to that of the standard units, so that when the subsequent iteration optimization is performed, virtual connecting wires can be added for different equivalent subunits/standard units based on the granularity of the standard unit size, and the connectivity aggregation of macro modules or units inside the group is further optimized.

In one possible design, the plurality of target objects include standard cells therein that need to be set on the chip, the method further comprising: and adding virtual connecting lines for target units in the plurality of target objects, wherein the target units comprise at least one equivalent subunit belonging to the same macro module and/or standard units and/or equivalent subunits belonging to the same group.

Through the scheme, based on granularity of standard unit sizes, the connectivity aggregation of the macro modules or the units inside the groups is further optimized by adding virtual connecting wires for target units belonging to the same macro modules or the same groups.

In a second aspect, an embodiment of the present application provides a chip layout apparatus, including: the processing unit is used for determining a first layout planning scheme of the plurality of target objects according to the first information; the first information comprises information for describing the plurality of target objects and the connection relation among the target objects, and the first layout planning scheme is used for describing the initial layout positions of the plurality of target objects in the chip; adjusting the first layout planning scheme according to at least one parameter to obtain a second layout planning scheme of the plurality of target objects, wherein the at least one parameter is used for representing the tightness degree of the plurality of target objects in the chip, and the second layout planning scheme is used for describing the target layout positions of the plurality of target objects in the chip; and the communication unit is used for outputting partition information corresponding to at least one group of the plurality of target objects on the chip according to the second layout planning scheme, wherein the partition information corresponding to each group on the chip is used for deploying the target objects belonging to the group on the chip.

In one possible design, the processing unit is configured to: according to a target model, adopting a gradient descent method to carry out iterative adjustment on the first layout planning scheme to obtain the second layout planning scheme; inputting a layout planning scheme under a current gradient and the value of the at least one parameter into the target model in each iteration process to obtain the layout planning scheme under the next gradient and the value of the at least one parameter; the target model is used for representing the corresponding relation between a layout planning scheme under two adjacent gradients and the at least one parameter; when the set adjustment termination condition is reached, determining that the layout plan obtained in the last iteration is the second layout plan, wherein the adjustment termination condition comprises: candidate parameter values for a target parameter of the at least one parameter are less than or equal to the corresponding parameter threshold.

In one possible design, the at least one parameter includes one or more of the following: line length, cell distribution density, cohesive tightness.

In one possible design, the target model is represented as:

f＝WL _r +λ _v *WL _v +λ _d *D+λ _g *G

wherein WL (WL) _r Representing the sum of the line lengths of the actual connecting lines between the plurality of target objects in each layout plan; WL (WL) _v Representation ofA sum of line lengths of virtual connection lines between the plurality of target objects in each layout plan; d represents the unit distribution density; g represents cohesive tightness of target objects belonging to the same group; lambda (lambda) _v 、λ _d 、λ _g Respectively the WL _v And D, G.

In one possible design, when the processing unit uses a gradient descent method to iteratively adjust the first layout plan, the processing unit is further configured to: and adjusting the weight in the target model according to the Lagrangian relaxation method.

In one possible design, the first information includes a feature value for describing at least one attribute feature of each target object; the processing unit is used for: grouping the plurality of target objects according to the target characteristics in the at least one attribute characteristic according to the first information to obtain at least one group; and initializing the positions based on the at least one group, and determining the first layout position of the target object in each group on the chip.

In one possible design, the plurality of target objects belong to a plurality of hierarchies, and the first information further includes information for describing a hierarchical relationship between the plurality of hierarchies; the processing unit is used for: and logically dividing the target object under each level into corresponding groups according to the hierarchical relationship of the multiple levels based on at least one characteristic value threshold.

In one possible design, the target feature is an area.

In one possible design, the plurality of target objects include macro blocks therein; the processing unit is further configured to: and splitting each macro module required to be arranged on the chip into at least one corresponding equivalent subunit according to the target utilization rate, wherein the area of each equivalent subunit is the same as the area of the preset standard unit serving as a splitting reference, or the difference value between the area of each equivalent subunit and the area of the standard unit is within a set error range.

In one possible design, the plurality of target objects includes standard cells that need to be set on the chip, and the processing unit is further configured to: and adding virtual connecting lines for target units in the plurality of target objects, wherein the target units comprise at least one equivalent subunit belonging to the same macro module and/or standard units and/or equivalent subunits belonging to the same group.

In a third aspect, embodiments of the present application provide a computer-readable medium, in which a computer program is stored which, when run on a computer, causes the computer to perform the method of any one of the first aspects above.

In a fourth aspect, embodiments of the present application provide a computer program product which, when run on a computer, causes the computer to perform the method of any one of the first aspects above.

Further combinations of the present application may be made to provide further implementations based on the implementations provided in the above aspects.

Drawings

FIG. 1 shows a flow diagram of a chip layout method according to an embodiment of the present application;

FIG. 2a shows a block diagram of a circuit configuration of an embodiment of the present application;

FIG. 2b shows a flow diagram of a chip layout method according to an embodiment of the present application;

FIG. 3 shows a grouping schematic of an embodiment of the present application;

FIG. 4 illustrates a macroblock logical split diagram of an embodiment of the present application;

FIGS. 5 a-5 b are schematic diagrams illustrating adding virtual connection lines to equivalent subunits of the same macroblock according to an embodiment of the present application;

FIG. 6 illustrates a schematic diagram of adding virtual connection lines to a sub-module according to an embodiment of the present application;

FIG. 7 illustrates a position initialization schematic of the present application;

FIGS. 8 a-8 b are schematic illustrations depicting cohesive tightness G of embodiments of the present application;

FIG. 9 illustrates a physical partition schematic diagram of an embodiment of the present application;

FIG. 10 shows a schematic diagram of a chip layout apparatus of an embodiment of the present application;

fig. 11 shows a schematic diagram of a communication device of the present application.

Detailed Description

In the current chip physical design, top layer layout planning and macro module placement mainly depend on manual placement of engineers, and have higher dependence on experience of the engineers and understanding degree of the engineers on the physical design, so that labor cost is higher.

The embodiment of the application provides a chip layout method and device, which are beneficial to automatically realizing top layer layout planning and macro module layout planning in VLSI physical design, reducing labor cost and improving quality of layout. The method and the device are based on the same technical conception, and because the principle of solving the problems by the method and the device is similar, the implementation of the device and the method can be mutually referred to, and the repeated parts are not repeated.

For easy understanding, the chip layout scheme of the present application will be described below with reference to the drawings and embodiments.

Fig. 1 shows a flow diagram of a chip layout method according to an embodiment of the present application. The method can be implemented by a chip layout device, which can be a terminal device or a server, or can be a component or a module for implementing the method, and the specific implementation of the chip layout device is not limited in this application.

Referring to fig. 1, the chip layout method may include the steps of:

s110: the chip layout device determines a first layout planning scheme of a plurality of target objects according to the first information.

In this application, the first information may be used to describe the plurality of target objects and the connection relationships between the respective target objects, and the first layout plan may be used to describe a first layout position of the plurality of target objects in the chip, where the first layout position may be, for example, an initial layout position.

In this application, the target object may be multiple, including but not limited to input/output ports, sub-modules, macro-modules, standard cells, etc. that need to participate in the physical design of the chip. The input/output port may also be referred to as a pin, and may be used to connect to a peripheral circuit. The sub-module may be a circuit structure, i.e. the sub-module may also comprise sub-modules. A macroblock is a sub-module that has implemented a physical design. Standard cells are the smallest circuit structures that are comparable in size and that have been physically designed. It should be understood that the target object described in the present application may further include all sub-modules under one sub-module, or all sub-units under the same macro-module, that is, a hardware module or a hardware unit that does not implement a physical design, or a sub-unit in a module that has implemented a physical design, etc., which may be all the target objects described in the present application are not described herein.

The information included in the first information for describing the respective target objects may include, for example, but not limited to, product identification information describing each target object, device information (e.g., size, manufacturer, model, category, other attributes, etc.), function information (e.g., storage function, communication function, processing function, display function, etc.), and other hardware/software attribute-related information, which is not limited in this application. It can be understood that, in the present application, the types of information included in the first information for describing different target objects may be the same or different, and specifically, the types of information need to be determined according to the actual situation of the target object, which is not limited in the present application. The information for describing each target object contained in the first information may be any form of information such as pictures, words, numbers, symbols, and the like according to description requirements or understanding requirements, may be natural language that can be understood by human beings, may also be in a formal language that can be understood by machines or programs, and may be organized into corresponding information format representations, which are not limited in this application.

The connection relationship between each target object may include a connection relationship between any two target objects in the plurality of target objects, for example, a connection relationship between an input/output port and a sub-module, a macro module, a standard unit, a connection relationship between a sub-module and a macro module, a standard unit, or a connection relationship between a macro module and a standard unit. Optionally, the connection relationship between the respective target objects may further include a position of a connection line between the arbitrary two target objects. It should be noted that the foregoing is merely illustrative of the target object in the present application, and is not limited in any way, and in other embodiments or in future development of the VISI, the target object that needs to be designed on the chip may also have other names or other descriptions. The connection relationship between any two target objects or between internal units of the same target object may be a physical connection relationship or a non-physical connection relationship, for example, a virtual connection relationship, which is not limited in this application.

Alternatively, when S110 is implemented, the chip layout device may read the design file, and further, the chip layout device may obtain the first information from the design file. The design file may be manufactured by a front-end engineer or by an automation tool, and may include related information required for performing physical design of the chip, where the related information may be used to describe a plurality of target objects and connection relationships between the target objects that need to be disposed on the chip. In the implementation of S110, specifically, the back-end engineer may import the design file into the chip layout device, and the chip layout device may parse the design file to obtain the first information. Or, the chip layout device may acquire the design file from a device (or cloud) storing the design file through a network or a physical connection device, and parse the design file, so as to obtain the first information. The method for acquiring the first information is not limited in this application.

In one possible implementation, the relevant information in the design file may be described, verified, and simulated using a hardware description language or other proprietary language. For example, one or more of the following may be included in the design file:

(1) The netlist can be used for hierarchically describing a circuit structure, and the circuit structure is composed of an input/output port, a plurality of sub-modules, a macro module, a plurality of standard units and a connection relation among the standard units.

It should be understood that, in this application, a netlist may be used to describe a circuit structure of multiple levels, and based on the logic depth of the circuit structure described by the netlist, the target objects (or referred to as design modules) that need to be disposed on a chip may be hierarchically divided, where the levels to which each target object belongs are gradually obtained from the smallest granularity (i.e., lowest level) to the largest granularity (i.e., highest level), and any one of the levels may also be referred to as a level. Wherein any level may have a relationship of a parent level and a child level, a parent level may contain all target objects under its child level, and all target objects under the child level may be considered as one target object under its parent level.

For example, referring to FIG. 2a, a hierarchical circuit structure based on netlist representation may result in a hierarchy to which a plurality of target objects belong. Such as display modules, sensor modules, memory modules, audio modules, etc., shown in dashed boxes, belong to level 1. The display module comprises a display screen, a display interface, a front camera, a main camera interface, a rear camera interface and the like, and belongs to the layer 2; the lower module (if any) included in any of the display screen, display interface, front camera, main camera interface, rear camera interface, etc., belongs to level 3, and so on. The sensor module comprises a touch screen signal circuit, a touch screen interface circuit, a coprocessor, a sensor interface and the like, and belongs to the level 2; the lower modules (if any) included for any of the touch screen signal circuits, touch screen interface circuits, coprocessors, sensor interfaces, etc., belong to level 3, and so on. For hard disks, chips, etc. included in the memory module, belonging to level 2; for the lower level modules (if any) included by any of the modules in the hard disk, chips, etc., it is level 3 and so on. An audio coding and decoding interface, an audio amplifier, a sensor interface and the like which are included in the audio module belong to the level 2; for the lower modules (if any) included in any of the audio codec interface, audio amplifier, sensor interface, etc., it is level 3, and so on. Wherein level 1 is a parent level of level 2, level 2 is a child level of level 1, level 2 is a parent level of level 3, and level 3 is a child level of level 2.

In addition, as shown in fig. 2a, based on the hierarchical circuit structure of the netlist, a connection relationship between each target object may also be obtained, for example, a connection relationship between another target object to which any target object needs to be connected, a pin of any target object and a corresponding pin of the other target object, and so on. It should be understood that fig. 2a is only a schematic block diagram of a hierarchical circuit structure based on a netlist description in the present application, and not any limitation on target objects, connection relationships, etc. of the netlist description, and the arrowed line segments shown in the drawing only indicate that the corresponding target objects may have connection relationships with other target objects, and the solid line boxes are only used to indicate that the respective target objects are connectable, and not to define a specific implementation of the connection relationships, which is not described herein.

It should be noted that, in this application, the logic depth described by different circuit structures may be different, and the hierarchy is generally determined from the minimum granularity to the maximum granularity based on the target object described in the circuit structure. For example, the display module in fig. 2a may include 4 levels in total, the sensor module may include 3 levels in total, the memory module may include 2 levels in total, and the audio module may include 3 levels in total. In this application, for convenience of description, the circuit structures based on different logic depths of netlist description may be named as level 1, level 2, and level 3 … … from top to bottom, respectively, for each level involved in the netlist. It should be understood that the hierarchy numbers are merely used in this application to facilitate distinguishing between different hierarchies, and are not used to define the function of the target object under the different hierarchies.

(2) A library for describing the shapes of the macro block, sub block, standard cell, etc. which need to be provided on the chip, and the relative positions of the ports of the macro block and/or sub block and/or standard cell, etc. on their own shapes.

(3) And the target shape information is used for describing a target shape and an area of the target shape, wherein the target shape and the area are expected to be obtained after the layout design of the chip is completed.

(4) Chip port location information.

The chip layout device can obtain the first information from the netlist, the library, the target shape information, the chip port position information and the like by analyzing the netlist, the library, the target shape information and the chip port position information so as to automatically complete the chip physical design. It should be understood that, in the specific implementation, other description information may also be included in the design file, which is not limited in this application.

Alternatively, when S110 is implemented, the chip layout apparatus may process the obtained first information, so as to determine the first layout positions of the plurality of target objects on the chip. Wherein the first information obtained by the chip layout apparatus in S110 is different according to the different description information contained in the design file, and the processing performed is different. For example, referring to fig. 2b, S110 may include the steps of:

S111: the chip layout device acquires first information.

In this application, the first information may include a feature value for describing at least one attribute feature of each target object. For example, the at least one attribute feature may include a shape, an area, a number, and the feature value of the at least one attribute feature may be a value corresponding to the corresponding attribute feature. For example, the attribute feature "area" corresponds to XX square centimeters. It is understood that "square centimeter" is only an example of a unit of area and is not limiting, and other units of area may be used in the implementation, and are not described here.

In one example, since the circuit structure is generally described hierarchically using a netlist in a hierarchical physical design of a chip, a plurality of target objects required to be set in the chip may belong to a plurality of hierarchies, a chip layout device may parse the netlist and the like to obtain a hierarchical relationship between hierarchies to which the plurality of target objects respectively belong, and the first information may further include information usable to describe the hierarchical relationship between the plurality of hierarchies.

S112: and the chip layout device groups the plurality of target objects according to the target characteristics in the at least one attribute characteristic according to the first information to obtain at least one group.

In this application, in order to effectively improve the efficiency of the automated chip layout design, and simultaneously enable a designer to more freely optimize among performance, area, power consumption, cost, and the like, a target feature may be selected from the at least one attribute feature to group a plurality of target objects, so as to obtain a better planning layout scheme according to a grouping result. It should be noted that, the selection of the target feature may be preset by a designer based on experience or simulation experiment, or may be selected based on automation, and the determination manner of the target feature is not limited in this application.

By way of example, the target feature may be any one of the at least one attribute feature, such as area, pin count, etc. Alternatively, the target feature may be a combination of two or more of the at least one attribute feature, such as a combination of area, pin count. In the case of two or more target features, different target features may be combined in a mode of sum, or the like, that is, in the case of sum, a certain target object needs to be divided into one group when the corresponding grouping rules of different target features are simultaneously satisfied, and in the case of or, only a certain corresponding grouping rule satisfying one of the target features is required. In the implementation, corresponding target characteristics can be determined according to actual design requirements and actual conditions of each target object, so that top layer layout planning and macro module layout planning in VLSI physical design can be automatically realized, labor cost is reduced, and good layout quality can be obtained at the same time, and details are omitted.

Because of the different module sizes and logic depths under each hierarchy in the hierarchical physical design, the fine-scale requirements of the chip layout apparatus in grouping target objects based on at least one attribute feature may be different. For example, S112 may include: and logically dividing the target objects under each level into corresponding groups according to the hierarchical relationship of the multiple levels, for example, according to the direction from the highest level to the lowest level, based on the target feature value threshold corresponding to at least one target feature.

Taking the block diagram shown in fig. 2a as an example, assume that the circuit structure of the netlist description includes 3 levels in total, where level 1 is the highest level, level 2 is the middle level, and level 3 is the lowest level, when performing grouping, the target objects under level 1 may be first grouped, then the target objects under level 2 are grouped, and finally the target objects under level 3 are grouped.

For example, the at least one target feature may be one, and the target feature value threshold corresponding to the at least one target feature may be two, including: a first target feature value threshold and a second target feature value threshold, the first target feature value threshold being greater than the second target feature value threshold; when the target object logic under each level is divided into corresponding groups in sequence, if the target characteristic value of a certain target object is smaller than or equal to the second target characteristic value threshold value, the target object and the father level belong to the same group; if the target characteristic value of a certain target object is larger than the second target characteristic value threshold and smaller than or equal to the first target characteristic value threshold, the target object is singly grouped; and if the target characteristic value of a certain target object is greater than or equal to the first target characteristic value threshold value, continuing to group the next level.

For ease of understanding, the specific implementation procedure of S112 will be described below taking an area as a target feature. Wherein the target feature value threshold is an area threshold, and the first target feature value threshold is expressed as a first area threshold A ₁ The second target eigenvalue threshold is represented as a second area threshold a ₂ For example, the area A of each target object under each level is used based on the top-down of the various levels of the netlist description _h And A ₂ And A ₁ These two area thresholds are logically grouped:

(1) If the area A of the target object _h The method meets the following conditions: a is that _h ≤A ₂ Then the target object is co-organized with its parent level;

(2) If the area A of the target object _h The method meets the following conditions: a is that ₂ ≤A _h ≤A ₁ The target object is individually grouped;

(3) If the area A of the target object _h The method meets the following conditions: a is that _h ≥A ₁ The next hierarchy is continued to be grouped.

Referring to FIG. 3, the circuit structure described in the netlist involves a total of 4 levels, A ₁ ＝15、A ₂ In the case of =9, from top to bottom, in level 1, for a _h ＝24≥A ₁ In the case of (A), the A _h The target object of=24 can be divided into one group, denoted G1; in level 1 there is a requirement of A ₂ ≤A _h ≤A ₁ The target object needs to be separately grouped, i.e. divided into groups different from G1, and can be denoted as G3; in the case that there are no other ungrouped target objects already in level 1, the grouping of target objects under the sub-level of level 1 (i.e., level 2) continues. It should be appreciated that, since a parent level typically contains all of the target objects under a child level, without loss of generality, the higher the level the greater the area of the target objects contained.

In level 2, for A _h ＝6、8≤A ₂ With its parent level A _h =24 can be divided into the same group, belonging to group G1, for a ₂ ≤A _h ＝10≤A ₁ Case of (A) _h The target object of=10 is divided into another group different from its parent level, denoted as G2, G2 being a group different from G1; in the case that no other ungrouped target objects are already in level 2, the sub-level of level 2 (i.e., level 3) continues to be grouped.

At the level of3, for A _h ＝5、3≤A ₂ With its parent level A _h =8 same groups, divided into groups G1; for A _h ＝5、5≤A ₂ With its parent level A _h =10 same groups, divided into groups G2; continuing to group sub-levels of level 3 (i.e., level 4) in the event that there are no other ungrouped target objects already in level 3; in level 4, for A _h ＝5、3≤A ₂ With its parent level A _h =5 is the same group, divided into packets G2.

Finally, the netlist logic containing 4 levels is divided into two groupings, G1 and G2. It should be understood that this is only an example of grouping and not a limitation, and that in other embodiments, at least one grouping may be obtained based on the specific case of the circuit structure described by the netlist and the grouping rules, and will not be described herein.

In order to obtain a layout plan with better line length, density, connectivity aggregation inside the group and the like from a plurality of candidate layout plans, after the grouping is performed in S112, the target objects in each group can be processed, so that the connectivity aggregation of the target objects in the group can be improved during the subsequent iterative optimization.

In one example, S112 may further include S113: the chip layout device logically splits each macro module (for example, a kernel (intellectual property, IP) module, an input-output (IO) module, or a Memory module) required to be set on the chip into at least one equivalent subunit according to the target utilization.

It should be noted that, in this application, the "logical splitting" is different from the actual splitting, that is, the actual splitting operation is not performed, and is only used to logically split the macro module with a larger size into equivalent subunits with a size similar to the size of the preset standard unit as the splitting reference, so that when the optimization adjustment is performed, virtual connection lines are added for different equivalent subunits/standard units based on the granularity of the standard unit size, so as to further optimize the connectivity aggregation of the macro module or the intra-packet unit. In this application, each equivalent subunit may be considered a standard cell.

It should be noted that, in the present application, the standard cell is a minimum circuit structure that has a size equivalent to that of the standard cell and has been designed physically, and the macro block is a sub-module that has been designed physically, and the size of the macro block is greater than or far greater than that of the standard cell. For example, the area of each equivalent subunit is the same as the standard cell area, or the difference between the area of each equivalent subunit and the area of the standard cell is within a set error range. And, at the target utilization, the equivalent subunit area (a _i ) Sum of (a) and the original macroblock area (a) _macro ) Equal.

By way of example, the area of n subunits satisfies the following expression (1):

where i=1, 2, 3 … …, n is an integer of 1 or more.

By way of example, the target utilization rate ρ satisfies the following expression (2):

it should be understood that in the present application, the determination of the target utilization rate ρ may be determined empirically by an engineer or according to the requirements of the chip physical design, etc., and the above expression (2) is merely an example and not a limitation.

For example, at A _macro For example, referring to fig. 4, in S123, the original macroblock may be split into 10×5 equivalent subunits, each equivalent subunit having an area a _i ＝1.6*0.8。

In general, the chip layout requires that the cells under the same logic level be laid out in the same area as much as possible to obtain a better PPA. Optionally, S114 may be further included after S113: the chip layout device adds virtual connection lines for target units in the plurality of target objects, wherein the target units comprise at least one equivalent subunit belonging to the same macro module and/or standard units and/or equivalent subunits belonging to the same group.

It should be noted that in the present application, an additional virtual connection line is added to all units belonging to the same macroblock or the same group, so as to enable interconnection between each unit in the macroblock or the group, so as to maintain high cohesion inside the macroblock or inside the group, and help to improve the optimization effect of the subsequent target model. In the implementation, the virtual connection lines may be added randomly or according to a set rule, for example, sequentially, or in a grid manner, which is not described herein.

For example, referring to fig. 5a, for one macro block, the chip layout apparatus may allocate virtual connection lines to n equivalent sub-units belonging to the same macro block in a random allocation manner. Alternatively, as shown in fig. 5b, the chip layout apparatus may allocate virtual connection lines to n equivalent sub-units belonging to the same macroblock in a grid allocation manner.

Alternatively, a group may be called a sub-module, and the sub-module may further include a sub-module, and as shown in fig. 6, for different sub-modules, the chip layout device may use a random allocation manner to allocate virtual connection lines to all units belonging to the same sub-module. For example, for four sub-modules A, B, C-C1, C-C2 (C-C1, C-C2 are sub-modules included in sub-module C, respectively), the chip layout apparatus may add virtual connection lines to all units in each sub-module randomly, and then, in sub-module a, unit a1 is connected to unit a2, and unit a2 is also connected to unit a 3; in the sub-module B, the unit B1 is connected with the unit B2, the unit B2 is also connected with the unit B3 and the unit B4 respectively, and the unit B3 is also connected with the unit B4; in the sub-module C-C1, the unit C11 is respectively connected with the units C12, C13 and C14, and the unit C12 is also connected with the unit C13; in the sub-module C-C2, the unit C21 is respectively connected with the unit C22 and the unit C24, the unit C22 is also connected with the unit C23, and the unit C23 is also connected with the unit C24; in the submodule C, the unit C11 is further connected with the unit C24, the unit C12 is further connected with the unit C21 and the unit C24, the unit C13 is further connected with the unit C23, and the unit C13 is further connected with the unit C23.

S115: the chip layout means may perform the position initialization based on the at least one packet after the processing of S113 to S114 described above, to determine the first layout plan of the plurality of target objects.

For example, the first layout plan may be used to describe a first layout position of the plurality of target objects in the chip, which may be, for example, an initial layout position. In the implementation S115, the chip layout apparatus may set the initial layout position for each group with the target objects belonging to the same group as a whole, where all units (including standard units and/or equivalent sub-units) in one group have the same initial layout position, so that a better intra-group connection effect and certainty of the corresponding positional relationship between groups can be obtained with respect to the non-differential random initialization.

For example, the chip placement device may determine the initial placement location of each group at the chip using a predetermined model, such as a square distance line length model (Quadratic WL model), for example.

As an example, the square distance line length model may describe the line length using the following expression (3):

where m is the number of packets, w _j,k Is the weight of the connection line between group j and group k, (x) _j ，y _j ) For the position of packet j, (x) _k ，y _k ) Is the position of packet k.

Referring to fig. 7, for three packets of unknown location: group 1 (x) ₁ ，y ₁ ) Group 2 (x) ₂ ，y ₂ ) Group 3 (x) ₃ ，y ₃ ) In the case where the positions of 3 chip ports are known (e.g., (0, 1), (1, 3), (3, 2)), weights of connection lines between groups (e.g., 0, 2, 5) and between groups and chip ports (e.g., 1) are known, the weights of connection lines and chip port position information may be substituted into the above expression (3), to obtain:

WL＝1*[(x ₁ -1) ² +(y ₁ -3) ² ]+2*[(x ₁ -x ₂ ) ² +(y ₁ -y ₂ ) ² ]+5*[(x ₂ -x ₃ ) ² +(y ₂ -y ₃ ) ² ]+1*[(x ₂ -3) ² +(y ₂ -2) ² ]+1*[(x ₃ -0) ² +(y ₃ -1) ² ]；(4)

the WL model obtains an equation set by deviant the position of each group in the expression (4), and obtains the initial layout position of each group by solving the equation set to obtain the position of each group. In each group, all cells (including standard cells and/or equivalent sub-cells) have the same initial layout position as the group.

It should be noted that, the WL model described in the above expression (3) may also be used in the following step to solve all units in each group at candidate positions of the chip with units as granularity until a layout plan solution meeting the target requirement is obtained, which will be described in detail below and will not be repeated herein.

S120: and the chip layout device adjusts the first layout planning scheme according to at least one parameter to obtain a second layout planning scheme of the plurality of target objects. The second layout planning scheme is used for describing target layout positions of the target objects in the chip.

Illustratively, the at least one parameter includes one or more of: line length, cell distribution density, cohesive tightness. In implementation, the chip layout device may, for example, perform iterative optimization based on the first layout planning scheme and using line length, cell distribution density, connectivity aggregation inside each group, and the like as optimization parameters until a second layout position of each cell is finally determined, so as to obtain a second layout planning scheme, thereby enabling the obtained global layout result to achieve effects of line length, uniform density, connectivity aggregation inside the group, and the like as much as possible.

In an example, in S120, the chip layout apparatus may iteratively adjust the first layout plan by using a gradient descent method according to the target model, to obtain the second layout plan. Inputting a layout planning scheme under a current gradient and the value of the at least one parameter into the target model in each iteration process to obtain the layout planning scheme under the next gradient and the value of the at least one parameter; the target model is used for representing the corresponding relation between the layout planning scheme and the at least one parameter under two adjacent gradients.

As an example, the object model is expressed as the following expression (5):

f＝WL _r +λ _v↓ *WL _v +λ _d *D+λ _g *G (5)

wherein WL (WL) _r Representing the sum of the line lengths of the physical connection lines between the plurality of target objects in a layout plan; WL (WL) _v Representing the sum of the line lengths of virtual connecting lines between the plurality of target objects and/or between internal units of each target object in a layout planning scheme; d represents the unit distribution density; g represents cohesive tightness of target objects belonging to the same group; lambda (lambda) _v 、λ _d 、λ _g Respectively the WL _v And D, G, wherein arrows are used for representing adjustment directions of the corresponding weights.

Optionally, when the chip layout device adjusts the first layout plan by adopting a gradient descent method, the weight in the target model may be adjusted according to a lagrangian method. Example(s)E.g. lambda _v↓ 、λ _d↑ 、λ _g↓ 。

Referring to fig. 2b, in implementation, S120 may include the following steps:

s121: and the chip layout device performs gradient calculation according to the target model based on the current layout planning scheme and the current value of the at least one parameter.

S122: the chip layout device calculates new layout positions of each standard cell (comprising equivalent subunits) based on the granularity of the standard cells according to the current gradient and the current layout planning scheme to obtain a new layout planning scheme, wherein the new layout planning scheme comprises a new candidate position set and a new value of the at least one parameter.

S123: the chip layout device judges whether the layout planning scheme obtained by the last iteration adjustment meets the standard or not. If yes, namely, the layout planning scheme obtained by the iterative adjustment reaches the standard, the step S130 is entered; if not, that is, if the layout planning scheme obtained by the iterative adjustment does not reach the standard, returning to the steps S121-S123, and continuing to iteratively adjust the current layout positions of the plurality of target objects by adopting a gradient descent method.

In each iterative adjustment process, the weight of each parameter is adjusted according to the Lagrangian relaxation method, the gradient of the standard unit is calculated for the target model in each iterative process, and the layout position of the standard unit is updated according to the current gradient, so that a new candidate position set is obtained until an adjustment termination condition is reached, for example: and stopping iterative adjustment when the candidate parameter value of the target parameter in the at least one parameter is smaller than or equal to the corresponding parameter threshold value, and determining the layout planning scheme obtained in the last iteration as the second layout planning scheme. For example, the target parameter may be a cell distribution density D, and in the iterative adjustment process, when a value of the cell distribution density D obtained based on the updated layout plan is less than or equal to a set target density threshold, an adjustment termination condition is reached.

It should be noted that, in this application, only the unit distribution density is taken as an example of the adjustment termination condition, and not any limitation, in a specific implementation, other one or more parameters may also be set as the target parameters, which are not described herein.

In this application, the chip layout apparatus may describe the cohesive closeness G of each Group (Group) in a number of alternative ways, for example, during each iterative adjustment.

Example 1: description of rectangular area with Fence (Fence force) and Group circumscribed G:

referring to fig. 8a, G is described by the following expression (6) using the nonce force:

wherein,a circumscribed rectangular area representing each Group; max (x) _g ) Represents the maximum abscissa, min (x _g ) Represents the minimum abscissa, max (y _g ) Represents the maximum ordinate, min (y _g ) Representing the minimum ordinate of the units contained in the Group. In fig. 8a, different groupings are outlined with different dashed lines, with the standard cells (including equivalent subunits) in the different groupings being represented by open circles and filled circles.

Example 2: describing G by way of center of gravity distance:

referring to fig. 8b, using the center of gravity distance, it is described by the following expression (7):

G＝∑((x _i -x _g ) ² +(y _i -y _g ) ² ) (7)

Wherein, (x) _i ，y _i ) Represents the location of standard cell i (including equivalent subunits) in each Group, (x) _g ，y _g ) Is the position of the center of gravity of the Group. In fig. 8b, standard cells (including equivalent subunits) in different groupings are represented by open circles and filled circles, and the arrows corresponding to each grouping point to the center of gravity position of the corresponding grouping, for ease of distinction, the center of gravity positions of the corresponding grouping are represented by open circles and filled circles of larger size in fig. 8 a.

After the global layout optimization is completed, the chip layout device can obtain the unit distribution results with uniform density and clustered inside the group.

S130: and the chip layout device outputs partition information corresponding to at least one group of the plurality of target objects on the chip according to the second layout planning scheme, wherein the partition information corresponding to each group on the chip is used for deploying the target objects belonging to the group on the chip.

In this application, the partition information corresponding to the at least one packet on the chip may include, for example, a partition shape corresponding to each of the at least one packet, and a location of each of the at least one packet on the chip. In implementation, the chip layout device may perform physical partitioning on the setting position of the at least one group in the chip based on the obtained global layout result (including the second layout position of each standard unit and/or macro module), and process the setting area corresponding to each group into a right-angle polygon, so as to obtain the shape of the corresponding partition of each group on the chip and the deployment position of the group area on the chip. Further, based on the obtained physical partition with a more standard shape, hierarchical design of the next stage or layout placement for macro blocks can be conveniently performed.

For example, referring to fig. 9, after global layout optimization, 7 grouping areas shown on the left side of fig. 9 can be obtained, each grouping area corresponding to one of the above-mentioned groupings. At this time, each group is irregularly shaped. By squaring these 7 grouping areas, 7 right-angled polygonal areas shown on the right side of fig. 9 can be obtained. The respective partition information may be used as an output for hierarchical design of the next stage or for layout placement of the macro blocks.

Optionally, the target object and the layout position thereof contained in each group can be used as output, so that when the hierarchical design of the next stage or the layout placement of the macro module is used, the setting of the related design module on the chip can be completed directly based on the output information.

Therefore, through the chip layout method, the top-level design layout planning problem and the macro-module layout position planning problem can be automatically solved through iterative global layout optimization, the problem of high dependence on experience of engineers and design understanding degree of the engineers in manual layout planning can be made up, and the method is beneficial to reducing labor cost and guaranteeing quality of layout.

Based on the same technical concept, the embodiments of the present application also provide a chip layout apparatus, as shown in fig. 10, the chip layout apparatus 1000 may include a processing unit 1010 and a communication unit 1020. Wherein, the processing unit 1010 is configured to determine a first layout plan of the plurality of target objects according to the first information; the first information comprises information for describing the plurality of target objects and the connection relation among the target objects, and the first layout planning scheme is used for describing the initial layout positions of the plurality of target objects in the chip; adjusting the first layout planning scheme according to at least one parameter to obtain a second layout planning scheme of the plurality of target objects, wherein the at least one parameter is used for representing the tightness degree of the plurality of target objects in the chip, and the second layout planning scheme is used for describing the target layout positions of the plurality of target objects in the chip; and a communication unit 1020, configured to output partition information corresponding to at least one group on the chip, where the partition information corresponds to each group on the chip, where the target objects belonging to the group are deployed on the chip according to the second layout plan.

In one possible design, the processing unit 1010 is configured to: according to a target model, adopting a gradient descent method to carry out iterative adjustment on the first layout planning scheme to obtain the second layout planning scheme; inputting a layout planning scheme under a current gradient and the value of the at least one parameter into the target model in each iteration process to obtain the layout planning scheme under the next gradient and the value of the at least one parameter; the target model is used for representing the corresponding relation between a layout planning scheme under two adjacent gradients and the at least one parameter; when the set adjustment termination condition is reached, determining that the layout plan obtained in the last iteration is the second layout plan, wherein the adjustment termination condition comprises: candidate parameter values for a target parameter of the at least one parameter are less than or equal to the corresponding parameter threshold.

In one possible design, the target model is represented as:

f＝WL _r +λ _v *WL _v +λ _d *D+λ _g *G

In one possible design, when the processing unit 1010 performs iterative adjustment on the first layout plan using a gradient descent method, the method is further used to: and adjusting the weight in the target model according to the Lagrangian relaxation method.

In one possible design, the first information includes a feature value for describing at least one attribute feature of each target object; the processing unit 1010 is configured to: grouping the plurality of target objects according to the target characteristics in the at least one attribute characteristic according to the first information to obtain at least one group; and carrying out position initialization based on the at least one group, and determining a first layout planning scheme of the plurality of target objects.

In one possible design, the plurality of target objects belong to a plurality of hierarchies, and the first information further includes information for describing a hierarchical relationship between the plurality of hierarchies; the processing unit 1010 is configured to: and according to the hierarchical relationship of the multiple layers, logically dividing the target objects under each layer into corresponding groups based on at least one target characteristic value threshold.

In one possible design, the target feature is an area.

In one possible design, the plurality of target objects include macro blocks therein; the processing unit 1010 is further configured to: and splitting each macro module required to be arranged on the chip into at least one corresponding equivalent subunit according to the target utilization rate, wherein the area of each equivalent subunit is the same as the area of a preset standard unit serving as a splitting reference, or the difference value between the area of each equivalent subunit and the area of the standard unit is within a set error range.

In one possible design, the plurality of target objects includes standard cells that need to be set on the chip, and the processing unit 1010 is further configured to: and adding virtual connecting lines for target units in the plurality of target objects, wherein the target units comprise at least one equivalent subunit belonging to the same macro block and/or standard units and/or equivalent subunits belonging to the same group.

Fig. 11 is a schematic diagram of a communication device according to an embodiment of the present application. The communication device has a structure as shown in fig. 11, and includes a processor 1101 and a memory 1102. The memory has stored therein one or more computer programs, the one or more computer programs comprising instructions; when the processor invokes the instruction, the communication apparatus is caused to perform the method provided in the above embodiment and the embodiment, and the functions of each unit device of the communication apparatus are described below.

The processor 1101 and the memory 1102 are connected to each other through a bus 1103. The bus 1103 may be a peripheral component interconnect standard (peripheral component interconnect, PCI) bus or an extended industry standard architecture (extended industry standard architecture, EISA) bus, among others. The buses may be classified as address buses, data buses, control buses, etc. For ease of illustration, only one thick line is shown in FIG. 11, but not only one bus or one type of bus.

Memory 1102 has stored therein one or more computer programs, including instructions. The memory 1102 may include random access memory (random access memory, RAM) and may also include non-volatile memory (non-volatile memory), such as at least one disk memory. The processor 1101 executes program instructions in the memory 1102 and uses the data stored in the memory 1102 to implement the functions described above, thereby implementing the methods provided by the embodiments described above.

It is to be appreciated that memory 1102 in fig. 11 of the subject application can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. The nonvolatile Memory may be a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable EPROM (EEPROM), or a flash Memory. The volatile memory may be random access memory (Random Access Memory, RAM) which acts as an external cache. By way of example, and not limitation, many forms of RAM are available, such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (Double Data Rate SDRAM), enhanced SDRAM (ESDRAM), synchronous DRAM (SLDRAM), and Direct RAM (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to comprise, without being limited to, these and any other suitable types of memory.

It should be noted that, in the above embodiments of the present application, the division of the modules is merely schematic, and there may be another division manner in actual implementation, and in addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or may exist separately and physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution, in the form of a software product stored in a storage medium, including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

Based on the above embodiments, the present application further provides a computer program, which when run on a computer causes the computer to perform the method provided by the above embodiments.

Based on the above embodiments, the present application further provides a computer-readable storage medium having stored therein a computer program, which when executed by a computer, causes the computer to perform the method provided in the above embodiments.

Wherein a storage medium may be any available medium that can be accessed by a computer. Taking this as an example but not limited to: the computer readable medium may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer.

Based on the above embodiments, the present application further provides a chip, where the chip is coupled to the memory, and the chip is configured to read the computer program stored in the memory, so as to implement the method provided in the above embodiments.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present invention, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another, for example, by wired (e.g., coaxial cable, optical fiber, digital Subscriber Line (DSL)), or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., a floppy Disk, a hard Disk, a magnetic tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a Solid State Disk (SSD)), or the like.

The various illustrative logical blocks and circuits described in the embodiments of the present application may be implemented or performed with a general purpose processor, a digital signal processor, an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the general purpose processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a digital signal processor and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a digital signal processor core, or any other similar configuration.

The steps of a method or algorithm described in the embodiments of the present application may be embodied directly in hardware, in a software element executed by a processor, or in a combination of the two. The software elements may be stored in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. In an example, a storage medium may be coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC, which may reside in a terminal device. In the alternative, the processor and the storage medium may reside in different components in a terminal device.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

Although the invention has been described in connection with specific features and embodiments thereof, it will be apparent that various modifications and combinations can be made without departing from the spirit and scope of the invention. Accordingly, the specification and drawings are merely exemplary illustrations of the present invention as defined in the appended claims and are considered to cover any and all modifications, variations, combinations, or equivalents that fall within the scope of the invention. It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

A chip layout method, comprising:

determining a first layout planning scheme of a plurality of target objects according to the first information; the first information comprises information for describing the plurality of target objects and the connection relation among the target objects, and the first layout planning scheme is used for describing the initial layout positions of the plurality of target objects in the chip;

adjusting the first layout planning scheme according to at least one parameter to obtain a second layout planning scheme of the plurality of target objects, wherein the at least one parameter is used for representing the tightness degree of the plurality of target objects in the chip, and the second layout planning scheme is used for describing the target layout positions of the plurality of target objects in the chip;

and outputting partition information corresponding to at least one group of the plurality of target objects on the chip according to the second layout planning scheme, wherein the partition information corresponding to each group on the chip is used for deploying the target objects belonging to the group on the chip.
The method of claim 1, wherein adjusting the first layout plan based on at least one parameter results in a second layout plan for the plurality of target objects, comprising:

According to a target model, adopting a gradient descent method to carry out iterative adjustment on the first layout planning scheme to obtain the second layout planning scheme; inputting a layout planning scheme under a current gradient and the value of the at least one parameter into the target model in each iteration process to obtain the layout planning scheme under the next gradient and the value of the at least one parameter; the target model is used for representing the corresponding relation between a layout planning scheme under two adjacent gradients and the at least one parameter;

when the set adjustment termination condition is reached, determining that the layout plan obtained in the last iteration is the second layout plan, wherein the adjustment termination condition comprises: candidate parameter values for a target parameter of the at least one parameter are less than or equal to the corresponding parameter threshold.
The method of claim 2, wherein the at least one parameter comprises one or more of: line length, cell distribution density, cohesive tightness.
A method according to claim 3, wherein the object model is represented as:

f＝WL _r +λ _v *WL _v +λ _d *D+λ _g *G

wherein WL (WL) _r Representing the sum of the line lengths of the actual connecting lines between the plurality of target objects in each layout plan; WL (WL) _v Representing a sum of line lengths of virtual connection lines between the plurality of target objects in each layout plan; d represents the unit distribution density; g represents cohesive tightness of target objects belonging to the same group; lambda (lambda) _v 、λ _d 、λ _g Respectively the WL _v And D, G.
The method according to any one of claims 1-4, wherein the first information includes a feature value for describing at least one attribute feature of each target object; determining a first layout plan for the plurality of target objects according to the first information, including:

grouping the plurality of target objects according to the target characteristics in the at least one attribute characteristic according to the first information to obtain at least one group;

and carrying out position initialization based on the at least one group, and determining a first layout planning scheme of the plurality of target objects.
The method according to claim 5, wherein the plurality of target objects belong to a plurality of hierarchies, and the first information further includes information for describing a hierarchical relationship between the plurality of hierarchies; grouping the plurality of target objects according to target features in the at least one attribute feature according to the first information, including:

And according to the hierarchical relationship of the multiple layers, logically dividing the target objects under each layer into corresponding groups based on at least one target characteristic value threshold.
The method of claim 5 or 6, wherein the target feature is an area.
The method of any of claims 1-7, wherein the plurality of target objects include macro blocks therein, the method further comprising:

and splitting each macro module required to be arranged on the chip into at least one corresponding equivalent subunit according to the target utilization rate, wherein the area of each equivalent subunit is the same as the area of a preset standard unit serving as a splitting reference, or the difference value between the area of each equivalent subunit and the area of the standard unit is within a set error range.
The method of claim 8, wherein the plurality of target objects include standard cells that need to be set on the chip, the method further comprising:

and adding virtual connecting lines for target units in the plurality of target objects, wherein the target units comprise at least one equivalent subunit belonging to the same macro block and/or standard units and/or equivalent subunits belonging to the same group.
A chip layout apparatus, comprising:

the processing unit is used for determining a first layout planning scheme of the plurality of target objects according to the first information; the first information comprises information for describing the plurality of target objects and the connection relation among the target objects, and the first layout planning scheme is used for describing the initial layout positions of the plurality of target objects in the chip; adjusting the first layout planning scheme according to at least one parameter to obtain a second layout planning scheme of the plurality of target objects, wherein the at least one parameter is used for representing the tightness degree of the plurality of target objects in the chip, and the second layout planning scheme is used for describing the target layout positions of the plurality of target objects in the chip;

and the communication unit is used for outputting partition information corresponding to at least one group of the plurality of target objects on the chip according to the second layout planning scheme, wherein the partition information corresponding to each group on the chip is used for deploying the target objects belonging to the group on the chip.
The apparatus of claim 10, wherein the processing unit is configured to:

According to a target model, adopting a gradient descent method to carry out iterative adjustment on the first layout planning scheme to obtain the second layout planning scheme; inputting a layout planning scheme under a current gradient and the value of the at least one parameter into the target model in each iteration process to obtain the layout planning scheme under the next gradient and the value of the at least one parameter; the target model is used for representing the corresponding relation between a layout planning scheme under two adjacent gradients and the at least one parameter;

when the set adjustment termination condition is reached, determining that the layout plan obtained in the last iteration is the second layout plan, wherein the adjustment termination condition comprises: candidate parameter values for a target parameter of the at least one parameter are less than or equal to the corresponding parameter threshold.
The apparatus of claim 11, wherein the at least one parameter comprises one or more of: line length, cell distribution density, cohesive tightness.
The apparatus of claim 12, wherein the object model is represented as:

f＝WL _r +λ _v *WL _v +λ _d *D+λ _g *G

wherein WL (WL) _r Representing the sum of the line lengths of the actual connecting lines between the plurality of target objects in each layout plan; WL (WL) _v Representing a sum of line lengths of virtual connection lines between the plurality of target objects in each layout plan; d represents the unit distribution density; g represents cohesive tightness of target objects belonging to the same group; lambda (lambda) _v 、λ _d 、λ _g Respectively the WL _v And D, G.
The apparatus according to any one of claims 10-13, wherein the first information comprises a feature value describing at least one attribute feature of each target object; the processing unit is used for:

grouping the plurality of target objects according to the target characteristics in the at least one attribute characteristic according to the first information to obtain at least one group;

and initializing the positions based on the at least one group, and determining the first layout position of the target object in each group on the chip.
The apparatus of claim 14, wherein the plurality of target objects belong to a plurality of hierarchies, and wherein the first information further includes information describing a hierarchical relationship between the plurality of hierarchies; the processing unit is used for:

and according to the hierarchical relationship of the multiple layers, logically dividing the target objects under each layer into corresponding groups based on at least one target characteristic value threshold.
The apparatus of claim 14 or 15, wherein the target feature is an area.
The apparatus of any one of claims 10-16, wherein the plurality of target objects include macro blocks therein; the processing unit is further configured to:

and splitting each macro module required to be arranged on the chip into at least one corresponding equivalent subunit according to the target utilization rate, wherein the area of each equivalent subunit is the same as the area of a preset standard unit serving as a splitting reference, or the difference value between the area of each equivalent subunit and the area of the standard unit is within a set error range.
The apparatus of claim 17, wherein the plurality of target objects include standard cells that need to be set on the chip, the processing unit further configured to:

and adding virtual connecting lines for target units in the plurality of target objects, wherein the target units comprise at least one equivalent subunit belonging to the same macro module and/or standard units and/or equivalent subunits belonging to the same group.
A computer readable storage medium, characterized in that the computer readable storage medium has stored therein a computer program which, when run on a computer, causes the computer to perform the method of any of claims 1-9.
A computer program product, characterized in that the computer program product, when run on a computer, causes the computer to perform the method of any of claims 1-9.