CN117558756A - Transistor and manufacturing method thereof - Google Patents

Transistor and manufacturing method thereof Download PDF

Info

Publication number
CN117558756A
CN117558756A CN202210935785.6A CN202210935785A CN117558756A CN 117558756 A CN117558756 A CN 117558756A CN 202210935785 A CN202210935785 A CN 202210935785A CN 117558756 A CN117558756 A CN 117558756A
Authority
CN
China
Prior art keywords
substrate
gate
dielectric layer
gate dielectric
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202210935785.6A
Other languages
Chinese (zh)
Inventor
金志勋
刘金彪
杨涛
李俊峰
贺晓彬
王垚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
Original Assignee
Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institute of Microelectronics of CAS, Zhenxin Beijing Semiconductor Co Ltd filed Critical Institute of Microelectronics of CAS
Priority to CN202210935785.6A priority Critical patent/CN117558756A/en
Publication of CN117558756A publication Critical patent/CN117558756A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention discloses a transistor and a manufacturing method thereof, which relate to the technical field of semiconductor manufacturing and are used for reducing parasitic capacitance in the transistor so as to improve the performance of the transistor. The transistor includes: the device comprises a substrate, a gate stack, side walls, source/drain regions and an air gap. A gate stack is formed on a substrate. The gate stack includes a gate dielectric layer formed on the substrate and a gate electrode on the gate dielectric layer. The side walls are formed on the substrate and at least located on two sides of the gate stack along the length direction. Source/drain regions are formed in the substrate and are located on both sides of the gate stack in the length direction. An air gap is formed over the substrate. The air gap is positioned between the substrate and the gate electrode and between the gate dielectric layer and the side wall. The manufacturing method of the transistor is used for manufacturing the transistor.

Description

Transistor and manufacturing method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a transistor and a method for manufacturing the same.
Background
With the rapid increase in the degree of integration of semiconductor fabrication techniques in device fabrication, transistors are increasingly being used as switches for semiconductor devices, and their size and performance are also increasingly affecting the performance of the semiconductor devices, with the size and performance of the transistors being directly related to their structure and fabrication method.
Due to the specificity of the transistor structure, parasitic capacitance may be generated between each of its terminals, causing a delay in resistance-capacitance (Rc). The small value of the parasitic capacitance is a significant cause of interference. Therefore, how to reduce the occurrence of parasitic capacitance in the transistor and improve the performance of the semiconductor device is a key technical problem at present.
Disclosure of Invention
The invention aims to provide a transistor and a manufacturing method thereof, which are used for reducing parasitic capacitance in the transistor so as to improve the performance of the transistor.
In order to achieve the above object, the present invention provides a transistor. The transistor includes: a substrate;
a gate stack formed on a substrate; the gate stack comprises a gate dielectric layer formed on the substrate and a gate electrode positioned on the gate dielectric layer;
the side walls are formed on the substrate and at least positioned at two sides of the gate stack along the length direction;
source/drain regions formed in the substrate and located on both sides of the gate stack in the length direction;
and an air gap formed on the substrate; the air gap is positioned between the substrate and the gate electrode and between the gate dielectric layer and the side wall.
Compared with the prior art, in the transistor provided by the invention, an air gap is formed between the substrate and the gate electrode. In this case, since the dielectric constant of air is smaller than that of the gate dielectric layer and the capacitance is proportional to the dielectric constant, the presence of the air gap may reduce the gate-source capacitance (Cgs), the gate-drain capacitance (Cgd), and the capacitance (Cgb) between the gate electrode and the substrate. At this time, on the premise that the area of the gate electrode is not changed, the gate capacitance (Cox) per unit area is reduced, so that the gate control capability of the transistor is improved, the drain induced barrier lowering effect (Drain Induced Barrier Lowering Effect, abbreviated as DIBL) is further reduced, and the working performance of the transistor is improved.
The invention also provides a manufacturing method of the transistor, which comprises the following steps:
providing a substrate;
forming a gate stack on a substrate; the gate stack comprises a gate dielectric layer formed on the substrate and a gate electrode positioned on the gate dielectric layer; an opening is formed between the substrate and the gate electrode, and the opening is at least positioned at two sides of the gate dielectric layer along the length direction;
forming source/drain regions on both sides of the gate stack in the length direction in the substrate;
and forming side walls at least on two sides of the grid stack along the length direction on the substrate, so that an air gap is formed by surrounding the opening by the side walls, the substrate and the grid stack.
Compared with the prior art, the transistor manufacturing method has the same beneficial effects as the transistor provided by the technical scheme, and the detailed description is omitted.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and do not constitute a limitation on the invention. In the drawings:
fig. 1 is a top view of a transistor structure provided in the related art;
fig. 2 is a top view of another transistor structure provided in the related art;
fig. 3 is a schematic longitudinal sectional view of a transistor structure provided in the related art;
FIG. 4 is a schematic longitudinal cross-sectional view of a substrate provided in an embodiment of the invention;
fig. 5 is a schematic longitudinal cross-sectional view of a structure after forming a gate dielectric layer on a substrate in an embodiment of the present invention;
FIG. 6 is a schematic longitudinal cross-sectional view of the structure after forming a sacrificial layer in an embodiment of the present invention;
FIG. 7 is a schematic top view of a structure after forming a sacrificial layer according to an embodiment of the present invention;
FIG. 8 is a schematic top view of another embodiment of the structure after forming a sacrificial layer;
FIG. 9 is a schematic longitudinal cross-sectional view of a structure after forming a gate electrode over a sacrificial layer and a gate dielectric layer in an embodiment of the present invention;
FIG. 10 is a schematic longitudinal cross-sectional view of a first structure after forming source/drain regions in an embodiment of the present invention;
FIG. 11 is a schematic longitudinal cross-sectional view of the structure after removal of the sacrificial layer in an embodiment of the present invention;
FIG. 12 is a schematic longitudinal cross-sectional view of a post-sidewall formation structure according to an embodiment of the present invention;
FIG. 13 is a schematic top view of a post-sidewall formation structure according to an embodiment of the present invention;
fig. 14 is a schematic longitudinal cross-sectional view of a structure after forming a gate dielectric material layer in an embodiment of the present invention;
fig. 15 is a schematic longitudinal cross-sectional view of a structure after forming a gate electrode on a gate dielectric material layer in an embodiment of the present invention;
fig. 16 is a schematic longitudinal cross-sectional view of a structure after selectively etching at least two side edge regions of a gate dielectric material layer according to an embodiment of the present invention;
FIG. 17 is a schematic longitudinal cross-sectional view of a second structure after forming source/drain regions in an embodiment of the present invention;
fig. 18 is a schematic longitudinal sectional view of another structure after forming a sidewall in an embodiment of the present invention;
fig. 19 is a flow chart of a method for manufacturing a transistor according to an embodiment of the present invention;
reference numerals: 100 is a substrate, 101 is an active region, 102 is an isolation region, 103 is a gate stack, 1031 is a gate dielectric layer, 1032 is a gate electrode, 104 is a sacrificial layer, 105 is a sidewall, 106 is an air gap, 107 is a gate dielectric material layer, and 108 is a source/drain region.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is only exemplary and is not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and techniques are omitted so as not to unnecessarily obscure the concepts of the present disclosure.
Various structural schematic diagrams according to embodiments of the present disclosure are shown in the drawings. The figures are not drawn to scale, wherein certain details are exaggerated for clarity of presentation and may have been omitted. The shapes of the various regions, layers and relative sizes, positional relationships between them shown in the drawings are merely exemplary, may in practice deviate due to manufacturing tolerances or technical limitations, and one skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, if one layer/element is located "on" another layer/element in one orientation, that layer/element may be located "under" the other layer/element when the orientation is turned.
Fig. 1 to 3 show schematic structural views of a transistor provided in the related art. As shown in fig. 1 to 3, a transistor provided in the related art includes: a substrate 100, and a gate stack 103, sidewalls 105, and source/drain regions 108 formed on the substrate 100. The gate stack 103 includes: a gate dielectric layer 1031 formed on the substrate 100, and a gate electrode 1032 formed on the gate dielectric layer 1031. The sidewalls 105 are located at least on both sides of the gate stack 103 in the length direction.
As shown in fig. 3, the substrate 100 has an active region 101 and an isolation region 102. The upper portion of the active region 101 is used to fabricate active devices, and the isolation region 102 isolates the active devices from the elements. The substrate 100 may be a substrate on which no film layer is formed, or may be a substrate on which some film layers are formed. The substrate on which any film layer is not formed may be a silicon substrate, a germanium substrate, a silicon-on-insulator substrate, a germanium-on-insulator substrate, a silicon-germanium-on-insulator substrate, or a substrate containing another element semiconductor or a compound semiconductor, for example: gallium arsenide, indium phosphide, silicon carbide, glass substrates, plastic substrates, etc., are not listed here.
As shown in fig. 3, the gate dielectric layer 1031 is formed on the substrate 100. The gate dielectric layer 1031 is located on the active region 101. The gate dielectric layer 1031 may be made of SiO 2 SiON or a mixture thereof is also possible. Wherein, when the substrate 100 is a silicon substrate, the silicon substrate is oxidized under certain process conditions to form a layer of SiO 2 The method is very simple and widely applied for the gate dielectric layer 1031 of the material. When the gate dielectric layer 1031 is SiON, the SiON film layer can be obtained by treating the oxide layer on the surface of the silicon substrate, or can be formed by introducing a nitrogen source to react directly with the silicon substrate. SiON film and SiO 2 The film layer has better anti-reflection capability.
As shown in fig. 3, the gate electrode 1032 is formed on the gate dielectric layer 1031, and the gate electrode 1032 is located above the active region 101. The gate electrode 1032 is a core film layer of the transistor, and mainly controls a transverse electric field in the transistor, and plays a role in turning on an electron flow direction and communicating a device function. The gate electrode 1032 may include one or more layers of conductive material, which may be polysilicon or a metal material, to form a polysilicon gate (poly gate) or a metal gate (metalgate).
As shown in fig. 1, the sidewall 105 may be a strip sidewall, which extends along the width direction of the gate stack 103 and covers both sides of the gate stack 103 along the length direction. Alternatively, as shown in fig. 2, the sidewall 105 may also be an annular sidewall, which surrounds the circumference of the gate stack 103. As shown in fig. 3, the thickness of the sidewall 105 is not uniform along the height of the sidewall 105, and the thickness of the bottom is greater than the thickness of the top. The sidewall 105 may be made of insulating materials such as silicon nitride and silicon oxynitride.
As shown in fig. 3, the source/drain regions 108 are formed in the substrate 100 and are located on both sides of the gate stack 103 in the length direction. Specifically, the source/drain region 108 is formed in the active region 101 provided in the substrate 100, and the impurity type doped in the source/drain region 108 is opposite to the impurity type doped in the active region 101 provided in the substrate 100. The doping concentration of the impurities in the source/drain region 108 and the relative positional relationship between the source region and the drain region in the source/drain region 108 and the gate stack 103, respectively, may be set according to the actual application scenario, and are not particularly limited herein. For example: the source region of the source/drain regions 108 may be formed in the active region 101 on the left side of the gate stack 103 in the length direction, while the drain region of the source/drain regions 108 is formed in the active region 101 on the right side of the gate stack 103 in the length direction. Also for example: the source region of the source/drain regions 108 may be formed in the active region 101 on the lengthwise right side of the gate stack 103, while the drain region of the source/drain regions 108 is formed in the active region 101 on the lengthwise left side of the gate stack 103.
As the integration level of integrated circuits is higher and higher, the size of transistors applied to the integrated circuits is smaller and smaller, which not only increases the structural complexity of the devices, but also causes various parasitic capacitances to occur inside the transistors, so that the performance of the transistors is difficult to improve. Based on this, fig. 12 and 18 illustrate two schematic structural diagrams of the transistor provided in the embodiment of the present invention.
For convenience of description, only the differences between fig. 4 to 18 and fig. 1 to 3 will be described below. It should be understood that, according to the core concept of the transistor described below, a person skilled in the art may appropriately modify various existing transistors according to the actual application scenario, so as to obtain the transistor described below.
As shown in fig. 12 and 18, an air gap 106 is formed between the substrate 100 and the gate electrode 1032. The air gap 106 is located between the gate dielectric layer 1031 and the sidewall 105. Specifically, the air gaps 106 are located at least on two sides of the gate dielectric layer 1031 along the length direction (i.e., the extending direction of a). Since the air gap 106 corresponds to a position occupying a part of the gate dielectric layer 1031, it is considered that the air gap 106 is formed by reducing the length or the area of the gate dielectric layer 1031 to make a space. Since the dielectric constant of air is minimal in all materials, the presence of the air gap 106 can reduce parasitic capacitance in the transistor, thereby reducing the gate-source capacitance (Cgs), gate-drain capacitance (Cgd), and capacitance between the gate electrode 1032 and the substrate 100 (Cgb), improving transistor performance.
For example, as shown in fig. 12 and 18, when the entire length a of the gate dielectric layer 1031 (or the top length a of the gate dielectric layer 1031) is smaller than the length L of the gate electrode 1032, the air gap 106 may be formed in the remaining length direction. It is to be understood that the length direction of the gate dielectric layer 1031 coincides with the length direction of the gate electrode 1032. In addition to the length, if the cross-sectional area of each portion of the gate dielectric layer 1031 (or the cross-sectional area of the top portion of the gate dielectric layer 1031) is smaller than the cross-sectional area of the gate electrode 1032, the capacitance (Cgb) between the gate electrode 1032 and the substrate 100 can be reduced by reducing the cross-sectional area of the gate dielectric layer 1031, and the gate capacitance (Cox) per unit area can be reduced, thereby improving the gate control capability.
Illustratively, as shown in fig. 12, when the sum of the length B of the air gap 106 and the length a of the gate dielectric layer 1031 is equal to the length L of the gate electrode 1032. At this time, as shown in fig. 5 to 12, a sacrificial layer 104 may be formed around the gate dielectric layer 1031. Then, a gate electrode 1032 is formed over gate dielectric layer 1031 and sacrificial layer 104, and then sacrificial layer 104 is removed. At this time, the sum of the length B of the air gap 106 and the length a of the gate dielectric layer 1031 is equal to the length L of the gate electrode 1032.
Specifically, the morphology of the air gap can be set according to the morphology of the side wall included in the transistor and actual requirements. For example: as described above, the sidewall may be a strip sidewall. At this time, the air gap may be a stripe-shaped air gap. The strip-shaped air gaps extend along the width direction of the gate dielectric layer and cover two sides of the gate dielectric layer along the length direction. Also for example: as described above, the side wall may also be an annular side wall. In this case, the air gap may be a stripe-shaped air gap or an annular air gap. For details of the strip-shaped air gap reference is made to the foregoing. When the air gap is an annular air gap, the annular air gap surrounds the periphery of the gate dielectric layer.
As can be seen from the above description, the transistor shown in fig. 12 and 18 according to the embodiment of the present invention includes the air gaps 106 at least on two sides of the gate dielectric layer 1031 along the length direction. The air gap 106 replaces a portion of the gate dielectric layer 1031. Based on this, according to the capacitance formula(wherein W represents the width of the gate electrode, L represents the length of the gate electrode, ε) ox Representing the dielectric constant, t, of the gate dielectric material between the gate electrode and the substrate ox Representing the thickness of the gate dielectric layer), since the dielectric constant of air is smaller than that of the gate dielectric layer 1031, the gate capacitance (Cox) per unit area is reduced on the premise that the area of the gate electrode 1032 is unchanged, so that the gate control capability of the transistor is increased, the drain induced barrier lowering effect is reduced, and the operation performance of the transistor is improved.
As shown in fig. 12 and 18, the air gaps 106 are located at least on both sides of the gate dielectric layer 1031 in the longitudinal direction, and therefore, the shape of the side surfaces of the gate dielectric layer 1031 has a large correlation with the shape of the air gaps 106.
Illustratively, as shown in fig. 12, when the side of the gate dielectric layer 1031 is a vertical plane, the side of the air gap 106 adjacent to the gate dielectric layer 1031 is also a vertical plane. It can be appreciated that the side surface of the gate dielectric layer 1031 is a vertical plane, which has a simple structure, and can be quickly formed on the substrate 100 without a special etching manner, which is beneficial to simplifying the transistor manufacturing process.
Illustratively, as shown in fig. 18, the side surface of the gate dielectric layer 1031 may be an inclined surface, and the top length a of the gate dielectric layer 1031 is smaller than the bottom length (i.e., the length L of the gate electrode 1032). At this time, the side of the air gap 106 close to the gate dielectric layer 1031 is also inclined. For example: when the side surface of the gate dielectric layer 1031 is a slope having a concave arc, the cross-sectional shape of the air gap 106 around the gate dielectric layer 1031 is a sector. In practical applications, after forming the gate electrode 1032, at least two side regions of the gate dielectric layer 1031 may be etched along the length direction of the gate electrode, so that the top length of the gate dielectric layer 1031 may be reduced, but the bottom width of the gate dielectric layer 1031 may not be changed.
The embodiment of the invention also provides a manufacturing method of the transistor. As shown in fig. 19, the method for manufacturing a transistor according to the embodiment of the present invention includes the following steps:
as shown in fig. 4, a substrate 100 is provided, and an active region 101 and an isolation region 102 are provided inside the substrate 100. The substrate 100 described above includes any applicable semiconductor substrate, and reference is made in particular to the description of the substrate 100 above.
As shown in fig. 5 to 9, and 14 to 16, a gate stack 103 is formed on a substrate 100. The gate stack 103 includes a gate dielectric layer 1031 formed on the substrate 100, and a gate electrode 1032 on the gate dielectric layer 1031. An opening is formed between the substrate 100 and the gate electrode 1032, and the opening is located at least on both sides of the gate dielectric layer 1031 in the longitudinal direction.
As shown in fig. 10 and 17, source/drain regions 108 located on both sides of the gate stack 103 in the length direction are formed in the substrate 100.
In the practical application process, after the gate stack is formed, the conductive particles may be doped on the portions of the substrate located at two sides of the gate stack along the length direction by using a diffusion or ion implantation process, so as to form the source/drain regions.
As shown in fig. 11 to 13 and fig. 18, side walls 105 are formed on the substrate 100 at least on both sides of the gate stack 103 in the length direction such that an air gap 106 is formed by surrounding the openings by the side walls 105, the substrate 100 and the gate stack 103.
It can be appreciated that the shape of the opening is matched with the shape of the air gap because the air gap is formed after the side wall is obtained at the position corresponding to the opening. Based on this, as described above, the specific forming process of the gate stack, the sidewall and the air gap is different due to the different side morphology of the gate dielectric layer and the different shape of the air gap. Specifically, the formation process may be divided into at least two types:
first kind: as shown in fig. 5, a gate dielectric layer 1031 is formed on the substrate 100. As shown in fig. 6 to 8, a sacrificial layer 104 is formed on the substrate 100 at least on both sides of the gate dielectric layer 1031 in the longitudinal direction. As shown in fig. 9, a gate electrode 1032 is formed over the gate dielectric layer 1031 and the sacrificial layer 104. As shown in fig. 11, the above-described sacrifice layer 104 is removed, and an opening between the substrate 100 and the gate electrode 1032 is obtained. As shown in fig. 11, the sidewall 105 is formed on the substrate 100. The sidewalls 105, substrate 100 and gate stack 103 surround the opening to form an air gap 106.
By way of example, a film of insulating material may be deposited on the substrate in a manner that deposits a thin film. The insulating material film layer is covered on the substrate. As shown in fig. 5, the gate dielectric layer 1031 is obtained by performing photolithography and etching on both ends of the insulating material film layer along the direction in which the source region and the drain region are distributed. At this time, the length direction of the gate dielectric layer 1031 coincides with the length direction of the source region and the drain region. Then, a material with a material density lower than that of the gate dielectric layer can be selected, a sacrificial material layer covering the side surface and the upper surface of the gate dielectric layer is formed on the substrate in a spin coating mode, and then the sacrificial material layer is subjected to back etching treatment to achieve a planarization effect, so that the height of the rest part of the sacrificial material layer is consistent with that of the gate dielectric layer, and the sacrificial layer is obtained. Compared with the material of the gate dielectric layer, the material with smaller density is selected for the sacrificial layer, so that the wet etching rate of the material of the sacrificial layer can be increased, the sacrificial layer can be removed at the same time, and the gate dielectric layer is reserved. In the case where the air gap is an annular air gap, the sacrificial layer is an annular sacrificial layer matching the annular air gap, as described above. In the case that the air gap is a stripe-shaped air gap, the sacrificial layer is a stripe-shaped sacrificial layer matching the stripe-shaped air gap. Then, a conductive material film layer can be formed on the gate dielectric layer in a deposition mode and covers the gate dielectric layer and the sacrificial layer. As shown in fig. 9, the gate electrode 1032 is obtained by patterning the conductive material film layer by photolithography and etching processes. For example, when the gate electrode 1032 is polysilicon, a polysilicon gate is formed. And when the gate electrode 1032 is made of a metal material, a metal gate is formed. As shown in fig. 10, the above-described process may be employed to form source/drain regions 108 in portions of the substrate 100 located on both sides of the gate stack 103 in the length direction. As shown in fig. 11, the sacrificial layer 104 may be removed by a wet etching method using an etchant having a high selectivity. The use of the etchant with a high selectivity is to etch the sacrificial layer 104 with the same etchant at a fast rate and etch the gate dielectric layer 1031 with a slow rate at the same time, so that the sacrificial layer 104 under the gate electrode 1032 can be removed, and the gate dielectric layer 1031 between the sacrificial layers 104 is remained. Throughout this operation, sacrificial layer 104 is preformed to preserve the spatial position of the subsequently formed openings. At this time, an opening may be formed between the substrate 100 and the gate electrode 1032, the opening being located at least at both sides of the gate dielectric layer 1031 in the longitudinal direction. As shown in fig. 11, a low step coverage process may be finally employed to form sidewalls 105 on the substrate 100 and outside of the gate stack 103. The low step coverage process can be a silane-based process, a sputtering process, or an evaporation process. For example: a low-coverage and dense sidewall 105 can be formed on the outside of the gate stack 103 and on the substrate 100 by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) process Plasma Enhanced Chemical Vapor Deposition at a lower temperature without affecting the substrate structure and physical properties. At this time, the sidewall 105, the substrate 100, and the gate stack 103 surround the opening to form the air gap 106.
Note that in the above manufacturing process, a sacrificial layer is formed around the gate dielectric layer in advance, and then, as shown in fig. 11 and 11, the sacrificial layer 104 is removed and the sidewall 105 is formed, so that an air gap 106 is formed between the substrate 100 and the gate electrode 1032 and covers around the gate dielectric layer 1031. Since the dielectric constant of air is smaller than that of the gate dielectric layer 1031, the gate-source capacitance (Cgs), the gate-drain capacitance (Cgd), and the capacitance (Cgb) between the gate electrode 1032 and the substrate 100 are reduced. At this time, on the premise that the area of the gate electrode 1032 is unchanged, the gate capacitance (Cox) per unit area is reduced, so that the gate control capability of the transistor is improved, the drain-induced barrier lowering effect is further reduced, and the working performance of the transistor is improved.
Second kind: as shown in fig. 14, a gate dielectric material layer 107 is formed on the substrate 100. As shown in fig. 15, a gate electrode 1032 is formed on the gate dielectric material layer 107. As shown in fig. 16, at least two side edge regions of the gate dielectric material layer 107 are etched along the length direction of the gate electrode 1032, so as to obtain a gate dielectric layer 1031 and an opening between the substrate 100 and the gate electrode 1032. As shown in fig. 18, the side wall 105 is formed on the substrate 100. At this time, the sidewall 105 and the gate stack 103 surround the opening to form the air gap 106.
For example, a layer of insulating material film can be deposited on the substrate in a mode of depositing a film, and the insulating material film is etched in a simple etching mode, so that the gate dielectric material layer is obtained. And forming a conductive material film layer on the gate dielectric material layer in a deposition mode, and obtaining the gate electrode by photoetching and etching processes so that the length of the rest part of the conductive material film layer is the same as that of the gate dielectric material layer. For example: when the gate electrode material is polysilicon, a polysilicon gate is formed. And when the gate electrode material is a metal material, a metal gate is formed. As shown in fig. 16, an etching solution with a high selectivity may be selected to use a wet etching method, and at least two side edge regions of the gate dielectric material layer 107 along the length direction are etched in combination with a photolithography process, so that the gate dielectric layer 1031 is formed on the remaining portion of the gate dielectric material layer 107, and an opening between the substrate 100 and the gate electrode 1032 is obtained. In the case where the air gap is an annular air gap, etching is required for both side edge regions of the gate dielectric material layer in the longitudinal direction and both side edge regions thereof in the width direction, as described above. And under the condition that the air gap is a strip-shaped air gap, only the edge areas at the two sides of the gate dielectric material layer along the length direction are required to be etched. In addition, due to the characteristics of the etchant, the side surface of the gate dielectric layer obtained at this time is mostly an inclined surface with a concave radian, which also makes the top length a of the gate dielectric layer smaller than the bottom length (i.e., the length L of the gate electrode 1032), and covers the opening around the gate dielectric layer, and the cross-sectional shape of the opening is mostly a sector shape because of the close contact with the side surface of the gate dielectric layer. In the same time, at least two side edge regions of the gate dielectric material layer below the gate electrode along the length direction need to be removed, an etchant with a slow etching rate to the gate electrode material and a fast etching rate to the gate dielectric material layer needs to be selected, so that the gate electrode on the gate dielectric material layer is not damaged, and the yield of the transistor is improved. As shown in fig. 17, the above-described process may be employed to form source/drain regions 108 in portions of the substrate 100 located on both sides of the gate stack 103 in the length direction. As shown in fig. 18, a low step coverage process may be finally used to form a sidewall 105 on the substrate 100 to obtain an air gap 106. The low step coverage process may be a silane-based process (e.g., a plasma enhanced chemical vapor deposition process), a sputtering process, or an evaporation process. For example: the low-coverage and dense sidewall 105 can be formed on the substrate 100 by a plasma enhanced chemical vapor deposition process at a lower temperature without affecting the structure and physical properties of the substrate 100.
It is to be noted that, as shown in fig. 14 to 18, the above manufacturing process is to etch at least two side edge regions of the gate dielectric material layer 107 between the substrate 100 and the gate electrode 1032 in the length direction along the length direction of the gate electrode 1032, so as to obtain the gate dielectric layer 1031 and the opening between the substrate 100 and the gate electrode 1032. At this time, the top length a of the gate dielectric layer 1031 is smaller than the bottom length (i.e., the length L of the gate electrode 1032), and the opening covers the periphery of the gate dielectric layer 1031. After the formation of the side wall 105, an air gap 106 is obtained at the location of the opening. The air gap 106 replaces a portion of the gate dielectric layer 1031 such that the area of the gate dielectric layer 1031 is reduced. At this time, on the premise that the area of the gate electrode 1032 is not changed, the overlapping area of the gate dielectric layer 1031 with the gate electrode 1032 and the source and drain regions is also reduced, and therefore, the gate-source capacitance (Cgs), the gate-drain capacitance (Cgd), and the capacitance (Cgb) between the gate electrode 1032 and the substrate 100 are reduced. According to the capacitance formula, the gate capacitance per unit area (Cox) decreases due to the decrease in epsilon ox due to the air gap 106 existing between the gate electrode 1032 and the substrate 100. At the same time Cgs and Cgd are further reduced by the reduction of Cox. At this time, the gate control capability of the transistor is raised, so that the drain-induced barrier lowering effect is reduced, and the working performance of the transistor is improved.
In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.
The embodiments of the present disclosure are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the disclosure, and such alternatives and modifications are intended to fall within the scope of the disclosure.

Claims (12)

1. A transistor, comprising:
a substrate;
a gate stack formed on the substrate; the grid stack comprises a grid dielectric layer formed on the substrate and a grid electrode positioned on the grid dielectric layer;
the side walls are formed on the substrate and at least positioned at two sides of the gate stack along the length direction;
source/drain regions formed in the substrate and located on both sides of the gate stack in the length direction;
and an air gap formed on the substrate; and the air gap is positioned between the substrate and the gate electrode and between the gate dielectric layer and the side wall.
2. The transistor of claim 1, wherein the sides of the gate dielectric layer are vertical planes;
or, the side surface of the gate dielectric layer is an inclined surface, and the top length of the gate dielectric layer is smaller than the bottom length.
3. The transistor of claim 1, wherein the sidewall is a strip sidewall; the strip-shaped side walls extend along the width direction of the gate stack and cover the two sides of the gate stack along the length direction.
4. The transistor of claim 1, wherein the air gap is a stripe-shaped air gap extending along a width direction of the gate stack and covering both sides of the gate dielectric layer along a length direction.
5. The transistor according to any one of claims 1 to 4, wherein the gate dielectric layer is made of SiO 2 And one or both of SiON;
and/or the substrate comprises an active region and an isolation region, and the gate dielectric layer and the gate electrode are positioned on the active region.
6. A method of manufacturing a transistor, comprising:
providing a substrate;
forming a gate stack on the substrate; the grid stack comprises a grid dielectric layer formed on the substrate and a grid electrode positioned on the grid dielectric layer; an opening is formed between the substrate and the gate electrode, and the opening is at least positioned at two sides of the gate dielectric layer along the length direction;
forming source/drain regions on two sides of the gate stack along the length direction in a substrate;
and forming side walls at least positioned on two sides of the grid stack along the length direction on the substrate, so that an air gap is formed by surrounding the opening by the side walls, the substrate and the grid stack.
7. The method of manufacturing a transistor according to claim 6, wherein the forming a gate stack over the substrate comprises:
forming a gate dielectric layer on the substrate;
forming a sacrificial layer at least positioned on two sides of the gate dielectric layer along the length direction on the substrate;
forming a gate electrode on the gate dielectric layer and the sacrificial layer;
and removing the sacrificial layer to obtain the opening between the substrate and the gate electrode.
8. The method of manufacturing a transistor according to claim 7, wherein forming a sacrificial layer on the substrate at least on both sides of the gate dielectric layer in a longitudinal direction comprises:
forming a sacrificial material layer covering the side surface and the upper surface of the gate dielectric layer on the substrate in a spin coating mode;
and carrying out back etching on the sacrificial material layer to obtain the sacrificial layer.
9. The method of manufacturing a transistor according to claim 7, wherein a material density of the sacrificial layer is lower than a material density of the gate dielectric layer.
10. The method of manufacturing a transistor according to claim 6, wherein the forming a gate stack over the substrate comprises:
forming a gate dielectric material layer on the substrate;
forming a gate electrode on the gate dielectric material layer;
and selectively etching at least two side edge regions of the gate dielectric material layer along the length direction of the gate electrode to obtain the gate dielectric layer and the opening between the substrate and the gate electrode.
11. The method of manufacturing a transistor according to claim 10, wherein selectively etching at least two side edge regions of the gate dielectric material layer comprises: etching at least two side edge area materials of the gate dielectric material layer in a photoetching and wet etching mode along the length direction of the gate electrode to obtain the gate dielectric layer; the side surface of the gate dielectric layer is an inclined surface.
12. The method of manufacturing a transistor according to claim 6, wherein forming sidewalls on the substrate at least on both sides of the gate stack in a length direction comprises:
and forming the side walls at least positioned at two sides of the gate stack along the length direction on the substrate by adopting a low-step coverage process.
CN202210935785.6A 2022-08-04 2022-08-04 Transistor and manufacturing method thereof Pending CN117558756A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202210935785.6A CN117558756A (en) 2022-08-04 2022-08-04 Transistor and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202210935785.6A CN117558756A (en) 2022-08-04 2022-08-04 Transistor and manufacturing method thereof

Publications (1)

Publication Number Publication Date
CN117558756A true CN117558756A (en) 2024-02-13

Family

ID=89813409

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202210935785.6A Pending CN117558756A (en) 2022-08-04 2022-08-04 Transistor and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN117558756A (en)

Similar Documents

Publication Publication Date Title
KR100487656B1 (en) Semiconductor device including an air gap between a semiconductor substrate and an L-shape spacer and method for forming the same
KR100627955B1 (en) Sectional Field Effect Devices and Method of Fabrication
US9190486B2 (en) Integrated circuits and methods for fabricating integrated circuits with reduced parasitic capacitance
US8962430B2 (en) Method for the formation of a protective dual liner for a shallow trench isolation structure
US11588051B2 (en) Semiconductor device and fabrication method thereof
CN112530943A (en) Semiconductor device and method for manufacturing the same
EP1565931A1 (en) Strained finfet cmos device structures
US11742245B2 (en) Semiconductor fabrication method and structure using multiple sacrificial layers to form sidewall spacers
CN112530942A (en) Semiconductor device and method of forming the same
JP4081006B2 (en) A method for manufacturing a semiconductor device.
US20230118901A1 (en) Semiconductor device
US10748814B2 (en) Fabrication method of semiconductor device by removing sacrificial layer on gate structures
US20130146966A1 (en) Semiconductor structure with enhanced cap and fabrication method thereof
KR100886708B1 (en) Soi device and method for fabricating the same
US7288447B2 (en) Semiconductor device having trench isolation for differential stress and method therefor
CN117558756A (en) Transistor and manufacturing method thereof
CN110690218B (en) Semiconductor device and method of forming the same
US20080038911A1 (en) Method for manufacturing semiconductor device
KR20050055501A (en) Methods of fabricating a semiconductor device including a t-shaped gate and an l-shaped spacer
CN113838934A (en) Semiconductor structure and forming method thereof
US20190019869A1 (en) Semiconductor device and method for manufacturing the same
US20120126337A1 (en) Source/drain-to-source/drain recessed strap and methods of manufacture of same
CN111755336B (en) Preparation method of field effect transistor, field effect transistor and semiconductor substrate
US10651092B2 (en) Semiconductor device and fabrication method thereof
CN102856198B (en) Semiconductor structure and preparation method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination