CN117558680A - Three-dimensional integrated circuit chip and high-level power supply network design method - Google Patents
Three-dimensional integrated circuit chip and high-level power supply network design method Download PDFInfo
- Publication number
- CN117558680A CN117558680A CN202311532763.6A CN202311532763A CN117558680A CN 117558680 A CN117558680 A CN 117558680A CN 202311532763 A CN202311532763 A CN 202311532763A CN 117558680 A CN117558680 A CN 117558680A
- Authority
- CN
- China
- Prior art keywords
- design
- chip
- area
- sub
- power
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000013461 design Methods 0.000 title claims abstract description 333
- 238000000034 method Methods 0.000 title claims abstract description 63
- 239000002184 metal Substances 0.000 claims abstract description 161
- 229910052751 metal Inorganic materials 0.000 claims abstract description 161
- 238000013507 mapping Methods 0.000 claims abstract description 22
- 229910052710 silicon Inorganic materials 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 238000013439 planning Methods 0.000 description 21
- 238000010586 diagram Methods 0.000 description 17
- 230000008569 process Effects 0.000 description 16
- 238000003860 storage Methods 0.000 description 16
- 239000000758 substrate Substances 0.000 description 12
- 238000013515 script Methods 0.000 description 9
- 239000011295 pitch Substances 0.000 description 8
- 230000003014 reinforcing effect Effects 0.000 description 6
- 238000004806 packaging method and process Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 238000004804 winding Methods 0.000 description 2
- 230000002146 bilateral effect Effects 0.000 description 1
- 238000013440 design planning Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 210000001503 joint Anatomy 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000010076 replication Effects 0.000 description 1
- 230000007723 transport mechanism Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- General Engineering & Computer Science (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
A three-dimensional integrated circuit chip and a high-level power network design method, the three-dimensional integrated circuit chip includes: the design method comprises the steps of: acquiring a layout structure of the highest-layer metal of the first chip and a power supply network requirement of the first chip in the second chip; designing a layout structure of the highest-layer metal of the second chip, wherein the highest-layer metal of the second chip comprises a mapping area, a first design area and a second design area, the layout structure of the highest-layer metal of the mapping area is the same as that of the highest-layer metal of the first chip, the first design area is used for providing a first-layer power supply network for the second chip, and the second design area is used for providing a first-layer reinforced power supply network for the first chip; the first design area includes a plurality of first sub-design areas of identical design and/or the second design area includes a plurality of second sub-design areas of identical design.
Description
Technical Field
The present disclosure relates to the field of chip design, and more particularly, to a wafer bonding layout structure and a three-dimensional integrated circuit chip.
Background
With the development of integrated circuits, large-scale circuits and ultra-large-scale circuits are being produced. Accordingly, transistor density in integrated circuits is also geometrically increasing. The manner in which transistors are connected by placing interconnect lines in-plane occupies excessive chip area and interconnect line delay has become a non-negligible part after the fabrication process iterates to a scale with moore's law. Therefore, three-dimensional stacking technology is becoming a currently mainstream breakthrough in designing chips.
For high-throughput three-dimensional integrated circuit (3 DIC) chips, we need to design at least two chips and stack them together. The highest Metal (Top Metal) of two chips needs to be completely connected, wherein the Power network (Power Good, PG) and the Signal Port (Signal Port) of one chip (called chip 1) use the highest Metal, the occupancy of the highest Metal is very large, basically the highest Metal of the other chip (called chip 2) is basically used for meeting the PG corresponding relation of the chip 1, and the Signal (Signal) of the chip 2 uses little of the highest Metal. The highest metal of the chip 2 affects the design scheme and routing resources of the next highest metal of the chip 2, so that the design planning of the high-level power supply network of the chip 2 is more limited and difficult.
Disclosure of Invention
The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.
The embodiment of the disclosure provides a high-level power supply network design method, which is applicable to a three-dimensional integrated circuit chip, wherein the three-dimensional integrated circuit chip comprises: the high-level power supply network design method comprises the following steps of:
acquiring a layout structure of the highest metal layer of the first chip and a power supply network requirement of the first chip in the second chip;
designing a layout structure of the highest-layer metal of the second chip, wherein the highest-layer metal of the second chip comprises a mapping area, a first design area and a second design area, the layout structure of the highest-layer metal of the mapping area is the same as that of the highest-layer metal of the first chip, the first design area is used for providing a first-layer power supply network for the second chip, and the second design area is used for providing a first-layer reinforced power supply network for the first chip; the first design area includes a plurality of first sub-design areas of identical design and/or the second design area includes a plurality of second sub-design areas of identical design.
The embodiment of the disclosure also provides a three-dimensional integrated circuit chip, which comprises a first chip and a second chip, wherein a high-level power supply network of the first chip is predefined, and the high-level power supply network of the second chip is designed by using the high-level power supply network design method according to any embodiment of the disclosure.
According to the three-dimensional integrated circuit chip and the high-level power supply network design method, the mapping area is arranged in the highest-level metal of the second chip, and the layout structure of the highest-level metal of the mapping area is the same as that of the highest-level metal of the first chip, so that the highest-level metal layers of the first chip and the second chip can be perfectly butted; the first layer of reinforced power supply network is designed in the highest layer of metal of the second chip, so that the requirement of the reinforced power supply network of the first chip is met; the voltage drop requirement of the second chip is met by designing a first layer of power supply network in the highest layer of metal of the second chip; the second chip is divided into a plurality of sub-design areas with the same design, the high-level power supply network of one sub-design area is designed firstly, then the designed structure is copied TO other sub-design areas, the time for planning the high-level power supply network of the three-dimensional integrated circuit chip is effectively saved, and the time for chip streaming (Tape-out, TO) is advanced.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. Other advantages of the present application may be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
The accompanying drawings are included to provide an understanding of the technical aspects of the present disclosure, and are incorporated in and constitute a part of this specification, illustrate the technical aspects of the present disclosure and together with the embodiments of the disclosure, not to limit the technical aspects of the present disclosure.
FIG. 1 is a flow chart of a method of designing a high-level power network according to an exemplary embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a three-dimensional integrated circuit chip according to an exemplary embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a first chip according to an exemplary embodiment of the disclosure;
FIG. 4 is a top-level metal layout plan schematic of a first chip according to an exemplary embodiment of the present disclosure;
FIG. 5 is a top-level metal layout plan schematic of each 1GB array region in accordance with an exemplary embodiment of the present disclosure;
FIG. 6 is a top level metal layout schematic of each minimum design unit according to an exemplary embodiment of the present disclosure;
FIG. 7 is a top level metal layout plan view of area A of one of the minimum design units shown in FIG. 5;
FIG. 8 is a schematic illustration of the locations of a first sub-design area and a second sub-design area in accordance with an exemplary embodiment of the present disclosure;
FIG. 9 is a schematic illustration of the location of a first sub-design area in accordance with an exemplary embodiment of the present disclosure;
FIG. 10 is a schematic diagram of a power line layout of a first sub-design area according to an exemplary embodiment of the present disclosure;
FIG. 11 is a schematic diagram of a power line layout of a second sub-design area according to an exemplary embodiment of the present disclosure;
FIG. 12 is a schematic diagram of a power line layout within a minimum design unit according to an exemplary embodiment of the present disclosure;
FIG. 13 is a schematic diagram of a layout of a sixth power line and a third power line according to an exemplary embodiment of the present disclosure;
FIG. 14 is a schematic illustration of placement of through-silicon vias within a minimum design unit in accordance with an exemplary embodiment of the present disclosure;
FIG. 15 is a schematic diagram of a layout of a third power line and a fourth power line according to an exemplary embodiment of the present disclosure;
FIG. 16 is a schematic diagram of a layout of a seventh power line according to an exemplary embodiment of the present disclosure;
FIG. 17 is a schematic diagram of a layout of an eighth power line according to an exemplary embodiment of the present disclosure;
FIG. 18 is a schematic diagram of a layout of an M10 power network in accordance with an exemplary embodiment of the present disclosure;
FIG. 19 is a schematic diagram of a layout of a ninth power line according to an exemplary embodiment of the present disclosure;
fig. 20 is a schematic diagram of a layout plan of an M9 power network according to an exemplary embodiment of the disclosure.
Detailed Description
The present application describes a number of embodiments, but the description is illustrative and not limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or in place of any other feature or element of any other embodiment unless specifically limited.
The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements of the present disclosure may also be combined with any conventional features or elements to form a unique inventive arrangement as defined in the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive arrangements to form another unique inventive arrangement as defined in the claims. Thus, it should be understood that any of the features shown and/or discussed in this application may be implemented alone or in any suitable combination. Accordingly, the embodiments are not to be restricted except in light of the attached claims and their equivalents. Further, various modifications and changes may be made within the scope of the appended claims.
Furthermore, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other sequences of steps are possible as will be appreciated by those of ordinary skill in the art. Accordingly, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Furthermore, the claims directed to the method and/or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present application.
Unless otherwise defined, technical or scientific terms used in the disclosure of the embodiments of the present disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present disclosure pertains. The terms "first," "second," and the like, as used in embodiments of the present disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, is intended to mean that elements or items preceding the word encompass the elements or items listed thereafter and equivalents thereof without precluding other elements or items.
As shown in fig. 1, an embodiment of the present disclosure provides a high-level power network design method, which is applicable to a second chip in a three-dimensional integrated circuit chip, where the three-dimensional integrated circuit chip further includes: the high-level power supply network of the first chip is predefined, and the high-level power supply network design method comprises the following steps:
step 101, obtaining a layout structure of the highest metal layer of a first chip and a power supply network requirement of the first chip in a second chip;
102, designing a layout structure of the highest metal of the second chip, wherein the highest metal of the second chip comprises a mapping area, a first design area and a second design area, the layout structure of the highest metal of the mapping area is the same as that of the highest metal of the first chip, the first design area is used for providing a first layer of power supply network for the second chip, and the second design area is used for providing a first layer of reinforced power supply network for the first chip; the first design area includes a plurality of first sub-design areas of identical design and/or the second design area includes a plurality of second sub-design areas of identical design.
According to the high-level power supply network design method provided by the embodiment of the disclosure, the mapping area is arranged in the highest-level metal of the second chip, and the layout structure of the highest-level metal of the mapping area is the same as that of the highest-level metal of the first chip, so that the highest-level metal layers of the first chip and the second chip can be perfectly butted; through dividing each layer of metal of the second chip into a plurality of sub-design areas with the same design, firstly designing a high-level power supply network of one sub-design area, and then copying the structure of the designed sub-design area to other sub-design areas, the time for planning the high-level power supply network of the three-dimensional integrated circuit chip is effectively saved, and the time for chip streaming is promoted.
It should be noted that, in the embodiment of the present disclosure, when the first design area is divided into a plurality of first sub-design areas with the same design, the second design area may be divided into a plurality of second sub-design areas with the same design, or may not be divided into a plurality of second sub-design areas with the same design. Similarly, when the second design area is divided into a plurality of second sub-design areas having the same design, the first design area may or may not be divided into a plurality of first sub-design areas having the same design.
In some exemplary embodiments, as shown in fig. 2, the first chip is flip-chip interconnected with the second chip; the surface of the first chip remote from the second chip includes a plurality of metal bumps (bumps), through which the first chip is electrically connected to the package substrate (not shown).
In some exemplary embodiments, the first chip may be a memory chip and the second chip may be a logic computing chip, however, the embodiments of the present disclosure are not limited thereto, and the first chip and the second chip may be other types of chips. In some exemplary embodiments, the memory chip may be a dynamic random access memory (Dynamic Random Access Memory, DRAM) memory chip.
In some exemplary embodiments, a package substrate is used for packaging the first chip and the second chip, and the package substrate may include a base, pads, wires (not shown in the drawings), and the like, and a lower surface of the package substrate may be electrically connected to a printed wiring board (Printed Circuit Board, PCB) through the pads. The packaging substrate can provide the effects of electric connection, protection, support, heat dissipation, assembly and the like for the first chip and the second chip, so as to realize the purposes of multi-pin, reduction of the volume of a packaging product, improvement of electric performance and heat dissipation, ultra-high density or multi-chip modularization.
In some exemplary embodiments, the first chip may include a substrate (not shown in the drawings) and a plurality of metal layers (only two metal layers are shown in the drawings) disposed on the substrate, and since the first chip adopts a flip-chip process, the substrate should be located on a side of the metal layers away from the second chip in fig. 2, the plurality of metal layers include a first metal layer to an nth metal layer (i.e., a top metal layer) sequentially disposed along a direction away from the substrate, n is an integer greater than or equal to 3, the first chip further includes at least one through silicon via penetrating the substrate and extending from a surface of the first chip on a side away from the second chip to one metal layer (illustratively, extending to the sub-top metal layer) of the plurality of metal layers, at least one metal layer of the plurality of metal layers being electrically connected to the metal bump through the through silicon via; the surface of the first chip close to the second chip is electrically connected with the second chip by Hybrid Bonding (HB) or the like.
In some exemplary embodiments, the number of layers of the plurality of metal layers in the first chip may be set according to design requirements. Illustratively, the first chip may include 11 or 12 metal layers, however, embodiments of the present disclosure are not limited in this regard.
In some exemplary embodiments, the first chip may further include a Re-routing layer (Re-distribution Layer, RDL) disposed on a surface of the first chip on a side thereof remote from the package substrate, through which the metal bumps may be electrically connected to the package substrate.
The first chip and the second chip of the embodiment of the disclosure adopt a 3DIC packaging mode, and the first chip and the second chip are packaged together in a 3D stacking mode, so that the size of the first chip and the size of the second chip are completely consistent.
Fig. 3 is a schematic design diagram of a first chip according to an exemplary embodiment of the present disclosure, as shown in fig. 3, assuming that a storage capacity of the first chip is 8GB (the storage capacity of the first chip may be actually set according to needs), the first chip is divided into 4 storage modules, and a storage capacity of each storage module is 2GB, where the storage module Node00 and the storage module Node01 are bilaterally symmetric about a center line O2 of the first chip along the first direction D1, and the storage module Node10 and the storage module Node11 are bilaterally symmetric about a center line O2 of the first chip along the first direction D1; the memory module Node00 and the memory module Node10 are vertically symmetrical with respect to a center line O1 of the first chip along the second direction D2, and the memory module Node01 and the memory module Node11 are vertically symmetrical with respect to a center line O1 of the first chip along the second direction D2. In the embodiment of the present disclosure, the first direction D1 and the second direction D2 intersect. For example, the first direction D1 and the second direction D2 may be perpendicular to each other.
Fig. 4 is a schematic diagram of a top metal layout of a first chip, and as shown in fig. 4, a white dotted filling area is a top metal area, and a gray non-dotted filling area is a non-top metal area.
As shown in fig. 4, one memory module is composed of two 1GB memory regions (one 1GB memory region may be referred to as one array region), and within each memory module, the top metals of the two 1GB memory regions are symmetrical up and down with respect to the center line O11 or O11' of the memory module in the second direction D2.
Fig. 5 is a schematic diagram of top metal layout plan of each 1GB array region, as shown in fig. 5, each 1GB array region includes a plurality of minimum design units arranged in an array (in fig. 5, each 1GB array region includes 12×4=48 minimum design units, and a capacity of each minimum design unit is 21.25 MB). The present disclosure plans the higher-level power network with a capacity of 21.25MB for the minimum design unit, but the present disclosure is not limited thereto, and in other examples, the higher-level power network may be planned with different sized minimum design units.
FIG. 6 is a schematic top metal layout diagram of each of the minimum design units, FIG. 7 is a schematic top metal layout diagram of the area A of one of the minimum design units shown in FIG. 5, and as shown in FIGS. 6 and 7, each of the minimum design units includes a plurality of first direction power supply network regions, a plurality of lead regions disposed between the plurality of first direction power supply network regions, and second direction power supply network regions disposed on both sides of the first direction power supply network regions and the lead regions along the first direction D1, the first direction power supply network regions include a plurality of fifth power supply lines extending along the first direction D1, the second direction power supply network regions include a plurality of sixth power supply lines extending along the second direction D2, and each of the fifth power supply lines and the sixth power supply lines is used for providing a power supply network for the first chip; the pin field includes a plurality of pins.
In some exemplary embodiments, the second chip includes a plurality of metal layers, and the number of the plurality of metal layers in the second chip may be set according to design requirements. Illustratively, the second chip may include 10, 11, or 12 metal layers, etc., however, embodiments of the present disclosure are not limited thereto.
In some exemplary embodiments, a first design area is located at a spacing region between two rows of minimum design cells adjacent in the second direction D2 within each array region, the first design area including a plurality of first power lines extending in the first direction, the plurality of first power lines for providing a first tier power network for the second chip.
In some exemplary embodiments, the second design area is located at a spacing region between two array regions adjacent along the second direction D2, the second design area including a plurality of second power lines extending along the first direction, the plurality of second power lines for providing the first chip with a first layer of enhanced power supply network.
In the present disclosure, a extends in the B direction means that a may include a main portion and a sub portion connected to the main portion, the main portion being a line, a line segment, or a bar-shaped body, the main portion extending in the B direction, and the main portion extending in the B direction over a length greater than that of the sub portion extending in other directions.
In some exemplary embodiments, designing the layout structure of the highest level metal of the second chip includes:
the layout structure of the highest-layer metal of the first chip is copied to the mapping area of the highest-layer metal of the second chip, the mapping areas of the highest-layer metal of the first chip and the highest-layer metal of the second chip respectively comprise a plurality of array areas symmetrically arranged along the first direction D1 and/or the second direction D2, and each array area comprises a plurality of minimum design units which are arranged in an array mode.
In some exemplary embodiments, designing the layout structure of the highest level metal of the second chip further includes:
dividing the first design area into a plurality of first sub-design areas, the first sub-design areas being disposed between two rows of minimum design units adjacently disposed along the second direction D2, as shown in fig. 8;
designing layout structures of a plurality of first power lines in a first sub-design area; copying the layout structure of the first power line of the designed first sub-design area to other first sub-design areas of the same array area, thereby completing the layout structure of the first power line of one array area (as the first power line extends along the first direction D1, the layout structure of the first power line of the array area is adopted by other array areas which are in the same row with the array area); and symmetrically copying the layout structure of the first power lines of the completed array area to other array areas along the first direction D1, wherein the plurality of first power lines are used for providing a first layer of power network for the second chip.
In some exemplary embodiments, designing the layout structure of the highest level metal of the second chip further includes:
dividing the second design area into a plurality of second sub-design areas, the second sub-design areas being disposed between two rows of array areas adjacently disposed along the second direction D2, as shown in fig. 8;
designing layout structures of a plurality of second power lines in a second sub-design area; and copying the layout structure of the second power lines of the designed second sub-design area to other second sub-design areas, wherein the second power lines are used for providing a first layer of reinforced power supply network for the first chip.
In the embodiment of the disclosure, the high-level power network of the second chip may be formed by the highest-level metal of the second chip and one or more metal layers from the highest-level metal down. Illustratively, assuming the second chip employs a 1P12M (one Poly layer 12 metal layer) process, the second chip includes 12 layers of metal, the highest layer of metal being the top metal layer, namely, the 12 th metal layer M12; the next highest metal layer is the next top metal layer, namely the 11 th metal layer M11; the third high-level metal is the first metal layer with the downward second top metal layer, namely the 10 th metal layer M10; the fourth higher metal layer refers to the second metal layer with the next highest metal layer down, namely the 9 th metal layer M9. The high-level power network of the second chip may be formed of the 10 th to 12 th metal layers M10 to M12, may be formed of the 9 th to 12 th metal layers M9 to M12, or may be formed of the 11 th to 12 th metal layers M11 to M12, however, the embodiment of the present disclosure is not limited thereto. For the 1P12M process, M9, M10, M11 and M12 can all be considered high-level metal layers. The following description will take the 1P12M process and the high-level power network located in the M9 to M12 layers as an example, but the disclosure is not limited to the 1P12M process and the number of high-level metal layers, and other processes and the number of high-level metal layers are equally applicable.
Taking the 1P12M process and the high-level power network being located in the M9-M12 layers as an example, the high-level power network scheme for designing and planning the second chip of the present disclosure may be implemented in four stages, where the first stage designs and plans the M12 power network in the second chip, the second stage designs and plans the M11 power network in the second chip, the third stage designs and plans the M10 power network in the second chip, and the fourth stage designs and plans the M9 power network in the second chip. Of course, for processes using different metal layers, there may be more or fewer than four layers (M9, M10, M11, M12) in the higher-level power network, and this disclosure only uses four layers as an example to plan the higher-level power network of the second chip, and other processes using similar schemes are within the scope of this disclosure.
In some exemplary embodiments, the method is preceded by:
the size of the second chip is determined based on an integrated circuit chip physical back end design interaction file (library exchange file, LEF) file provided by the first chip.
In the embodiment of the disclosure, the LEF file information provided by the first chip includes information such as the size of the first chip, all high-level power supply networks and pins of the top metal layer of the first chip, and the like. The size of the second chip is identical to that of the first chip because the first chip and the second chip adopt a 3DIC packaging mode. And acquiring the layout structure of the highest-layer metal of the first chip and the power supply network requirement of the first chip in the second chip according to the LEF file information provided by the first chip. Because the layout structure of the highest-layer metal of the mapping area is the same as that of the highest-layer metal of the first chip, the obtained layout structure of the highest-layer metal of the first chip is mapped into the mapping area of the highest-layer metal of the second chip one by one according to the real coordinate position. The power network requirements of the first chip in the second chip include, but are not limited to, any of the following: the first chip has a placing requirement on a Through Silicon Via (TSV); m12 line width requirements; the requirements of the power network of the first chip need to be enhanced in the respective areas of the second chip, etc. These requirements for the first chip are very numerous but must be met in the high-level power network planning of the second chip.
In the embodiment of the disclosure, the layout structure of the highest metal of the mapping area of the second chip is the same as that of the highest metal of the first chip, and the highest metal power supply network in the highest metal of the second chip can only be arranged between two adjacent rows of the minimum design units, that is, the highest metal power supply network of the second chip is placed between the highest metal power supply networks of the first chip, as shown in fig. 9.
In some exemplary embodiments, the method further comprises:
and planning the type of power required to be used by the high-level power network of the second chip in the second chip.
Illustratively, the types of power supplies that the high-level power supply network of the second chip needs to use include three power supply lines of a first chip operating positive Voltage (VDD), a chip operating negative Voltage (VSS), and a second chip operating positive Voltage (VDDM), however, the embodiments of the present disclosure are not limited thereto, and the types and numbers of power supply lines included in the high-level power supply network of the second chip may be set as needed.
In some exemplary embodiments, in one first sub-design area, a layout structure of a plurality of first power lines is designed, including:
and calculating the distance between the upper and lower adjacent rows of minimum design units (namely the width of a first sub-design area along the second direction D2), and reasonably planning the total number and arrangement sequence of the first power lines in the first sub-design area according to the calculated distance.
In some exemplary embodiments, rationally planning the total number and arrangement order of the first power lines in a first sub-design area according to the calculated distance, including:
determining the number N of types of the first power lines;
in the first sub-design area, M groups of first power lines sequentially arranged along the second direction D2 are designed, each group of first power lines comprises N different types of first power lines sequentially arranged along the second direction D2, the width of each first power line in the first sub-design area is the same, the distance between every two adjacent first power lines is the same, wherein N is more than or equal to 2, and M is more than or equal to 2.
As shown in fig. 10, M groups of first power lines are designed in one first sub-design area, each group includes one VDD line, one VSS line, and one VDDM line, and the line widths of the three first power lines VDD, VSS, VDDM are the same, and the pitches between two adjacent first power lines are the same. It should be noted that the shape, line width, pitch, etc. of the power lines designed by the high-level power network design method of the present disclosure may be modified according to the actual voltage drop requirement during the chip manufacturing stage.
After the first power line arrangement sequence in one first sub-design area is arranged, the first power line arrangement sequence in the one first sub-design area can be quickly copied for a plurality of times by writing an electronic design automation (Electronic Design Automation, EDA) tool to identify scripts, so that the first power line arrangement sequence of all the first sub-design areas in one array area can be completed, that is, in one array area, the first power line arrangement sequences in different first sub-design areas are the same (as the first power lines extend along the first direction D1, the layout structure of the first power lines in the array area can be adopted in other array areas in the same row as the array area). And then, the script can be identified by programming the EDA tool to perform up-down mirror image operation on the first power line arrangement in one array area, so that the arrangement planning of the first power lines in all the first sub-design areas of the whole second chip is realized.
In a plurality of second sub-design areas (the second sub-design areas are arranged between two rows of array areas adjacently arranged along the second direction D2), second power lines for reinforcing the high-level power supply network of the first chip are planned, and these second power lines are mainly used for meeting the power supply requirement of the first chip, so the second power lines are called as first reinforcing power supply network. The connection performance between the power lines of the first chip is enhanced by arranging the second power line.
In some exemplary embodiments, in one first sub-design area, a layout structure of a plurality of first power lines may be designed, and a portion of the second power lines may be disposed in the first sub-design area, so as to further enhance the connection performance between the power lines of the first chip.
In some exemplary embodiments, while designing the layout structure of the plurality of second power lines in one second sub-design area, the method further includes:
in a second sub-design area, a layout structure of a plurality of first power lines is designed, and the first power lines and the second power lines are sequentially arranged along a second direction D2 in the second sub-design area according to a preset sequence.
In this embodiment, the second sub-design area further includes a portion of the first power line to ensure that the voltage drop (IR-drop) of the high-level power network of the first chip is not problematic. An exemplary layout of the power lines of the second sub-design area is shown in fig. 11, where the meaning of each power line in the first chip is shown in table 1:
| VBLHP | Voltage Backlight High Pressure | High background light pressure |
| VPPEX | Voltage Precharge Power EXtension | Memory prefetch supply voltage |
| VDDQ | Voltage Data Drain Quiescent | Data bus supply voltage |
| VCC | Voltage Common Collector | Supply voltage |
| VYIO | Voltage Yellow Input/Output | I/O supply voltage |
| VDDA | Voltage Digital-to-Analog | Analog supply voltage |
| VDDP | Voltage Data-plane Drain Power | Data plane supply voltage |
| VDLEQ | Voltage Delay Equalizer | Delay balancer supply voltage |
TABLE 1
In some exemplary embodiments, in the second sub-design area, each power line has the same width, and the adjacent two power lines have the same pitch, and the power lines include the first power line and/or the second power line.
After the layout structure of the second power lines of one second sub-design area is designed, the layout structure of the second power lines of the designed second sub-design area is copied to other second sub-design areas, and then the layout design of the second power lines in all the second sub-design areas can be completed.
The power supply layout planning of the top metal layer (M12) of the second chip is realized by planning the power supply network in the mapping area, the first sub-design area and the second sub-design area, and the planning meets the reinforcing requirement of the first chip on the top metal layer and the requirement of the second chip on voltage drop (IR-drop). When planning the power supply network of the top metal layer of the second chip, firstly, according to the actual size in the first chip, mapping all the power supply networks (PG) and pins (HB pin) of the top metal layer of the first chip into a second chip mapping area one by one according to the actual position information, then, inserting M12 power supply networks (including but not limited to VDD, VSS, VDDM and other first power supply wires) required by the second chip into a first sub-design area of the second chip according to a certain interval and a certain width, and simultaneously, inserting second power supply wires for reinforcing the top metal layer of the first chip into a second sub-design area of the second chip according to the design requirement of the first chip, including but not limited to VBLHP, VPPEX, VDDQ, VCC, VYIO, VDDA, VDDP, VDLEQ and the like, so as to plan the power supply network planning of the top metal layer (M12) of the second chip.
In some exemplary embodiments, the method further comprises:
designing a layout structure of a secondary high-level metal of the second chip, wherein the secondary high-level metal of the second chip comprises a third design area and a fourth design area, and the third design area is used for providing a second-level reinforced power supply network for the first chip; the fourth design area is used for providing a second layer of power supply network for the second chip; the third design area includes a plurality of third sub-design areas of identical design and/or the fourth design area includes a plurality of fourth sub-design areas of identical design.
In the embodiment of the disclosure, when the third design area is divided into a plurality of third sub-design areas with the same design, the fourth design area may be divided into a plurality of fourth sub-design areas with the same design, or may not be divided into a plurality of fourth sub-design areas with the same design. Similarly, when the fourth design area is divided into a plurality of the same-design fourth sub-design areas, the third design area may or may not be divided into a plurality of the same-design third sub-design areas.
In some exemplary embodiments, the front projection of the third sub-design area on the second chip and the front projection of the second direction power network area on the second chip comprise overlapping areas, the third sub-design area including a plurality of third power lines extending along the second direction, the plurality of third power lines for providing a second layer of the enhanced power network for the first chip.
In some example embodiments, the plurality of pins includes a first pin extending in a first direction and a second pin extending in a second direction; the orthographic projection of the fourth sub-design area on the second chip passes through the interval area between two adjacent second pins along the first direction, and the fourth sub-design area comprises a plurality of fourth power lines which extend along the second direction and are used for providing a second layer of power network for the second chip.
According to the high-level power supply network design method provided by the embodiment of the disclosure, the first-level reinforced power supply network and the second-level reinforced power supply network are respectively designed in the highest-level metal and the second-level metal of the second chip, so that the reinforced power supply network requirement of the first chip is met; the first layer power supply network and the second layer power supply network are respectively designed in the highest layer metal and the second highest layer metal of the second chip, so that the voltage drop requirement of the second chip is met.
In some exemplary embodiments, as shown in fig. 12 and 13, the category, the number, the line width, and the arrangement order of the third power lines included in the third sub-design area are the same as the category, the number, the line width, and the arrangement order of the sixth power lines included in the second direction power network area, respectively, and the orthographic projection of the third power lines of the third sub-design area on the second chip covers the orthographic projection of the sixth power lines of the second direction power network area on the second chip.
In the embodiment of the disclosure, the minimum design unit includes a plurality of first direction power supply network areas, a pin area disposed between the plurality of first direction power supply network areas, and second direction power supply network areas disposed on both sides of the first direction power supply network areas and the pin area along a first direction D1, the first direction power supply network areas include a plurality of fifth power supply lines extending along the first direction D1, the second direction power supply network areas include a plurality of sixth power supply lines extending along a second direction D2, and the fifth power supply lines and the sixth power supply lines are all used for providing a power supply network for the first chip; the pin field includes a plurality of pins. According to the power supply system and the power supply method, the third power supply line is arranged, the left-side power supply network area and the right-side power supply network area of each two adjacent minimum design units are connected in a penetrating mode, and therefore connection performance between the power supply lines of the first chip is improved.
In some exemplary embodiments, designing a layout structure of a second chip's next-higher level metal includes:
designing layout structures of a plurality of third power lines in a third sub-design area; the arrangement sequence of the third power lines in the third sub-design area is the same as the arrangement sequence of the sixth power lines in the second direction power network area, and the orthographic projection of the third power lines in the third sub-design area on the second chip covers the orthographic projection of the sixth power lines in the second direction power network area on the second chip;
Copying the layout structure of the third power supply line in the designed third sub-design area to other third sub-design areas in the same array area, thereby completing the layout structure of the third sub-design area of one array area; and symmetrically copying the layout structure of the third sub-design area in the completed array area to other array areas along the second direction.
In some exemplary embodiments, the fourth sub-design area is further configured to provide a plurality of third power lines, and design a layout structure of a second chip of a second metal layer, and further includes:
determining the placing position of the through silicon vias in a minimum design unit;
in a fourth sub-design area in a minimum design unit, designing layout structures of a plurality of third power lines and fourth power lines, wherein the types of the third power lines or the fourth power lines passing through the silicon through holes are the same as the types of power supplies connected through the silicon through holes;
copying the layout structure of the third power line and the fourth power line in the designed minimum design unit to other minimum design units in the same array area, thereby completing the layout structure of the third power line and the fourth power line in one array area (as the third power line and the fourth power line extend along the second direction D2, the layout structure of the third power line and the fourth power line in the array area can be adopted in other array areas in the same column as the array area); and symmetrically copying the layout structure of the third power line and the fourth power line in the completed array area to other array areas along the second direction D2.
As shown in fig. 14, all Through Silicon Vias (TSVs) are arranged in the second chip according to the design requirement of the first chip, and the power type of each through silicon via is determined, when designing the layout positions of the third power line and the fourth power line, the positions of the through silicon vias of the same power type passing through the corresponding power types need to be considered as far as possible, so that the continuity of the power lines of the corresponding power types is maintained as far as possible, and the through silicon vias can lead out the hybrid bonding pins through the next-higher metal layer of the first chip.
A large number of scattered pins (M12 HB pins) are distributed in each minimum design unit, and the pin arrangement sequence in each minimum design unit is identical, so that only the power line layout of the longitudinal M11 in one minimum design unit is planned and then copied into other minimum design units. As shown in fig. 15, the pins include a first pin extending along a first direction D1 and a second pin extending along a second direction D2, and the layout of the third power line and the fourth power line is planned in the gap between the second pins adjacently arranged along the first direction D1 as much as possible, that is, the third power line and the fourth power line basically fall in the gap between the second pins adjacently arranged along the first direction D1, so that the third power line and the fourth power line of M11 can be ensured to be continuously penetrated up and down in full chips, and short circuit errors or metal design rule checking (Design Rule Check, DRC) errors cannot be caused by the winding of the later period of the second pins.
After the third power lines and the fourth power lines in the minimum design unit area are planned according to the steps described above, the layout of the third power lines and the fourth power lines in the minimum design unit area may be copied into the minimum design units of the other three columns in the array area by writing a script recognizable by the EDA tool (this disclosure is not limited thereto, and the present disclosure describes that one array area includes four columns of minimum design units).
Since the third power line and the fourth power line extend along the second direction D2, the layout structure of the third power line and the fourth power line in the array region may be adopted in other array regions in the same column as the array region, and then the layout structure of the third power line and the fourth power line in the completed array region may be symmetrically copied to other array regions along the second direction D2 (the present disclosure describes that one chip includes two array regions, however, the present disclosure is not limited thereto), for example, the layout structure of the second chip may be completed by copying from the left array region to the right array region or copying from the right array region to the left array region.
In some exemplary embodiments, the method further comprises:
designing a layout structure of a third high-level metal of the second chip, wherein the third high-level metal of the second chip comprises a fifth design area and a sixth design area, and the fifth design area is used for providing a third-level reinforced power supply network for the first chip; the sixth design area is used for providing a third layer of power supply network for the second chip, the fifth design area comprises a plurality of fifth sub-design areas with the same design, and/or the sixth design area comprises a plurality of sixth sub-design areas with the same design.
In the embodiment of the disclosure, when the fifth design area is divided into a plurality of fifth sub-design areas with the same design, the sixth design area may be divided into a plurality of sixth sub-design areas with the same design, or may not be divided into a plurality of sixth sub-design areas with the same design. Similarly, when the sixth design area is divided into a plurality of sixth sub-design areas having the same design, the fifth design area may or may not be divided into a plurality of fifth sub-design areas having the same design.
In some exemplary embodiments, the fifth sub-design area is configured to provide a plurality of seventh power lines extending along the first direction D1, the plurality of seventh power lines being configured to provide a third layer of the enhanced power network for the first chip.
In some exemplary embodiments, the sixth sub-design area is configured to provide a plurality of eighth power lines, where the plurality of eighth power lines extend along the first direction D1, and the plurality of eighth power lines are configured to provide a third layer of power network for the second chip.
In some exemplary embodiments, designing a layout structure of a third high-level metal of a second chip includes:
dividing the third high-level metal of the second chip into a plurality of fifth sub-design areas arranged along the second direction D2;
designing a plurality of seventh power lines in a fifth sub-design area;
the layout structure of the seventh power line of the fifth designed sub-design area is symmetrically copied to the adjacent fifth sub-design area along the second direction D2.
In some exemplary embodiments, designing a layout structure of a third high-level metal of a second chip includes:
dividing the third high-level metal of the second chip into a plurality of sixth sub-design areas arranged along the second direction D2;
designing a plurality of eighth power lines in a sixth sub-design area;
the layout structure of the eighth power supply line of the designed sixth sub-design area is symmetrically copied to the adjacent sixth sub-design area along the second direction D2.
As shown in fig. 16, the third high-level metal layer in the lower half area of the second chip is preferably provided with a seventh power line for reinforcing the first chip according to the power supply reinforcing requirement of the first chip. As shown in fig. 17, the eighth power line (VDD/VSS/VDDM) of the lower half area of the second chip is planned according to a certain interval and a certain width, and as shown in fig. 18, scripts which can be recognized by the EDA tool are written, and the seventh power line and the eighth power line of the lower half area of the second chip are all copied to the upper half area of the second chip in an up-down symmetrical manner, so that the power lines of the third high-layer metal of the upper and lower two areas of the second chip are ensured to be completely symmetrical. In other exemplary embodiments, after the seventh power line and the eighth power line are planned in the third high-level metal layer of the upper half area of the second chip, the seventh power line and the eighth power line of the upper half area of the second chip may be all symmetrically copied to the lower half area of the second chip.
In some exemplary embodiments, in one sixth sub-design area, each eighth power line has the same width, and the adjacent two eighth power lines have the same pitch. However, the embodiment of the present disclosure is not limited thereto, and the width and pitch of the eighth power supply line may be adjusted as needed.
In some exemplary embodiments, the method further comprises:
designing a layout structure of a fourth high-level metal of the second chip, wherein the fourth high-level metal of the second chip comprises a plurality of seventh design areas, the seventh design areas are used for providing a fourth-level power supply network for the second chip, and the seventh design areas comprise a plurality of seventh sub-design areas with the same design.
In some exemplary embodiments, the seventh sub-design area is configured to provide a plurality of ninth power lines extending along the second direction D2, the plurality of ninth power lines configured to provide a fourth tier power network for the second chip
In some exemplary embodiments, designing a layout structure of a fourth high-level metal of a second chip includes:
dividing a fourth high-level metal of the second chip into a plurality of seventh sub-design areas arranged along the first direction D1;
designing a plurality of ninth power supply lines in a seventh sub-design area;
The layout structure of the ninth power supply line in the designed seventh sub-design area is symmetrically copied to the adjacent seventh sub-design area along the first direction D1.
In the embodiment of the disclosure, according to the power network requirement of the first chip in the second chip, the power network of the first chip is not required to be reinforced by adopting the fourth high-level metal (M9) in the second chip, so that the layout structure of the fourth high-level metal is easier to plan in the second chip. As shown in fig. 19 and 20, since the power line of the fourth high-level metal is designed to extend longitudinally, the ninth power line of the left half area of the second chip is first planned with a certain width and pitch. And writing a script which can be identified by an EDA tool, and copying all the ninth power lines of the left half area of the second chip to the right half area of the second chip in a bilateral symmetry mode, so that M9 power networks of the left and right half areas of the second chip are guaranteed to be completely symmetrical.
In some exemplary embodiments, in one seventh sub-design area, each of the ninth power lines has the same width, and the pitches of the adjacent two ninth power lines are the same. However, the embodiment of the present disclosure is not limited thereto, and the width and pitch of the ninth power supply line may be adjusted as needed.
Taking a 1P12M process as an example, the present disclosure proposes a high-level power network implementation scheme of a second chip capable of meeting the requirements of a first chip on a reinforced power supply, a voltage drop (IR-drop) and a winding windable on simultaneously based on the design of an 8GB high throughput 3DIC chip under the 1P12M process.
In the disclosed embodiment, the power lines in M12 and M10 are lateral and the power lines in M11 and M9 are longitudinal. Because the second chip is symmetrical up and down and left and right, in order to rapidly and accurately design and plan four layers of high-level power networks of M12, M11, M10 and M9, for transverse PG (such as M12 and M10), only the lower half part of the second chip is planned, and then the power network planning of the upper half part is completed by writing scripts which can be identified by EDA tools; for longitudinal PG (e.g. M11, M9), only the left half of the second chip is planned, and then the power network planning of the right half is completed by writing a script recognizable by EDA tools. Of course, the power network planning of the upper half or the right half can be planned first, and then the power network planning of the lower half or the left half can be completed by writing scripts recognizable by the EDA tool. Through the strategy, a plurality of array areas of the second chip are ensured to be symmetrical up and down and symmetrical left and right, so that the requirement of rapidly designing and planning a high-level power supply network of the second chip in the second chip of the 3DIC is met.
The high-level power supply network design method for the 3DIC second chip has the following advantages:
(1) The enhancement requirement of the first chip on the power supply network is met;
(2) The highest metal layers of the first chip and the second chip are guaranteed to be in seamless butt joint completely;
(3) The requirement of the second chip on the IR-drop is ensured;
(4) The high-level power supply network of the second chip is ensured to be perfectly symmetrical up and down and left and right about the multi-array area;
(5) Through only planning the M11 power supply network of the minimum design unit, the EDA identifiable script is rewritten TO complete the full-chip power supply network replication of the second chip, so that the time for planning the high-level power supply network of the 3DIC second chip is effectively shortened, and the time for planning the chip TO is shortened.
The embodiment of the disclosure also provides a three-dimensional integrated circuit chip, which comprises a first chip and a second chip, wherein a high-level power supply network of the first chip is predefined, and the high-level power supply network of the second chip is designed by the high-level power supply network design method according to any embodiment of the disclosure.
Those of ordinary skill in the art will appreciate that all or some of the steps, systems, functional modules/units in the apparatus, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed cooperatively by several physical components. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.
Claims (13)
1. The utility model provides a high-level power network design method which is characterized in that, is applicable to three-dimensional integrated circuit chip, three-dimensional integrated circuit chip includes: the high-level power supply network design method comprises the following steps of:
acquiring a layout structure of the highest metal layer of the first chip and a power supply network requirement of the first chip in the second chip;
designing a layout structure of the highest-layer metal of the second chip, wherein the highest-layer metal of the second chip comprises a mapping area, a first design area and a second design area, the layout structure of the highest-layer metal of the mapping area is the same as that of the highest-layer metal of the first chip, the first design area is used for providing a first-layer power supply network for the second chip, and the second design area is used for providing a first-layer reinforced power supply network for the first chip; the first design area includes a plurality of first sub-design areas of identical design and/or the second design area includes a plurality of second sub-design areas of identical design.
2. The method of claim 1, wherein said designing a layout structure of a highest level metal of said second chip comprises:
And copying the layout structure of the highest-layer metal of the first chip to the mapping area, wherein the highest-layer metal of the first chip and the mapping area respectively comprise a plurality of array areas symmetrically arranged along a first direction and/or a second direction, each array area comprises a plurality of minimum design units arranged in an array manner, and the first direction and the second direction are intersected.
3. The method of claim 2, wherein the designing the layout structure of the highest level metal of the second chip further comprises:
dividing the first design area into a plurality of first sub-design areas, the first sub-design areas being disposed between two of the minimum design units disposed adjacently along the second direction;
designing layout structures of a plurality of first power lines in one first sub-design area; copying the layout structure of the first power line of the designed first sub-design area to other first sub-design areas of the same array area, thereby completing the layout structure of the first power line of one array area; and symmetrically copying the layout structure of the first power lines of the completed array area to other array areas along the first direction, wherein a plurality of the first power lines are used for providing a first layer of power network for the second chip.
4. A method according to claim 3, wherein said designing a layout structure of a plurality of first power lines in one of said first sub-design areas comprises:
determining a width of the first sub-design area along the second direction;
determining the number N of types of the first power lines;
according to the width of the first sub-design area along the second direction and the number N of types of the first power lines, M groups of first power lines sequentially arranged along the second direction are designed in the first sub-design area, each group of first power lines comprises N different types of first power lines sequentially arranged along the second direction, wherein N is more than or equal to 2, and M is more than or equal to 2.
5. The method of claim 2, wherein the designing the layout structure of the highest level metal of the second chip further comprises:
dividing the second design area into a plurality of second sub-design areas, the second sub-design areas being disposed between two of the array areas disposed adjacently along the second direction;
designing layout structures of a plurality of second power lines in one second sub-design area; and copying the layout structure of the second power lines of the designed second sub-design area to other second sub-design areas, wherein a plurality of the second power lines are used for providing a first layer of reinforced power supply network for the first chip.
6. The method of claim 5, wherein while designing the layout structure of the plurality of second power supply lines in one of the second sub-design areas, the method further comprises:
and in the second sub-design area, designing layout structures of a plurality of first power lines, wherein the first power lines and the second power lines are sequentially arranged along the second direction in the second sub-design area according to a preset sequence, and the first power lines are used for providing a first layer of power network for the second chip.
7. The method according to claim 2, wherein the method further comprises:
designing a layout structure of a secondary high-level metal of the second chip, wherein the secondary high-level metal of the second chip comprises a third design area and a fourth design area, and the third design area is used for providing a second-level reinforced power supply network for the first chip; the fourth design area is used for providing a second layer of power supply network for the second chip, the third design area comprises a plurality of third sub-design areas with the same design, and/or the fourth design area comprises a plurality of fourth sub-design areas with the same design.
8. The method of claim 7, wherein the minimum design unit includes a plurality of first direction power network regions, a pin region disposed between the plurality of first direction power network regions, and second direction power network regions disposed on both sides of the first direction power network regions and the pin region along the first direction, the first direction power network regions including a plurality of fifth power lines extending along the first direction, the second direction power network regions including a plurality of sixth power lines extending along the second direction, the fifth power lines and the sixth power lines each for providing a power network for the first chip; the pin field includes a plurality of pins.
9. The method of claim 8, wherein the orthographic projection of the third sub-design area onto the second chip and the orthographic projection of the second direction power network area onto the second chip comprise overlapping areas, the designing a layout structure of a next-higher-level metal of the second chip comprising:
designing layout structures of a plurality of third power lines in a third sub-design area, wherein the arrangement sequence of the third power lines in the third sub-design area is the same as that of the sixth power lines in the second direction power network area, and the orthographic projection of the third power lines in the third sub-design area on the second chip covers the orthographic projection of the sixth power lines in the second direction power network area on the second chip;
copying the layout structure of the third power line in the designed third sub-design area to other third sub-design areas in the same array area, thereby completing the layout structure of the third sub-design area of one array area; and symmetrically copying the layout structure of the third sub-design area in the completed array area to other array areas along the second direction.
10. The method of claim 8, wherein the plurality of pins includes a first pin extending in the first direction and a second pin extending in the second direction; the orthographic projection of the fourth sub-design area on the second chip passes through a spacing area between two second pins adjacent along the first direction, and the layout structure for designing the second chip of the next higher-level metal comprises:
determining the placing position of the through silicon vias in one minimum design unit;
designing layout structures of a plurality of third power lines and fourth power lines in the fourth sub-design area in one minimum design unit, wherein the types of the third power lines or the fourth power lines passing through the silicon through hole placement positions are the same as the types of power supplies connected through the silicon through holes;
copying the layout structure of the third power line and the fourth power line in the designed fourth sub-design area to other fourth sub-design areas in the same array area, thereby completing the layout structure of the fourth sub-design area of one array area; and symmetrically copying the layout structure of the fourth sub-design area in the completed array area to other array areas along the second direction.
11. The method according to claim 1, wherein the method further comprises:
designing a layout structure of a third high-level metal of the second chip, wherein the third high-level metal of the second chip comprises a fifth design area and a sixth design area, and the fifth design area is used for providing a third-level reinforced power supply network for the first chip; the sixth design area is used for providing a third layer of power supply network for the second chip, the fifth design area comprises a plurality of fifth sub-design areas with the same design, and/or the sixth design area comprises a plurality of sixth sub-design areas with the same design.
12. The method according to claim 1, wherein the method further comprises:
the layout structure of the fourth high-level metal of the second chip is designed, the fourth high-level metal of the second chip comprises a plurality of seventh design areas, the seventh design areas are used for providing a fourth-level power supply network for the second chip, and the seventh design areas comprise a plurality of seventh sub-design areas with the same design.
13. A three-dimensional integrated circuit chip comprising a first chip and a second chip, wherein a high-level power supply network of the first chip is predefined, and a high-level power supply network of the second chip is designed by the high-level power supply network design method according to any one of claims 1 to 12.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311532763.6A CN117558680A (en) | 2023-11-16 | 2023-11-16 | Three-dimensional integrated circuit chip and high-level power supply network design method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311532763.6A CN117558680A (en) | 2023-11-16 | 2023-11-16 | Three-dimensional integrated circuit chip and high-level power supply network design method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117558680A true CN117558680A (en) | 2024-02-13 |
Family
ID=89814194
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311532763.6A Pending CN117558680A (en) | 2023-11-16 | 2023-11-16 | Three-dimensional integrated circuit chip and high-level power supply network design method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117558680A (en) |
-
2023
- 2023-11-16 CN CN202311532763.6A patent/CN117558680A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10510651B2 (en) | Hard macro having blockage sites, integrated circuit including same and method of routing through a hard macro | |
| KR102423040B1 (en) | Method for generating three-dimensional integrated circuit design | |
| JP5659244B2 (en) | Method and apparatus for interconnect layout in integrated circuits | |
| US8856710B2 (en) | Tool and method for modeling interposer RC couplings | |
| US10747933B2 (en) | Channel-less integrated circuit layout wiring for chips including a plurality of partitions | |
| US8445918B2 (en) | Thermal enhancement for multi-layer semiconductor stacks | |
| US8283771B2 (en) | Multi-die integrated circuit device and method | |
| US8689160B2 (en) | Method and apparatus of an integrated circuit | |
| US6516446B2 (en) | Design system for flip chip semiconductor device | |
| Jung et al. | A study of IR-drop noise issues in 3D ICs with through-silicon-vias | |
| US20130256908A1 (en) | Inter-die connection within an integrated circuit formed of a stack of circuit dies | |
| US9881118B2 (en) | IR-aware sneak routing | |
| US20170364625A1 (en) | Method for Increasing the Decoupling Capacity in a Microelectronic Circuit | |
| CN117558680A (en) | Three-dimensional integrated circuit chip and high-level power supply network design method | |
| Patti | Homogeneous 3D integration | |
| Healy et al. | Power-supply-network design in 3D integrated systems | |
| JP4786989B2 (en) | Semiconductor integrated circuit device | |
| Liu et al. | Substrate topological routing for high-density packages | |
| US20240005078A1 (en) | Through silicon via macro with dense layout for placement in an integrated circuit floorplan | |
| Wang | Reliable Design of Three-Dimensional Integrated Circuits | |
| Mohapatra | Dynamic through-Silicon via Clustering in 3D IC Floorplanning for Early Performance Optimization | |
| Li | Cavity, Chip Stack and TSV Design | |
| KR20230147505A (en) | Static Random Access Memory Device and 3D Semiconductor Integrated Circuit thereof | |
| Vaidyanathan et al. | Techniques for early package closure in system-in-packages | |
| Knechtel | Interconnect planning for physical design of 3D integrated circuits |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |