CN117558629A - FinFET device and manufacturing method thereof - Google Patents

FinFET device and manufacturing method thereof Download PDF

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Publication number
CN117558629A
CN117558629A CN202210935605.4A CN202210935605A CN117558629A CN 117558629 A CN117558629 A CN 117558629A CN 202210935605 A CN202210935605 A CN 202210935605A CN 117558629 A CN117558629 A CN 117558629A
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side wall
sidewall
dummy gate
finfet device
layer
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徐长文
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Shanghai IC R&D Center Co Ltd
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Shanghai IC R&D Center Co Ltd
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Priority to CN202210935605.4A priority Critical patent/CN117558629A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6653—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using the removal of at least part of spacer, e.g. disposable spacer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention provides a FinFET device and a manufacturing method thereof, wherein the method comprises the following steps: providing a substrate, wherein a plurality of dummy gates are formed on the substrate, and a first side wall is covered on the side wall of the dummy gates; forming a side wall oxide layer on the first side wall with the thickness of the oxidized part, and removing the side wall oxide layer; forming a second side wall covering the first side wall; forming an interlayer dielectric layer filling up gaps between adjacent dummy gates; and removing the pseudo grid electrode and the first side wall to form a groove. In the process of removing the dummy gate and the first side wall, although the size of the groove is increased due to over etching of the second side wall, the size of the groove is reduced due to the fact that the overall size of the dummy gate and the first side wall is reduced after the side wall oxide layer is formed on the first side wall with the thickness of the oxide part and is removed, and therefore the size of the finally formed groove reaches a process target, and performance of the device is improved.

Description

FinFET device and manufacturing method thereof
Technical Field
The invention relates to the technical field of integrated circuit manufacturing, in particular to a FinFET device and a manufacturing method thereof.
Background
With the continuous development of semiconductor technology, it has been difficult for conventional planar devices to meet the demands of high-performance devices. A Fin-Field-Effect Transistor (FinFET) is a three-dimensional device, which includes a Fin vertically formed on a substrate and a high-k metal gate intersecting the Fin, and the design can greatly improve circuit control and reduce leakage current, and can also greatly shorten the gate length of the Transistor.
In the advanced manufacturing process of the FinFET, after the source-drain epitaxy process and the intermediate dielectric layer process are finished, the dummy gate needs to be removed to form a recess, then a metal gate of the FinFET is formed in the recess, and the size (CD) of the recess after removing the dummy gate determines the final size of the metal gate. However, in the process of removing the dummy gate, a loss is inevitably caused to the low-k dielectric layers at two sides of the dummy gate, so that the size of the groove is enlarged, and the size of the finally formed metal gate is enlarged, thereby affecting the performance of the device.
In the prior art, the change of the size of the groove is generally reduced by reducing the size of the pseudo gate so that the size of the groove reaches the process target, however, the reduction of the size of the pseudo gate can increase the depth-to-width ratio of the pseudo gate, thereby increasing the process difficulty in the process of removing the pseudo gate subsequently.
Disclosure of Invention
The invention aims to provide a FinFET device and a manufacturing method thereof, which can enable the size of a groove to reach a process target, improve the device performance, and simultaneously not increase the process difficulty.
In order to solve the technical problems, the invention provides a manufacturing method of a FinFET device, which comprises the following steps:
providing a substrate, wherein a plurality of dummy gates and a first side wall covering the side wall of the dummy gates are formed on the substrate;
forming a side wall oxide layer on the first side wall with the thickness of the oxidized part, and removing the side wall oxide layer;
forming a second side wall, wherein the second side wall covers the rest of the first side wall;
forming an interlayer dielectric layer, wherein the interlayer dielectric layer fills gaps between adjacent pseudo gates; and
and removing the dummy gate and the first side wall to form a groove.
Optionally, a mask layer is formed on the dummy gate, and the first sidewall covers the sidewall and the top of the mask layer and covers the surface of the substrate.
Optionally, after the interlayer dielectric layer is formed, before the dummy gate and the first sidewall are removed, the manufacturing method further includes: and flattening the interlayer dielectric layer and the mask layer until the dummy gate is exposed.
Optionally, the material of the dummy gate includes polysilicon, and the mask layer includes a nitride layer and an oxide layer sequentially located on the dummy gate.
Optionally, in the process of removing the dummy gate and the first side wall, over etching is performed on the second side wall, and the thickness of the oxidized first side wall is determined by the over etching amount.
Optionally, the thickness of the oxidized first side wall is half of the thickness of the first side wall.
Optionally, the material of the first side wall comprises SICN, the material of the second side wall comprises SIOCN, and the material of the interlayer dielectric layer comprises silicon oxide.
Optionally, a cleaning process is adopted to remove the side wall oxide layer.
Optionally, the cleaning solution of the cleaning process comprises HF.
Correspondingly, the invention also provides a semiconductor device manufactured by adopting the manufacturing method of the FinFET device.
According to the FinFET device and the manufacturing method thereof, the first side wall with the thickness of the oxidized part forms the side wall oxide layer, and then the side wall oxide layer is removed, so that the overall size of the pseudo gate and the first side wall is reduced, in the process of removing the pseudo gate and the first side wall, although the size of the groove is increased due to over etching of the second side wall, the size of the groove is reduced due to the fact that the overall size of the pseudo gate and the first side wall is reduced, and the size of the finally formed groove reaches a technological target, so that the performance of the device is improved. Meanwhile, compared with the prior art, the size of the pseudo gate is not reduced, and the depth-to-width ratio is unchanged when the pseudo gate is removed, so that a process window is enlarged, and the process difficulty is not increased.
Drawings
It will be appreciated by those skilled in the art that the drawings are provided for a better understanding of the invention and do not constitute any limitation on the scope of the invention.
Fig. 1 is a flowchart of a method for fabricating a FinFET device according to an embodiment of the present invention.
Fig. 2 to fig. 7 are schematic structural diagrams illustrating steps of a method for fabricating a FinFET device according to an embodiment of the present invention.
Reference numerals:
10-a substrate; 11-dummy gate; 12-a nitride layer; 13-an oxide layer; 14-a first side wall; 15-a side wall oxide layer; 16-a second side wall; 17-an interlayer dielectric layer; 18-grooves.
Detailed Description
The invention will be described in further detail with reference to the drawings and the specific embodiments thereof in order to make the objects, advantages and features of the invention more apparent. It should be noted that the drawings are in a very simplified form and are not drawn to scale, merely for convenience and clarity in aiding in the description of embodiments of the invention. Furthermore, the structures shown in the drawings are often part of actual structures. In particular, the drawings are shown with different emphasis instead being placed upon illustrating the various embodiments.
As used in this disclosure, the singular forms "a," "an," and "the" include plural referents, the term "or" are generally used in the sense of comprising "and/or" and the term "several" are generally used in the sense of comprising "at least one," the term "at least two" are generally used in the sense of comprising "two or more," and the term "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying any relative importance or number of features indicated. Thus, a feature defining "a first", "a second", and "a third" may include one or at least two of the feature, either explicitly or implicitly, unless the context clearly dictates otherwise.
Fig. 1 is a flowchart of a method for fabricating a FinFET device according to an embodiment of the present invention.
As shown in fig. 1, the manufacturing method of the FinFET device includes the following steps:
s1: providing a substrate, wherein a plurality of dummy gates and a first side wall covering the side wall of the dummy gates are formed on the substrate;
s2: forming a side wall oxide layer on the first side wall with the thickness of the oxidized part, and removing the side wall oxide layer;
s3: forming a second side wall, wherein the second side wall covers the rest of the first side wall;
s4: forming an interlayer dielectric layer, wherein the interlayer dielectric layer fills gaps between adjacent pseudo gates;
s5: and removing the dummy gate and the first side wall to form a groove.
Fig. 2 to fig. 7 are schematic structural diagrams illustrating steps of a method for fabricating a FinFET device according to an embodiment of the present invention. Next, a method for fabricating a FinFET device according to an embodiment of the present invention will be described in detail with reference to fig. 1 and fig. 2 to fig. 7.
In step S1, referring to fig. 2, a substrate 10 is provided, and a plurality of dummy gates 11 and first spacers 14 covering sidewalls of the dummy gates 11 are formed on the substrate 10.
The material of the substrate 10 may be silicon, germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or the like, or may be silicon on insulator, germanium on insulator; or may be other materials such as III-V compounds such as gallium arsenide.
A plurality of fins (not shown) may be formed in the substrate 10, adjacent fins are isolated by an isolation structure, and the dummy gate 11 spans over the fins. In this embodiment, a mask layer is formed on the dummy gate 11, and the mask layer plays a role of a mask in the process of forming the dummy gate, that is, the mask layer is used as a mask to etch the dummy gate material layer to form the dummy gate. Illustratively, the mask layer includes a nitride layer 12 and an oxide layer 13 sequentially disposed on the dummy gate 11, the nitride layer 12 is preferably silicon nitride, and the oxide layer 13 is preferably silicon oxide.
The dummy gate electrode 11 may be formed by a suitable deposition process such as Low Pressure Chemical Vapor Deposition (LPCVD) and Plasma Enhanced Chemical Vapor Deposition (PECVD). In some embodiments, additional dielectric and/or conductive layers may be formed on the dummy gate 11, such as an interfacial layer, a capping layer, a diffusion/barrier layer, other suitable layers, and/or combinations thereof, which are not limited in this regard.
In order to prepare for the subsequent shallow doping implantation process of the source and drain (not shown), a first sidewall 14 needs to be formed on the sidewall of the dummy gate 11. The first side wall 14 covers the side wall of the dummy gate 11, and also covers the side wall and the top of the mask layer, and the exposed surface of the substrate 10. The material of the first sidewall 14 includes SICN (silicon carbonitride).
In step S2, referring to fig. 3 and 4, a sidewall oxide layer 15 is formed by oxidizing the partial thickness of the first sidewall 14, and the sidewall oxide layer 15 is removed.
After the first side wall 14 is formed, a photolithography process is performed on the remaining area of the device, and an oxidation process is required to prevent organic matters such as photoresist from directly contacting the first side wall 14. The first side wall 14 with partial thickness is oxidized by the oxidation process to form a side wall oxide layer 15, so as to form a structure shown in fig. 3.
Next, as shown in fig. 4, the spacer oxide layer 15 is removed, so that the total size of the dummy gate 11 and the first spacer 14 is reduced (the total size refers to the total width in the horizontal direction in fig. 4), so that the size of the recess formed after the subsequent removal of the dummy gate 11 and the first spacer 14 is also reduced, and although the recess is enlarged due to over etching during the removal of the dummy gate 11 and the first spacer 14, the recess reaches the target size due to the offset of the two. Therefore, the thickness of the oxidized first sidewall 14 may be determined by the over-etching amount, if the over-etching amount is large, the thickness of the oxidized first sidewall 14 may be increased, the total size of the dummy gate 11 and the remaining first sidewall 14 may be further reduced, and if the over-etching amount is small, the thickness of the oxidized first sidewall 14 may be reduced, and the total size of the dummy gate 11 and the remaining first sidewall 14 may be increased.
In an embodiment of the present invention, the dimension of the dummy gate 11 is 19nm, the dimension of the first sidewall 14 is 2nm, the total dimension of the dummy gate 11 and the first sidewall 14 is 23nm, and then, in the process of etching the recess formed by the dummy gate 11 and the first sidewall 14, the over-etching amount is 1nm, i.e. the dimension of the recess is enlarged to two sides by 2nm, i.e. the dimension of the recess reaches 25nm, and the ideal dimension is 23nm. Therefore, in this step, the first sidewall 14 is oxidized by 1nm, that is, the thickness of the oxidized first sidewall 14 is half of the thickness of the first sidewall 14, and after the sidewall oxide layer 15 is removed, the total size of the dummy gate 11 and the remaining first sidewall 14 is reduced by 2nm, which is 21nm. It will be appreciated that the dimensions referred to in this embodiment are widths in the horizontal direction of fig. 4, and that only standard dimensions are exemplified in this embodiment, and that the actual dimensions may fluctuate within a certain range around the standard dimensions, specifically determined by the actual process conditions. Of course, the dimensions of the dummy gate 11, the first sidewall 14, and the oxidized first sidewall 14 are not limited thereto.
In this embodiment, a cleaning process may be used to remove the sidewall oxide layer 15, where the cleaning solution of the cleaning process includes HF (hydrofluoric acid), but is not limited thereto.
In step S3, as shown in fig. 5, a second sidewall 16 is formed, and the second sidewall 16 covers the remaining first sidewall 14.
The second sidewall 16 is a low-k dielectric layer, the material of the second sidewall 16 includes SIOCN (carbon oxynitride), and Plasma Enhanced Atomic Layer Deposition (PEALD) may be used to form the second sidewall 16, where the second sidewall 16 covers the first sidewall 14, that is, the sidewalls and top of the dummy gate 11, the nitride layer 12, and the oxide layer 13, and covers the exposed surface of the substrate 10. The thickness of the second sidewall 16 may be 7nm.
In step S4, as shown in fig. 6, an interlayer dielectric layer 17 is formed, and the interlayer dielectric layer 17 fills the gap between adjacent dummy gates 11.
In this embodiment, the interlayer dielectric layer 17 fills the gaps between the adjacent dummy gates 11 and fills the gaps between the mask layers, that is, the interlayer dielectric layer 17 fills the gaps shown in fig. 5. Then, the interlayer dielectric layer 17 and the mask layer are planarized until the dummy gate 11 is exposed, so as to form a structure as shown in fig. 6, for example, the interlayer dielectric layer 17 and the mask layer may be planarized by a chemical mechanical polishing method.
The material of the interlayer dielectric layer 17 comprises silicon oxide, which may comprise doped silicon oxide such as borophosphosilicate glass (BPSG), fused Silica Glass (FSG), phosphosilicate glass (PSG), boron doped silicate glass (BSG), and/or other suitable dielectric materials, for example. The interlayer dielectric layer 17 may be deposited by a PECVD process or other suitable deposition technique. In one embodiment, the interlayer dielectric layer 17 is formed by flow-through chemical vapor deposition (Flow chemical vapor deposition, FCVD). The FCVD process includes depositing a flowable material (such as a liquid compound) on the substrate 10 to fill the gap between the dummy gate 11 (with the first sidewall 14 and the second sidewall 16 on its sidewalls) and converting the flowable material to a solid material by a suitable technique (such as annealing in one example). Of course, in other embodiments, the interlayer dielectric layer 17 may also be formed by, for example, chemical vapor deposition (chemical vapor deposition, CVD), physical vapor deposition (physical vapor deposition, PVD), atomic layer deposition (atomic layer deposition, ALD), or combinations thereof.
In step S6, as shown in fig. 7, the dummy gate 11 and the first sidewall 14 are removed to form a recess 18.
The dummy gate 11 and the first sidewall 14 may be removed by an etching process selectively tuned to remove the dummy gate 11 and the first sidewall 14 while substantially retaining the second sidewall 16. The etching process may include suitable wet etching, dry (plasma) etching, and/or othersAnd (3) processing. For example, the dry etching process may use chlorine-containing gases, fluorine-containing gases, other etching gases, or combinations thereof. The wet etching solution may include NH 4 OH, HF (hydrofluoric acid), TMAH (tetramethylammonium hydroxide), other suitable wet etching solutions, or combinations thereof.
In this etching process, the loss of the second sidewall 16, for example, the loss of 1nm on one side, is unavoidable, and the thickness of the dummy gate 11 and the remaining first sidewall 14 is reduced by 2nm by removing the sidewall oxide 15 after forming the sidewall oxide 15 by oxidizing the partial thickness of the first sidewall 14, and the total dimension of the dummy gate 11 and the remaining first sidewall 14 is 21nm. In this step, 2nm of over-etching is caused, and the size of the finally formed recess 18 is 23nm, which is exactly equal to the total size of the dummy gate 11 and the first sidewall 14 in step S1, i.e. the size of the recess 18 is not increased, so as to achieve the process objective.
In the method for manufacturing the FinFET device provided by the present invention, after the first side wall 14 is formed, the first side wall 14 with the thickness of the oxidized portion forms the side wall oxide layer 15, and the side wall oxide layer 15 is removed, so that the overall dimensions of the dummy gate 11 and the first side wall 14 are reduced, and in the process of removing the dummy gate 11 and the first side wall 14, although the dimension of the groove 18 is increased due to over etching of the second side wall 16, the dimension of the groove 18 is reduced due to the reduction of the overall dimensions of the dummy gate 11 and the first side wall 14, so that the dimension of the finally formed groove 18 reaches the process target, thereby improving the performance of the device. Meanwhile, compared with the prior art, the size of the dummy gate 11 is not reduced, and the aspect ratio is unchanged when the dummy gate 11 is removed, so that the process window is increased, and the process difficulty is not increased.
Correspondingly, the invention also provides a FinFET device manufactured by adopting the manufacturing method of the FinFET device. Referring to fig. 7, the FinFET device includes:
a substrate 10, a plurality of spaced interlayer dielectric layers 17 on the substrate 10;
the second side wall 16 covers the side wall and the bottom of the interlayer dielectric layer 17;
the first side wall 14 is positioned at the bottom of the interlayer dielectric layer 17 and is positioned between the substrate 10 and the second side wall 16;
and grooves 18 between adjacent interlayer dielectric layers 17.
The size of the recess 18 (i.e., the cross-sectional width in the horizontal direction of fig. 7) of the FinFET device fabricated by the method for fabricating a FinFET device as described above can achieve a process target, and the size of the metal gate subsequently formed in the recess 18 can also achieve a process target, thereby improving the performance of the final device.
In summary, in the FinFET device and the method for manufacturing the same, the first sidewall with the thickness of the oxidized portion forms the sidewall oxide layer, and then the sidewall oxide layer is removed, so that the overall dimensions of the dummy gate and the first sidewall are reduced, and in the process of removing the dummy gate and the first sidewall, although the dimension of the groove is increased due to over etching of the second sidewall, the dimension of the groove is reduced due to the overall dimension reduction of the dummy gate and the first sidewall, so that the dimension of the finally formed groove reaches the process target, thereby improving the performance of the device. Meanwhile, compared with the prior art, the size of the pseudo gate is not reduced, and the depth-to-width ratio is unchanged when the pseudo gate is removed, so that a process window is enlarged, and the process difficulty is not increased.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.

Claims (10)

1. A method of fabricating a FinFET device, comprising:
providing a substrate, wherein a plurality of dummy gates and a first side wall covering the side wall of the dummy gates are formed on the substrate;
forming a side wall oxide layer on the first side wall with the thickness of the oxidized part, and removing the side wall oxide layer;
forming a second side wall, wherein the second side wall covers the rest of the first side wall;
forming an interlayer dielectric layer, wherein the interlayer dielectric layer fills gaps between adjacent pseudo gates; and
and removing the dummy gate and the first side wall to form a groove.
2. The method of fabricating a FinFET device of claim 1, wherein a mask layer is formed on the dummy gate, the first sidewall covering sidewalls and a top of the mask layer and covering a surface of the substrate.
3. The method of fabricating the FinFET device of claim 2, wherein after forming the interlayer dielectric layer, before removing the dummy gate and the first sidewall, the method further comprises: and flattening the interlayer dielectric layer and the mask layer until the dummy gate is exposed.
4. The method of fabricating a FinFET device of claim 2, wherein the material of the dummy gate comprises polysilicon and the mask layer comprises a nitride layer and an oxide layer sequentially on the dummy gate.
5. The method of claim 1, wherein the second sidewall is over-etched in the removing the dummy gate and the first sidewall, and the thickness of the oxidized first sidewall is determined by an over-etching amount.
6. The method of fabricating a FinFET device of claim 1, wherein the thickness of the oxidized first sidewall is one-half of the thickness of the first sidewall.
7. The method of claim 1, wherein the material of the first sidewall comprises SICN, the material of the second sidewall comprises SIOCN, and the material of the interlayer dielectric layer comprises silicon oxide.
8. The method of claim 1, wherein a cleaning process is used to remove the sidewall oxide layer.
9. The method of fabricating a FinFET device of claim 8, in which a cleaning solution of the cleaning process comprises HF.
10. A FinFET device fabricated by the method of fabricating the FinFET device of any of claims 1-9.
CN202210935605.4A 2022-08-04 2022-08-04 FinFET device and manufacturing method thereof Pending CN117558629A (en)

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