CN117558317A - Method and device for detecting cold start attack and memory - Google Patents

Method and device for detecting cold start attack and memory Download PDF

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Publication number
CN117558317A
CN117558317A CN202210938465.6A CN202210938465A CN117558317A CN 117558317 A CN117558317 A CN 117558317A CN 202210938465 A CN202210938465 A CN 202210938465A CN 117558317 A CN117558317 A CN 117558317A
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memory
tested
data
cold start
detected
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章恒嘉
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4078—Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
    • G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40626—Temperature related aspects of refresh operations
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4072—Circuits for initialization, powering up or down, clearing memory or presetting

Abstract

The embodiment of the disclosure provides a method, a device and a memory for detecting cold start attacks, wherein the method comprises the following steps: providing a memory to be tested, wherein the memory to be tested comprises a memory area to be tested; when the temperature of the memory to be tested is detected to be lower than a preset temperature, writing test data in the memory area to be tested; after the memory to be tested is restarted and powered on, reading storage data from the storage area to be tested; and determining whether the memory to be tested is attacked by cold start according to the test data and the storage data.

Description

Method and device for detecting cold start attack and memory
Technical Field
The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a method and device for detecting cold start attacks and a memory.
Background
Typically, after the power to the computer system is turned off, the data stored in the dynamic random access memory (Dynamic Random Access Memory, DRAM) is preserved for a few seconds after power loss without significant loss (i.e., a reversal of the value of the memory cell). If cooling techniques are used to cool down, the data retention time can be greatly increased. The cold start attack is based on the fact that an attacker can steal data in the DRAM by using short data retention time.
At present, the process of cold start attack is as follows: firstly, cooling the memory of a target machine (namely, a computer to be attacked) in operation by using a coolant; then, cutting off the power supply of the target machine, pulling out the memory, rapidly inserting the memory into an execution machine (namely, a computer for executing attack), and starting the execution machine; then, after the execution machine is started, the automatic loading guide program is carried out, and the guide program dumps the memory of the target machine to a permanent storage medium such as a magnetic disk for subsequent analysis; finally, a specific algorithm is used for recovering the secret key from the memory image of the target machine, and the password system is broken.
Disclosure of Invention
In view of this, an embodiment of the present disclosure provides a method, an apparatus, and a memory for detecting a cold start attack to solve at least one technical problem existing in the prior art.
In order to achieve the above purpose, the technical scheme of the present disclosure is realized as follows:
in a first aspect, embodiments of the present disclosure provide a method of detecting a cold start attack, the method comprising: providing a memory to be tested, wherein the memory to be tested comprises a memory area to be tested; when the temperature of the memory to be tested is detected to be lower than a preset temperature, writing test data in the memory area to be tested; after the memory to be tested is restarted and powered on, reading storage data from the storage area to be tested; and determining whether the memory to be tested is attacked by cold start according to the test data and the storage data.
In some embodiments, the determining whether the memory under test is attacked by cold boot according to the test data and the stored data includes: and if the test data and the storage data are basically the same, determining that the memory to be tested is attacked by cold start.
In some embodiments, after the determining that the memory under test is attacked by the cold boot, the method further comprises: and setting the voltage mode of the memory to be tested as a destruction mode so as to destroy the data stored in the memory to be tested.
In some embodiments, the memory region to be tested includes a plurality of memory cells to be tested, each of the memory cells to be tested including a memory capacitor to be tested and a transistor; the storage capacitor to be tested is used for storing data written into the storage unit to be tested.
In some embodiments, writing test data in the memory area under test when the temperature of the memory under test is detected to be lower than a preset temperature includes: when the temperature of the memory to be detected is detected to be lower than a preset temperature, and the memory to be detected enters a self-refresh mode, the storage capacitor to be detected of the storage area to be detected is charged to a preset potential value.
In some embodiments, the reading the storage data from the storage area under test after the memory under test is restarted, includes: and after the memory to be tested is restarted and electrified, reading an actual potential value from the storage capacitor to be tested in the storage area to be tested.
In some embodiments, the determining whether the memory under test is attacked by cold boot according to the test data and the stored data includes: and determining whether the memory to be tested is attacked by cold start or not according to the preset potential value and the actual potential value.
In some embodiments, after the detecting that the temperature of the memory under test is lower than a preset temperature, the method further includes: acquiring the use state of a redundant area of the memory to be tested; and setting the unused redundant area as a storage area to be tested according to the use state.
In some embodiments, the storage capacitor under test includes at least one of: MOS capacitance, nickel capacitance and the storage capacitance of the memory to be tested.
In a second aspect, embodiments of the present disclosure provide an apparatus for detecting a cold start attack, the apparatus comprising: the temperature detection module is used for detecting whether the temperature of the memory to be detected is lower than a preset temperature; the data writing module is used for writing test data in the storage area to be tested when the temperature of the memory to be tested is detected to be lower than a preset temperature; the memory to be tested comprises the memory area to be tested; the data reading module is used for reading storage data from the storage area to be detected after the storage area to be detected is restarted and electrified; and the data analysis module is used for determining whether the memory to be tested is attacked by cold start according to the test data and the storage data.
In some embodiments, the data analysis module is specifically configured to: and if the test data and the storage data are basically the same, determining that the memory to be tested is attacked by cold start.
In some embodiments, the apparatus further comprises: and the data destruction module is used for setting the voltage mode of the memory to be detected as a destruction mode so as to destroy the data stored in the memory to be detected.
In some embodiments, the memory region to be tested includes a plurality of memory cells to be tested, each of the memory cells to be tested including a memory capacitor to be tested and a transistor; the storage capacitor to be tested is used for storing data written into the storage unit to be tested.
In some embodiments, the data writing module is specifically configured to: when the temperature of the memory to be detected is detected to be lower than a preset temperature, and the memory to be detected enters a self-refresh mode, the storage capacitor to be detected of the storage area to be detected is charged to a preset potential value.
In some embodiments, the data reading module is specifically configured to: and after the memory to be tested is restarted and electrified, reading an actual potential value from the storage capacitor to be tested in the storage area to be tested.
In some embodiments, the data analysis module is specifically configured to: and determining whether the memory to be tested is attacked by cold start or not according to the preset potential value and the actual potential value.
In some embodiments, the apparatus further comprises: the state acquisition module is used for acquiring the use state of the redundant area of the memory to be detected; and the region setting module is used for setting the unused redundant region as a storage region to be tested according to the use state.
In some embodiments, the storage capacitor under test includes at least one of: MOS capacitance, nickel capacitance and the storage capacitance of the memory to be tested.
In a third aspect, an embodiment of the present disclosure provides a memory, where the memory includes a device for detecting a cold start attack described in the foregoing technical solution.
The embodiment of the disclosure provides a method, a device and a memory for detecting cold start attacks, wherein the method comprises the following steps: providing a memory to be tested, wherein the memory to be tested comprises a memory area to be tested; when the temperature of the memory to be tested is detected to be lower than a preset temperature, writing test data in the memory area to be tested; after the memory to be tested is restarted and powered on, reading storage data from the storage area to be tested; and determining whether the memory to be tested is attacked by cold start according to the test data and the storage data. In the embodiment of the disclosure, when the temperature of the memory to be detected is detected to be lower than the preset temperature, the memory to be detected is suspected to possibly suffer from cold start attack; and writing test data into the storage area to be tested, reading storage data from the storage area to be tested after the storage area to be tested is restarted and electrified, comparing the test data with the storage data, and determining whether the storage area to be tested is attacked by cold start.
In addition, if the memory to be tested is determined to be attacked by cold start, the voltage mode of the memory to be tested can be set to be a destruction mode, and data stored in the memory to be tested is destroyed, so that the problem that the data is stolen after the memory to be tested is restarted is solved.
Drawings
FIG. 1 is a flow diagram of a cold start attack;
FIG. 2 is a flow chart of a method for detecting a cold start attack according to an embodiment of the present disclosure;
FIG. 3 is a timing diagram of a memory after power-up is restarted according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a detection circuit for detecting a cold start attack according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of a storage capacitor to be tested according to an embodiment of the present disclosure;
fig. 6 is a schematic diagram of a setting position of a storage capacitor to be measured according to an embodiment of the disclosure;
fig. 7 is a schematic diagram of selecting an unused redundant area as a storage area to be tested according to an embodiment of the present disclosure.
Detailed Description
The following description of the embodiments of the present disclosure will be made clearly and fully with reference to the embodiments of the present disclosure and the accompanying drawings, it being apparent that the described embodiments are only some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without inventive effort, based on the embodiments in this disclosure are intended to be within the scope of this disclosure.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.
For a thorough understanding of the present disclosure, detailed steps and detailed structures will be presented in the following description in order to illustrate the technical aspects of the present disclosure. Preferred embodiments of the present disclosure are described in detail below, however, the present disclosure may have other implementations in addition to these detailed descriptions.
Referring to fig. 1, fig. 1 is a schematic flow chart of a cold start attack. As shown in fig. 1, the cold start attack includes the steps of:
step S101: extending Dynamic Random Access Memory (DRAM) data retention time under low temperature conditions;
step S102: transferring the DRAM and restarting after power failure;
step S103: data is read and transferred.
It is understood that the DRAM stores data using a storage capacitor, and more particularly, represents data information of one bit using both a charged state and a ground state of the capacitor. If no external power supply exists, the capacitor in a charged state gradually discharges and finally turns into a ground state. Because of the characteristics of the DRAM, when the external power supply is cut off, the data stored in the DRAM can be kept for a period of time after the power is lost; if the DRAM is placed under low temperature conditions, the data retention time will be greatly extended.
In step S101, the attacker needs to cool the DRAM memory chip of the operating target machine by using the data remaining characteristics of the DRAM to extend the data retention time in the DRAM memory chip.
In step 102, the attacker needs to cut off the power supply of the target machine, unplug the DRAM memory chip, insert the DRAM memory chip into the execution machine, and start the execution machine.
In step S103, the attacker automatically loads the boot program after starting the execution machine, and the boot program dumps the data of the DRAM memory chip of the target machine to the disk.
From the above analysis, it is clear that cooling and power-down restarting of the DRAM in operation is a key step in a cold start attack. Among them, cooling of the DRAM in operation is a necessary precondition for performing a cold start attack.
In view of this, embodiments of the present disclosure provide a method, an apparatus, and a memory for detecting a cold start attack.
Referring to fig. 2, fig. 2 is a flowchart of a method for detecting a cold start attack according to an embodiment of the disclosure. As shown in fig. 2, an embodiment of the present disclosure provides a method of detecting a cold start attack, the method including the steps of:
step S201: providing a memory to be tested, wherein the memory to be tested comprises a memory area to be tested;
Step S202: when the temperature of the memory to be tested is detected to be lower than the preset temperature, writing test data in the memory area to be tested;
step S203: after restarting the memory to be tested and powering up, reading storage data from a storage area to be tested;
step S204: and determining whether the memory to be tested is attacked by cold start according to the test data and the storage data.
In the embodiment of the present disclosure, in step S201, a memory to be tested includes a memory area to be tested, where the memory area to be tested includes a plurality of memory units to be tested, and the memory units to be tested are used for detecting whether the memory to be tested is attacked by cold start.
It should be noted that, the main function of the memory to be tested is to store data, so the memory to be tested includes a plurality of memory cells, the original memory cells in the memory to be tested are used for storing data, and unused memory cells in the original memory cells can be selected to be set as the memory cells to be tested for detecting whether the memory to be tested is attacked by cold start. Or, some additional storage units to be tested may be set in the memory to be tested in advance, and the storage capacity of these additional storage units to be tested may be the same as or different from the storage capacity of the original storage units in the memory to be tested, and these additional storage units to be tested are used to detect whether the memory to be tested is attacked by cold start.
In the embodiment of the disclosure, in step S202, it is necessary to detect the temperature of the memory to be detected first and determine whether the temperature of the memory to be detected is lower than a preset temperature. When the temperature of the memory to be tested is lower than the preset temperature, the memory to be tested is suspected to be possibly in the key process of cold start attack, and an attacker can restart the memory to be tested after cooling in order to acquire the data in the memory to be tested.
In the embodiment of the disclosure, when the temperature of the memory to be measured is detected to be lower than the preset temperature, two situations may exist. In the first case, the memory to be tested is attacked by cold start, so that a corresponding operation needs to be performed on the memory to be tested, for example, the voltage mode of the memory to be tested is set to be a destruction mode, so as to destroy the data stored in the memory to be tested, thereby avoiding the data stored in the memory to be tested from being stolen. In the second case, the memory under test is not attacked by cold start, but is subjected to extreme cold weather, and there is no need to worry about the theft of the data stored in the memory under test. Therefore, when the temperature of the memory to be tested is detected to be lower than the preset temperature, it is necessary to further detect whether the memory to be tested is attacked by cold start, and determine the subsequent operation to be executed by the memory to be tested according to the detection result.
It should be noted that, a person skilled in the art may perform the cold start attack under different temperature conditions, determine whether the cold start attack is successful under different temperature conditions, and finally determine the maximum temperature for the cold start attack to be successful, and set the maximum temperature as the preset temperature. For example, the temperature of the memory to be measured can be reduced to 10 ℃, 0 ℃, 10 ℃ below zero, -20 ℃, 30 ℃ below zero and 40 ℃ below zero by spraying a coolant on the memory to be measured in operation; then, restarting the power-off of the memory to be tested; and finally, dumping the data stored in the memory to be tested onto a disk by utilizing an automatic loading bootstrap program, and determining the data retention rate of the memory to be tested under different temperature conditions. The data retention rate refers to the proportion of data dumped to the disk to the data originally stored in the memory to be tested. Under different temperature conditions, the data retention rate of the memory to be tested is different. For example, if the data retention rate is greater than or equal to 95%, determining that the cold start attack is successful; when the temperature is reduced to minus 20 ℃, minus 30 ℃ and minus 40 ℃, the data retention rate of the memory to be tested is more than 95%, and the success of the cold start attack is determined; when the temperature is reduced to 10 ℃, 0 ℃ and-10 ℃, determining that the cold start attack fails if the data retention rate of the memory to be tested is less than 95%; the-20 c may be set to a preset temperature.
In the embodiment of the present disclosure, in step S202, test data is written in a memory area to be tested; in step S203, after the memory to be tested is restarted and powered on, the stored data is read from the memory to be tested; in step S204, it is determined whether the memory to be tested is attacked by cold start according to the test data and the storage data. In the process of cold start attack, an attacker can quickly power off and restart the memory after cooling the memory in order to obtain more data in the memory, so as to reduce the data loss in the memory. Therefore, for the memory under test that is attacked by cold start, the data loss of the memory under test is very small. By writing test data into a storage area to be tested of the memory to be tested, after the memory to be tested is restarted and electrified, the storage data is read from the storage area to be tested, and whether the memory to be tested is attacked by cold start can be determined according to the test data and the storage data.
For example, an attacker cools all the memories to be tested in operation to-20 ℃; then, simultaneously powering off a plurality of memories to be tested in operation; then, restarting the memory to be tested to power up after waiting for different preset time periods; finally, the method includes the steps of; and dumping the data stored in the memory to be tested to a disk by using an automatic loading bootstrap program, and determining the data retention rate of the memory to be tested under different preset time periods. Under different power-off time periods, the data retention rates of the memories to be tested are different; more specifically, the shorter the power-off duration, the higher the data retention rate of the memory to be tested. Therefore, in order to obtain more data in the memory, an attacker can restart the memory to power up in the shortest time after cooling and powering down the memory, so as to preserve as much data in the memory as possible.
In some embodiments, if the test data and the stored data are substantially the same, it is determined that the memory under test is being attacked by the cold boot.
In the embodiment of the disclosure, by utilizing the characteristic that an attacker can acquire data in the memory to be tested more, when the temperature of the memory to be tested is detected to be lower than the preset temperature, test data is written in the memory to be tested rapidly; after restarting the memory to be tested and powering up, reading storage data from the memory to be tested; determining whether the memory to be tested is attacked by cold start according to the test data and the storage data; more specifically, if the test data and the stored data are substantially the same, it is determined that the memory under test is being attacked by the cold boot.
In the embodiment of the disclosure, when the temperature of the memory to be detected is detected to be lower than the preset temperature, the memory to be detected is suspected to possibly suffer from cold start attack; and writing test data into the storage area to be tested, reading storage data from the storage area to be tested after the storage area to be tested is restarted and electrified, comparing the test data with the storage data, and determining whether the storage area to be tested is attacked by cold start.
In addition, if it is determined that the memory to be tested is attacked by cold start, a corresponding operation needs to be performed on the memory to be tested, for example, a voltage mode of the memory to be tested is set to be a destruction mode to destroy data stored in the memory to be tested, so that the data stored in the memory to be tested is prevented from being stolen; if the memory to be tested is determined not to be attacked by cold start, the corresponding operation is not required to be executed on the memory to be tested, and the data stored in the memory to be tested is not required to be stolen.
Referring to fig. 3, fig. 3 is a timing chart of a memory after restarting and powering up according to an embodiment of the present disclosure. As shown in fig. 3, the beginning of Ta is marked by VDD1 power up and enters a power ramp up (power ramp) phase that requires VDD2 power up no earlier than VDD1 power up and VDDQ power up no earlier than VDD2 power up, i.e., the memory starts from VDD1 power up to VDDQ power up end. The maximum value of the duration of the memory from Ta to Tb must not exceed 20ms, i.e., tinit0=20 ms (max). Where VDD1 and VDD2 are core logic (core) power supplies of the memory, and VDDQ is Input/Output (I/O) interface power supplies of the memory.
The start of time Tb is marked by the completion of VDDQ power-up, and enters a Reset (Reset) operation phase, which requires that the Reset signal reset_n be switched to a high state after at least 200 μs of the low state is maintained, i.e., tinit1=200 μs (min). Also, the clock signal CKE must remain in the low state for at least 10ns, i.e., tinit2=10 ns (min), before the Reset signal reset_n is switched from the low state to the high state.
The start of Tc is marked by the Reset signal reset_n switching to a high state, and enters an Initialization (Initialization) phase, which requires that the clock signal CKE must remain in a low state for at least 2ms after the Reset signal reset_n is switched to a high state, i.e., tinit3=2 ms (min). Also, before the clock signal CKE is switched from the low level state to the high level state, the differential clock signals ck_c and ck_t are required to start operation and hold for at least 5 clock cycles, i.e., tinit4=5 tCK (min).
The start of time Td is marked by the switching of the clock signal CKE to the high state, which requires that the mode register read (Mode Register Read, MRR) command and the mode register write (Mode Register Write, MRW) command be sent after the clock signal CKE remains at least 2 mus high to operate the mode register, i.e., tinit5=2 mus (min). After time Td, the memory exits the Power Down mode (Exit Power Down, exit PD).
Exiting the power down mode indicates that after the memory is restarted and powered up, the Reset signal reset_n is changed from the low state to the high state, the clock signal CKE is changed from the low state to the high state, and the differential clock signals ck_c and ck_t are already activated. Therefore, whether the memory exits the power down mode can be determined according to the reset signal and the clock signal. Wherein the differential clock signals ck_c and ck_t have been put into action means that both address and control input signals can be sampled at the intersection of the rising edge of ck_t and the falling edge of ck_c.
After Te time, after finishing setting of the pull-up resistance value, the pull-down resistance value and the receiving end resistance value through the MRW instruction, the controller can send a ZQ calibration Start (ZQ Cal Start) command, wherein the ZQ calibration command is used for calibrating the output high level and the output resistance under different voltages and temperatures.
After the Tf time instant, a ZQ Cal Latch command is sent after waiting at least 1 μs after sending the ZQ calibration command to update the calibration parameters, i.e., tzqcal=1 μs (min).
After the time Tg, after a waiting time tzqlat=max (30 ns,8 tck) (min), the command bus starts to prepare for high-speed operation. The MRW command is sent causing the memory to enter a command bus training mode (Command Bus Training Mode) to train the command bus.
After Th time, since the memory includes a plurality of memory chips, the time at which the command address signal reaches each memory chip in the memory is different, but the time at which the data reaches each memory chip in the memory is substantially the same, it is necessary to train one offset compensation (Write Leveling) between clock and data for each memory chip. The clock may be represented by a clock signal CKE and the data by a DQs signal.
Still referring to FIG. 3, the focus in this scenario is on the memory restarting during power-up to exiting power-down mode. After determining that the memory to be tested is attacked by cold start, the voltage mode of the memory to be tested needs to be set to be a destruction mode to destroy the data stored in the memory to be tested, and after exiting the power-down mode, even if an attacker can execute a reading operation on the memory to be tested, the attacker cannot acquire the original data in the memory to be tested, so that the problem that the data is stolen after restarting the memory to be tested is solved.
In the embodiment of the disclosure, the data stored in the storage area to be tested is destroyed during the period from restarting the power-up to exiting the power-down mode by using the memory. Considering that the Reset signal reset_n can be switched from the low level state to the high level state after at least 200 μs after the memory to be tested is restarted and is powered up, and the clock signal CKE can be switched from the low level state to the high level state after at least 2ms, at this time, the memory to be tested exits the power-down mode. In other words, the duration of destroying the data stored in the memory under test is at least 2.2ms.
In embodiments of the present disclosure, the memory under test may include DRAM. Thus, the memory area to be measured comprises a plurality of memory cells to be measured, and each memory cell to be measured comprises a memory capacitor to be measured and a transistor; the storage capacitor to be tested is used for storing data written into the storage unit to be tested.
The DRAM represents data information by using both the charged state and the ground state of the storage capacitor. The potential of the storage capacitor is higher than 0.5 VCC, which represents writing "1", and the potential of the storage capacitor is lower than 0.5 VCC, which represents writing "0". Even if the external power source is used, the storage capacitor in a charged state may be gradually discharged, the charge of the storage capacitor may be gradually lost, and the data in the storage capacitor may be gradually disappeared. Therefore, all memory cells of the DRAM must be refreshed using a timed refresh method. The refreshing process is also a process of rewriting data in the storage capacitor, that is, a process of charging the storage capacitor.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a detection circuit for detecting a cold start attack according to an embodiment of the present disclosure. As shown in fig. 4, the detection circuit for detecting the cold start attack includes a temperature sensing circuit and a comparator, wherein the temperature sensing circuit is used for detecting the actual temperature of the memory to be detected, and the comparator is used for comparing the actual temperature of the memory to be detected with the preset temperature; if the actual temperature of the memory to be tested is lower than the preset temperature, the memory to be tested is suspected to be possibly attacked by cold start.
In the embodiment of the disclosure, after detecting that the temperature of the memory to be tested is lower than a preset temperature, suspected that the memory to be tested may be attacked by cold start, writing test data into the storage capacitor to be tested; after restarting and powering up the memory to be tested, reading storage data from the storage capacitor to be tested; and determining whether the memory to be tested is attacked by cold start according to the test data and the storage data.
Still referring to fig. 4, the detection circuit for detecting a cold start attack further includes a self-refresh circuit, and the self-refresh circuit is used to refresh the memory to be tested at regular time to ensure that the data in the memory to be tested does not disappear.
In the embodiment of the disclosure, after detecting that the temperature of the memory to be tested is lower than a preset temperature and suspected that the memory to be tested is possibly attacked by cold start, charging a storage capacitor to be tested of a storage area to be tested to a preset potential value when the memory to be tested enters a self-refresh mode; after restarting the memory to be tested and powering up, reading an actual potential value from a storage capacitor to be tested in a storage area to be tested; and determining whether the memory to be tested is attacked by cold start according to the preset potential value and the actual potential value.
In some embodiments, if the preset potential value and the actual potential value are substantially the same, it is determined that the memory under test is attacked by cold start.
It should be noted that, in order to obtain more data in the memory, an attacker will restart the memory to power up in a shortest time after cooling down the memory, so as to preserve as much data in the memory as possible. By utilizing the characteristic that an attacker aims at acquiring more data in the memory to be detected, when the temperature of the memory to be detected is detected to be lower than a preset temperature, the memory capacitor to be detected is rapidly charged to a preset potential value; detecting an actual potential value of a storage capacitor to be detected after restarting and powering up the storage capacitor to be detected; determining whether the memory to be tested is attacked by cold start according to the preset potential value and the actual potential value; more specifically, if the preset potential value and the actual potential value are substantially the same, it is determined that the memory to be tested is attacked by cold start.
In the embodiment of the disclosure, the preset potential value and the actual potential value are the same or the preset potential value and the actual potential value meet the error range requirement. For example, the storage capacitor to be tested is charged to a preset potential value of 5V, after the storage capacitor to be tested is restarted and electrified, the actual potential value of the storage capacitor to be tested is detected to be 4.9V, the potential change of the storage capacitor to be tested is-0.1V, and the error range requirement is met.
In some embodiments, the storage capacitor to be measured includes at least one of: MOS capacitance, nickel capacitance and storage capacitance of the memory to be tested.
In the embodiment of the disclosure, an unused storage unit can be selected from original storage units in the memory to be tested to be set as the storage unit to be tested, and a storage capacitor of the unused storage unit is selected to be set as the storage capacitor to be tested to be used for detecting whether the memory to be tested is attacked by cold start; additional memory cells to be tested, including storage capacitors to be tested, such as MOS capacitors and nickel capacitors, may also be provided in advance in the memory to be tested, and used to detect whether the memory to be tested is attacked by cold start.
Referring to fig. 5, fig. 5 is a schematic structural diagram of a storage capacitor to be tested according to an embodiment of the disclosure. As shown in fig. 5 (a), the storage capacitor to be measured is a nickel capacitor; as shown in fig. 5 (b), the storage capacitor to be measured is the storage capacitor of the memory to be measured.
In the embodiment of the disclosure, a nickel capacitor and a storage capacitor C are formed in a memory to be tested simultaneously 1 The nickel capacitor is a plurality of capacitors C 1 The set, more specifically, the nickel capacitance is a plurality of capacitances C 1 And are connected in parallel. Therefore, the capacitance value of the nickel capacitor is larger than that of a single storage capacitor, and when the memory to be tested is attacked by cold start, the charge loss speed of the nickel capacitor is slower than that of the storage capacitor of the storage unit.
In the embodiments of the present disclosure, the additionally provided storage capacitor to be tested (for example, MOS capacitor and nickel capacitor) may share a Sense Amplifier (SA) with the original storage capacitor in the memory to be tested.
Referring to fig. 6, fig. 6 is a schematic diagram illustrating a setting position of a storage capacitor to be measured according to an embodiment of the disclosure. As shown in fig. 6, the additional storage capacitor to be measured is disposed in the edge region of the memory to be measured, and at this time, the temperature of the edge region of the memory to be measured is lower than that of the central region of the memory to be measured, and the charge loss rate of the storage capacitor to be measured is slower than that of the memory cells in the central region.
There is typically a redundant area on the DRAM that includes a plurality of redundant memory cells that can replace defective memory cells when they are generated by the DRAM to repair the DRAM. In repairing a DRAM chip, one Time Program (OTP) devices, such as antifuse cells, are used.
Referring to fig. 7, fig. 7 is a schematic diagram illustrating a selection of an unused redundant area to be set as a storage area to be tested according to an embodiment of the present disclosure. As shown in fig. 7, the use state of the redundant area of the memory to be tested is determined according to the antifuse state (anti-fuse); if the redundant area 1 is a used memory cell and the redundant area 2 is an unused memory cell; the unused redundant area 2 is set as a memory area to be measured according to the use state of the redundant area.
Based on the technical conception that the method for detecting the cold start attack is the same as the method for detecting the cold start attack, the embodiment of the disclosure provides a device for detecting the cold start attack. The embodiment of the disclosure may divide the functional modules of the device for detecting the cold start attack according to the embodiment of the method, for example, each functional module may be divided corresponding to each function, or two or more functions may be integrated into one processing module. The integrated modules described above may be implemented either in hardware or in software functional modules. It should be noted that, in the embodiment of the present disclosure, the division of the modules is merely a logic function division, and other division manners may be implemented in actual practice. The following description will be given by taking an example of dividing each function module into corresponding functions.
The embodiment of the disclosure also provides a device for detecting cold start attack, which comprises: the temperature detection module is used for detecting whether the temperature of the memory to be detected is lower than a preset temperature; the data writing module is used for writing test data in the storage area to be tested when the temperature of the memory to be tested is detected to be lower than a preset temperature; the memory to be tested comprises the memory area to be tested; the data reading module is used for reading storage data from the storage area to be detected after the storage area to be detected is restarted and electrified; and the data analysis module is used for determining whether the memory to be tested is attacked by cold start according to the test data and the storage data.
In the embodiment of the disclosure, when the temperature detection module detects that the temperature of the memory to be detected is lower than the preset temperature, the memory to be detected is suspected to possibly suffer from cold start attack; further writing test data in the storage area to be tested by utilizing the data writing module; after restarting the memory to be tested and powering up, reading the stored data from the memory area to be tested by utilizing a data reading module; and finally, comparing the test data with the storage data by utilizing a data analysis module, and determining whether the memory to be tested is attacked by cold start. And determining the subsequent operation to be executed by the memory to be tested according to the detection result.
In some embodiments, the data analysis module is specifically configured to: and if the test data and the storage data are basically the same, determining that the memory to be tested is attacked by cold start.
In some embodiments, the apparatus further comprises: and the data destruction module is used for setting the voltage mode of the memory to be detected as a destruction mode so as to destroy the data stored in the memory to be detected.
In the embodiment of the disclosure, after determining that the memory to be tested is attacked by cold start, the voltage mode of the memory to be tested is set to be a damage mode by using the data damage module, and data stored in the memory to be tested is damaged, so that the problem that the data is stolen after restarting the memory to be tested is solved.
In some embodiments, the memory region to be tested includes a plurality of memory cells to be tested, each of the memory cells to be tested including a memory capacitor to be tested and a transistor; the storage capacitor to be tested is used for storing data written into the storage unit to be tested.
In some embodiments, the data writing module is specifically configured to: when the temperature of the memory to be detected is detected to be lower than a preset temperature, and the memory to be detected enters a self-refresh mode, the storage capacitor to be detected of the storage area to be detected is charged to a preset potential value.
In some embodiments, the data reading module is specifically configured to: and after the memory to be tested is restarted and electrified, reading an actual potential value from the storage capacitor to be tested in the storage area to be tested.
In some embodiments, the data analysis module is specifically configured to: and determining whether the memory to be tested is attacked by cold start or not according to the preset potential value and the actual potential value.
In some embodiments, the apparatus further comprises: the state acquisition module is used for acquiring the use state of the redundant area of the memory to be detected; and the region setting module is used for setting the unused redundant region as a storage region to be tested according to the use state.
In some embodiments, the storage capacitor under test includes at least one of: MOS capacitance, nickel capacitance and the storage capacitance of the memory to be tested.
The embodiment of the disclosure also provides a device for detecting the cold start attack, which comprises a processor; a memory module; the storage module stores instructions executable by the processor, where the instructions are executed by the processor, so that the device for detecting a cold start attack can execute the method for detecting a cold start attack according to the technical scheme.
In the disclosed embodiment, the memory module may be separate or integrated with the processor.
When the memory module is a device independent of the processor, the apparatus for detecting a cold start attack further comprises: and the bus is used for connecting the memory module and the processor.
It should be appreciated that the processors referred to in the embodiments of the present disclosure may be central processing units (Central Processing Unit, CPUs), but may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSPs), application specific integrated circuits (Application Specific Integrated Circuit, ASICs), off-the-shelf programmable gate arrays (Field Programmable Gate Array, FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
In an embodiment of the disclosure, the bus may be an industry standard architecture (Industry Standard Architecture, ISA) bus, an external device interconnect (Peripheral Component Interconnect, PCI) bus, or an extended industry standard architecture (Extended Industry Standard Architecture, EISA) bus, among others. The buses may be divided into address buses, data buses, control buses, etc.
The embodiment of the disclosure also provides a chip, including: the processing module and the communication interface, the processing module can execute the technical scheme in any method embodiment.
Further, the chip further includes a storage module (e.g., a memory), where the storage module is configured to store the instructions, and the processing module is configured to execute the instructions stored in the storage module, and execution of the instructions stored in the storage module causes the processing module to execute the technical solution in any of the foregoing method embodiments.
The embodiment of the disclosure provides a memory, which comprises the device for detecting cold start attacks according to any one of the technical schemes.
In some embodiments, the memory is a dynamic random access memory.
In some embodiments, the memory of the dynamic random access memory meets DDR2 memory specifications.
In some embodiments, the memory of the dynamic random access memory meets DDR3 memory specifications.
In some embodiments, the memory of the dynamic random access memory meets DDR4 memory specifications.
In some embodiments, the memory of the dynamic random access memory meets DDR5 memory specifications.
In some embodiments, the memory of the dynamic random access memory meets DDR6 memory specifications.
In some embodiments, the memory of the dynamic random access memory meets the LPDDR4 memory specification.
In some embodiments, the memory of the dynamic random access memory meets the LPDDR5 memory specification.
The embodiment of the disclosure provides a method, a device and a memory for detecting cold start attacks, wherein the method comprises the following steps: providing a memory to be tested, wherein the memory to be tested comprises a memory area to be tested; when the temperature of the memory to be tested is detected to be lower than a preset temperature, writing test data in the memory area to be tested; after the memory to be tested is restarted and powered on, reading storage data from the storage area to be tested; and determining whether the memory to be tested is attacked by cold start according to the test data and the storage data. In the embodiment of the disclosure, when the temperature of the memory to be detected is detected to be lower than the preset temperature, the memory to be detected is suspected to possibly suffer from cold start attack; and writing test data into the storage area to be tested, reading storage data from the storage area to be tested after the storage area to be tested is restarted and electrified, comparing the test data with the storage data, and determining whether the storage area to be tested is attacked by cold start.
In addition, if the memory to be tested is determined to be attacked by cold start, the voltage mode of the memory to be tested can be set to be a destruction mode, and data stored in the memory to be tested is destroyed, so that the problem that the data is stolen after the memory to be tested is restarted is solved.
It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present disclosure, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by their functions and internal logic, and should not constitute any limitation on the implementation of the embodiments of the present disclosure. The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments.
The foregoing description is only of the preferred embodiments of the present disclosure, and is not intended to limit the scope of the present disclosure, but rather, the equivalent structural changes made by the present disclosure and the accompanying drawings under the inventive concept of the present disclosure, or the direct/indirect application in other related technical fields are included in the scope of the present disclosure.

Claims (19)

1. A method of detecting a cold start attack, the method comprising:
providing a memory to be tested, wherein the memory to be tested comprises a memory area to be tested;
when the temperature of the memory to be tested is detected to be lower than a preset temperature, writing test data in the memory area to be tested;
after the memory to be tested is restarted and powered on, reading storage data from the storage area to be tested;
and determining whether the memory to be tested is attacked by cold start according to the test data and the storage data.
2. The method of claim 1, wherein determining whether the memory under test is under cold-boot attack based on the test data and the stored data comprises:
and if the test data and the storage data are basically the same, determining that the memory to be tested is attacked by cold start.
3. The method of detecting a cold start attack according to claim 2, wherein after the determining that the memory under test is under cold start attack, the method further comprises:
and setting the voltage mode of the memory to be tested as a destruction mode so as to destroy the data stored in the memory to be tested.
4. The method of claim 1, wherein the memory region to be tested comprises a plurality of memory cells to be tested, each memory cell to be tested comprising a memory capacitor to be tested and a transistor; the storage capacitor to be tested is used for storing data written into the storage unit to be tested.
5. The method for detecting a cold start attack according to claim 4, wherein writing test data in the memory area to be detected when the temperature of the memory to be detected is detected to be lower than a preset temperature, comprises:
when the temperature of the memory to be detected is detected to be lower than a preset temperature, and the memory to be detected enters a self-refresh mode, the storage capacitor to be detected of the storage area to be detected is charged to a preset potential value.
6. The method of claim 5, wherein the reading the stored data from the memory area under test after the memory under test is powered up again comprises:
and after the memory to be tested is restarted and electrified, reading an actual potential value from the storage capacitor to be tested in the storage area to be tested.
7. The method of claim 6, wherein determining whether the memory under test is under cold-boot attack based on the test data and the stored data comprises:
And determining whether the memory to be tested is attacked by cold start or not according to the preset potential value and the actual potential value.
8. The method of detecting a cold start attack according to claim 4, wherein after detecting that the temperature of the memory under test is lower than a preset temperature, the method further comprises:
acquiring the use state of a redundant area of the memory to be tested;
and setting the unused redundant area as a storage area to be tested according to the use state.
9. The method of claim 4, wherein the storage capacitor under test comprises at least one of: MOS capacitance, nickel capacitance and the storage capacitance of the memory to be tested.
10. An apparatus for detecting a cold start attack, the apparatus comprising:
the temperature detection module is used for detecting whether the temperature of the memory to be detected is lower than a preset temperature;
the data writing module is used for writing test data in the storage area to be tested when the temperature of the memory to be tested is detected to be lower than a preset temperature; the memory to be tested comprises the memory area to be tested;
the data reading module is used for reading storage data from the storage area to be detected after the storage area to be detected is restarted and electrified;
And the data analysis module is used for determining whether the memory to be tested is attacked by cold start according to the test data and the storage data.
11. The apparatus for detecting a cold start attack according to claim 10, wherein the data analysis module is specifically configured to: and if the test data and the storage data are basically the same, determining that the memory to be tested is attacked by cold start.
12. The apparatus for detecting a cold start attack of claim 11 wherein the apparatus further comprises:
and the data destruction module is used for setting the voltage mode of the memory to be detected as a destruction mode so as to destroy the data stored in the memory to be detected.
13. The apparatus for detecting a cold start attack according to claim 10, wherein the memory region to be tested comprises a plurality of memory cells to be tested, each of the memory cells to be tested comprising a memory capacitor to be tested and a transistor; the storage capacitor to be tested is used for storing data written into the storage unit to be tested.
14. The apparatus for detecting a cold start attack according to claim 13, wherein the data writing module is specifically configured to: when the temperature of the memory to be detected is detected to be lower than a preset temperature, and the memory to be detected enters a self-refresh mode, the storage capacitor to be detected of the storage area to be detected is charged to a preset potential value.
15. The apparatus for detecting a cold start attack according to claim 14, wherein the data reading module is specifically configured to: and after the memory to be tested is restarted and electrified, reading an actual potential value from the storage capacitor to be tested in the storage area to be tested.
16. The apparatus for detecting a cold start attack according to claim 15, wherein the data analysis module is specifically configured to: and determining whether the memory to be tested is attacked by cold start or not according to the preset potential value and the actual potential value.
17. The apparatus for detecting a cold start attack of claim 13 wherein the apparatus further comprises:
the state acquisition module is used for acquiring the use state of the redundant area of the memory to be detected;
and the region setting module is used for setting the unused redundant region as a storage region to be tested according to the use state.
18. The apparatus for detecting a cold start attack of claim 13 wherein the storage capacitor under test comprises at least one of: MOS capacitance, nickel capacitance and the storage capacitance of the memory to be tested.
19. A memory comprising a means of detecting a cold start attack as claimed in any one of claims 10 to 18.
CN202210938465.6A 2022-08-05 2022-08-05 Method and device for detecting cold start attack and memory Pending CN117558317A (en)

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