CN117556753B - Method, device, equipment and storage medium for analyzing energy consumption of storage chip - Google Patents
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Abstract
The application relates to the technical field of artificial intelligence and discloses an energy consumption analysis method, device and equipment of a storage chip and a storage medium. The method comprises the following steps: performing energy consumption test on the target stacked memory chip based on the initial memory chip stacking and packaging scheme to obtain target chip power consumption data and target chip temperature data; performing data decomposition to obtain a plurality of sub-power consumption data sets and a plurality of sub-temperature data sets; extracting features to obtain a power consumption fusion feature set and a temperature fusion feature set; vector code conversion is carried out to obtain a target power consumption characteristic input vector and a target temperature characteristic input vector; performing power consumption prediction to obtain chip power consumption prediction data and chip temperature prediction data; the multi-target optimization is carried out to obtain a target storage chip stacking and packaging scheme, and the intelligent energy consumption analysis of the stacked storage chips is realized by adopting a machine learning technology, so that the optimization accuracy of the storage chip stacking and packaging scheme is improved.
Description
Technical Field
The present disclosure relates to the field of artificial intelligence technologies, and in particular, to a method, an apparatus, a device, and a storage medium for analyzing energy consumption of a storage chip.
Background
In the present information age, stacked memory chips are increasingly used in various fields, such as data centers, internet of things devices, mobile devices, and the like. However, the power consumption of stacking memory chips has been an important issue because it relates to the performance, stability, and energy efficiency of the device. With the continued development and complexity of stacked memory chips, conventional energy consumption analysis methods have been difficult to meet, and therefore, a more accurate and efficient method is needed to evaluate the power consumption and temperature of memory chips for optimization at the design and manufacturing stages to achieve better performance and energy utilization.
The conventional stacked memory chip energy consumption analysis method has some problems. The structure and complexity of stacked memory chips are increasing, and it is difficult for conventional methods to efficiently process large-scale and high-dimensional data. Second, outliers and missing values of data negatively affect the analysis results, requiring efficient data processing methods. In addition, the correlation between power consumption and temperature also requires finer modeling and analysis in order to more accurately predict power consumption and temperature.
Disclosure of Invention
The application provides an energy consumption analysis method, device and equipment for a memory chip and a memory medium, which are used for realizing intelligent energy consumption analysis of stacked memory chips by adopting a machine learning technology so as to improve the optimization accuracy of a memory chip stacking and packaging scheme.
In a first aspect, the present application provides a method for analyzing energy consumption of a memory chip, where the method for analyzing energy consumption of a memory chip includes:
performing energy consumption test on the target stacked memory chip based on a preset initial memory chip stacking and packaging scheme to obtain target chip power consumption data and target chip temperature data;
respectively carrying out data decomposition on the target chip power consumption data and the target chip temperature data through a preset fast integrated experience model decomposition algorithm to obtain a plurality of sub-power consumption data sets and a plurality of sub-temperature data sets;
extracting features of the plurality of sub-power consumption data sets through a preset first long-short time memory network to obtain a power consumption fusion feature set, and extracting features of the plurality of sub-temperature data sets through a preset second long-short time memory network to obtain a temperature fusion feature set;
vector coding conversion is carried out on the power consumption fusion feature set and the temperature fusion feature set, so that a target power consumption feature input vector and a target temperature feature input vector are obtained;
inputting the target power consumption characteristic input vector into a preset first twin support vector regression model to conduct power consumption prediction to obtain chip power consumption prediction data, and inputting the target temperature characteristic input vector into a preset second twin support vector regression model to conduct temperature prediction to obtain chip temperature prediction data;
And calculating power consumption error data of the chip power consumption prediction data and temperature error data of the chip temperature prediction data, and performing multi-objective optimization on the initial storage chip stacking and packaging scheme according to the power consumption error data and the temperature error data to obtain a target storage chip stacking and packaging scheme.
In a second aspect, the present application provides an energy consumption analysis device of a memory chip, the energy consumption analysis device of the memory chip including:
the testing module is used for carrying out energy consumption testing on the target stacked memory chip based on a preset initial memory chip stacking and packaging scheme to obtain target chip power consumption data and target chip temperature data;
the decomposition module is used for respectively carrying out data decomposition on the power consumption data of the target chip and the temperature data of the target chip through a preset rapid integrated experience model decomposition algorithm to obtain a plurality of sub-power consumption data sets and a plurality of sub-temperature data sets;
the characteristic extraction module is used for extracting the characteristics of the plurality of sub-power consumption data sets through a preset first long-short-time memory network to obtain a power consumption fusion characteristic set, and extracting the characteristics of the plurality of sub-temperature data sets through a preset second long-short-time memory network to obtain a temperature fusion characteristic set;
The encoding module is used for carrying out vector encoding conversion on the power consumption fusion feature set and the temperature fusion feature set to obtain a target power consumption feature input vector and a target temperature feature input vector;
the prediction module is used for inputting the target power consumption characteristic input vector into a preset first twin support vector regression model to conduct power consumption prediction to obtain chip power consumption prediction data, and inputting the target temperature characteristic input vector into a preset second twin support vector regression model to conduct temperature prediction to obtain chip temperature prediction data;
and the optimizing module is used for calculating the power consumption error data of the chip power consumption prediction data and the temperature error data of the chip temperature prediction data, and carrying out multi-objective optimization on the initial storage chip stacking and packaging scheme according to the power consumption error data and the temperature error data to obtain a target storage chip stacking and packaging scheme.
A third aspect of the present application provides an energy consumption analysis apparatus of a memory chip, comprising: a memory and at least one processor, the memory having instructions stored therein; the at least one processor invokes the instructions in the memory to cause the energy consumption analysis device of the memory chip to perform the energy consumption analysis method of the memory chip described above.
A fourth aspect of the present application provides a computer-readable storage medium having instructions stored therein, which when run on a computer, cause the computer to perform the method of energy consumption analysis of a memory chip as described above.
In the technical scheme provided by the application, multi-level data processing and feature extraction are adopted, and the method comprises the steps of fast integration of an experience model and a long-short-time memory network, so that the power consumption and temperature data of a memory chip can be predicted more accurately, and the prediction accuracy is improved. Using a multi-objective optimization technique, two key performance indicators of power consumption and temperature can be considered simultaneously to obtain an optimal memory chip stack packaging scheme. This helps to reduce the power consumption of the chip and improve the energy efficiency without sacrificing performance. By using a fast integrated empirical model decomposition algorithm and long and short term memory networks, useful characteristic information can be effectively extracted from raw power consumption and temperature data. This helps to predict power consumption and temperature more accurately, thereby optimizing the design. The feature set is converted into the vector and analyzed by using the feature ratio and the feature weight data, so that the comprehensive consideration of a plurality of features is facilitated, and the performance and the accuracy of the model are improved. The twin support vector regression model is adopted to predict the power consumption and the temperature, so that the method has higher prediction precision and robustness, and is beneficial to better controlling the power consumption and the temperature of the chip in the design process. The design process of the stacking and packaging scheme of the memory chip is automated, the requirement of manual intervention is reduced, and the design efficiency is improved. The method can comprehensively consider the parameters of the memory chips in different layers, including the parameters of the memory chips in the bottom layer, the middle layer and the top layer, so as to realize more comprehensive performance optimization, and adopts a machine learning technology to realize intelligent energy consumption analysis of the stacked memory chips, thereby improving the optimization accuracy of the stacked memory chip packaging scheme.
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In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained based on these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an embodiment of a method for analyzing energy consumption of a memory chip according to an embodiment of the present application;
fig. 2 is a schematic diagram of an embodiment of an energy consumption analysis device of a memory chip in an embodiment of the present application.
Detailed Description
The embodiment of the application provides an energy consumption analysis method, device and equipment of a memory chip and a memory medium. The terms "first," "second," "third," "fourth" and the like in the description and in the claims of this application and in the above-described figures, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments described herein may be implemented in other sequences than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed or inherent to such process, method, article, or apparatus.
For ease of understanding, the following describes a specific flow of an embodiment of the present application, referring to fig. 1, and one embodiment of a method for analyzing energy consumption of a memory chip in an embodiment of the present application includes:
step S101, performing energy consumption test on a target stacked memory chip based on a preset initial memory chip stacking and packaging scheme to obtain target chip power consumption data and target chip temperature data;
it is understood that the execution body of the present application may be an energy consumption analysis device of a memory chip, and may also be a terminal or a server, which is not limited herein. The embodiment of the present application will be described by taking a server as an execution body.
Specifically, parameters of the bottom, middle and top memory chips of the target stacked memory chip are obtained, including physical dimensions, electrical characteristics, thermal characteristics, and manufacturing processes of the chips. And initializing a stack packaging scheme for the target stacked memory chip according to the parameters. The determination of the initial stack packaging scheme is a process that comprehensively considers chip performance, cost, and manufacturing process, requiring the use of computer aided design software for simulation and optimization. And performing energy consumption test on the target stacked memory chips. And the power consumption data and the temperature data of the first chip are accurately acquired by professional testing equipment under actual or simulated working conditions. These data are the basis for analyzing the chip energy consumption and reflect the performance of the chip in the actual operating state. The acquired data contains outliers and missing values, which can affect the accuracy of the analysis. Therefore, it is necessary to perform outlier removal and missing value interpolation processing on the power consumption data and the temperature data of the first chip. Outlier removal is to reject atypical or erroneous data points, while outlier interpolation is to complement the data sequence, ensuring data integrity and consistency. Statistical methods such as box graph analysis, mean filling, or more complex interpolation algorithms such as K-nearest neighbor interpolation are typically employed. The processed second chip energy consumption data and temperature data are standardized, and the data are converted into a common standard for subsequent analysis and comparison. Data normalization includes normalization and de-normalization operations that help to eliminate the effects of data dimensions so that different data sets can be compared and analyzed under the same criteria. And after the standardization processing, obtaining the power consumption data of the target chip and the temperature data of the target chip.
Step S102, respectively carrying out data decomposition on target chip power consumption data and target chip temperature data through a preset fast integrated empirical model decomposition algorithm to obtain a plurality of sub-power consumption data sets and a plurality of sub-temperature data sets;
specifically, raw power consumption and temperature data is processed through a fast integrated empirical model decomposition algorithm, and the data is decomposed into several subsets that are easier to analyze and process through data decomposition techniques such as Principal Component Analysis (PCA) or Independent Component Analysis (ICA). This helps to simplify the data structure and also reveals hidden patterns and associations in the data resulting in multiple first power consumption data sets and multiple first temperature data sets. And performing square sum error calculation on each first power consumption data set and each first temperature data set, and evaluating consistency and reliability of each data set. By calculating the sum of squares error, the degree of deviation between each point in the data set and its average can be determined, which facilitates subsequent data screening and reconstruction. The first sum of squares error value for each first power consumption dataset and the second sum of squares error value for each first temperature dataset are key indicators for evaluating the data quality of each sub-set. A sum of squares error threshold for the first power consumption data and the second temperature data is set, the thresholds being a quantization criterion for the quality of the data set. The sum of squares error value for each data set is compared to a corresponding threshold value in order to determine which data sets meet a predetermined quality criterion. This comparison process will yield a plurality of first and second comparison results that will guide the subsequent dataset screening process. And screening the first power consumption data set and the first temperature data set according to the comparison results, removing the data sets which do not meet the quality standard, and reserving the data sets with higher quality so as to obtain a plurality of second power consumption data sets and a plurality of second temperature data sets. Reconstructing the filtered second power consumption data set and second temperature data set to form a final plurality of sub-power consumption data sets and a plurality of sub-temperature data sets. The purpose of data reconstruction is to integrate and optimize the data for more thorough and accurate analysis. In this process, various data reconstruction techniques, such as interpolation, smoothing or resampling, may be employed to ensure the integrity and consistency of the data set.
Step S103, extracting features of a plurality of sub-power consumption data sets through a preset first long-short time memory network to obtain a power consumption fusion feature set, and extracting features of a plurality of sub-temperature data sets through a preset second long-short time memory network to obtain a temperature fusion feature set;
specifically, feature extraction is performed on a plurality of sub-power consumption data sets through a preset first long-short time memory network. These features include time series features, ripple features, and periodicity features of the data. These features are extracted to capture the dynamic changes in power consumption data over time and the inherent patterns. And carrying out feature fusion on the target power consumption features of each sub-power consumption data set to obtain a comprehensive power consumption fusion feature set. The features of the different data sets are combined together to form a more comprehensive and representative feature set. And extracting the characteristics of the plurality of sub-temperature data sets through a preset second long-short-time memory network, so as to obtain the target temperature characteristics of each sub-temperature data set. These features reflect the characteristics of the chip temperature over time, including the rate of temperature rise and fall, the magnitude of temperature fluctuations, etc. And carrying out feature fusion on the temperature features to form a comprehensive temperature fusion feature set. The core of the long and short term memory network is that it is capable of handling and memorizing long-term dependency information, which benefits from its unique network architecture, including input gates, forget gates and output gates, as well as corresponding cell states and hidden states. The first long-short-term memory network and the second long-term memory network are identical in structure, including specific mathematical operations and functions. These networks process input data through a series of computational processes including updating of hidden states, computation of cell states, operation of input gates, output gates, and forget gates. Each stage of the network involves specific weight and bias parameters that are optimized during the network training process. The activation function, sigmoid function, and tanh function in the network play a vital role in processing data. These functions are responsible for adjusting the nonlinear characteristics of the data, ensuring that the network is able to capture complex data patterns. In addition, the hadamard Ma Chengji acts in processing unit state and output state, further enhancing the processing capacity of the network. The difference between the output predictions and the actual values is calculated by a loss function, which aids in network training and optimization. The calculation of the loss function value reflects the accuracy of network prediction and is a key index for optimizing network performance.
Step S104, carrying out vector code conversion on the power consumption fusion feature set and the temperature fusion feature set to obtain a target power consumption feature input vector and a target temperature feature input vector;
specifically, the power consumption fusion feature set is subjected to calculation of feature mean values and feature standard deviations, and the central trend and the dispersion degree of each feature value in the feature set are quantized. The average level of the power consumption data can be obtained by calculating the average value of the power consumption characteristics, and the fluctuation range of the data can be known by calculating the standard deviation. And calculating a characteristic mean value and a characteristic standard deviation of the temperature fusion characteristic set, wherein the mean value and the standard deviation of the temperature characteristic represent the mean level and the fluctuation range of the temperature data. The power consumption characteristic ratio and the temperature characteristic ratio can be obtained by calculating the ratio of the power consumption characteristic mean to the standard deviation and the ratio of the temperature characteristic mean to the standard deviation. These ratios reflect the importance and reliability of the individual features, providing a basis for determining the weight of each feature. Vector code conversion is carried out on the power consumption fusion feature set and the temperature fusion feature set, and the feature sets are converted into numerical forms which can be processed by a computer. And converting each characteristic value into a numerical value within a certain range, thereby forming a power consumption fusion characteristic vector and a temperature fusion characteristic vector. And carrying out weighted analysis on the power consumption fusion characteristic vector and the temperature fusion characteristic vector according to the characteristic weight data. By giving different weights to different features, the accuracy and rationality of data analysis are ensured. The result of the weighted analysis is a target power consumption characteristic input vector and a target temperature characteristic input vector.
Step S105, inputting a target power consumption characteristic input vector into a preset first twin support vector regression model to conduct power consumption prediction to obtain chip power consumption prediction data, and inputting a target temperature characteristic input vector into a preset second twin support vector regression model to conduct temperature prediction to obtain chip temperature prediction data;
specifically, the target power consumption characteristic input vector is input into a first twin support vector regression model. The input vector is feature mapped by a first kernel function, mapping the original feature space to a higher dimensional feature space. Such mapping helps reveal complex nonlinear relationships that enable the model to better understand and process the data. After mapping, the result is a target power consumption feature map vector that represents the behavior of the original input data in the new feature space. And carrying out regression analysis on the target power consumption characteristic mapping vector through a first prediction function in the first twin support vector regression model. And analyzing the data by using a statistical learning theory so as to predict future power consumption. Through regression analysis, the model can estimate future power consumption values based on historical data and patterns thereof. This process not only takes into account the current characteristics of the data, but also predicts how these characteristics change over time and conditions. Likewise, the target temperature feature input vector is input into a second twin support vector regression model, and a second kernel function is used for feature mapping. This mapping process converts the features of the temperature data into a new dimensional space, enabling the model to understand more deeply the inherent structure and relevance of the data. And carrying out regression analysis on the target temperature characteristic mapping vector through a second prediction function in the second twin support vector regression model. The model is able to predict the temperature of the chip based on the mapped feature vector. This predictive process takes into account various factors such as historical temperature data, environmental conditions, and the operating mode of the chip. The first twin support vector regression model can accurately predict the power consumption of the chip, and the second twin support vector regression model can accurately predict the temperature of the chip. These two predictions help to understand and optimize the energy consumption and temperature management of the memory chip.
And S106, calculating power consumption error data of the chip power consumption prediction data and temperature error data of the chip temperature prediction data, and performing multi-objective optimization on the initial storage chip stacking and packaging scheme according to the power consumption error data and the temperature error data to obtain the objective storage chip stacking and packaging scheme.
Specifically, prediction error calculation is performed, and actually measured power consumption data of the target chip is compared with power consumption prediction data obtained by prediction of a support vector regression model, so that power consumption error data is obtained. And similarly, comparing the actually measured target chip temperature data with temperature prediction data to obtain temperature error data. These error data directly reflect the accuracy of the predictive model and the performance of the current stacked packaging scheme. A multi-objective optimization function is defined based on the power consumption and temperature error data. The purpose of this function is to find a balance point taking both power consumption and temperature into account, i.e. to ensure that the chip power consumption is minimized while also ensuring that the temperature is controlled within a safe range. Under the direction of this function, it can be determined which stacked packaging schemes are better. And processing the initial memory chip stacking and packaging scheme through a preset seeker optimization algorithm to obtain a plurality of candidate schemes. The seeker optimization algorithm is an advanced search algorithm that can efficiently explore a large number of solutions, finding the most potential candidates. A selection probability value for each candidate is calculated using a multi-objective optimization function. Each solution is evaluated for efficiency in meeting power consumption and temperature requirements, and the higher the probability value, the more optimal solution is selected. And screening the candidate schemes according to the selection probability values to determine the current optimal storage chip stacking and packaging scheme. This choice is based on a multi-objective optimization result that comprehensively considers power consumption and temperature errors. And carrying out further multi-objective optimization and iterative solution on the current optimal scheme. By continuously adjusting and optimizing the parameters of the scheme, the ideal memory chip stacking and packaging scheme is gradually approximated. The iterative solving process is dynamic, and can ensure that the finally obtained target storage chip stacking and packaging scheme achieves the optimal balance in the aspects of power consumption and temperature management according to the real-time feedback adjustment scheme. Through the calculation, optimization and iteration processes, the energy consumption efficiency maximization of the memory chip can be ensured, meanwhile, the temperature is kept in a safe and effective operation range, and powerful guarantee is provided for the reliability and performance of the chip.
In the embodiment of the application, multi-level data processing and feature extraction are adopted, and the method comprises the steps of fast integration of an experience model and a long-short-time memory network, so that the power consumption and temperature data of a memory chip can be predicted more accurately, and the prediction accuracy is improved. Using a multi-objective optimization technique, two key performance indicators of power consumption and temperature can be considered simultaneously to obtain an optimal memory chip stack packaging scheme. This helps to reduce the power consumption of the chip and improve the energy efficiency without sacrificing performance. By using a fast integrated empirical model decomposition algorithm and long and short term memory networks, useful characteristic information can be effectively extracted from raw power consumption and temperature data. This helps to predict power consumption and temperature more accurately, thereby optimizing the design. The feature set is converted into the vector and analyzed by using the feature ratio and the feature weight data, so that the comprehensive consideration of a plurality of features is facilitated, and the performance and the accuracy of the model are improved. The twin support vector regression model is adopted to predict the power consumption and the temperature, so that the method has higher prediction precision and robustness, and is beneficial to better controlling the power consumption and the temperature of the chip in the design process. The design process of the stacking and packaging scheme of the memory chip is automated, the requirement of manual intervention is reduced, and the design efficiency is improved. The method can comprehensively consider the parameters of the memory chips in different layers, including the parameters of the memory chips in the bottom layer, the middle layer and the top layer, so as to realize more comprehensive performance optimization, and adopts a machine learning technology to realize intelligent energy consumption analysis of the stacked memory chips, thereby improving the optimization accuracy of the stacked memory chip packaging scheme.
In a specific embodiment, the process of executing step S101 may specifically include the following steps:
(1) Acquiring bottom layer memory chip parameters, middle layer memory chip parameters and top layer memory chip parameters of a target stacked memory chip;
(2) Initializing a stacking and packaging scheme of the target stacked memory chip according to the bottom layer memory chip parameters, the middle layer memory chip parameters and the top layer memory chip parameters to obtain an initial memory chip stacking and packaging scheme;
(3) Performing energy consumption test on the target stacked memory chip according to the initial memory chip stacking and packaging scheme, and collecting first chip power consumption data and first chip temperature data of the target stacked memory chip;
(4) Respectively carrying out outlier removal and outlier interpolation on the first chip power consumption data and the first chip temperature data to obtain second chip energy consumption data and second chip temperature data;
(5) And respectively carrying out data standardization processing on the second chip energy consumption data and the second chip temperature data to obtain target chip power consumption data and target chip temperature data.
Specifically, parameters of the bottom layer, the middle layer and the top layer of the target stacked memory chip are obtained. These parameters include the physical dimensions, electrical characteristics, thermal characteristics, and manufacturing processes of the chip, among others. For example, the bottom chip has a larger physical size and higher electrical capacity, while the top chip is designed to be thinner and thinner to accommodate the heat conduction requirements. And initializing a stack packaging scheme for the target stacked memory chip according to the parameters. This is a process that comprehensively considers chip performance, cost, and manufacturing process. For example, if the underlying chip has higher heat resistance, it is placed close to the heat source, while the chip with more electrical properties is placed in a location that requires more energy. A preliminary stacking scheme can be developed by simulation and optimization with computer aided design software. Based on an initial scheme, performing energy consumption test on the target stacked memory chip, and collecting power consumption data and temperature data of the first chip. For example, the power consumption of the chip is tested under simulated actual operating conditions while its temperature change is recorded. These data are the basis for analyzing the chip energy consumption and reflect the performance of the chip in the actual operating state. The acquired data contains outliers and missing values, which can affect the accuracy of the analysis. Therefore, the abnormal value removal and missing value interpolation processing is performed on the power consumption data and the temperature data of the first chip. Outlier removal is to reject atypical or erroneous data points, while outlier interpolation is to complement the data sequence, ensuring data integrity and consistency. For example, if a point in a continuous temperature record suddenly jumps to an unreasonably high value, which is an outlier, it should be rejected; if data at a certain point in time is lost, the value of this point can be estimated from the data at the surrounding points in time. And carrying out standardized processing on the processed second chip energy consumption data and temperature data. The data is converted to a common standard for subsequent analysis and comparison. Normalization processes include normalization and de-normalization operations that help to eliminate the effects of data dimensions so that different data sets can be compared and analyzed under the same criteria. For example, all power consumption data may be divided by a maximum power consumption value, normalizing the data to between 0 and 1; or subtracting the average value of the whole data set from each data point to perform the de-averaging process.
In a specific embodiment, the process of executing step S102 may specifically include the following steps:
(1) Respectively carrying out data decomposition on the power consumption data of the target chip and the temperature data of the target chip through a preset fast integrated empirical model decomposition algorithm to obtain a plurality of first power consumption data sets and a plurality of first temperature data sets;
(2) Respectively carrying out square sum error calculation on a plurality of first power consumption data sets to obtain first square sum error values of each first power consumption data set, and respectively carrying out square sum error calculation on a plurality of first temperature data sets to obtain second square sum error values of each first temperature data set;
(3) Acquiring a first square sum error threshold of power consumption data of a target chip, and comparing the first square sum error threshold with a first square sum error value respectively to obtain a plurality of first comparison results; meanwhile, a second square sum error threshold value of the temperature data of the target chip is obtained, and the second square sum error threshold value and the second square sum error value are respectively compared to obtain a plurality of second comparison results;
(4) Performing data set screening on the plurality of first power consumption data sets according to the plurality of first comparison results to obtain a plurality of second power consumption data sets, and performing data set screening on the plurality of first temperature data sets according to the plurality of second comparison results to obtain a plurality of second temperature data sets;
(5) And respectively carrying out data set reconstruction on the plurality of second power consumption data sets and the plurality of second temperature data sets to obtain a plurality of sub-power consumption data sets and a plurality of sub-temperature data sets.
Specifically, the power consumption and temperature data of the target chip are subjected to data decomposition by a fast integrated empirical model decomposition algorithm, and an original large data set is decomposed into a plurality of small data sets. For example, if raw power consumption data is collected from a plurality of different test conditions, the data may be broken down into sub-data sets that are separated according to particular conditions or time periods. Such decomposition not only helps identify and isolate data characteristics under different operating conditions, but also reveals potential data patterns and trends. And respectively carrying out square sum error calculation on the first power consumption data set and the first temperature data set. The consistency and reliability inside each sub-dataset is evaluated. Specifically, for each dataset, the extent of fluctuation of the dataset is determined by summing the squares of the differences between its data points and the mean. For example, if a power consumption data set shows small fluctuations in different measurements, its sum of squares error value will be relatively small, indicating that the data set has a high reliability. The sum of squares error threshold values of the first power consumption data and the second temperature data are set as criteria for evaluating the quality of the data set. The sum of squares error value for each sub-data set is compared to these thresholds to determine whether each data set meets quality criteria. For example, if the sum of squares error value of a certain power consumption sub-dataset is above a preset threshold, this indicates that the dataset contains outliers or measurement conditions thereof are not representative and are therefore excluded from subsequent analysis. And screening the first power consumption data set and the first temperature data set according to the comparison results, and removing the data sets which do not meet the quality standard so as to ensure the accuracy and the reliability of subsequent analysis. For example, through the screening process, those data sets that exhibit lower squares and errors will be retained, while those data sets that are more erroneous will be discarded. Reconstructing the filtered second power consumption data set and the second temperature data set to form a final sub-power consumption data set and a final sub-temperature data set. These datasets are integrated and optimized to make them more suitable for subsequent in-depth analysis and model creation. For example, mathematical methods such as interpolation, smoothing, or resampling techniques may be employed to ensure the integrity and consistency of the data set. The final sub-data set can better reflect the key characteristics of the original data, and the structure is more suitable for complex data analysis and model establishment.
In a specific embodiment, the process of executing step S103 may specifically include the following steps:
(1) Respectively extracting characteristics of a plurality of sub-power consumption data sets through a preset first long-short time memory network to obtain target power consumption characteristics of each sub-power consumption data set;
(2) Performing feature fusion on the target power consumption features of each sub-power consumption data set to obtain a power consumption fusion feature set;
(3) Respectively extracting characteristics of a plurality of sub-temperature data sets through a preset second long-short-time memory network to obtain target temperature characteristics of each sub-temperature data set;
(4) Performing feature fusion on the target temperature features of each sub-temperature dataset to obtain a temperature fusion feature set;
(5) Wherein, the first long-short-time memory network is the same with the second long-short-time memory network, and the first long-short-time memory network includes:
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indicating hidden status->Representing the state of the cell->Representing the network weight parameter,/->Network bias parameters->Representing an activation function->Representing sigmoid function->Representing the tanh function>Indicated at the time +.>Is->Indicated at the time +.>Is expressed as Loss function value, < ->Representing Hadamard Ma Chengji, " >Representing a Unit update function, & lt + & gt>Representing an input door->Indicates the output door, ++>Representing the actual value at time t.
Specifically, feature extraction is performed on a plurality of sub-power consumption data sets through a preset first long-short time memory network. Including time series, ripple, and periodicity characteristics of the data. The extraction of these features is to capture dynamic changes in power consumption data over time and internal patterns, providing important information for subsequent analysis and prediction. And carrying out feature fusion on the target power consumption features of each sub-power consumption data set, thereby obtaining a comprehensive power consumption fusion feature set. The features of the different data sets are combined together to form a more comprehensive and representative feature set that helps to understand and predict the power consumption behavior of the entire chip. And extracting the characteristics of the plurality of sub-temperature data sets through a preset second long-short-time memory network, so as to obtain the target temperature characteristics of each sub-temperature data set. These features reflect the characteristics of the chip temperature over time, including the rate of temperature rise and fall, the magnitude of temperature fluctuations, etc. And carrying out feature fusion on the temperature features to form a comprehensive temperature fusion feature set. L (L) The core of an STM network is that it is capable of handling and memorizing long-term dependency information, depending on its unique network architecture, including input gates, forget gates, and output gates, as well as the corresponding cell states and hidden states.Representing a hidden state,/->Represented are cell states that are updated stepwise over time and are adjusted by various weight and bias parameters of the network. In this process, the network conditions and passes information by activating functions f (e.g., reLU or tanh), sigmoid function σ, and tanh function. Input data +.>Processed by the network and generates an output prediction +.>. The performance of the whole network is evaluated by a Loss function Loss, which is typically the sum of squares of the differences between the actual and predicted values. Through the feature extraction and fusion of the two LSTM networks to the power consumption and temperature data, the energy consumption and temperature characteristics of the chip under different working conditions can be effectively captured.
In a specific embodiment, the process of executing step S104 may specifically include the following steps:
(1) Performing characteristic average value calculation on the power consumption fusion characteristic set to obtain a power consumption characteristic average value, and performing characteristic standard deviation calculation on the power consumption fusion characteristic set to obtain a power consumption characteristic standard deviation;
(2) Calculating a characteristic mean value of the temperature fusion characteristic set to obtain a temperature characteristic mean value, and calculating a characteristic standard deviation of the temperature fusion characteristic set to obtain a temperature characteristic standard deviation;
(3) Calculating the ratio of the power consumption characteristic mean value to the power consumption characteristic standard deviation to obtain a power consumption characteristic ratio, and calculating the ratio of the temperature characteristic mean value to the temperature characteristic standard deviation to obtain a temperature characteristic ratio;
(4) Calculating feature weight data corresponding to the power consumption fusion feature set and the temperature fusion feature set according to the power consumption feature ratio and the temperature feature ratio;
(5) Performing vector code conversion on the power consumption fusion feature set to obtain a power consumption fusion feature vector, and performing vector code conversion on the temperature fusion feature set to obtain a temperature fusion feature vector;
(6) And respectively carrying out weighted analysis on the power consumption fusion feature vector and the temperature fusion feature vector according to the feature weight data to obtain a target power consumption feature input vector and a target temperature feature input vector.
Specifically, the feature mean value and the feature standard deviation are calculated for the power consumption fusion feature set and the temperature fusion feature set. Feature mean refers to the mean of each feature over all data points, and feature standard deviation is a statistical indicator that measures the range of variation of each feature over the data points. By calculating these two statistics, the central trends of the power consumption and temperature characteristics, as well as their degree of dispersion, can be captured. For example, if the mean value of a power consumption feature is high and the standard deviation is low, this means that the feature is relatively stable under different operating conditions; conversely, if the standard deviation is higher, this characteristic is shown to vary significantly under different conditions. And calculating the ratio of the power consumption characteristic mean value to the standard deviation, and the ratio of the temperature characteristic mean value to the standard deviation. These ratios help evaluate the stability of the features. Features with higher ratios mean that are higher relative to their range of variation, such features are generally considered more stable and reliable. Weights for the features are determined based on the calculated power consumption feature ratios and temperature feature ratios. The determination of feature weights is based on the importance and stability of the features, with higher weight features being given a greater specific gravity in subsequent analysis. For example, if the feature ratio of a certain power consumption feature is high, it will be given a larger weight, reflecting that this feature has a larger impact on the overall power consumption. And performing vector code conversion on the power consumption fusion feature set and the temperature fusion feature set. Vector coding is the conversion of feature data into a format suitable for machine learning and statistical analysis. The eigenvalues are normalized or normalized and converted to vector form. For example, all of the feature values in a power consumption feature set may be converted into a vector, where each element represents a feature value. And carrying out weighted analysis on the obtained power consumption fusion feature vector and the temperature fusion feature vector to obtain a target power consumption feature input vector and a target temperature feature input vector. In this process, each element in each feature vector will be weighted according to its corresponding feature weight. Such weighted analysis can highlight those more important or stable features, thereby playing a greater role in the final power consumption and temperature prediction model. For example, if a power consumption feature is given a higher weight, then in the weighted target power consumption feature input vector, this feature will take up a greater weight.
In a specific embodiment, the process of executing step S105 may specifically include the following steps:
(1) Inputting the target power consumption characteristic input vector into a preset first twin support vector regression model, and carrying out characteristic mapping on the target power consumption characteristic input vector through a first kernel function in the first twin support vector regression model to obtain a target power consumption characteristic mapping vector;
(2) Carrying out regression analysis and power consumption prediction on the target power consumption characteristic mapping vector through a first prediction function in a first twin support vector regression model to obtain chip power consumption prediction data;
(3) Inputting the target temperature characteristic input vector into a preset second twin support vector regression model, and carrying out characteristic mapping on the target temperature characteristic input vector through a second kernel function in the second twin support vector regression model to obtain a target temperature characteristic mapping vector;
(4) And carrying out regression analysis and temperature prediction on the target temperature characteristic mapping vector through a second prediction function in the second twin support vector regression model to obtain chip temperature prediction data.
Specifically, the target power consumption characteristic input vector is input into a preset first twin support vector regression model, and characteristic mapping is carried out through a first kernel function in the model. The kernel function is able to map the input data to a higher dimensional space in which otherwise inseparable data becomes separable. For example, common kernel functions include a linear kernel, a polynomial kernel, and a Radial Basis Function (RBF) kernel. Which kernel function is chosen depends on the nature of the data and the complexity of the problem. Under the action of the kernel function, the target power consumption characteristic input vector is converted into a new characteristic space, namely a target power consumption characteristic mapping vector. And carrying out regression analysis and power consumption prediction on the mapping vector through a first prediction function of the first twin support vector regression model. This prediction function is based on the principle of a support vector machine, trying to find an optimal regression plane, so that the prediction error is minimized. By mathematical calculations and optimization algorithms, such as the Sequence Minimum Optimization (SMO) algorithm. Through this process, predictive data of the power consumption of the chip can be obtained, which reflects the power consumption behavior of the chip under different conditions. And simultaneously, inputting the target temperature characteristic input vector into a preset second twin support vector regression model, and carrying out characteristic mapping on the target temperature characteristic input vector through a second kernel function in the second twin support vector regression model to obtain a target temperature characteristic mapping vector. And mapping the temperature characteristic vector to a new high-dimensional characteristic space to form a target temperature characteristic mapping vector. The second prediction function of the second twin support vector regression model performs regression analysis and temperature prediction on the mapped vector. The temperature performance of the chip under different operation conditions is accurately predicted by using a machine learning algorithm, which helps to ensure the reliability and performance of the chip. The advantage of the twin support vector regression model is its accuracy for efficient processing and prediction of data. The twin support vector regression model can process large-scale data sets more efficiently and perform better in processing non-linear and high-dimensional data than a conventional single support vector machine. For example, when processing power consumption data with complex time series characteristics, such a model can more accurately capture the inherent dynamics of the data, thereby providing more accurate predictions.
In a specific embodiment, the process of executing step S106 may specifically include the following steps:
(1) Performing prediction error calculation on the target chip power consumption data and the chip power consumption prediction data to obtain power consumption error data, and performing prediction error calculation on the target chip temperature data and the chip temperature prediction data to obtain temperature error data;
(2) Defining a corresponding multi-objective optimization function according to the power consumption error data and the temperature error data;
(3) Initializing an initial memory chip stacking and packaging scheme through a preset seeker optimization algorithm to obtain a plurality of candidate memory chip stacking and packaging schemes;
(4) Respectively calculating the selection probability value of each candidate memory chip stacking and packaging scheme through a multi-objective optimization function;
(5) According to the selection probability value, performing optimal solution selection of the current scheme on the multiple candidate storage chip stacking and packaging schemes to obtain the current optimal storage chip stacking and packaging scheme;
(6) And performing multi-objective optimization and iterative solution on the current optimal storage chip stacking and packaging scheme to obtain the objective storage chip stacking and packaging scheme.
Specifically, prediction error calculation is performed on target chip power consumption data and chip power consumption prediction data, and error calculation is performed on temperature data and temperature prediction data. The difference between the predicted and actual values is determined, and commonly used calculation methods include mean absolute error (Mean Absolute Error, MAE) or mean square error (Mean Squared Error, MSE). A multi-objective optimization function is defined that will be based on the power consumption error data and the temperature error data obtained as described above. In multi-objective optimization, the objective is to minimize both power consumption errors and temperature errors, while also taking into account other factors such as cost, size or weight. Defining a multi-objective optimization function typically involves setting weights and constraints to reflect the relative importance and feasibility between different objectives. For example, power consumption errors and temperature errors may be assigned different weights, balancing the optimization emphasis of both according to the specific requirements of the chip design. Initializing an initial memory chip stacking and packaging scheme through a preset seeker optimization algorithm to obtain a plurality of candidate memory chip stacking and packaging schemes. The seeker optimization algorithm is an optimization algorithm that mimics the process of a seeker of a missile or rocket searching for a target. In this algorithm, each candidate is like a seeker trying to find the optimal solution. For example, candidates for different stacking levels, different materials, or different thermal management strategies may be generated, each representing a packaging design. And respectively calculating the selection probability value of each candidate memory chip stacking packaging scheme through a multi-objective optimization function. The performance index of each candidate scheme, such as power consumption error and temperature error, is input into an optimization function to calculate the optimization degree and selection probability of each scheme. For example, a scheme with smaller power consumption errors and better temperature control will result in a higher probability of selection. And according to the selection probability values, performing optimal solution selection of the current scheme on the plurality of candidate storage chip stacking and packaging schemes, thereby obtaining the current optimal storage chip stacking and packaging scheme. One or more schemes with optimal performance are selected from all the candidate schemes for further analysis and verification. For example, if a certain scheme is excellent in both power consumption and temperature control, it may be selected as the currently optimal scheme. And performing multi-objective optimization and iterative solution on the current optimal storage chip stacking and packaging scheme to obtain the objective storage chip stacking and packaging scheme. This is an iterative process that continually adjusts and improves on the solution until the final optimal solution is found. In this process, the scheme can be verified and adjusted through simulation, experiment and data analysis, so that the effectiveness and feasibility of the scheme in practical application are ensured. For example, the temperature performance of the different stacking schemes may be tested by thermal simulation, or their power consumption performance may be evaluated by electrical testing.
The method for analyzing the energy consumption of the memory chip in the embodiment of the present application is described above, and the device for analyzing the energy consumption of the memory chip in the embodiment of the present application is described below, referring to fig. 2, one embodiment of the device for analyzing the energy consumption of the memory chip in the embodiment of the present application includes:
the test module 201 is configured to perform an energy consumption test on a target stacked memory chip based on a preset initial memory chip stacking packaging scheme, so as to obtain target chip power consumption data and target chip temperature data;
the decomposition module 202 is configured to perform data decomposition on the target chip power consumption data and the target chip temperature data through a preset fast integrated empirical model decomposition algorithm, so as to obtain a plurality of sub-power consumption data sets and a plurality of sub-temperature data sets;
the feature extraction module 203 is configured to perform feature extraction on the multiple sub-power consumption data sets through a preset first long-short-time memory network to obtain a power consumption fusion feature set, and perform feature extraction on the multiple sub-temperature data sets through a preset second long-short-time memory network to obtain a temperature fusion feature set;
the encoding module 204 is configured to perform vector encoding conversion on the power consumption fusion feature set and the temperature fusion feature set to obtain a target power consumption feature input vector and a target temperature feature input vector;
The prediction module 205 is configured to input the target power consumption feature input vector into a preset first twin support vector regression model to perform power consumption prediction to obtain chip power consumption prediction data, and input the target temperature feature input vector into a preset second twin support vector regression model to perform temperature prediction to obtain chip temperature prediction data;
and the optimizing module 206 is configured to calculate power consumption error data of the chip power consumption prediction data and temperature error data of the chip temperature prediction data, and perform multi-objective optimization on the initial storage chip stacking and packaging scheme according to the power consumption error data and the temperature error data, so as to obtain a target storage chip stacking and packaging scheme.
Through the cooperation of the components, multi-level data processing and feature extraction are adopted, and the method comprises the steps of fast integration of an experience model and a long-short-time memory network, so that the power consumption and temperature data of the memory chip can be predicted more accurately, and the prediction accuracy is improved. Using a multi-objective optimization technique, two key performance indicators of power consumption and temperature can be considered simultaneously to obtain an optimal memory chip stack packaging scheme. This helps to reduce the power consumption of the chip and improve the energy efficiency without sacrificing performance. By using a fast integrated empirical model decomposition algorithm and long and short term memory networks, useful characteristic information can be effectively extracted from raw power consumption and temperature data. This helps to predict power consumption and temperature more accurately, thereby optimizing the design. The feature set is converted into the vector and analyzed by using the feature ratio and the feature weight data, so that the comprehensive consideration of a plurality of features is facilitated, and the performance and the accuracy of the model are improved. The twin support vector regression model is adopted to predict the power consumption and the temperature, so that the method has higher prediction precision and robustness, and is beneficial to better controlling the power consumption and the temperature of the chip in the design process. The design process of the stacking and packaging scheme of the memory chip is automated, the requirement of manual intervention is reduced, and the design efficiency is improved. The method can comprehensively consider the parameters of the memory chips in different layers, including the parameters of the memory chips in the bottom layer, the middle layer and the top layer, so as to realize more comprehensive performance optimization, and adopts a machine learning technology to realize intelligent energy consumption analysis of the stacked memory chips, thereby improving the optimization accuracy of the stacked memory chip packaging scheme.
The application also provides an energy consumption analysis device of a memory chip, where the energy consumption analysis device of the memory chip includes a memory and a processor, and the memory stores computer readable instructions, where the computer readable instructions when executed by the processor cause the processor to execute the steps of the energy consumption analysis method of the memory chip in the foregoing embodiments.
The present application also provides a computer readable storage medium, which may be a non-volatile computer readable storage medium, or may be a volatile computer readable storage medium, where instructions are stored in the computer readable storage medium, where the instructions when executed on a computer cause the computer to perform the steps of the energy consumption analysis method of the storage chip.
It will be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, systems and units may refer to the corresponding processes in the foregoing method embodiments, which are not repeated herein.
The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a storage medium, including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a read-only memory (ROM), a random access memory (random acceS memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The above embodiments are merely for illustrating the technical solution of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the corresponding technical solutions.
Claims (7)
1. The energy consumption analysis method of the memory chip is characterized by comprising the following steps of:
performing energy consumption test on the target stacked memory chip based on a preset initial memory chip stacking and packaging scheme to obtain target chip power consumption data and target chip temperature data;
respectively carrying out data decomposition on the target chip power consumption data and the target chip temperature data through a preset fast integrated experience model decomposition algorithm to obtain a plurality of sub-power consumption data sets and a plurality of sub-temperature data sets; the method specifically comprises the following steps: respectively carrying out data decomposition on the target chip power consumption data and the target chip temperature data through a preset fast integrated experience model decomposition algorithm to obtain a plurality of first power consumption data sets and a plurality of first temperature data sets; respectively carrying out square sum error calculation on the plurality of first power consumption data sets to obtain first square sum error values of each first power consumption data set, and respectively carrying out square sum error calculation on the plurality of first temperature data sets to obtain second square sum error values of each first temperature data set; acquiring a first square sum error threshold of the power consumption data of the target chip, and comparing the first square sum error threshold with the first square sum error value respectively to obtain a plurality of first comparison results; meanwhile, a second square sum error threshold value of the target chip temperature data is obtained, and the second square sum error threshold value and the second square sum error value are respectively compared to obtain a plurality of second comparison results; performing data set screening on the plurality of first power consumption data sets according to the plurality of first comparison results to obtain a plurality of second power consumption data sets, and performing data set screening on the plurality of first temperature data sets according to the plurality of second comparison results to obtain a plurality of second temperature data sets; respectively carrying out data set reconstruction on the plurality of second power consumption data sets and the plurality of second temperature data sets to obtain a plurality of sub-power consumption data sets and a plurality of sub-temperature data sets;
Extracting features of the plurality of sub-power consumption data sets through a preset first long-short time memory network to obtain a power consumption fusion feature set, and extracting features of the plurality of sub-temperature data sets through a preset second long-short time memory network to obtain a temperature fusion feature set;
vector coding conversion is carried out on the power consumption fusion feature set and the temperature fusion feature set, so that a target power consumption feature input vector and a target temperature feature input vector are obtained;
inputting the target power consumption characteristic input vector into a preset first twin support vector regression model to conduct power consumption prediction to obtain chip power consumption prediction data, and inputting the target temperature characteristic input vector into a preset second twin support vector regression model to conduct temperature prediction to obtain chip temperature prediction data; the method specifically comprises the following steps: inputting the target power consumption characteristic input vector into a preset first twin support vector regression model, and carrying out characteristic mapping on the target power consumption characteristic input vector through a first kernel function in the first twin support vector regression model to obtain a target power consumption characteristic mapping vector; carrying out regression analysis and power consumption prediction on the target power consumption characteristic mapping vector through a first prediction function in the first twin support vector regression model to obtain chip power consumption prediction data; inputting the target temperature characteristic input vector into a preset second twin support vector regression model, and carrying out characteristic mapping on the target temperature characteristic input vector through a second kernel function in the second twin support vector regression model to obtain a target temperature characteristic mapping vector; carrying out regression analysis and temperature prediction on the target temperature characteristic mapping vector through a second prediction function in the second twin support vector regression model to obtain chip temperature prediction data;
Calculating power consumption error data of the chip power consumption prediction data and temperature error data of the chip temperature prediction data, and performing multi-objective optimization on the initial storage chip stacking and packaging scheme according to the power consumption error data and the temperature error data to obtain a target storage chip stacking and packaging scheme; the method specifically comprises the following steps: performing prediction error calculation on the target chip power consumption data and the chip power consumption prediction data to obtain power consumption error data, and performing prediction error calculation on the target chip temperature data and the chip temperature prediction data to obtain temperature error data; defining a corresponding multi-objective optimization function according to the power consumption error data and the temperature error data; initializing the initial memory chip stacking and packaging scheme through a preset seeker optimization algorithm to obtain a plurality of candidate memory chip stacking and packaging schemes; calculating the selection probability value of each candidate storage chip stacking and packaging scheme through the multi-objective optimization function respectively; according to the selection probability value, performing optimal solution selection of the current scheme on the multiple candidate storage chip stacking and packaging schemes to obtain the current optimal storage chip stacking and packaging scheme; and performing multi-objective optimization and iterative solution on the current optimal storage chip stacking and packaging scheme to obtain the objective storage chip stacking and packaging scheme.
2. The method for analyzing energy consumption of a memory chip according to claim 1, wherein the performing energy consumption test on the target stacked memory chip based on a preset initial memory chip stacking and packaging scheme to obtain target chip power consumption data and target chip temperature data includes:
acquiring bottom layer memory chip parameters, middle layer memory chip parameters and top layer memory chip parameters of a target stacked memory chip;
initializing a stacking and packaging scheme of the target stacked memory chip according to the bottom layer memory chip parameters, the middle layer memory chip parameters and the top layer memory chip parameters to obtain an initial memory chip stacking and packaging scheme;
performing energy consumption test on the target stacked memory chip according to the initial memory chip stacking and packaging scheme, and collecting first chip power consumption data and first chip temperature data of the target stacked memory chip;
respectively carrying out outlier removal and outlier interpolation on the first chip power consumption data and the first chip temperature data to obtain second chip energy consumption data and second chip temperature data;
and respectively carrying out data standardization processing on the second chip energy consumption data and the second chip temperature data to obtain target chip power consumption data and target chip temperature data.
3. The method for analyzing energy consumption of a memory chip according to claim 1, wherein the performing feature extraction on the plurality of sub-power consumption data sets through a preset first long-short time memory network to obtain a power consumption fusion feature set, and performing feature extraction on the plurality of sub-temperature data sets through a preset second long-short time memory network to obtain a temperature fusion feature set, includes:
respectively extracting the characteristics of the plurality of sub-power consumption data sets through a preset first long-short time memory network to obtain the target power consumption characteristics of each sub-power consumption data set;
performing feature fusion on the target power consumption features of each sub-power consumption data set to obtain a power consumption fusion feature set;
respectively extracting the characteristics of the plurality of sub-temperature data sets through a preset second long-short-time memory network to obtain target temperature characteristics of each sub-temperature data set;
performing feature fusion on the target temperature features of each sub-temperature dataset to obtain a temperature fusion feature set;
the first long-time memory network is the same as the second long-time memory network, and the first long-time memory network comprises:
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Loss；
indicating hidden status- >Representing the state of the cell->Representing the parameters of the weight of the network,representing network bias parameters, +.>Representing an activation function->Representing sigmoid function->The tanh function is represented by a table,indicated at the time +.>Is->Indicated at the time +.>Is expressed as Loss function value, < ->Representing Hadamard Ma Chengji, ">Representing a Unit update function, & lt + & gt>Representing an input door->Indicates the output door, ++>Representing the actual value at time t.
4. The method for analyzing energy consumption of a memory chip according to claim 1, wherein performing vector code conversion on the power consumption fusion feature set and the temperature fusion feature set to obtain a target power consumption feature input vector and a target temperature feature input vector comprises:
performing feature mean value calculation on the power consumption fusion feature set to obtain a power consumption feature mean value, and performing feature standard deviation calculation on the power consumption fusion feature set to obtain a power consumption feature standard deviation;
calculating a characteristic mean value of the temperature fusion characteristic set to obtain a temperature characteristic mean value, and calculating a characteristic standard deviation of the temperature fusion characteristic set to obtain a temperature characteristic standard deviation;
calculating the ratio of the power consumption characteristic mean value to the power consumption characteristic standard deviation to obtain a power consumption characteristic ratio, and calculating the ratio of the temperature characteristic mean value to the temperature characteristic standard deviation to obtain a temperature characteristic ratio;
Calculating feature weight data corresponding to the power consumption fusion feature set and the temperature fusion feature set according to the power consumption feature ratio and the temperature feature ratio;
vector code conversion is carried out on the power consumption fusion feature set to obtain a power consumption fusion feature vector, and vector code conversion is carried out on the temperature fusion feature set to obtain a temperature fusion feature vector;
and respectively carrying out weighted analysis on the power consumption fusion feature vector and the temperature fusion feature vector according to the feature weight data to obtain a target power consumption feature input vector and a target temperature feature input vector.
5. An energy consumption analysis device of a memory chip, characterized in that the energy consumption analysis device of the memory chip comprises:
the testing module is used for carrying out energy consumption testing on the target stacked memory chip based on a preset initial memory chip stacking and packaging scheme to obtain target chip power consumption data and target chip temperature data;
the decomposition module is used for respectively carrying out data decomposition on the power consumption data of the target chip and the temperature data of the target chip through a preset rapid integrated experience model decomposition algorithm to obtain a plurality of sub-power consumption data sets and a plurality of sub-temperature data sets; the method specifically comprises the following steps: respectively carrying out data decomposition on the target chip power consumption data and the target chip temperature data through a preset fast integrated experience model decomposition algorithm to obtain a plurality of first power consumption data sets and a plurality of first temperature data sets; respectively carrying out square sum error calculation on the plurality of first power consumption data sets to obtain first square sum error values of each first power consumption data set, and respectively carrying out square sum error calculation on the plurality of first temperature data sets to obtain second square sum error values of each first temperature data set; acquiring a first square sum error threshold of the power consumption data of the target chip, and comparing the first square sum error threshold with the first square sum error value respectively to obtain a plurality of first comparison results; meanwhile, a second square sum error threshold value of the target chip temperature data is obtained, and the second square sum error threshold value and the second square sum error value are respectively compared to obtain a plurality of second comparison results; performing data set screening on the plurality of first power consumption data sets according to the plurality of first comparison results to obtain a plurality of second power consumption data sets, and performing data set screening on the plurality of first temperature data sets according to the plurality of second comparison results to obtain a plurality of second temperature data sets; respectively carrying out data set reconstruction on the plurality of second power consumption data sets and the plurality of second temperature data sets to obtain a plurality of sub-power consumption data sets and a plurality of sub-temperature data sets;
The characteristic extraction module is used for extracting the characteristics of the plurality of sub-power consumption data sets through a preset first long-short-time memory network to obtain a power consumption fusion characteristic set, and extracting the characteristics of the plurality of sub-temperature data sets through a preset second long-short-time memory network to obtain a temperature fusion characteristic set;
the encoding module is used for carrying out vector encoding conversion on the power consumption fusion feature set and the temperature fusion feature set to obtain a target power consumption feature input vector and a target temperature feature input vector;
the prediction module is used for inputting the target power consumption characteristic input vector into a preset first twin support vector regression model to conduct power consumption prediction to obtain chip power consumption prediction data, and inputting the target temperature characteristic input vector into a preset second twin support vector regression model to conduct temperature prediction to obtain chip temperature prediction data; the method specifically comprises the following steps: inputting the target power consumption characteristic input vector into a preset first twin support vector regression model, and carrying out characteristic mapping on the target power consumption characteristic input vector through a first kernel function in the first twin support vector regression model to obtain a target power consumption characteristic mapping vector; carrying out regression analysis and power consumption prediction on the target power consumption characteristic mapping vector through a first prediction function in the first twin support vector regression model to obtain chip power consumption prediction data; inputting the target temperature characteristic input vector into a preset second twin support vector regression model, and carrying out characteristic mapping on the target temperature characteristic input vector through a second kernel function in the second twin support vector regression model to obtain a target temperature characteristic mapping vector; carrying out regression analysis and temperature prediction on the target temperature characteristic mapping vector through a second prediction function in the second twin support vector regression model to obtain chip temperature prediction data;
The optimizing module is used for calculating power consumption error data of the chip power consumption prediction data and temperature error data of the chip temperature prediction data, and performing multi-objective optimization on the initial storage chip stacking and packaging scheme according to the power consumption error data and the temperature error data to obtain a target storage chip stacking and packaging scheme; the method specifically comprises the following steps: performing prediction error calculation on the target chip power consumption data and the chip power consumption prediction data to obtain power consumption error data, and performing prediction error calculation on the target chip temperature data and the chip temperature prediction data to obtain temperature error data; defining a corresponding multi-objective optimization function according to the power consumption error data and the temperature error data; initializing the initial memory chip stacking and packaging scheme through a preset seeker optimization algorithm to obtain a plurality of candidate memory chip stacking and packaging schemes; calculating the selection probability value of each candidate storage chip stacking and packaging scheme through the multi-objective optimization function respectively; according to the selection probability value, performing optimal solution selection of the current scheme on the multiple candidate storage chip stacking and packaging schemes to obtain the current optimal storage chip stacking and packaging scheme; and performing multi-objective optimization and iterative solution on the current optimal storage chip stacking and packaging scheme to obtain the objective storage chip stacking and packaging scheme.
6. An energy consumption analysis apparatus of a memory chip, characterized in that the energy consumption analysis apparatus of a memory chip comprises: a memory and at least one processor, the memory having instructions stored therein;
the at least one processor invokes the instructions in the memory to cause the energy consumption analysis device of the memory chip to perform the energy consumption analysis method of the memory chip of any one of claims 1-4.
7. A computer readable storage medium having instructions stored thereon, which when executed by a processor, implement the energy consumption analysis method of a memory chip according to any of claims 1-4.
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