CN117555827A - Data transmission method, device, system, chip and storage medium - Google Patents

Data transmission method, device, system, chip and storage medium Download PDF

Info

Publication number
CN117555827A
CN117555827A CN202311448690.2A CN202311448690A CN117555827A CN 117555827 A CN117555827 A CN 117555827A CN 202311448690 A CN202311448690 A CN 202311448690A CN 117555827 A CN117555827 A CN 117555827A
Authority
CN
China
Prior art keywords
data
bandwidth
module
source
strategy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202311448690.2A
Other languages
Chinese (zh)
Inventor
周晶晶
沈阳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Calterah Semiconductor Technology Shanghai Co Ltd
Original Assignee
Calterah Semiconductor Technology Shanghai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Calterah Semiconductor Technology Shanghai Co Ltd filed Critical Calterah Semiconductor Technology Shanghai Co Ltd
Priority to CN202311448690.2A priority Critical patent/CN117555827A/en
Publication of CN117555827A publication Critical patent/CN117555827A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/781—On-chip cache; Off-chip memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computing Systems (AREA)
  • Communication Control (AREA)

Abstract

Disclosed herein are a data transmission method, apparatus, system, chip and storage medium. The method comprises the following steps: generating bandwidth according to the data of the source data and data output bandwidth of the data sending module, and determining a bandwidth matching strategy; after corresponding operation is executed according to the bandwidth matching strategy, data is sent through the data sending module; wherein the bandwidth matching policy comprises: a source data interpolation strategy and/or a data transmission module clock frequency division strategy. According to the data transmission scheme provided by the embodiment of the disclosure, under the condition that the data generation rate of the on-chip data source and the data output rate of the chip sending port are not matched, a large on-chip buffer space does not need to be correspondingly configured, the bandwidth matching of data generation and data sending is dynamically completed, and under the condition that the reliability and the instantaneity of data transmission are ensured, the hardware design complexity of the SoC is simplified, the on-chip memory space requirement is reduced, and the chip cost of the SoC is reduced.

Description

Data transmission method, device, system, chip and storage medium
Technical Field
The present disclosure relates to the field of chip technologies, and in particular, to a data transmission method, device, system, chip, and storage medium.
Background
Along with the continuous expansion of the application field of the SoC (System on Chip), various requirements for data acquisition and processing by adopting integrated data sources in the SoC are also continuously proposed. Because of the capacity limitation of the buffer space SRAM (Static Random-Access Memory) inside the SoC, the data to be processed cannot be placed in the SRAM inside, and the data to be processed often needs to be transmitted to an external data acquisition module, and then the external data acquisition module receives, buffers and transmits the data to an upper computer for further processing. However, if the data rate of the SoC on-chip data source is not matched with the data rate sent by the chip port, to ensure that the data is not lost, it is often necessary to buffer the data generated by the SoC on-chip data source first, and then send the data in the buffer out of the chip.
Therefore, with the increasing of the data collection amount, the buffer memory space in the SoC chip to be correspondingly configured is also required to be increased, and huge pressure is caused on the hardware cost, the circuit complexity and the chip area of the SoC.
Disclosure of Invention
The application provides a data transmission method, a device, a system, a chip and a storage medium, which are applied to an SoC, and can dynamically complete bandwidth matching of data generation and data transmission without correspondingly configuring a larger on-chip buffer space under the condition that the data generation rate of an on-chip data source and the data output rate of a chip transmission port are not matched, so that the hardware design complexity of the SoC is simplified, the on-chip memory space requirement is reduced, and the chip cost of the SoC is reduced under the condition that the data transmission reliability and instantaneity are ensured.
The embodiment of the disclosure provides a data transmission method, which comprises the following steps:
generating bandwidth according to the data of the source data and data output bandwidth of the data sending module, and determining a bandwidth matching strategy;
after corresponding operation is executed according to the bandwidth matching strategy, data is sent through the data sending module;
wherein the bandwidth matching policy comprises:
a source data interpolation strategy and/or a data transmission module clock frequency division strategy.
The embodiment of the disclosure also provides a data transmission device, which comprises:
the matching strategy determining module is used for determining a bandwidth matching strategy according to the data generation bandwidth of the source data and the data output bandwidth of the data sending module;
the sending module is used for sending data through the data sending module after corresponding operation is executed according to the bandwidth matching strategy;
wherein the bandwidth matching policy comprises:
a source data interpolation strategy and/or a data transmission module clock frequency division strategy.
The disclosed embodiments also provide a system on a chip, comprising:
the system comprises a data generation module, a data transmission module and an interpolation module;
the data generation module is used for generating source data;
the interpolation module is configured to generate data to be transmitted based on the source data according to a source data interpolation strategy included in a bandwidth matching strategy;
The data transmitting module is configured to transmit the source data or the data to be transmitted; or setting a clock frequency division strategy of a data transmission module included according to the bandwidth matching strategy, and transmitting the source data or the data to be transmitted at the clock frequency after frequency division;
wherein the bandwidth matching strategy determines according to the data generation bandwidth of the source data and the data output bandwidth of the data transmission module
The disclosed embodiments also provide a chip comprising a processor configured to implement the data transmission method according to any of the disclosed embodiments.
The disclosed embodiments also provide a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements a data transmission method according to any of the embodiments of the disclosure.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. Other advantages of the present application may be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
The accompanying drawings are included to provide an understanding of the technical aspects of the present application, and are incorporated in and constitute a part of this specification, illustrate the technical aspects of the present application and together with the examples of the present application, and not constitute a limitation of the technical aspects of the present application.
Fig. 1 is a flowchart of a data transmission method provided in an embodiment of the present application;
fig. 2 is a flowchart of another data transmission method according to an embodiment of the present application;
fig. 3 is a frame diagram of a data transmission device according to an embodiment of the present application;
FIG. 4 is a system-on-chip frame diagram provided in an embodiment of the present application;
fig. 5 is a diagram of another system-on-chip framework provided in an embodiment of the present application.
Detailed Description
The present application describes a number of embodiments, but the description is illustrative and not limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or in place of any other feature or element of any other embodiment unless specifically limited.
The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements of the present disclosure may also be combined with any conventional features or elements to form a unique inventive arrangement as defined in the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive arrangements to form another unique inventive arrangement as defined in the claims. Thus, it should be understood that any of the features shown and/or discussed in this application may be implemented alone or in any suitable combination. Accordingly, the embodiments are not to be restricted except in light of the attached claims and their equivalents. Further, various modifications and changes may be made within the scope of the appended claims.
Furthermore, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other sequences of steps are possible as will be appreciated by those of ordinary skill in the art. Accordingly, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Furthermore, the claims directed to the method and/or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present application.
Aiming at the situation that the data rate generated by the on-chip data generating module is not matched with the data rate transmitted by the chip data transmitting module, in order to avoid the data loss generated in the chip, in some possible SoC schemes, the data generated by an on-chip data source is completely cached by adopting a Block Memory (Block Memory), then the cached data is packaged and processed, and finally the data is transmitted out of the chip through a chip transmitting port. The use of a large amount of block memories in the SoC chip not only causes the increase of the hardware cost of the SoC chip, but also obviously increases the area of the SoC chip and the complexity of the hardware.
An embodiment of the present disclosure provides a data transmission method, as shown in fig. 1, including:
step 110, bandwidth matching strategies are determined according to the data generation bandwidth of the source data and the data output bandwidth of the data transmission module;
step 120, after executing the corresponding operation according to the bandwidth matching policy, transmitting data through the data transmitting module;
wherein the bandwidth matching policy comprises: a source data interpolation strategy and/or a data transmission module clock frequency division strategy.
It should be noted that, the data transmission scheme provided by the embodiments of the present disclosure is not limited to a specific type of source data, and is not limited to a specific transmission mode. The source data is the data which needs to be sent out of the chip. Under the condition that the data generation bandwidth and the data output bandwidth of the source data are determined, bandwidth matching can be performed by adopting the aspects provided by the embodiment of the disclosure, so that the requirement on a large-capacity on-chip memory and transmission delay caused by buffering caused by a large amount of buffering of data to be transmitted are avoided. The generation bandwidth of the source data can be known in advance according to the data generation scheme and configuration parameters of the on-chip data source; the data output bandwidth of the data transmission module, the maximum data transmission bandwidth of the data transmission module, may also be known in advance according to the type of the specific transmission module.
In the case of determining the data generation bandwidth and the data output bandwidth, the bandwidth matching policy determined in step 110 is determined accordingly, and in the case where the data generation bandwidth and/or the data output bandwidth are changed and are known, specific aspects of the bandwidth matching policy may be changed correspondingly, and are not limited to specific aspects.
In some exemplary embodiments, taking the application of the data transmission method to a system on a chip SoC as an example, the SoC includes an on-chip data source, also referred to as a local data source, and generates/generates source data, where the corresponding bandwidth is referred to as a data generation bandwidth of the source data, and further includes a sending module with an LVDS (Low Voltage Differential Signal, low voltage differential signaling) interface, and sends the generated source data to an off-chip system or device using one or more LVDS channels (chanels). For example, the radar sensor in the chip is used as a data source to generate source data, namely radar signal sampling data, and the data generation bandwidth is the bandwidth for generating sampling data; the data output bandwidth is the bandwidth of sampling data output through one or more LVDS channels.
In some exemplary embodiments, in the single data rate SDR mode, the data output bandwidth of the data transmission module=the clock frequency F of the data transmission module×the number of transmission channels ChanelNum of the data transmission module.
In some exemplary embodiments, in the double data rate DDR mode, the data output bandwidth of the data transmission module=2×the clock frequency of the data transmission module×the number of transmission channels ChanelNum of the data transmission module.
In some exemplary embodiments, the number of transmit channels is preconfigured to a fixed number.
In some exemplary embodiments, in the case of a SoC hardware scheme, the clock frequency of the data sending module is a fixed reference clock frequency, and is also referred to as a clock frequency before frequency division compared to the clock frequency obtained after frequency division in the embodiments of the present disclosure. And frequency division is carried out according to different frequency division parameters, and the obtained frequency-divided clock frequencies are different. The specific frequency division scheme is not discussed in detail in the embodiments of the present application. It will be appreciated that in the case of a fixed transmit mode (SDR/DDR), a fixed number of transmit channels, and a fixed reference clock frequency, the data output bandwidth of the transmit module is also fixed.
In some exemplary embodiments, the determining the bandwidth matching policy according to the data generating bandwidth of the source data and the data output bandwidth of the data sending module includes at least one of:
at BW send ＝n×BW gen In the case of (2), the bandwidth matching policy includes a data transmission module clock frequency division policy;
At 2 XBW gen >BW send >BW gen The bandwidth matching policy includes a source data interpolation policy;
at BW send ≠n×BW gen And BW is send >2×BW gen Case(s)The bandwidth matching strategy comprises a data sending module clock frequency division strategy and a source data interpolation strategy;
wherein BW is send For the data output bandwidth, BW gen Generating a bandwidth for the data, n being an integer greater than 1.
It can be seen that in the disclosed embodiments, the data output bandwidth is greater than the data generation bandwidth.
In some exemplary embodiments, in a case where the bandwidth matching policy includes a data transmission module clock frequency division policy, after performing a corresponding operation according to the bandwidth matching policy, transmitting data by the data transmission module includes:
frequency division processing is carried out on the clock frequency of the data transmission module, so that F' =F/n; wherein F' is the clock frequency after frequency division, and F is the clock frequency before frequency division;
and transmitting the source data through the data transmitting module according to the frequency-divided clock frequency F'.
It can be seen that BW send ＝n×BW gen The data output bandwidth of the data sending module is an integer multiple (n is greater than 1) of the data generating bandwidth in the chip, at this time, the bandwidth matching strategy includes a clock frequency division strategy of the data sending module, according to the strategy, the frequency division processing is performed on the reference clock of the data sending module, and the actual data sending frequency is reduced, so that the bandwidth matching of the generated data stream and the sent data stream can be realized. n is the frequency division parameter=bw send /BW gen . That is, the frequency division processing is performed on the reference clock of the transmitting module according to the proportional relationship between the data output bandwidth and the data generation bandwidth.
For example, soC has a reference clock frequency of F, and on-chip source data generates bandwidth BW gen The LVDS port of the data transmission module comprises 4 channels for 320Mbps, and the corresponding data output bandwidth BW send When 1600 mbps=5×320Mbps and n=5, the clock frequency of the data transmitting module is subjected to frequency division processing to make F '=f/5, and it can be seen that the frequency-divided clock frequency F' is 1/5 of the SoC reference clock frequency, and 4 channels are continuously adoptedThe channel performs data transmission, the actual data transmission bandwidth is changed from 1600Mbps to 320Mbps, and the matching with the data generation bandwidth is realized.
In some exemplary embodiments, in a case where the bandwidth matching policy includes a source data interpolation policy, after performing a corresponding operation according to the bandwidth matching policy, transmitting data through the data transmitting module includes:
periodically inserting setting data into the source data to obtain data to be transmitted;
transmitting the data to be transmitted through the data transmitting module;
wherein the generation bandwidth of the data to be transmitted=the data output bandwidth.
In some exemplary embodiments, the periodically inserting the setting data into the source data to obtain the data to be sent includes:
in each period, setting data are inserted according to the following proportion to obtain the data to be transmitted:
source data unit number: (number of source data units+number of set data units) =the data generation bandwidth BW gen The data output bandwidth BW send 。
The data unit means a unit for calculating the data amount, and the number of data units means how many data units are. For example, the data unit is a byte, and the number of data units is 5, representing 5 bytes. Accordingly, the number of source data units indicates how many data units the source data corresponds to, for example, the number of source data units is 10, indicating that the source data corresponds to 10 bytes; the set data unit number indicates that the inserted set data includes a plurality of data units, for example, the set data unit number is 2, and indicates that 2 bytes of set data are inserted.
In some exemplary embodiments, the setting data includes one or more of:
verification information corresponding to the source data, a data source identity and configuration data.
Wherein, the verification information includes: odd/even parity information, CRC (Cyclic Redundancy Check ) information, and the like, are not limited in particular respects.
It will be appreciated that in some example embodiments, the inserted setting data is determined based on the source data or data source, and the specific manner of determination is not limited in this respect and may include multiple types of data. And correspondingly deleting the inserted data by the data receiver outside the chip according to the pre-known insertion condition, so as to obtain the source data. In the case of including the verification information, the corresponding verification is sufficient, and more detailed aspects will not be discussed in detail in this embodiment.
In some exemplary embodiments, the inserted configuration data is preconfigured in firmware or a configuration file of the system-on-chip, the data selection does not conflict with the source data, and the data that can be clearly identified by the off-chip data receiver is not limited in specific aspects. For example, the data unit is a byte, the setting data is one-byte configuration data FF, and the unit number of the setting data determined according to the above insertion method is 2, which indicates that the setting data FFFF of 2 bytes is inserted; the unit number of the determined setting data is 1, which indicates that 1 byte of the setting data FF is inserted; the number of units of the set data determined is 5, which means that 5 bytes of set data FFFFFFFFFF are inserted.
It can be seen that 2 XBW gen >BW send >BW gen In the case where the data output bandwidth representing the data transmission module is not an integer multiple of the on-chip data generation bandwidth, is greater than 1 multiple but less than 2 times the data generation bandwidth, the bandwidth matching policy includes a source data interpolation policy according to which source data is interpolated, which corresponds to generating new data to be transmitted such that the generation bandwidth of the new data to be transmitted is equal to the data output bandwidth of the transmission module, i.e., the generation bandwidth is BW gen Interpolation is carried out on source data to obtain a generated bandwidth BW send New data to be transmitted; and then, the transmission module packs and transmits the new data to be transmitted obtained after interpolation according to the corresponding transmission data specification.
For example, soC has a reference clock frequency of F, and on-chip source data generates bandwidth BW gen The LVDS port of the data transmission module comprises 4 channels for 320Mbps, and the corresponding data output bandwidth BW send For 400Mbps, the data generates bandwidth: the data output bandwidth=320:400=4:5, namely, the data generation bandwidth of the data source is 4/5 of the data output bandwidth of the data sending module, the source data is interpolated periodically according to a source data interpolation strategy, and every 4 data units of the source data are inserted into 1 data unit of the set data; alternatively, 2 data units of setting data are inserted every 8 data units of source data; alternatively, data units of 3 setting data are inserted every 12 data units of source data, and so on. At this time, the data transmission module keeps the reference clock frequency F to perform data transmission using 4 channels, and the actual data transmission bandwidth is 400Mbps, except that the effective bandwidth of the source data included therein is 320Mbps. It can be seen that although redundant setting data is sent at this time, the source data is not affected, and the matching with the output bandwidth of the sending module can be realized according to the generation speed of the source data, so that the source data is sent to the off-chip system in real time without using a large on-chip cache memory.
The insertion position of the setting data may be configured in advance, and is not limited to a specific aspect. The data transmitting end and the data receiving end are pre-configured.
In some exemplary embodiments, in a case where the bandwidth matching policy includes a data transmission module clock frequency division policy and a source data interpolation policy, after performing a corresponding operation according to the bandwidth matching policy, transmitting data through the data transmission module includes:
periodically inserting setting data into the source data to obtain data to be transmitted;
frequency division processing is carried out on the clock frequency of the data transmission module, so that F' =F/m; wherein F' is the clock frequency after frequency division, and F is the clock frequency before frequency division;
according to the frequency-divided clock frequency F', the data to be transmitted are transmitted through the data transmitting module;
wherein BW' gen ＝BW send /m, and 2 XBW gen >BW′ gen >BW gen ；
BW′ gen And generating bandwidth for the data to be transmitted, wherein m is an integer greater than 1.
It can be seen that BW send ≠n×BW gen And BW is send >2×BW gen The method comprises the steps that under the condition that the data output bandwidth of a data sending module is not an integral multiple of the data generating bandwidth in a chip and is more than 2 times of the data generating bandwidth, the bandwidth matching strategy comprises a clock frequency division strategy of the data sending module and a source data interpolation strategy, interpolation is needed to be carried out on source data according to the two strategies, and frequency division processing is carried out on a reference clock of the data sending module; interpolation is carried out on the source data, which is equivalent to generating new data to be transmitted, frequency division processing is carried out on a reference clock of a transmitting module, the actual data transmitting frequency is reduced, and bandwidth matching of the generated data stream of the new data to be transmitted and the transmitting data stream of the data transmitting module can be realized through the two steps of processing. In this case, after the reference clock F of the data transmission module is divided according to the frequency division parameter m, the frequency-divided clock frequency F ' is obtained, so that the actual data transmission bandwidth corresponding to the data transmission is matched with the generation bandwidth of the new data to be transmitted, that is, the actual data transmission bandwidth corresponding to the data transmission=the generation bandwidth BW ' of the data to be transmitted is performed at the frequency-divided clock frequency F ' gen 。
Wherein, the bandwidth is BW for the generation gen Interpolation is carried out on source data to obtain a generated bandwidth BW' gen New data to be transmitted, and pair generating bandwidth BW gen Interpolation is carried out on source data to obtain a generated bandwidth BW send The specific mode of the new data to be transmitted is the same, including:
and periodically inserting the setting data into the source data to obtain data to be transmitted.
In some exemplary embodiments, the periodically inserting the setting data into the source data to obtain the data to be sent includes:
in each period, setting data are inserted according to the following proportion to obtain the data to be transmitted:
source data unit number: (number of source data units+number of set data units) =the data generation bandwidth BW gen Generating bandwidth BW 'of the data to be transmitted' gen 。
For example, soC has a reference clock frequency of F, and on-chip source data generates bandwidth BW gen The LVDS port of the data transmission module comprises 4 channels for 320Mbps, and the corresponding data output bandwidth BW send BW 'was determined at 2000Mbps in the range of greater than 320Mbps and less than 640 Mbps' gen =400 Mbps, so that BW send BW 'for' gen And integer multiples. It can be seen that BW' gen Satisfy 2 XBW gen >BW′ gen >BW gen And BW' gen ＝BW send The/m case includes one or more, e.g., m=4, bw' gen =2000/4=500 Mbps, or, m=5, bw' gen =2000/5=400 Mbps. One of them may be selected, and is not limited to a specific aspect. The larger m is, the smaller the amount of setting data inserted is.
For example, at this time, m=5, the clock frequency of the data transmission module is subjected to frequency division processing, so that F '=f/5, and it can be seen that the frequency-divided clock frequency F' is 1/5 of the SoC reference clock frequency, and data transmission is continued by using 4 channels, the actual data transmission bandwidth 2000Mbps becomes 400Mbps, and at this time, the generation bandwidth BW 'of the data to be transmitted newly generated after interpolation is required' gen =400 Mbps, the data generates a bandwidth BW gen : the generation bandwidth BW 'of the data to be transmitted' gen The data generation bandwidth of the data source is 4/5 of the generation bandwidth of the new data to be transmitted, the source data is periodically interpolated according to the source data interpolation strategy, 1 data unit of the set data is inserted into every 4 data units of the source data (or 2 data units of the set data are inserted into every 8 data units of the source data, or 3 data units of the set data are inserted into every 12 data units of the source data, etc.), the data transmission module performs data transmission by adopting the clock frequency F' after frequency division and still adopting 4 channels, the actual data transmission bandwidth is 400Mbps, and the data transmission is realized The new data to be transmitted generates a match of bandwidths.
In the case where m=4, the specific aspect of interpolation of setting data is not described in detail here, and can be estimated from the above example.
It can be appreciated that in BW send ≠n×BW gen And BW is send >2×BW gen In the case, firstly, the bandwidth of the output port is adjusted to a range by a reference clock frequency division method, namely, the bandwidth is adjusted to a range which is larger than the data generation bandwidth of the on-chip data source and smaller than twice the data generation bandwidth of the on-chip data source; and then, the generation bandwidth of the data to be transmitted is consistent with the actual transmission bandwidth of the transmission module by periodically inserting the setting data.
According to the data transmission scheme provided by the embodiment of the disclosure, the SoC realizes the matching of the data generation bandwidth and the transmission bandwidth by configuring the frequency division and/or the periodic data insertion of the reference clock of the data transmission module. Therefore, the processing of the data can be completed in a packed and transmitted mode without a large amount of buffer processing in the chip, the reliability of the external transmission of the source data is ensured, the area and the cost of a hardware circuit are reduced, and the processing complexity of SoC software is simplified.
The embodiment of the disclosure also provides a data transmission method applied to a system on chip SoC, including:
Acquiring source data generated by an on-chip data source;
generating data to be transmitted based on the source data according to a source data interpolation strategy included in a bandwidth matching strategy;
according to a clock frequency division strategy of a data transmission module included in the bandwidth matching strategy, transmitting the data to be transmitted at the clock frequency after frequency division;
and the bandwidth matching strategy is used for determining the bandwidth according to the data generation bandwidth of the source data and the data output bandwidth of the data transmission module.
In some exemplary embodiments, the data output bandwidth is greater than the data generation bandwidth.
The embodiment of the disclosure also provides a data transmission method applied to a system on chip SoC, as shown in fig. 2, including:
step 210, acquiring source data generated by an on-chip data source;
step 220, performing interpolation processing based on the source data according to the setting data to generate data to be transmitted;
step 230, according to the set frequency dividing parameter, transmitting the data to be transmitted at the frequency-divided clock frequency;
the frequency division parameters are determined according to the data generation bandwidth of the source data and the data output bandwidth of the data transmission module; the clock frequency before frequency division is the reference clock frequency of the data transmission module in the system on chip.
In some exemplary embodiments, the data output bandwidth is greater than the data generation bandwidth.
In some exemplary embodiments, in the case where the setting data is empty, the data to be transmitted is the same as the source data, i.e., no interpolation processing is performed.
In some exemplary embodiments, in the case where the frequency division parameter is not an integer greater than 1, the frequency division process is not performed, that is, the data to be transmitted is transmitted at the reference clock frequency.
The embodiment of the disclosure further provides a data transmission device, as shown in fig. 3, including:
a matching policy determining module 310 configured to determine a bandwidth matching policy according to the data generation bandwidth of the source data and the data output bandwidth of the data transmitting module;
the sending module 320 is configured to send data through the data sending module after performing a corresponding operation according to the bandwidth matching policy;
wherein the bandwidth matching policy comprises:
a source data interpolation strategy and/or a data transmission module clock frequency division strategy;
in some exemplary embodiments, the data output bandwidth is greater than the data generation bandwidth.
In some exemplary embodiments, the matching policy determination module 310 is configured to,
at BW send ＝n×BW gen In the case of (2), the bandwidth matching policy includes a data transmission module clock frequency division policy;
At 2 XBW gen >BW send >BW gen The bandwidth matching policy includes a source data interpolation policy;
at BW send ≠n×BW gen And BW is send >2×BW gen Under the condition, the bandwidth matching strategy comprises a data sending module clock frequency division strategy and a source data interpolation strategy;
wherein BW is send For the data output bandwidth, BW gen Generating a bandwidth for the data, n being an integer greater than 1.
In some exemplary embodiments, in a case where the bandwidth matching policy includes a data transmission module clock frequency division policy, the transmission module 320 is configured to perform frequency division processing on a clock frequency of the data transmission module, so that F' =f/n; wherein F' is the clock frequency after frequency division, and F is the clock frequency before frequency division; and transmitting the source data through the data transmitting module according to the frequency-divided clock frequency F'.
In some exemplary embodiments, in the case that the bandwidth matching policy includes a source data interpolation policy, the sending module 320 is configured to periodically insert setting data into the source data to obtain data to be sent; transmitting the data to be transmitted through the data transmitting module;
wherein the generation bandwidth of the data to be transmitted=the data output bandwidth.
In some exemplary embodiments, the sending module 320 periodically inserts setting data into source data to obtain data to be sent, including:
In each period, setting data are inserted according to the following proportion to obtain the data to be transmitted:
source data unit number: (source data unit number+set data unit number) =the data generation bandwidth: the data output bandwidth.
In some exemplary embodiments, where the bandwidth matching policy includes a data transmission module clock divide policy and a source data interpolation policy, the transmission module 320 is configured to,
periodically inserting setting data into the source data to obtain data to be transmitted;
frequency division processing is carried out on the clock frequency of the data transmission module, so that F' =F/m; wherein F' is the clock frequency after frequency division, and F is the clock frequency before frequency division;
according to the frequency-divided clock frequency F', the data to be transmitted are transmitted through the data transmitting module;
wherein BW' gen ＝BW send /m, and 2 XBW gen >BW′ gen >BW gen ；
BW′ gen And generating bandwidth for the data to be transmitted, wherein m is an integer greater than 1.
The embodiment of the disclosure further provides a system on chip SoC, as shown in fig. 4, including: a data generation module 410, a data transmission module 420, and an interpolation module 430;
the data generation module 410 is configured to generate source data;
the interpolation module 430 is configured to generate data to be sent based on the source data according to a source data interpolation policy included in a bandwidth matching policy;
The data transmitting module 420 is configured to transmit the source data or the data to be transmitted; or, according to a clock frequency division strategy of a data transmission module included in the bandwidth matching strategy, transmitting the source data or the data to be transmitted at the clock frequency after frequency division;
the bandwidth matching strategy is used for determining the bandwidth generated according to the data of the source data and the data output bandwidth of the data sending module; the data output bandwidth is greater than the data generation bandwidth.
In some example implementations, the bandwidth matching policy includes: a source data interpolation strategy and/or a data transmission module clock frequency division strategy.
In some exemplary embodiments, the system further comprises: and a control module configured to determine the bandwidth matching policy according to the data generation bandwidth of the source data and the data output bandwidth of the data transmission module 420.
In some exemplary embodiments, the data transmission module 420 includes: low voltage differential signaling LVDS transmit port 4210.
In some example embodiments, the LVDS transmit port includes one or more transmit channels (chanels).
In some exemplary embodiments, the data transmission module 420 includes: a frequency division parameter register;
In some exemplary embodiments, the interpolation module 430 includes: an interpolation register;
the frequency division parameter register stores frequency division parameters, and the interpolation register stores setting data for being inserted into the source data to obtain the data to be sent.
In some exemplary embodiments, the interpolation module 430 is configured to generate data to be transmitted based on the source data according to the setting data.
In some exemplary embodiments, the data transmitting module 420 is configured to perform frequency division processing according to the frequency division parameter, and transmit the source data or the data to be transmitted at the clock frequency after frequency division.
In some exemplary embodiments, in BW send ＝n×BW gen The bandwidth matching policy includes a data transmission module clock divide policy.
In some exemplary embodiments, at 2 XBW gen >BW send >BW gen The bandwidth matching policy includes a source data interpolation policy.
In some exemplary embodiments, in BW send ≠n×BW gen And BW is send >2×BW gen In this case, the bandwidth matching policy includes a data transmission module clock frequency division policy and a source data interpolation policy.
Wherein BW is send For the data output bandwidth, BW gen Generating a bandwidth for the data, n being an integer greater than 1.
In some exemplary embodiments, in the single data rate SDR mode, the data output bandwidth of the data transmission module 420 = clock frequency of the data transmission module x number of transmission channels of the data transmission module.
In some exemplary embodiments, in the double data rate DDR mode, the data output bandwidth of the data transmission module 420=2×the clock frequency of the data transmission module×the number of transmission channels of the data transmission module.
In some exemplary embodiments, in a case where the bandwidth matching policy includes a data transmission module clock frequency division policy, the data transmission module 420 is configured to perform frequency division processing on a clock frequency of the data transmission module, so that F' =f/n; transmitting source data according to the frequency-divided clock frequency F'; wherein F' is the clock frequency after frequency division and F is the clock frequency before frequency division.
In some exemplary embodiments, in the case that the bandwidth matching policy includes a source data interpolation policy, the interpolation module 430 is configured to periodically insert setting data into the source data to obtain data to be sent; the data transmitting module 420 is configured to transmit the data to be transmitted;
Wherein the generation bandwidth of the data to be transmitted=the data output bandwidth.
In some exemplary embodiments, the interpolation module 430 periodically inserts setting data into source data to obtain data to be transmitted, including:
in each period, setting data are inserted according to the following proportion to obtain the data to be transmitted:
source data unit number: (source data unit number+set data unit number) =the data generation bandwidth: the data output bandwidth.
In some exemplary embodiments, where the bandwidth matching policy includes a data transmission module clock divide policy and a source data interpolation policy,
the interpolation module 430 is configured to periodically insert setting data into the source data to obtain data to be sent;
the data transmission module 420 is configured to divide the clock frequency of the data transmission module, so that F' =f/m; transmitting the data to be transmitted according to the frequency-divided clock frequency F';
wherein F' is the clock frequency after frequency division, and F is the clock frequency before frequency division;
BW′ gen ＝BW send /m, and 2 XBW gen >BW′ gen >BW gen ；
BW′ gen And generating bandwidth for the data to be transmitted, wherein m is an integer greater than 1.
In some exemplary embodiments, the interpolation module 430 does not perform interpolation processing in the case where the setting data is empty.
In some exemplary embodiments, the data transmission module 420 includes: the clock frequency dividing sub-module 4220 is configured to perform frequency dividing processing on the reference clock according to the frequency dividing parameter. The frequency before the division of the reference clock is also referred to as the reference clock frequency.
In some exemplary embodiments, where the frequency division parameter is 0 or 1, or other integer not greater than 1, the clock frequency division sub-module 4220 does not divide the reference clock, i.e., the data transmission module 420 uses the reference clock frequency for actual data transmission.
In some exemplary embodiments, as shown in fig. 5, the data transmission module 420 includes an LVDS port having 4 channels, and the clock dividing submodule divides the clock to obtain the LVDS clock signal.
The data sending module 420 is configured to receive the source data from the data generating module 410 or the data to be sent from the interpolation module 430, and perform a packaging process: the packet header, the Package ID, and the CRC check value are inserted, and after being converted into serial data, the data is sent out of the chip through four output channels of the LVDS port (interface).
It will be appreciated that in some exemplary embodiments, the source data from the data generation module 410 or the data to be transmitted from the interpolation module 430 is also referred to as payload data (payload) with respect to the transmission data packed by the data transmission module. The data to be sent from the interpolation module 430 is data obtained by interpolation based on the source data, and includes the source data and the setting data.
It can be understood that, when the frequency division parameter is greater than 1, the clock frequency division submodule 4220 performs clock frequency division processing on the LVDS reference clock, so as to reduce the clock of the data transmission module, thereby reducing the rate of packet transmission, realizing the reduction of the bandwidth of the data output of the LVDS port, and achieving the purpose of matching with the input bandwidth of the source data or the data to be transmitted received by the data transmission module. The input bandwidth of the source data or the data to be transmitted, which is received by the data transmitting module, is the data generating bandwidth of the source data or the data generating bandwidth of the data to be transmitted.
The embodiment of the disclosure also provides a system-on-chip SoC, including: a data generation module 410 and a data transmission module 420;
the data generation module 410 is configured to generate source data;
the data transmitting module 420 is configured to transmit the source data at the clock frequency after frequency division according to a data transmitting module clock frequency division policy included in the bandwidth matching policy;
and the bandwidth matching strategy is used for determining the bandwidth according to the data generation bandwidth of the source data and the data output bandwidth of the data transmission module.
In some exemplary embodiments, the data output bandwidth is greater than the data generation bandwidth.
At BW send ＝n×BW gen In the case of (2), the bandwidth matching policy includes a data transmission module clock frequency division policy; wherein BW is send For the data output bandwidth, BW gen Generating a bandwidth for the data, n being an integer greater than 1.
That is, in BW send ＝n×BW gen The data transmission module is configured to transmit the source data at the divided clock frequency.
The embodiment of the disclosure also provides a system-on-chip SoC, including: a data generation module 410, a data transmission module 420, and an interpolation module 430;
the data generation module 410 is configured to generate source data;
the interpolation module 430 is configured to generate data to be sent based on the source data according to a source data interpolation policy included in a bandwidth matching policy;
the data transmitting module 420 is configured to transmit the data to be transmitted;
and the bandwidth matching strategy is used for determining the bandwidth according to the data generation bandwidth of the source data and the data output bandwidth of the data transmission module.
In some exemplary embodiments, the data output bandwidth is greater than the data generation bandwidth.
At 2 XBW gen >BW send >BW gen The bandwidth matching policy includes a source data interpolation policy; that is, at 2 XBW gen >BW send >BW gen In the case of (a), the interpolation module 430 is configured to generate data to be transmitted based on the source data; the data transmitting module 420 is configured to transmit the data to be transmitted.
The disclosed embodiments also provide a chip comprising a processor configured to implement the data transmission method according to any of the disclosed embodiments.
The disclosed embodiments also provide a computer storage medium having a computer program stored therein, wherein the computer program is configured to perform the data transmission method according to any of the embodiments of the disclosure when run.
The disclosed embodiments also provide an electronic device, comprising,
one or more processors;
storage means for storing one or more programs,
the one or more programs, when executed by the one or more processors, cause the one or more processors to implement a data transmission method as described in any of the embodiments of the present disclosure.
According to the data transmission scheme provided by the embodiment of the disclosure, under the condition that the bandwidth (rate) for generating the data of the on-chip data source and the bandwidth (rate) for outputting the data of the data transmission module are determined, the frequency division processing of the data transmission module and/or the interpolation processing of the source data are carried out by configuring the frequency division parameters and/or the interpolation data, so that the speed matching/bandwidth matching between the data generation of the on-chip system and the data transmission to the outside of the chip can be realized, the on-chip data can be completely packaged and transmitted without buffering the source data in a large quantity, the area of a hardware circuit is reduced, the hardware cost is reduced, and the real-time from the generation of the on-chip data to the output to the outside of the chip is ensured. When the generation speed (bandwidth) of the source data and/or the output speed (bandwidth) of the sending module are changed, matching can be realized only by adjusting the configured frequency division parameters and/or interpolation data, and the configuration and processing complexity of software are greatly simplified.
Those of ordinary skill in the art will appreciate that all or some of the steps, systems, functional modules/units in the apparatus, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed cooperatively by several physical components. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.

Claims (14)

1. A data transmission method, comprising:
generating bandwidth according to the data of the source data and data output bandwidth of the data sending module, and determining a bandwidth matching strategy;
after corresponding operation is executed according to the bandwidth matching strategy, data is sent through the data sending module;
wherein the bandwidth matching policy comprises:
a source data interpolation strategy and/or a data transmission module clock frequency division strategy.
2. The method of claim 1, wherein,
the bandwidth matching strategy is determined according to the data generation bandwidth of the source data and the data output bandwidth of the data transmission module, and at least one of the following is included:
at BW send ＝n×BW gen In the case of (2), the bandwidth matching policy includes a data transmission module clock frequency division policy;
at 2 XBW gen >BW send >BW gen The bandwidth matching policy includes a source data interpolation policy;
at BW send ≠n×BW gen And BW is send >2×BW gen Under the condition, the bandwidth matching strategy comprises a data sending module clock frequency division strategy and a source data interpolation strategy;
wherein BW is send For the data output bandwidth, BW gen Generating a bandwidth for the data, n being an integer greater than 1.
3. The method of any one of claim 1 to 2, wherein,
In the single data rate SDR mode, the data output bandwidth of the data transmission module=the clock frequency of the data transmission module×the number of transmission channels of the data transmission module;
or,
in the double data rate DDR mode, the data output bandwidth of the data transmission module=2×the clock frequency of the data transmission module×the number of transmission channels of the data transmission module.
4. The method of claim 2, wherein,
when the bandwidth matching policy includes a clock frequency division policy of the data sending module, sending data through the data sending module after the corresponding operation is executed according to the bandwidth matching policy, including:
frequency division processing is carried out on the clock frequency of the data transmission module, so that F' =F/n; wherein F' is the clock frequency after frequency division, and F is the clock frequency before frequency division;
and transmitting the source data through the data transmitting module according to the frequency-divided clock frequency F'.
5. The method of claim 2, wherein,
when the bandwidth matching policy includes a source data interpolation policy, after the performing a corresponding operation according to the bandwidth matching policy, sending data through the data sending module includes:
Periodically inserting setting data into the source data to obtain data to be transmitted;
transmitting the data to be transmitted through the data transmitting module;
wherein the generation bandwidth of the data to be transmitted=the data output bandwidth.
6. The method of claim 5, wherein,
the periodically inserting the setting data into the source data to obtain the data to be sent includes:
in each period, setting data are inserted according to the following proportion to obtain the data to be transmitted:
source data unit number: (source data unit number+set data unit number) =the data generation bandwidth: the data output bandwidth.
7. The method of claim 2, wherein,
when the bandwidth matching policy includes a clock frequency division policy and a source data interpolation policy of the data sending module, sending data through the data sending module after the corresponding operation is executed according to the bandwidth matching policy, including:
periodically inserting setting data into the source data to obtain data to be transmitted;
frequency division processing is carried out on the clock frequency of the data transmission module, so that F' =F/m; wherein F' is the clock frequency after frequency division, and F is the clock frequency before frequency division;
According to the frequency-divided clock frequency F', the data to be transmitted are transmitted through the data transmitting module;
wherein BW' gen ＝BW send /m, and 2 XBW gen >BW′ gen >BW gen ；
BW′ gen And generating bandwidth for the data to be transmitted, wherein m is an integer greater than 1.
8. A data transmission apparatus, comprising:
the matching strategy determining module is used for determining a bandwidth matching strategy according to the data generation bandwidth of the source data and the data output bandwidth of the data sending module;
the sending module is used for sending data through the data sending module after corresponding operation is executed according to the bandwidth matching strategy;
wherein the bandwidth matching policy comprises:
a source data interpolation strategy and/or a data transmission module clock frequency division strategy.
9. A system on a chip, comprising:
the system comprises a data generation module, a data transmission module and an interpolation module;
the data generation module is used for generating source data;
the interpolation module is configured to generate data to be transmitted based on the source data according to a source data interpolation strategy included in a bandwidth matching strategy;
the data transmitting module is configured to transmit the source data or the data to be transmitted; or setting a clock frequency division strategy of a data transmission module included according to the bandwidth matching strategy, and transmitting the source data or the data to be transmitted at the clock frequency after frequency division;
And the bandwidth matching strategy is used for determining the bandwidth according to the data generation bandwidth of the source data and the data output bandwidth of the data transmission module.
10. The system on a chip of claim 9, wherein,
the data transmitting module includes: low voltage differential signaling LVDS transmit ports.
11. The system on a chip of claim 9 or 10, wherein,
the data transmitting module includes: a frequency division parameter register;
the interpolation module includes: an interpolation register;
the frequency division parameter register stores frequency division parameters, and the interpolation register stores setting data for being inserted into the source data to obtain the data to be sent.
12. The system on a chip of claim 9 or 10, wherein,
at BW send ＝n×BW gen In the case of (a), the bandwidth matching policy includes a numberAccording to a clock frequency division strategy of the sending module;
at 2 XBW gen >BW send >BW gen The bandwidth matching policy includes a source data interpolation policy;
at BW send ≠n×BW gen And BW is send >2×BW gen Under the condition, the bandwidth matching strategy comprises a data sending module clock frequency division strategy and a source data interpolation strategy;
wherein BW is send For the data output bandwidth, BW gen Generating a bandwidth for the data, n being an integer greater than 1.
13. A chip comprising a processor configured to implement the data transmission method of any one of claims 1-7.
14. A computer-readable storage medium, on which a computer program is stored, characterized in that the program, when being executed by a processor, implements the data transmission method according to any one of claims 1-7.
CN202311448690.2A 2023-11-01 2023-11-01 Data transmission method, device, system, chip and storage medium Pending CN117555827A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311448690.2A CN117555827A (en) 2023-11-01 2023-11-01 Data transmission method, device, system, chip and storage medium

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311448690.2A CN117555827A (en) 2023-11-01 2023-11-01 Data transmission method, device, system, chip and storage medium

Publications (1)

Publication Number Publication Date
CN117555827A true CN117555827A (en) 2024-02-13

Family

ID=89819522

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311448690.2A Pending CN117555827A (en) 2023-11-01 2023-11-01 Data transmission method, device, system, chip and storage medium

Country Status (1)

Country Link
CN (1) CN117555827A (en)

Similar Documents

Publication Publication Date Title
US9825852B2 (en) Method and device for serial data transmission which is adapted to memory sizes
US8132076B1 (en) Method and apparatus for interleaving portions of a data block in a communication system
CN109873692B (en) Reception method and reception LSI
CN113381918B (en) In-vehicle signal transmission method and system
US7434150B1 (en) Methods, circuits, architectures, software and systems for determining a data transmission error and/or checking or confirming such error determinations
US10567194B2 (en) User station for a bus system and method for increasing the transmission capacity in a bus system
US7360142B1 (en) Methods, architectures, circuits, software and systems for CRC determination
US20220006745A1 (en) Service sending and receiving methods, device, system and storage medium
US20170235630A1 (en) Subscriber station for a bus system, and method for checking the correctness of a message
CN104486442A (en) Method and device for transmitting data of distributed storage system
CN117555827A (en) Data transmission method, device, system, chip and storage medium
US8793410B2 (en) Data rate throttling in an internal packet-based interface
US9122411B2 (en) Signal order-preserving method and apparatus
CN111225077B (en) Network distribution method, device and system for Internet of things equipment
JP2003518874A (en) data communication
CN110169023A (en) A kind of data transmission method, data receiver and data transmitting equipment
CN106954103B (en) Transmission system and transmission method for downlink service in 100G EPON system
US7020094B2 (en) Method and system for transmitting at least one client signal within a server signal
US20230198802A1 (en) Vehicle Control Device and Data Transfer Control Method
CN112188446B (en) Synchronization signal sending method, terminal, device and storage medium
US8832309B2 (en) Generating packets with low overhead or selectable sequence number generation
CN114245241B (en) Time-delay self-adaptive BMP mapping realization method and system
CN116318376B (en) Method, device and storage medium for transmitting remote control application data by using virtual channel
US11206096B2 (en) Electronic control apparatus
WO2024066414A1 (en) Service transmission method, and device and medium

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination