CN117555474A

CN117555474A - Data processing method for storage device, related device and storage medium

Info

Publication number: CN117555474A
Application number: CN202210933509.6A
Authority: CN
Inventors: 孔维镇
Original assignee: Shanghai Jiangbolong Digital Technology Co ltd
Current assignee: Shanghai Jiangbolong Digital Technology Co ltd
Priority date: 2022-08-04
Filing date: 2022-08-04
Publication date: 2024-02-13

Abstract

The application discloses a data processing method for storage equipment, related equipment and a storage medium. In the method, the storage device includes at least one page, each page for storing n first LDPC codewords, each first LDPC codeword including first user data and LDPC check data, the method comprising: performing a data writing operation such that m second LDPC codewords are stored per page, each of the second LDPC codewords including second user data and the LDPC check data; wherein m and n are positive integers, and m is greater than n, and the length of the second user data is smaller than the length of the first user data. Related devices and storage media are also disclosed. According to the LDPC code with the main control fixed code rate, the preset model data is filled/deleted on the read-write path, the proportion of the space occupied by the LDPC check data is increased in a phase-changing mode, the LDPC code rate is reduced, and the effect of improving the error correction capability of the LDPC code is achieved.

Description

Data processing method for storage device, related device and storage medium

Technical Field

The present invention relates to the field of semiconductor storage, and in particular, to a data processing method for a storage device, a related device, and a storage medium.

Background

Solid State Disk (SSD) based on flash memory is a novel storage device with a semiconductor flash memory chip as a storage component, and compared with a traditional mechanical hard disk, the solid state disk has obvious advantages in the aspects of read-write performance, power consumption, shock resistance and the like because the solid state disk does not comprise any mechanical component. Its appearance can be made in a variety of patterns, for example: notebook hard disk, micro hard disk, memory card, U disk, etc. The SSD solid state disk has the greatest advantages of being movable, protecting data from being controlled by a power supply, being applicable to various environments and being applicable to individual users.

NAND flash is a better storage device than conventional hard disk drives, and uses nonvolatile memory technology, i.e., a storage device that retains data after power is turned off. NAND flash is composed of a plurality of bit-Cell units, and the mainstream NAND flash is generally 3D TLC (Triple Level Cell, three-layer Cell)/QLC (four-layer Cell), and most products will prefer TLC/QLC because of its much lower cost than SLC (Single Level Cell, single-layer Cell)/MLC (Multi-layer Cell). But the data reliability is much reduced due to the increased density of the stored data. In most application scenes, the requirements on the storage capacity are loose, the requirements on the reliability of data are strict, and the reliability specification of the TLC/QLC cannot meet the use requirements of products at present.

Disclosure of Invention

Therefore, the application provides a data processing method for a storage device, a related device and a storage medium, so as to improve the error correction capability of the LDPC code.

A first aspect of the present application provides a data processing method for a storage device, the storage device including at least one page, each page being for storing n first LDPC codewords, each first LDPC codeword including first user data and LDPC check data, the method comprising: performing a data writing operation such that m second LDPC codewords are stored per page, each of the second LDPC codewords including second user data and the LDPC check data; wherein m and n are positive integers, and m is greater than n, and the length of the second user data is smaller than the length of the first user data.

In some embodiments, the performing the data write operation includes: dividing the first user data in each of the first LDPC codewords into x of the second user data, where x is a positive integer greater than 1; combining each second user data with preset model data according to preset rules and performing LDPC coding to generate corresponding LDPC check data of each second user data, wherein the sum of the length of the second user data and the length of the preset model data is the length of the first user data; deleting the preset model data to obtain each piece of second user data and corresponding LDPC verification data; and sequentially writing the x second user data and the corresponding LDPC check data, thereby realizing the storage of m second LDPC codewords per page.

In some embodiments, the preset rules include: and splicing the preset model data with the second user data, wherein the preset model data is positioned at a preset position of the second user data.

In some embodiments, the preset location includes a front, a rear, or a specific location of the second user data.

In some embodiments, the performing a data write operation further comprises: virtual data is written into the remaining space of each page, wherein the length of the remaining space is the difference between the length of n first LDPC codewords and the length of m second LDPC codewords.

In some embodiments, the method of any one of the above further comprises: a data read operation is performed to acquire m second LDPC codewords stored in each page.

In some embodiments, the performing a data read operation includes: sequentially acquiring the x second LDPC codewords; supplementing the preset model data into each second LDPC codeword according to the preset rule, and performing LDPC decoding to obtain the x second user data and the preset model data; and deleting the preset model data, and combining and reading the x pieces of second user data.

A second aspect of the present application provides a storage device comprising at least one page, each page for storing n first LDPC codewords, each first LDPC codeword comprising first user data and LDPC check data, being implemented as a data processing method according to any of the first aspects.

A third aspect of the present application provides a terminal device, including a memory and a processor coupled to each other, where the processor is configured to execute program instructions stored in the memory, so as to implement the data processing method in the first aspect.

A fourth aspect of the present application provides a non-transitory computer readable storage medium having stored thereon program instructions which, when executed by a processor, implement the data processing method of the first aspect described above.

According to the scheme, based on the fact that the storage device comprises at least one page, each page is used for storing n first LDPC codewords, each first LDPC codeword comprises first user data and LDPC check data, data writing operation is carried out, so that m second LDPC codewords are stored in each page, each second LDPC codeword comprises second user data and the LDPC check data, m and n are positive integers, m is larger than n, the length of the second user data is smaller than that of the first user data, namely, LDPC codes are utilized, and by carrying out data writing operation, part of effective storage space is sacrificed to reduce LDPC code rate, therefore, the improvement of the error correction capability of the codes under higher storage data density is achieved, the reliability of related products is improved, and the service life of the products is prolonged.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and, together with the description, serve to explain the technical aspects of the application.

FIG. 1 is a schematic diagram of a page of a memory device according to an embodiment of the present application;

FIG. 2 is a flow chart of a data processing method for a storage device according to an embodiment of the present application;

FIG. 3 is a schematic view of a scenario of a data processing method for a storage device according to an embodiment of the present application;

FIG. 4 is a flow chart of a data writing operation of the data processing method according to the embodiment of the present application;

FIG. 5 is a schematic diagram illustrating one embodiment of a data write operation of a data processing method of the present application;

FIG. 6 is a schematic diagram of a process of a data write operation of the data processing method of the embodiment of the present application;

FIG. 7 is a schematic diagram of a framework of a storage device according to an embodiment of the present application;

fig. 8 is a schematic diagram of a frame of a terminal device according to an embodiment of the present application;

fig. 9 is a schematic diagram of a framework of a non-volatile computer-readable storage medium of an embodiment of the present application.

Detailed Description

The following describes the embodiments of the present application in detail with reference to the drawings.

In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, interfaces, techniques, etc., in order to provide a thorough understanding of the present application.

The term "and/or" is herein merely an association relationship describing an associated object, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship. Further, "a plurality" herein means two or more than two. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of A, B, C, and may mean including any one or more elements selected from the group consisting of A, B and C.

Certain terms are used throughout the description and claims to refer to particular components. As will be appreciated by those skilled in the art, electronic device manufacturers may refer to a component by different names. The components are not distinguished by name herein, but rather by function. In the following description and claims, the terms "include" and "comprise" are defined as open-ended terms, and thus should be interpreted to mean "include, but not limited to …". In addition, the term "coupled" is intended to mean either an indirect electrical connection or a direct electrical connection. Thus, when one device is coupled to another device, then the connection may be a direct electrical connection or an indirect electrical connection via other devices and connections.

The current NAND flash memory in the market is generally 3D TLC/QLC, but the data reliability is greatly reduced due to the increased density of the stored data. Because the data is easy to make mistakes along with the increase of the data storage time, the increase of the reading times, the influence of interference such as the reading-writing temperature difference and the like. For some engineering and vehicle rule products, although the reliability requirements on the data are strict, the requirements on the storage capacity are loose, so that a part of storage space can be sacrificed to ensure the reliability of the data. The main control chip in the current market has the LDPC code rate controlled between 85% and 95% and no LDPC code with lower code rate, so that the code rate of the LDPC code needs to be reduced by phase change through special technology, and the error correction capability of the LDPC code is improved.

For this purpose, the present application proposes a data processing method for a storage device, a related device, and a storage medium according to the following embodiments.

In order to facilitate understanding of the present application, pages of the memory device according to the following embodiments of the present application will be described in detail.

Referring to fig. 1, fig. 1 is a schematic diagram of a page of a memory device according to an embodiment of the present application, where the page 100 is configured to store n first LDPC codewords 110, and each first LDPC codeword 110 includes first User Data (User Data) and LDPC Parity Data (LDPC Parity).

Page 100 is a NAND flash read-only unit, typically 4K or a multiple of 4K bytes in size, and a write operation can only write to an empty page. Each page 100 is used to store n first LDPC codewords 110, i.e., different numbers of codewords may be stored according to different size storage capacities of the pages. The user data is created or owned by the user, and may be image data, document data, data to be stored, and the like. LDPC check data, namely LDPC code (Low Density Parity Check Code ), LDPC code is a kind of error correction code (ECC, error correcting code), wherein ECC code is a tool for error detection and correction in information transmission, namely usually used in unreliable or noisy channels, a data sender enables a receiver to detect and correct errors occurring in transmission by utilizing redundant information in error correction code, and LDPC code can be used for correcting errors occurring in information transmission, and is characterized in that its check matrix is a sparse matrix, namely a matrix with few non-zero elements, and the error correction capability of the code is very close to theoretical maximum.

For example, the length of the page 100 of the NAND used may be 16kb+2048b, the code length of the first LDPC codeword 110 may be 2048b+256b, the code rate may be 88.88%, and it may be assumed that its error correction capability is a, i.e., one codeword may be 2KB of first user data and 256BLDPC check data, and the error correction capability is a. It will be understood that if the total length of one page is 18KB and the effective capacity is 16KB, then 8 codewords, i.e. 8 User Data and 8 LDPC Parity Data, i.e. 8 "2KB User Data and 256B LDPC Parity" can be stored therein, and the maximum allowable error bit number of the read page 100 is 8A.

Referring to fig. 2, fig. 2 is a flowchart of a data processing method for a storage device according to an embodiment of the present application. The memory device comprises at least one page, each page may be a page 100 of read units in the embodiment of fig. 1 described above, i.e. each page 100 is configured to store n first LDPC codewords 110, each first LDPC codeword 110 comprising first user data and LDPC check data.

The execution subject of the method may be a terminal device having a memory and a processor coupled to each other, for example, a microcomputer, a server, a mobile device such as a notebook computer, a tablet computer, etc. In some possible implementations, the data processing method may be implemented by way of a processor invoking computer readable instructions stored in a memory. Specifically, the method may include the steps of:

step S21: the data writing operation is performed such that m second LDPC codewords are stored per page, each second LDPC codeword including second user data and LDPC check data.

After performing the data writing operation, m second LDPC codewords 120 are stored in the page 100, each second LDPC codeword 120 including second user data and LDPC check data. As shown in fig. 3, fig. 3 is a schematic view of a scenario of a data processing method for a storage device according to an embodiment of the present application.

Wherein m and n are positive integers, m is greater than n, and the length of the second user data is smaller than the length of the first user data.

The positive integer n is the number of the first LDPC codewords 110 storable per page, the positive integer m is the number of the second LDPC codewords 120 storable per page, and m is greater than n. The second user data may be obtained by performing a data writing operation, i.e. splitting the first user data in the first LDPC codeword 110, wherein the length of the second user data is smaller than the length of the first user data.

In this embodiment, based on the storage device including at least one page, each page is used for storing n first LDPC codewords, each first LDPC codeword includes first user data and LDPC parity data, by performing a data write operation, so that each page stores m second LDPC codewords, each second LDPC codeword includes second user data and the LDPC parity data, where m and n are positive integers, and m is greater than n, and the length of the second user data is less than the length of the first user data, in this process, by performing a data write operation, the number of LDPC codewords in a page is increased, so as to improve the error correction capability of the LDPC code under a higher storage data density, increase the reliability of a related product, and prolong the service life of the product.

As described above, after performing the data writing operation, m second LDPC codewords 120 are stored in the page 100, each second LDPC codeword 120 includes second user data and LDPC check data, and in some embodiments, referring to fig. 4, fig. 4 is a schematic flow chart of performing the data writing operation of the data processing method according to the embodiment of the present application, and in combination with fig. 3, the performing the data writing operation includes the following steps:

step S41: the first user data in each first LDPC codeword is divided into x second user data, where x is a positive integer greater than 1.

Each first LDPC codeword 110 may include first user data and LDPC check data, and the first user data in each first LDPC codeword 110 is divided to obtain x second user data, where x is a positive integer greater than 1, and 2 second user data or 3 second user data or more second user data may be obtained.

The page 100 length of the NAND flash memory used above is 16kb+2048b as an example. With reference to fig. 5, fig. 5 is a schematic diagram of an embodiment of performing a data writing operation by the data processing method of the present application, that is, 8 first LDPC codewords 110, that is, 8 "2KB first user data and 256BLDPC check data" may be originally stored in a page 100, and by dividing the first user data in each first LDPC codeword 110, 1KB first user data in the first LDPC codeword 110 may be divided into 21 KB second user data.

Step S42: and combining each second user data with the preset model data according to preset rules and performing LDPC coding to generate LDPC check data corresponding to each second user data.

The second user data is obtained by dividing the first user data in each first LDPC codeword 110, and each second user data is combined with the preset model data according to a preset rule to obtain "second user data and preset model data", at this time, the "second user data and preset model data" are LDPC-coded to generate LDPC check data corresponding to each second user data, that is, the "second user data and preset model data and LDPC check data" are obtained.

Continuing to take the page of the NAND flash memory as an example, as shown in fig. 5, namely combining the 1KB second user data with the preset model data according to a preset rule to obtain an intermediate combination of the 1KB second user data and the 1KB model data, and performing LDPC encoding to generate LDPC check data corresponding to each second user data, so as to obtain "1KB second user data and 1KB model data and 256BLDPC check data", wherein the sum of the length of the second user data and the length of the preset model data is the length of the first user data, that is, the sum of the length of the 1KB second user data and the 1KB model data is 2KB, and the length of the second user data and the length of the first user data is equal to 2 KB.

Step S43: and deleting the preset model data to obtain each second user data and corresponding LDPC check data.

Continuing to take the page of the NAND flash memory as an example, as shown in fig. 5, deleting the preset model data to obtain each second user data and corresponding LDPC check data, that is, deleting 1KB preset model data may obtain "1KB second user data and 256BLDPC check data".

Step S44: and sequentially writing the x second user data and the corresponding LDPC check data, thereby realizing the storage of m second LDPC code words in each page.

And sequentially writing the second user data and the corresponding LDPC verification data, namely sequentially writing the second user data, the preset model data and the LDPC verification data into the page 100 to realize that m second LDPC codewords 120 are stored in each page, wherein m is the number of codewords written into the page 100 to the maximum limit according to the length of the codewords of the second user data, the preset model data and the LDPC verification data.

Continuing with the above example of the page of the NAND flash memory, the page 100 is 18KB in length, that is, according to the obtained code length of "1KB second user data and 256BLDPC check data" being 1kb+256B, it is sequentially written until the page 100 is fully written with the full codeword length to the maximum extent of 18KB in length, that is, when the page 100 is 18KB in length, 14 second LDPC codewords 120, that is, 14 "1KB second user data and 256BLDPC check data" codewords can be written to the maximum extent, and the remaining 512B space, at this time, the code rate phase becomes reduced to 80.00%, and the maximum allowable error bit number is 14A.

In order to generate the corresponding LDPC verification data of each second user data, each second user data and preset model data are combined according to preset rules and LDPC coding is carried out, wherein the preset rules comprise that the preset model data and the second user data are spliced, and the preset model data are spliced at preset positions of the second user data.

Wherein the preset location comprises a front, a rear or a specific location of the second user data.

Splicing the preset model data with the second user data, namely splicing the preset model data with the second user data at preset positions, wherein the preset positions comprise the front, the back or specific positions of the second user data, namely splicing the preset model data with the second user data can be completed at the front, the back or the specific positions of the second user data.

In some embodiments, performing the data write operation further comprises: virtual data is written into the remaining space of each page, wherein the length of the remaining space is the difference between the length of the n first LDPC codewords and the length of the m second LDPC codewords.

Referring to fig. 6, fig. 6 is a schematic diagram illustrating a Data writing process of the Data processing method according to the embodiment of the present application, where a page 100 is used to store n second LDPC codewords 120, each second LDPC codeword 120 includes first user Data and LDPC check Data, and a remaining space is a space left after the full codeword length of the second LDPC codeword is written into the page 100 to the maximum extent, where the length of the remaining space is a difference between the length of n first LDPC codewords 110 and the length of m second LDPC codewords 120, that is, a difference between the lengths of n "first user Data and LDPC check Data" codewords and m "second user Data and LDPC check Data" codewords, virtual Data (Dummy Data) 130 is written into the remaining space of the page 100, that is, after the second LDPC codewords 120 are written into the page 100 in sequence with the full codeword, the virtual Data 130 can be written into the remaining space of the page 100.

Continuing with the explanation of the above page of the NAND flash memory as an example, the obtained "1KB second user data and 256BLDPC check data" have a code length of 1kb+256B, and writing sequentially, so that the page 100 is written with a full codeword to the maximum extent, that is, if the page 100 has a length of 18KB, 8 "2KB first user data and 256BLDPC check data" can be written originally, 14 "1KB second user data and 256BLDPC check data" can be written to the maximum extent now, the remaining space 512B, and the virtual data 130 can be written into the remaining 512B space. Wherein 512B is a length difference between 8 "2KB first user data and 256BLDPC check data" codeword lengths and 14 "1KB second user data and 256BLDPC check data" codeword lengths.

As described above, a data read operation is further performed to acquire m second LDPC codewords stored in each page.

By performing a data read operation, m second LDPC codewords 120 stored in each page are acquired, see fig. 6.

Sequentially acquiring x second LDPC code words; supplementing preset model data into each second LDPC code word according to preset rules, and performing LDPC decoding to obtain x second user data and preset model data; deleting preset model data, deleting the preset model data, and combining and reading the x pieces of second user data.

After the second LDPC codewords 120 are sequentially acquired, the preset model data are supplemented to each second LDPC codeword 120 according to a preset rule, so that corresponding "second user data and model data and LDPC check data" are obtained, and LDPC decoding is performed to obtain "second user data and preset model data", and then the preset model data are deleted, so that the second user data can be combined to complete reading under the condition that the maximum allowable error bit number of a page increases, and since the supplemented preset model data have no bit errors, the error correction capability of the LDPC code is not reduced.

Continuing taking the page of the NAND flash memory as an example, the length of the page 100 is 18KB, the effective capacity is 16KB, the second LDPC codeword 120 is sequentially acquired, the preset rule model data is supplemented into the second LDPC codeword according to the preset rule, so as to obtain "1KB second user data and 1KB model data and 256BLDPC check data", LDCP decoding is performed, so as to obtain "1KB second user data and 1KB model data", the 1KB model data is deleted, so as to obtain 1KB second user data, and the page 1KB second user data is combined to complete reading.

It will be appreciated by those skilled in the art that in the above-described method of the specific embodiments, the written order of steps is not meant to imply a strict order of execution but rather should be construed according to the function and possibly inherent logic of the steps.

Referring to fig. 7, fig. 7 is a schematic diagram of a frame of a memory device according to an embodiment of the present application, where a memory device 700 may include a flash memory 710, the flash memory 710 including at least one block (block) 711, the block 711 including at least one page, each page for storing a corresponding number of first LDPC codewords 110, each first LDPC codeword 110 including first user data and LDPC check data, and the data processing method of any of the above is performed. The storage device can be a novel storage device taking a semiconductor flash memory chip as a storage component, such as a solid state disk based on flash memory.

Referring to fig. 8, fig. 8 is a schematic diagram of a frame of an embodiment of a terminal device 80 of the present application. The terminal device 80 comprises a memory 81 and a processor 82 coupled to each other, the processor 82 being adapted to execute program instructions stored in the memory 81 for implementing the steps of any of the data processing method embodiments for a storage device described above. In one particular implementation scenario, terminal device 80 may include, but is not limited to: the microcomputer, server, and the terminal device 80 may also include mobile devices such as a notebook computer and a tablet computer, which are not limited herein.

In particular, the processor 82 is operative to control itself and the memory 81 to implement the steps in any of the data processing method embodiments for a storage device described above. The processor 82 may also be referred to as a CPU (Central Processing Unit ). The processor 82 may be an integrated circuit chip having signal processing capabilities. The processor 82 may also be a general purpose processor, a digital signal processor (Digital Signal Processor, DSP), an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), a Field programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. In addition, the processor 82 may be commonly implemented by an integrated circuit chip.

Referring to FIG. 9, FIG. 9 is a schematic diagram illustrating an embodiment of a non-transitory computer readable storage medium 90 of the present application. The non-transitory computer readable storage medium 90 stores program instructions 901 executable by a processor, the program instructions 901 for implementing steps in any of the data processing method embodiments for a storage device described above.

In some embodiments, functions or modules included in an apparatus provided by the embodiments of the present disclosure may be used to perform a method described in the foregoing method embodiments, and specific implementations thereof may refer to descriptions of the foregoing method embodiments, which are not repeated herein for brevity.

The foregoing description of various embodiments is intended to highlight differences between the various embodiments, which may be the same or similar to each other by reference, and is not repeated herein for the sake of brevity.

In the several embodiments provided in the present application, it should be understood that the disclosed methods and apparatus may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of modules or units is merely a logical functional division, and there may be additional divisions of actual implementation, e.g., units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical, or other forms.

In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be embodied essentially or in part or all or part of the technical solution contributing to the prior art or in the form of a software product stored in a storage medium, including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) to perform all or part of the steps of the methods of the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

Claims

1. A data processing method for a storage device, the storage device comprising at least one page, each page for storing n first LDPC codewords, each first LDPC codeword comprising first user data and LDPC check data, the method comprising:

performing a data writing operation such that m second LDPC codewords are stored per page, each of the second LDPC codewords including second user data and the LDPC check data;

wherein m and n are positive integers, and m is greater than n, and the length of the second user data is smaller than the length of the first user data.

2. The method of claim 1, wherein the performing a data write operation comprises:

dividing the first user data in each of the first LDPC codewords into x of the second user data, where x is a positive integer greater than 1;

combining each second user data with preset model data according to preset rules and performing LDPC coding to generate corresponding LDPC check data of each second user data, wherein the sum of the length of the second user data and the length of the preset model data is the length of the first user data;

deleting the preset model data to obtain each piece of second user data and corresponding LDPC verification data;

and sequentially writing the x second user data and the corresponding LDPC check data, thereby realizing the storage of m second LDPC codewords per page.

3. The method of claim 2, wherein the preset rule comprises:

and splicing the preset model data with the second user data, wherein the preset model data is positioned at a preset position of the second user data.

4. A method according to claim 3, wherein the preset location comprises a front, a rear or a specific location of the second user data.

5. The method of claim 2, wherein performing the data write operation further comprises:

virtual data is written into the remaining space of each page, wherein the length of the remaining space is the difference between the length of n first LDPC codewords and the length of m second LDPC codewords.

6. The method of any one of claims 1-5, further comprising: :

a data read operation is performed to acquire m second LDPC codewords stored in each page.

7. The method of claim 6, wherein the performing a data read operation comprises:

sequentially acquiring the x second LDPC codewords;

supplementing the preset model data into each second LDPC codeword according to the preset rule, and performing LDPC decoding to obtain the x second user data and the preset model data;

and deleting the preset model data, and combining and reading the x pieces of second user data.

8. A storage device comprising at least one page, each page for storing n first LDPC codewords, each first LDPC codeword comprising first user data and LDPC check data, being executed with a data processing method according to any of claims 1 to 7.

9. A terminal device comprising a memory and a processor coupled to each other, the processor being configured to execute program instructions stored in the memory to implement the data processing method for a storage device according to any one of claims 1-7.

10. A non-transitory computer readable storage medium having stored thereon program instructions, which when executed by a processor implement the data processing method for a storage device of any of claims 1-7.