CN117554774A - Chip signal amplitude measuring device - Google Patents
Chip signal amplitude measuring device Download PDFInfo
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- CN117554774A CN117554774A CN202210942928.6A CN202210942928A CN117554774A CN 117554774 A CN117554774 A CN 117554774A CN 202210942928 A CN202210942928 A CN 202210942928A CN 117554774 A CN117554774 A CN 117554774A
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- 238000002955 isolation Methods 0.000 claims abstract description 37
- 238000005070 sampling Methods 0.000 claims abstract description 3
- 238000012360 testing method Methods 0.000 claims description 39
- 230000005669 field effect Effects 0.000 claims description 35
- 238000005259 measurement Methods 0.000 claims description 15
- 239000003990 capacitor Substances 0.000 claims description 14
- 238000001514 detection method Methods 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 11
- 238000000034 method Methods 0.000 description 8
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000008054 signal transmission Effects 0.000 description 3
- 238000007599 discharging Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
- G01R19/2503—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques for measuring voltage only, e.g. digital volt meters (DVM's)
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Environmental & Geological Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The application discloses chip signal amplitude measuring device, wherein, signal amplitude measuring device includes: the input end of the signal isolation module is connected with the IO bus of the chip and is used for receiving the level signal of the chip and isolating the level signal from the IO bus of the chip; the input end of the amplitude maintaining module is connected with the output end of the signal isolation module and is used for receiving the level signal, sampling the level signal and maintaining the maximum amplitude of the level signal; the control module is connected with the output end of the amplitude maintaining module to receive the maximum amplitude of the level signal and convert the received maximum amplitude of the level signal into the output voltage amplitude of the chip. With the structure, the signal amplitude of the chip can be measured.
Description
Technical Field
The application relates to the technical field of system-level testing, in particular to a chip signal amplitude measuring device.
Background
At present, testing of DRAM (Dynamic Random Access Memory ) mainly relies on machine stations for testing, including T5588 and T5503A machine stations, and relevant parameter testing is carried out on LPDDR2/3, but the machine station testing method is high in cost and inflexible.
Besides the machine test, the whole machine test scheme is adopted, and a DRAM test seat is directly added at the original welding DRAM packaging position on the whole machine so as to achieve the purpose of test. The complete machine test scheme mounts the complete DRAM test socket on this module. The modules added with the test parameters comprise a current test module, a serial port communication module and the like, and a DRAM test frame is formed by the combination of the modules, but the current whole machine test method is unstable, and can not independently test some parameters, in particular can not measure the amplitude of signals output by the whole machine.
Aiming at the fact that the chip cannot measure the amplitude of a signal output by the chip in an SLT system, a new measuring device is needed to be provided.
Disclosure of Invention
The technical problem that this application mainly solves is to provide a chip signal amplitude measuring device, can measure the signal amplitude of chip.
The application provides a chip signal amplitude measuring device, wherein, signal amplitude measuring device includes: the input end of the signal isolation module is connected with the IO bus of the chip and is used for receiving the level signal of the chip and isolating the level signal from the IO bus of the chip; the input end of the amplitude maintaining module is connected with the output end of the signal isolation module and is used for receiving the level signal, sampling the level signal and maintaining the maximum amplitude of the level signal; the control module is connected with the output end of the amplitude maintaining module to receive the maximum amplitude of the level signal and convert the received maximum amplitude of the level signal into the output voltage amplitude of the chip.
The signal amplitude measuring device further comprises a main control module, wherein the main control module is connected with the chip through the IO bus interface so as to input signals to the chip.
The signal amplitude measuring device further comprises a test seat, wherein the test seat is used for fixing the chip, and an IO bus interface is arranged on the test seat, so that the chip is respectively connected with the signal isolation module or the main control module through the IO bus interface.
The signal isolation module is also connected with the main control module through the IO bus interface so as to detect signals input by the main control module to the chip.
Wherein the chip is a digital chip; the digital chip receives the digital signal input by the main control module and converts the digital signal into a level signal.
The control module is provided with a serial interface and is connected with the main control module through the serial interface so as to control signals input by the main control module to the chip.
The amplitude maintaining module comprises a junction field effect transistor and a first operational amplifier, wherein the input end of the junction field effect transistor is connected with the output end of the signal isolation module, the output end of the junction field effect transistor is connected with the non-inverting input end of the first operational amplifier, and the output end of the junction field effect transistor is also connected with a capacitor device so as to store the received high-level signal through the capacitor device; the inverting input end of the first operational amplifier is connected with the output end of the first operational amplifier so as to reduce the interference of the high-level signal on the control module.
The signal isolation module comprises a second operational amplifier; the positive input end of the second operational amplifier is connected with the IO bus of the digital chip, the output end of the second operational amplifier is connected with the input end of the junction field effect transistor, and the negative input end of the second operational amplifier is connected with the output end of the junction field effect transistor.
The output end of the junction field effect transistor is also connected with a resistor device through a switch, and after detection is completed, the switch conducts the voltage device and the resistor device so as to release the high-level signal.
The control module is an MCU, and an ADC interface is arranged on the control module so as to receive the level signal output by the chip through the ADC interface and convert the level signal into an amplitude value of the chip.
The beneficial effects of this application are: the signal isolation module is used for receiving the level signal of the chip and transmitting the level signal to the amplitude maintaining module, the amplitude maintaining module is used for maintaining the level signal at the maximum amplitude of the level signal, the control module is used for receiving the maximum amplitude of the level signal and converting the maximum amplitude of the level signal into the output voltage amplitude of the chip, and therefore the signal amplitude value of the chip in the test is measured.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a first embodiment of a signal amplitude measuring device of a chip of the present application;
FIG. 2 is a first circuit diagram of a chip signal amplitude measuring device according to the present application;
FIG. 3 is a second circuit diagram of the chip signal amplitude measuring device of the present application;
fig. 4 is a schematic structural diagram of a second embodiment of a signal amplitude measuring device of the chip of the present application.
Detailed Description
The following describes the embodiments of the present application in detail with reference to the drawings.
In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, interfaces, techniques, etc., in order to provide a thorough understanding of the present application.
The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise, the "plurality" generally includes at least two, but does not exclude the case of at least one.
It should be understood that the term "and/or" as used herein is merely one relationship describing the association of the associated objects, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship. The terms first, second and the like in the description and in the claims of the present application and in the above-described figures, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.
It should be understood that the terms "comprises," "comprising," or any other variation thereof, as used herein, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.
It should be noted that, in the embodiment of the present application, directional indications (such as up, down, left, right, front, and rear … …) are referred to, and the directional indications are merely used to explain the relative positional relationship, movement conditions, and the like between the components in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indications are correspondingly changed.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
The present application provides a first chip signal amplitude measurement device, referring to fig. 1 specifically, fig. 1 is a schematic structural diagram of a first embodiment of the chip signal amplitude measurement device of the present application, as shown in fig. 1, where the chip signal amplitude measurement device includes: chip 10, signal isolation module 11, amplitude maintenance module 12 and control module 13.
The input end of the signal isolation module 11 is connected with the IO bus of the chip 10, and is used for receiving the IO bus of the chip 10, receiving the level signal of the chip 10, and isolating the received level signal from the signal on the IO bus of the chip 10, so as to avoid the signal flowing into the measuring device from affecting the signal transmission of the original circuit of the chip 10.
In the present embodiment, the chip 10 is a digital chip, and in other embodiments, the chip 10 may be an analog chip or other memory chip, which is not limited herein.
In one embodiment, the signal amplitude measuring device further includes a test socket (not shown in fig. 1), where the test socket is used to fix and mount the chip 10, and the test socket corresponds to a plurality of interfaces, including a plurality of IO bus interfaces or other interfaces, which are not limited herein. Each interface may be connected to a metal trace to turn on signals. In this embodiment, the IO bus corresponding to the IO bus interface on the test socket is connected to the chip 10 and the signal isolation module 11 respectively, so that the chip 10 and the signal isolation module 11 form signal conduction.
The input end of the amplitude maintaining module 12 is connected to the output end of the signal isolation module 11, and is configured to receive the level signal of the chip 10 and maintain the level signal at the maximum amplitude, so as to measure the amplitude value of the level signal of the chip 10 conveniently.
The control module 13 is connected to the output end of the amplitude maintaining module 12, so as to receive the maximum amplitude of the level signal, and convert the level signal into the output voltage value of the chip 10, thereby obtaining the maximum amplitude of the output voltage of the chip 10. Thereby measuring the amplitude of the output signal of the chip 10.
In this embodiment, the control module 13 may be an MCU controller. The control module 13 is provided with an ADC interface, and a trace on the ADC interface is connected to an output end of the amplitude maintaining module 12, so as to receive a level signal output by the chip 10 through the ADC interface, and convert the level signal into an output voltage value of the chip. Wherein the maximum amplitude of the level signal corresponds to the maximum amplitude of the output voltage of the chip 10.
The beneficial effects of this embodiment are: the maximum amplitude of the level signal of the chip is collected and held by the amplitude holding module, the maximum amplitude is detected by the control module, and the maximum amplitude of the level signal is converted into the maximum output voltage amplitude of the chip by the ADC of the control module, so that the signal amplitude value of the chip is measured, and the good grade of the chip is screened out.
The application further provides a circuit diagram corresponding to the first signal amplitude measuring device, and referring to fig. 2 specifically, fig. 2 is a first circuit diagram of the chip signal amplitude measuring device. Fig. 2 is a circuit diagram corresponding to fig. 1, and as shown in fig. 2, the signal isolation module 11 includes at least one second operational amplifier 111. The amplitude maintaining module 12 includes at least one junction field effect transistor 121 and a first operational amplifier 122 and a capacitor device 123.
The high-level signal of the chip is collected through the junction field effect transistor 121 and is held through the capacitor device 123, so that the control module can conveniently detect the high-level signal.
Specifically, the non-inverting input end of the second operational amplifier 111 is connected to the IO bus of the chip 10, and the output end of the second operational amplifier 111 is connected to the input end of the junction field effect transistor 121, so as to transmit the level signal of the chip 10 to the junction field effect transistor 121 for collection. The inverting input terminal of the second operational amplifier 111 is connected to the output terminal of the junction field effect transistor 121 to receive the feedback signal of the junction field effect transistor 121 and gradually reach a voltage signal equal to the non-inverting input terminal, so as to reduce the load voltage of the IO bus of the chip 10, and isolate the electrical signal input to the signal isolation module 11 to affect the normal signal transmission of the IO bus of the chip 10.
The input end of the junction field effect transistor 121 is connected with the output end of the signal isolation module 11, the output end is connected with the non-inverting input end of the first operational amplifier 122, and the output end of the junction field effect transistor 121 is also connected with a capacitor device 123, so that the high-level signal received by the junction field effect transistor 121 is stored through the capacitor device 123. The inverting input terminal of the first operational amplifier 122 is connected to the output terminal thereof, and receives the feedback signal from the output terminal thereof and gradually reaches the voltage equal to the non-inverting input terminal thereof, thereby reducing the load voltage of the junction field effect transistor 121, avoiding the output terminal of the junction field effect transistor 121 from discharging too fast, and further, avoiding the output voltage of the junction field effect transistor 121 from affecting the test voltage of the control module 13.
In this embodiment, a junction field effect transistor and a capacitor device are used to collect the signal amplitude voltage of the chip when the chip is in a high level signal, and the first operational amplifier and the second operational amplifier are used to isolate the load influence on the original circuit when the junction field effect transistor collects the signal voltage of the chip, so that the signal amplitude value of the chip is measured while the normal signal transmission of the original circuit is ensured.
The application further provides a circuit diagram corresponding to the second chip signal amplitude measuring device, and specifically please refer to fig. 3, fig. 3 is a second circuit diagram of the chip signal amplitude measuring device. As shown in fig. 3, the signal isolation module 11 includes at least one second operational amplifier 111. The amplitude maintaining module 12 includes at least one junction field effect transistor 121 and a first operational amplifier 122 and a capacitor device 123. The specific connection manner is described with reference to fig. 2, and is not described herein.
In this embodiment, the output end of the junction field effect transistor 121 of the amplitude holding module 12 is further connected to a switch 124 and a resistor device 125 controlled by the switch 124. One end of the resistor 125 is grounded to the output end of the junction field effect transistor 121 through the switch 124, and the other end is controlled to be opened and closed by the control switch 124, so that the resistor 125 is controlled to be conducted with the output end of the junction field effect transistor 121 or the capacitor 123 after detection is completed, and an electric signal on the output end of the junction field effect transistor 121 or the capacitor 123 is released, so that measurement of a next chip is facilitated. Meanwhile, the switch 124 controls the resistor 125 to be disconnected from the output end of the junction field effect transistor 121 or the capacitor 123 during detection, so that the capacitor 123 maintains the voltage signal of the output end of the junction field effect transistor 121, and the signal amplitude value of the current chip is measured.
In this embodiment, by adding a controllable connected resistor device in the signal amplitude holding circuit, the device is used for discharging after the measurement is finished and eliminating possible ripples, thereby improving the reliability of the measurement circuit.
The present application further provides a second chip signal amplitude measurement device, and referring specifically to fig. 4, fig. 4 is a schematic structural diagram of a second embodiment of the chip signal amplitude measurement device. The second chip signal amplitude measuring device is specifically applied to the SLT test, and therefore, may also be referred to as a chip signal amplitude measuring device in the SLT test. As shown in fig. 4, the signal amplitude measuring device of the chip in the SLT test includes:
the input end of the signal isolation module 41 is connected with the IO bus of the chip 401, and is used for receiving the level signal of the chip 401 and isolating the level signal from the IO bus of the chip 401.
And the amplitude maintaining module 42, wherein an input end of the amplitude maintaining module 42 is connected with an output end of the signal isolation module 41, and is used for receiving the level signal acquired by the signal isolation module 41 and maintaining the level signal on the high level signal.
The control module 43, the control module 43 is connected with the output end of the amplitude keeping module 42, so as to receive the high-level signal, and convert the received high-level signal into the signal amplitude value of the chip 401.
The main control module 44, the main control module 44 may be a main controller, for inputting signals to the chip 401. In a specific embodiment, the chip 401 is a digital chip, and the main control module 44 inputs a digital signal to the chip 401. Specifically, the main control module 44 is connected to the chip 401 through an IO bus, so as to input a digital signal to the chip 401, and the chip 401 outputs a level signal after receiving the digital signal.
In a specific embodiment, the signal amplitude measuring device further includes a test socket 40, where the test socket 40 is used to fix and mount the chip 401, and a plurality of interfaces corresponding to the test socket 40 include a plurality of IO bus interfaces or other interfaces, which are not limited herein. Each interface may be connected to a metal trace to turn on signals. In a specific embodiment, the IO bus corresponding to the IO bus interface on the test socket 40 is connected to the chip 401, the signal isolation module 41 and the main control module 44 respectively, so that the chip 401 is in signal conduction with the signal isolation module 41 and the main control module 44 respectively through the IO bus interface. So that the chip 401 receives the signal input by the main control module 44 and outputs a corresponding level signal according to the input signal.
In this embodiment, the chip 401 is connected to the signal isolation module 41 and the main control module 44 through the IO bus respectively, so as to receive the signal input by the main control module 44, and output a corresponding level signal to the signal isolation module 41 according to the input signal. The main control module 44 inputs a digital signal "1" to the chip 401, so that the chip 401 outputs a high level signal.
In an embodiment, the IO bus interface on the test socket 40 may draw out a plurality of IO buses at the same time, where the signal isolation module 41 may be connected to one of the IO bus interfaces. The main control module 44 is connected to the plurality of IO buses to continuously input signals to the chip.
In this embodiment, the main control module 44 is further connected to the signal isolation module 41 through the IO bus interface, so as to detect a signal written into the chip 401 of the main control module 44 through the signal isolation module 41, so as to detect whether the signal written into the chip 401 by the main control module 44 is normal.
In this embodiment, the chip 401 is a digital chip, and after receiving the digital signal input by the main control module 44, the digital chip converts the digital signal into a level signal. The level signals include a high level signal and a low level signal. In this embodiment, the main control module 44 can continuously write the digital signal "1" into the chip 401 to keep the chip 401 at the high level signal output, so as to facilitate amplitude detection.
In this embodiment, the control module 43 is further provided with a serial interface UART, and the control module 43 is connected with the main control module 44 through a UART interface to control the signals input by the main control module 44 to the chip 401. The control module 43 can control the main control module 44 to continuously input the digital signal "1" into the chip 401.
In this embodiment, the control module 43 is an MCU system for SLT testing and amplitude detection of the control chip 401.
In this embodiment, the control module 43 further includes an ADC interface, and is connected to the output end of the amplitude maintaining module 42 through the ADC interface, so as to convert the high level signal of the chip 401 into a signal amplitude value, thereby detecting the output signal amplitude value of the chip 401.
The beneficial effects of this embodiment are: by adding the signal isolation module and the amplitude holding module in the conventional SLT test, the control module can control the main control module to input test signals to the chip to perform SLT test on the chip, and meanwhile, the control module can measure the amplitude value of the chip through the signal isolation module and the amplitude holding module, so that the chip with excellent performance is screened out, the chip with poor performance is eliminated, and a plurality of devices are not required to be added. The circuit structures of the signal isolation module and the amplitude holding module are further shown in fig. 2 and 3, and the detailed description is omitted herein.
The foregoing is only the embodiments of the present application, and not the patent scope of the present application is limited by the foregoing description, but all equivalent structures or equivalent processes using the contents of the present application and the accompanying drawings, or directly or indirectly applied to other related technical fields, which are included in the patent protection scope of the present application.
Claims (10)
1. A chip signal amplitude measurement device, characterized in that the signal amplitude measurement device comprises:
the input end of the signal isolation module is connected with the IO bus of the chip and is used for receiving the level signal of the chip and isolating the level signal from the IO bus of the chip;
the input end of the amplitude maintaining module is connected with the output end of the signal isolation module and is used for receiving the level signal, sampling the level signal and maintaining the maximum amplitude of the level signal;
the control module is connected with the output end of the amplitude maintaining module to receive the maximum amplitude of the level signal and convert the received maximum amplitude of the level signal into the output voltage amplitude of the chip.
2. The chip signal amplitude measurement device of claim 1, further comprising a master control module connected to the chip through the IO bus interface to input signals to the chip.
3. The chip signal amplitude measurement device according to claim 1 or 2, further comprising a test socket, wherein the test socket is used for fixing the chip, and an IO bus interface is arranged on the test socket, so that the chip is connected with the signal isolation module or the main control module through the IO bus interface respectively.
4. The apparatus for measuring amplitude of a chip signal according to claim 2, wherein,
the signal isolation module is also connected with the main control module through the IO bus interface so as to detect signals input by the main control module to the chip.
5. The chip signal amplitude measurement device according to claim 1, wherein the chip is a digital chip; the digital chip receives the digital signal input by the main control module and converts the digital signal into a level signal.
6. The chip signal amplitude measuring device according to claim 3, wherein the control module is provided with a serial interface, and is connected with the main control module through the serial interface, so as to control the signal input by the main control module to the chip.
7. The apparatus of claim 1, wherein the chip signal amplitude measuring means,
the amplitude maintaining module comprises a junction field effect transistor and a first operational amplifier, wherein the input end of the junction field effect transistor is connected with the output end of the signal isolation module, the output end of the junction field effect transistor is connected with the non-inverting input end of the first operational amplifier, and the output end of the junction field effect transistor is also connected with a capacitor device so as to store the received high-level signal through the capacitor device;
the inverting input end of the first operational amplifier is connected with the output end of the first operational amplifier so as to reduce the interference of the high-level signal on the control module.
8. The chip signal amplitude measurement device of claim 7, wherein the signal isolation module comprises a second operational amplifier;
the positive input end of the second operational amplifier is connected with the IO bus of the chip, the output end of the second operational amplifier is connected with the input end of the junction field effect transistor, and the negative input end of the second operational amplifier is connected with the output end of the junction field effect transistor.
9. The device according to claim 7, wherein the output terminal of the junction field effect transistor is further connected to a resistor device through a switch, and the switch turns on the voltage device and the resistor device to release the high level signal after the detection is completed.
10. The chip signal amplitude measurement device according to claim 1, wherein the control module is an MCU, and an ADC interface is provided on the control module, so as to receive a level signal output by the chip through the ADC interface, and convert the level signal into a voltage amplitude value of the chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210942928.6A CN117554774A (en) | 2022-08-05 | 2022-08-05 | Chip signal amplitude measuring device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210942928.6A CN117554774A (en) | 2022-08-05 | 2022-08-05 | Chip signal amplitude measuring device |
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| Publication Number | Publication Date |
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| CN117554774A true CN117554774A (en) | 2024-02-13 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202210942928.6A Pending CN117554774A (en) | 2022-08-05 | 2022-08-05 | Chip signal amplitude measuring device |
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| CN (1) | CN117554774A (en) |
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- 2022-08-05 CN CN202210942928.6A patent/CN117554774A/en active Pending
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