CN117542857A - Semiconductor structure and preparation method thereof - Google Patents

Semiconductor structure and preparation method thereof Download PDF

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Publication number
CN117542857A
CN117542857A CN202210917695.4A CN202210917695A CN117542857A CN 117542857 A CN117542857 A CN 117542857A CN 202210917695 A CN202210917695 A CN 202210917695A CN 117542857 A CN117542857 A CN 117542857A
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doped region
type
type doped
well
region
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宋彬
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8252—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices

Abstract

The embodiment of the disclosure provides a semiconductor structure and a preparation method thereof. The semiconductor structure includes: a substrate; the N-type well and the P-type well are adjacently arranged in the substrate; the first N-type doped region and the first P-type doped region are positioned in the N-type well; the first P-type doped region is configured to be connected with the anode; the second N-type doped region and the second P-type doped region are positioned in the P-type well; the second N-type doped region is configured to be connected with the negative electrode; the first N-type doped region is electrically connected with the second P-type doped region; the third P-type doped region is positioned in the N-type well, below the first P-type doped region and is adjacently arranged with the first P-type doped region; the doping concentration of the third P-type doping region is greater than that of the first P-type doping region; the third N-type doped region is positioned in the P-type well, below the second N-type doped region and is adjacently arranged with the second N-type doped region; the doping concentration of the third N-type doped region is greater than that of the second N-type doped region.

Description

Semiconductor structure and preparation method thereof
Technical Field
The disclosure relates to the technical field of semiconductors, and in particular relates to a semiconductor structure and a preparation method thereof.
Background
An Electro-Static discharge (ESD) phenomenon refers to a charge transfer phenomenon occurring when objects having different electric potentials are close to or in contact with each other, and a large current is generated during the discharge due to an extremely short discharge time; for integrated circuits, chips are more susceptible to damage caused by electrostatic discharge (ESD), and such high currents can damage or even burn out internal devices, resulting in chip failure; the electrostatic discharge phenomenon is likely to occur in each link of the chip production, transportation and use, so that the ESD protection measures of the chip are indispensable for the reliability of the chip.
The direct-connected triggered silicon controlled rectifier (for example, nwell to Pwell Directly Connected Silicon-Controlled Rectifier) is an SCR device with low trigger voltage, has the advantages of small resistance, high robustness and the like, and is widely applied to ESD protection under advanced process. However, DCSCR has a problem of a slow turn-on speed and a high overshoot voltage.
Disclosure of Invention
Accordingly, embodiments of the present disclosure provide a semiconductor structure and a method for fabricating the same to solve at least one of the problems in the prior art.
In order to achieve the above object, the technical solution of the embodiments of the present disclosure is implemented as follows:
a first aspect of embodiments of the present disclosure provides a semiconductor structure comprising: a substrate; the N-type well and the P-type well are adjacently arranged in the substrate; the first N-type doped region and the first P-type doped region are positioned in the N-type well; the first P-type doped region is configured to be connected with an anode; the second N-type doped region and the second P-type doped region are positioned in the P-type well; the second N-type doped region is configured to be connected with a negative electrode; the first N-type doped region is electrically connected with the second P-type doped region; the third P-type doped region is positioned in the N-type well, below the first P-type doped region and is adjacently arranged with the first P-type doped region; the doping concentration of the third P-type doping region is larger than that of the first P-type doping region; the third N-type doped region is positioned in the P-type well, below the second N-type doped region and is adjacently arranged with the second N-type doped region; the doping concentration of the third N-type doping region is larger than that of the second N-type doping region.
In some embodiments, the substrate is a P-type substrate; the N-type well surrounds the P-type well and exposes a side of the P-type well away from the substrate.
In some embodiments, the semiconductor structure further comprises an N-type deep well within the substrate, at least the P-type well of the N-type well and the P-type well being disposed on the N-type deep well.
In some embodiments, the semiconductor structure further includes a fourth P-type doped region within the substrate, the fourth P-type doped region surrounding the N-well.
In some embodiments, the substrate is an N-type substrate; the P-well surrounds the N-well and exposes a side of the N-well remote from the substrate.
In some embodiments, the semiconductor structure further comprises a P-type deep well within the substrate, at least the N-type well of the N-type well and the P-type well being disposed on the P-type deep well.
In some embodiments, the semiconductor structure further includes a fourth N-type doped region within the substrate, the fourth N-type doped region surrounding the P-type well.
In some embodiments, the first P-type doped region is located between the first N-type doped region and the second P-type doped region; the second N-type doped region is located between the second P-type doped region and the first P-type doped region.
In some embodiments, the semiconductor structure further comprises an isolation structure; the isolation structure includes a first isolation structure between the first N-type doped region and the first P-type doped region, a second isolation structure between the first P-type doped region and the second N-type doped region, a third isolation structure between the second N-type doped region and the second P-type doped region, a fourth isolation structure between the second P-type doped region and the fourth P-type doped region or the fourth N-type doped region, and a fifth isolation structure between the first N-type doped region and the fourth P-type doped region or the fourth N-type doped region.
In some embodiments, the first P-type doped region, the third P-type doped region, the N-type well, and the P-type well form a PNP transistor; the first P-type doped region and the third P-type doped region are emitters of the PNP-type transistor.
In some embodiments, the second N-doped region, the third N-doped region, the P-well, and the N-well form an NPN transistor; the second N-type doped region and the third N-type doped region are emitters of the NPN transistor.
In some embodiments, the N-well has a first resistance; the first resistor is connected with the base electrode of the PNP transistor; the base of the PNP transistor is connected with the collector of the NPN transistor.
In some embodiments, the P-well has a second resistance; the second resistor is connected with the base electrode of the NPN transistor; the base of the NPN transistor is connected with the collector of the PNP transistor.
In some embodiments, the first P-type doped region, the third P-type doped region, the N-type well, and the first N-type doped region form a first diode; the second N-type doped region, the third N-type doped region, the P-type well and the second P-type doped region form a second diode.
A second aspect of embodiments of the present disclosure provides a method for manufacturing a semiconductor structure, the method including: providing a substrate; forming an N-type well and a P-type well which are adjacently arranged in the substrate; forming a first N-type doped region and a first P-type doped region in the N-type well; forming a third P-type doped region adjacent to the first P-type doped region in the N-type well and below the first P-type doped region through a first ion implantation process; the doping concentration of the third P-type doping region is larger than that of the first P-type doping region; forming a second N-type doped region and a second P-type doped region in the P-type well; forming a third N-type doped region adjacent to the second N-type doped region in the P-type well and below the second N-type doped region through a second ion implantation process; the doping concentration of the third N-type doping region is larger than that of the second N-type doping region.
A third aspect of embodiments of the present disclosure provides a method for manufacturing a semiconductor structure, the method including: providing a substrate; forming an N-type well and a P-type well which are adjacently arranged in the substrate; forming a first N-type doped region in the N-type well; forming a third P-type doped region in the N-type well through a first ion implantation process; forming a first P-type doped region adjacent to the third P-type doped region in the N-type well and on the third P-type doped region; the doping concentration of the third P-type doping region is larger than that of the first P-type doping region; forming a second P-type doped region in the P-type well; forming a third N-type doped region in the P-type well through a second ion implantation process; forming a second N-type doped region adjacent to the third N-type doped region in the P-type well and on the third N-type doped region; the doping concentration of the third N-type doping region is larger than that of the second N-type doping region.
In some embodiments, the first ion implantation process and the second ion implantation process are halo ion implantation processes.
Embodiments of the present disclosure provide a semiconductor structure and a method of fabricating the same, the semiconductor structure including: a substrate; the N-type well and the P-type well are adjacently arranged in the substrate; the first N-type doped region and the first P-type doped region are positioned in the N-type well; the first P-type doped region is configured to be connected with an anode; the second N-type doped region and the second P-type doped region are positioned in the P-type well; the second N-type doped region is configured to be connected with a negative electrode; the first N-type doped region is electrically connected with the second P-type doped region; the third P-type doped region is positioned in the N-type well, below the first P-type doped region and is adjacently arranged with the first P-type doped region; the doping concentration of the third P-type doping region is larger than that of the first P-type doping region; the third N-type doped region is positioned in the P-type well, below the second N-type doped region and is adjacently arranged with the second N-type doped region; the doping concentration of the third N-type doping region is larger than that of the second N-type doping region.
According to the PNP type transistor, the third P type doped region with the doping concentration larger than that of the first P type doped region is arranged below the first P type doped region, so that the first P type doped region and the third P type doped region jointly form the emitter of the PNP type transistor, the doping concentration of the emitter of the PNP type transistor and the size of the emitter region can be increased, the gain coefficient of the PNP type transistor is further increased, and the size of the base region of the PNP type transistor can be reduced due to the fact that the third P type doped region is formed in the N type well, and the gain coefficient of the PNP type transistor is further increased; meanwhile, a third N-type doped region with doping concentration larger than that of the second N-type doped region is arranged below the second N-type doped region, so that the second N-type doped region and the third N-type doped region jointly form an emitter of the NPN-type transistor, the doping concentration of the emitter of the NPN-type transistor and the size of the emitter region can be increased, the gain coefficient of the NPN-type transistor is further increased, and the size of the base region of the NPN-type transistor can be reduced due to the fact that the third N-type doped region is formed in the P-type well, and the gain coefficient of the NP N-type transistor is further increased. By increasing the gain coefficients of the PNP transistor and the NPN transistor, the positive feedback of the PNP transistor and the NPN transistor can be established more quickly, so that the starting speed of a semiconductor structure formed by the PNP transistor and the NPN transistor can be increased, the overshoot voltage of the semiconductor structure can be reduced, and further the ESD protection can be realized more effectively.
Drawings
FIG. 1 is a schematic diagram of a DCSCR device provided by an embodiment of the present disclosure;
fig. 2 is a cross-sectional view of a semiconductor structure provided in an embodiment of the present disclosure;
fig. 3 is a top view of a semiconductor structure provided in an embodiment of the present disclosure;
fig. 4 is a circuit diagram corresponding to a semiconductor structure according to an embodiment of the disclosure;
FIG. 5 is a voltage variation diagram of a semiconductor structure according to an embodiment of the present disclosure;
fig. 6 is a schematic flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the disclosure;
fig. 7 is a flow chart illustrating a method for fabricating another semiconductor structure according to an embodiment of the disclosure.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known features have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.
In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.
It will be appreciated that spatially relative terms such as "under … …," "under … …," "below," "under … …," "over … …," "above," and the like may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under … …" and "under … …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Fig. 1 is a schematic diagram of a DCSCR device according to an embodiment of the present disclosure. As shown in fig. 1, the DCSCR device includes a substrate 110 and N-type deep well 120, N-type well 130, and P-type well 140 within substrate 110. Wherein the P-type well 140 and the N-type well 130 are adjacently disposed and are both located on the N-type deep well 120, and the P-type well 140 is surrounded by the N-type well 130. The DCSCR device further includes a first N-type doped region 151 and a first P-type doped region 161 located within the N-type well 130, and a second N-type doped region 152 and a second P-type doped region 162 located within the P-type well 140. The first P-type doped region 161 is located between the first N-type doped region 151 and the second P-type doped region 162, the second N-type doped region 152 is located between the second P-type doped region 162 and the first P-type doped region 161, and the first N-type doped region 151 and the first P-type doped region 161 are located in the N-type well. The first P-type doped region 161 is configured to connect to the positive electrode and the second N-type doped region 152 is configured to connect to the negative electrode. The first N-type doped region 151 and the second P-type doped region 162 are electrically connected through an interconnection line 180.
The DCSCR device also includes a fourth P-type doped region 164 located within the substrate 110, wherein the fourth P-type doped region 164 is located on a side of the N-well 130 remote from the P-well 140. Isolation structures 170 are disposed between the fourth P-type doped region 164 and the first N-type doped region 151, between the first N-type doped region 151 and the first P-type doped region 161, between the second N-type doped region 152 and the second P-type doped region 162, and between the second P-type doped region 162 and the fourth P-type doped region 164.
As shown in fig. 1, the first P-type doped region 161, the N-type well 130 and the first N-type doped region 151 form one diode, and the second P-type doped region 162, the P-type well 140 and the second N-type doped region 152 form another diode; the first P-type doped region 161, the N-type well 130 and the P-type well 140 form a PNP transistor, wherein the first P-type doped region 161 is an emitter of the PNP transistor, the N-type well 130 is a base of the PNP transistor, and the P-type well 140 is a collector of the PNP transistor; the second N-doped region 152, the P-well 140 and the N-well 130 form an NPN transistor, wherein the second N-doped region 152 is an emitter of the NPN transistor, the P-well 140 is a base of the NPN transistor, and the N-well 130 is a collector of the NPN transistor.
When ESD occurs, since the first P-type doped region 161 is connected to the positive electrode and the second N-type doped region 152 is connected to the negative electrode, current will first flow through the diode formed by the first P-type doped region 161, the N-type well 130 and the first N-type doped region 151, and then through the diode formed by the second P-type doped region 162, the P-type well 140 and the second N-type doped region 152 via the interconnect 180, and when the voltages of the two diodes reach their turn-on voltages, the two diodes are turned on, and the DCSCR device is triggered. At this time, since the PN junction formed by the first P-type doped region 161 and the N-type well 130 is forward biased, the PNP transistor formed by the first P-type doped region 161, the N-type well 130 and the P-type well 140 is turned on; similarly, since the PN junction formed by the P-well 140 and the second N-doped region 152 is forward biased, the NPN transistor formed by the second N-doped region 152, the P-well 140 and the N-well 130 is turned on. The collector current of the PNP transistor provides the base current for the NPN transistor, and the collector current of the NPN transistor provides the base current for the PNP transistor, so that the PNP transistor and the NPN transistor form a current positive feedback mechanism, and further, a current drain path formed by the first P-type doped region 161, the N-type well 130, the P-type well 140, and the second N-type doped region 152 is turned on, so as to drain the ESD current, thereby realizing ESD protection.
When ESD occurs, the voltage of the DCSCR device will first rise to a larger value (i.e., an overshoot voltage) and then gradually decrease until it is substantially stable within a certain voltage range. The DCSCR device shown in fig. 1 has a higher overshoot voltage. In addition, the DCSCR device has the problem of slower starting speed.
To this end, embodiments of the present disclosure provide a semiconductor structure. Fig. 2 is a cross-sectional view of a semiconductor structure according to an embodiment of the disclosure, and fig. 3 is a top view of the semiconductor structure according to the embodiment of the disclosure. Note that fig. 2 is a cross-sectional view of the semiconductor structure shown in fig. 3 along line AA. As shown in connection with fig. 2 and 3, the semiconductor structure includes a substrate 110 and N-type well 130 and P-type well 140 disposed adjacent within substrate 110. In some embodiments, substrate 110 is a P-type substrate. The material of the P-type substrate may be silicon, germanium, gallium arsenide (GaAs), indium phosphide (InP), or gallium nitride (GaN), or may be silicon-on-insulator (SOI) or germanium-on-insulator (GOI), or may be other materials, such as gallium arsenide, or other group iii-v compounds. The N-well 130 surrounds the P-well 140 and exposes a side of the P-well 140 away from the substrate 110. As shown in fig. 3, P-well 140 is surrounded by N-well 130. In some embodiments, the semiconductor structure further includes an N-type deep well 120. As shown in fig. 2, at least P-type well 140 of N-type well 130 and P-type well 140 is located on N-type deep well 120, and N-type well 130 and N-type deep well 120 surround the portion of P-type well 140 located in substrate 110 to isolate P-type well 140 from substrate 110. Wherein the N-type well 130 and the N-type deep well 120 may be formed by implanting N-type ions into the substrate 110 through an ion implantation process, for example, the N-type ions may be one or more of phosphorus (P) ions, arsenic (As) ions, and antimony (Sb) ions; the P-type well 140 may be formed by implanting P-type ions into the substrate 110 through an ion implantation process, for example, the P-type ions may be one or more of boron (B) ions, boron fluoride (bf2+) ions, gallium (Ga) ions, and indium (In) ions.
The semiconductor structure further includes a first N-type doped region 151, a first P-type doped region 161, and a third P-type doped region 163 located within the N-type well 130, and a second N-type doped region 152, a third N-type doped region 153, and a second P-type doped region 162 located within the P-type well 140. Wherein, the first N-type doped region 151, the first P-type doped region 161 and the third P-type doped region 163 may be formed by respectively implanting N-type ions and P-type ions into the N-type well 130 through an ion implantation process; the second N-type doped region 152, the third N-type doped region 153, and the second P-type doped region 162 may be formed by implanting N-type ions and P-type ions into the P-type well 140, respectively, through an ion implantation process. It should be noted that the P-well 140 is surrounded by the N-well 130, and the first N-doped region 151, the first P-doped region 161, and the third P-doped region 163 are located in the N-well 130. The first P-type doped region 161 is located between the first N-type doped region 151 and the second P-type doped region 162, the first P-type doped region 161 is configured to be connected to the positive electrode, the third P-type doped region 163 is located below the first P-type doped region 161 and is adjacent to the first P-type doped region 161, and the doping concentration of the third P-type doped region 163 is greater than the doping concentration of the first P-type doped region 161; the second N-doped region 152 is located between the second P-doped region 162 and the first P-doped region 161, the second N-doped region 152 is configured to be connected to the negative electrode, the third N-doped region 153 is located below the second N-doped region 152 and is disposed adjacent to the second N-doped region 152, and the doping concentration of the third N-doped region 153 is greater than the doping concentration of the second N-doped region 152. The first N-type doped region 151 and the second P-type doped region 162 are electrically connected through an interconnection line 180. In some embodiments, interconnect 180 is a metal (metal) interconnect.
The semiconductor structure further includes an isolation structure and a fourth P-type doped region 164 located within the substrate 110. The fourth P-type doped region 164 may be formed by implanting P-type ions into the substrate 110 through an ion implantation process. The isolation structures may be formed by etching first to form isolation openings and then depositing an insulating material (e.g., silicon oxide or silicon oxynitride) in the isolation openings to form the isolation structures. For example, the top of the isolation structure is at least not lower than the top of the first N-type doped region 151, the first P-type doped region 161, the second N-type doped region 152, the second P-type doped region 162, and the fourth P-type doped region 164, and the bottom of the isolation structure is at least not higher than the bottoms of the first N-type doped region 151, the first P-type doped region 161, the second N-type doped region 152, the second P-type doped region 162, and the fourth P-type doped region 164. As shown in fig. 3, the fourth P-type doped region 164 surrounds the N-well 130. Wherein the fourth P-type doped region 164 is used to fix the potential of the substrate 110. In some embodiments, substrate 110 is grounded through fourth P-type doped region 164. As shown in fig. 2, the isolation structure includes a first isolation structure 171 between the first N-type doped region 151 and the first P-type doped region 161, a second isolation structure 172 between the first P-type doped region 161 and the second N-type doped region 152, a third isolation structure 173 between the second N-type doped region 152 and the second P-type doped region 162, a fourth isolation structure 174 between the second P-type doped region 162 and the fourth P-type doped region 164, and a fifth isolation structure 175 between the fourth P-type doped region 164 and the first N-type doped region 151. In some embodiments, the first isolation structure 171, the second isolation structure 172, the third isolation structure 173, the fourth isolation structure 174, and the fifth isolation structure 175 are formed in the same step. In some embodiments, the isolation structure may be a shallow trench isolation structure (Shallow Trench Isolation, STI). Note that the isolation structures and the interconnect lines 180 are not shown in fig. 3.
In other embodiments, the substrate is an N-type substrate. The P-type well surrounds the N-type well and exposes a side of the N-type well away from the N-type substrate. The semiconductor structure further includes a P-type deep well within the N-type substrate, wherein at least the N-type well of the N-type well and the P-type well is disposed on the P-type deep well, and the P-type well and the P-type deep well surround a portion of the N-type well located in the N-type substrate to isolate the N-type well from the N-type substrate. The semiconductor structure further includes a fourth N-type doped region within the substrate, the fourth N-type doped region surrounding the P-well. The fourth N-type doped region is used for fixing the potential of the N-type substrate. In some embodiments, the N-type substrate is grounded through a fourth N-type doped region. The fourth isolation structure is positioned between the second P-type doped region and the fourth N-type doped region, and the fifth isolation structure is positioned between the first N-type doped region and the fourth N-type doped region.
Referring back to fig. 2, the first P-type doped region 161, the third P-type doped region 163, the N-type well 130 and the first N-type doped region 151 form a first diode, wherein the first P-type doped region 161 and the third P-type doped region 163 are the anode of the first diode, and the N-type well 130 and the first N-type doped region 151 are the cathode of the first diode; the second P-doped region 162, the P-well 140, the third N-doped region 153 and the second N-doped region 152 form a second diode, wherein the second P-doped region 162 and the P-well 140 are anodes of the second diode, and the third N-doped region 153 and the second N-doped region 152 are cathodes of the second diode. The first N-type doped region 151 and the second P-type doped region 162 are electrically connected through the interconnection line 180, that is, the cathode of the first diode and the anode of the second diode are electrically connected.
The first P-type doped region 161, the third P-type doped region 163, the N-type well 130 and the P-type well 140 form a PNP transistor. The first P-type doped region 161 and the third P-type doped region 163 are emitters of PNP transistors, the N-well 130 is a base of a PNP transistor, and the P-well 140 is a collector of a PNP transistor; the second N-doped region 152, the third N-doped region 153, the P-well 140 and the N-well 130 form an NPN transistor. The second N-doped region 152 and the third N-doped region 153 form an emitter of an NPN transistor, the P-well 140 forms a base of the NPN transistor, and the N-well 130 forms a collector of the NPN transistor.
Fig. 4 is a circuit diagram corresponding to a semiconductor structure according to an embodiment of the disclosure. As shown in fig. 4, the base of the PNP transistor is connected to the collector of the NPN transistor, and the base of the NPN transistor is connected to the collector of the PNP transistor. N-well 130 has a first resistance R NW First resistor R NW The base electrode of the PNP transistor is connected with the base electrode of the PNP transistor; the P-well 140 has a second resistance R PW A second resistor R PW Is connected with the base electrode of the NPN transistor. The emitter of the PNP transistor is connected with the positive voltage, and the emitter of the NPN transistor is connected with the negative voltage.
When ESD occurs, since the first P-type doped region 161 and the third P-type doped region 163 (i.e., the emitter of the PNP transistor) are connected to the positive electrode and the second N-type doped region 152 and the third N-type doped region 153 (i.e., the emitter of the NPN transistor) are connected to the negative electrode, current will first flow through the first diode formed by the first P-type doped region 161, the third P-type doped region 163, the N-type well 130 and the first N-type doped region 151, and then through the second diode formed by the second P-type doped region 162, the P-type well 140, the third N-type doped region 153 and the second N-type doped region 152 through the interconnect 180, and when the voltages of the first diode and the second diode reach their turn-on voltages, respectively, the first diode and the second diode are turned on, and the DCSCR device is triggered. At this time, since the PN junction formed by the first P-type doped region 161, the third P-type doped region 163 and the N-type well 130 is forward biased, the PNP transistor formed by the first P-type doped region 161, the third P-type doped region 163, the N-type well 130 and the P-type well 140 is turned on; similarly, since the PN junction formed by the P-type well 140, the third N-type doped region 153 and the second N-type doped region 152 is forward biased, the NPN transistor formed by the second N-type doped region 152, the third N-type doped region 153, the P-type well 140 and the N-type well 130 is turned on. The collector current of the PNP transistor provides the base current for the NPN transistor, and the collector current of the NPN transistor provides the base current for the PNP transistor, so that the PNP transistor and the NPN transistor form a current positive feedback mechanism, and a current drain path formed by the first P-type doped region 161, the third P-type doped region 163, the N-type well 130, the P-type well 140, the third N-type doped region 153, and the second N-type doped region 152 is turned on, so as to drain the ESD current, thereby realizing ESD protection.
In the semiconductor structure shown in fig. 2, a third P-type doped region 163 adjacent to the first P-type doped region 161 is disposed under the first P-type doped region 161 compared to the device shown in fig. 1, so that the first P-type doped region 161 and the third P-type doped region 163 having a doping concentration greater than that of the first P-type doped region 161 together form an emitter of a PNP transistor, and the doping concentration of the emitter of the PNP transistor formed by the first P-type doped region 161 and the third P-type doped region 163 together is greater and the emitter region is greater than that of the PNP transistor formed by the first P-type doped region 161 in fig. 1, so that the gain factor of the PNP transistor can be increased. Meanwhile, since the third P-type doped region 163 is formed in the N-type well 130, the region of the N-type well 130, which is the base of the PNP transistor, is made smaller, that is, the base region of the PNP transistor is made smaller, so that the gain factor of the PNP transistor can be further increased.
Similarly, in the semiconductor structure shown in fig. 2, the third N-type doped region 153 adjacent to the second N-type doped region 152 is disposed below the second N-type doped region 152, so that the second N-type doped region 152 and the third N-type doped region 153 with a doping concentration greater than that of the second N-type doped region 152 together form an emitter of the NPN transistor, and compared with the emitter of the NPN transistor formed by the second N-type doped region 152 in fig. 1, the doping concentration of the emitter of the NPN transistor formed by the second N-type doped region 152 and the third N-type doped region 153 together is greater and the emitter region is greater, so that the gain factor of the NPN transistor can be increased. Meanwhile, since the third N-type doped region 153 is formed in the P-type well 140, the region of the P-type well 140, which is the base of the NPN transistor, is made smaller, that is, the base region of the NPN transistor is made smaller, so that the gain factor of the NPN transistor can be further increased. By increasing the gain coefficients of the PNP transistor and the NPN transistor, the establishment of the current positive feedback mechanism formed by the PNP transistor and the NPN transistor can be accelerated, and thus the turn-on speed of the semiconductor structure can be increased and the overshoot voltage thereof can be reduced.
Fig. 5 is a voltage variation diagram of a semiconductor structure according to an embodiment of the present disclosure. As shown in fig. 5, the horizontal axis in fig. 5 represents time in nanoseconds (ns), and the vertical axis represents voltage in volts (V). Curve 501 represents the voltage change during operation of the device shown in fig. 1 and curve 502 represents the voltage change during operation of the semiconductor structure shown in fig. 2. As shown in fig. 5, the overshoot voltage of the device shown in fig. 1 is about 14.2V, and the on-time (i.e., the time required to reach the overshoot voltage) is about 0.8ns; the overshoot voltage of the semiconductor structure shown in fig. 2 is about 9V, and the turn-on time is about 0.75ns, and it is known that, compared with the device shown in fig. 1, the semiconductor structure shown in fig. 2 has smaller overshoot voltage, and the turn-on time is shorter, i.e. the turn-on speed is faster, so that the ESD protection can be more effectively realized.
The embodiment of the disclosure also provides a preparation method of the semiconductor structure. Fig. 6 is a flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of the disclosure, as shown in fig. 6, in step 601, a substrate is provided.
In step 602, an adjacently disposed N-type well and P-type well are formed within a substrate.
In step 603, a first N-type doped region and a first P-type doped region are formed within the N-type well.
In step 604, a third P-type doped region is formed in the N-well and under the first P-type doped region by a first ion implantation process. The doping concentration of the third P-type doping region is larger than that of the first P-type doping region.
In some embodiments, the first ion implantation process is a Halo ion implantation process (Halo Implant). Specifically, a third P-type doped region may be formed under the first P-type doped region by a P-type halo ion implantation process (P-type Halo Implant).
In step 605, a second N-type doped region and a second P-type doped region are formed within the P-type well.
In step 606, a third N-type doped region is formed in the P-well and under the second N-type doped region by a second ion implantation process. The doping concentration of the third N-type doping region is larger than that of the second N-type doping region.
In some embodiments, the second ion implantation process may also be a halo ion implantation process. Specifically, a third N-type doped region may be formed under the second N-type doped region by an N-type halo ion implantation process (N-type Halo Implant).
It should be appreciated that the above-described fabrication method may further include the step of forming an N-type deep well or P-type deep well, a fourth P-type doped region or a fourth N-type doped region, and an isolation structure. Some steps in the preparation method are not necessarily accurately executed in order, but a plurality of steps may be processed in any order or simultaneously.
The embodiment of the disclosure also provides a preparation method of another semiconductor structure. Fig. 7 is a flowchart illustrating another method for manufacturing a semiconductor structure according to an embodiment of the disclosure, as shown in fig. 7, in step 701, a substrate is provided.
In step 702, adjacently disposed N-type and P-type wells are formed in a substrate.
In step 703, a first N-type doped region is formed in the N-type well.
In step 704, a third P-type doped region is formed in the N-type well by a first ion implantation process.
In step 705, a first P-type doped region is formed in the N-well over the third P-type doped region adjacent to the third P-type doped region. The doping concentration of the third P-type doping region is larger than that of the first P-type doping region.
In step 706, a second P-type doped region is formed within the P-type well.
In step 707, a third N-type doped region is formed in the P-type well by a second ion implantation process.
In step 708, a second N-type doped region is formed in the P-well over the third N-type doped region adjacent to the third N-type doped region. The doping concentration of the third N-type doping region is larger than that of the second N-type doping region.
In some embodiments, the first ion implantation process and the second ion implantation process are both halo ion implantation processes.
The preparation process of the semiconductor structure provided by the embodiment of the disclosure is simple, the third P-type doped region and the third N-type doped region can be formed only by adding the first ion implantation process and the second ion implantation process in the original preparation process, the original process is not required to be greatly improved, and the process implementation cost is low.
It should be noted that, the description of the preparation method of the semiconductor structure is similar to the description of the embodiment of the semiconductor structure, and has similar beneficial effects as the embodiment of the semiconductor structure, so that a detailed description is omitted. For technical details not disclosed in the method for manufacturing a semiconductor structure according to the embodiments of the present disclosure, please refer to the description of the semiconductor structure according to the embodiments of the present disclosure for understanding.
It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present disclosure, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by their functions and internal logic, and should not constitute any limitation on the implementation of the embodiments of the present disclosure. The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments.
The methods disclosed in the several method embodiments provided in the present disclosure may be arbitrarily combined without collision to obtain a new method embodiment.
The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (17)

1. A semiconductor structure, the semiconductor structure comprising:
a substrate;
the N-type well and the P-type well are adjacently arranged in the substrate;
the first N-type doped region and the first P-type doped region are positioned in the N-type well; the first P-type doped region is configured to be connected with an anode;
the second N-type doped region and the second P-type doped region are positioned in the P-type well; the second N-type doped region is configured to be connected with a negative electrode; the first N-type doped region is electrically connected with the second P-type doped region;
the third P-type doped region is positioned in the N-type well, below the first P-type doped region and is adjacently arranged with the first P-type doped region; the doping concentration of the third P-type doping region is larger than that of the first P-type doping region;
the third N-type doped region is positioned in the P-type well, below the second N-type doped region and is adjacently arranged with the second N-type doped region; the doping concentration of the third N-type doping region is larger than that of the second N-type doping region.
2. The semiconductor structure of claim 1, wherein the substrate is a P-type substrate; the N-type well surrounds the P-type well and exposes a side of the P-type well away from the substrate.
3. The semiconductor structure of claim 2, further comprising an N-type deep well within the substrate, at least the P-type well of the N-type well and the P-type well being disposed over the N-type deep well.
4. The semiconductor structure of claim 3, further comprising a fourth P-type doped region within the substrate, the fourth P-type doped region surrounding the N-type well.
5. The semiconductor structure of claim 1, wherein the substrate is an N-type substrate; the P-well surrounds the N-well and exposes a side of the N-well remote from the substrate.
6. The semiconductor structure of claim 5, further comprising a P-type deep well within the substrate, at least the N-type well of the N-type well and the P-type well being disposed over the P-type deep well.
7. The semiconductor structure of claim 6, further comprising a fourth N-type doped region within the substrate, the fourth N-type doped region surrounding the P-type well.
8. The semiconductor structure of claim 4 or 7, wherein the first P-type doped region is located between the first N-type doped region and the second P-type doped region; the second N-type doped region is located between the second P-type doped region and the first P-type doped region.
9. The semiconductor structure of claim 8, wherein the semiconductor structure further comprises an isolation structure; the isolation structure includes a first isolation structure between the first N-type doped region and the first P-type doped region, a second isolation structure between the first P-type doped region and the second N-type doped region, a third isolation structure between the second N-type doped region and the second P-type doped region, a fourth isolation structure between the second P-type doped region and the fourth P-type doped region or the fourth N-type doped region, and a fifth isolation structure between the first N-type doped region and the fourth P-type doped region or the fourth N-type doped region.
10. The semiconductor structure of claim 1, wherein the first P-type doped region, the third P-type doped region, the N-type well, and the P-type well form a PNP transistor; the first P-type doped region and the third P-type doped region are emitters of the PNP-type transistor.
11. The semiconductor structure of claim 10, wherein the second N-doped region, the third N-doped region, the P-well, and the N-well form an NPN transistor; the second N-type doped region and the third N-type doped region are emitters of the NPN transistor.
12. The semiconductor structure of claim 11, wherein the N-well has a first resistance; the first resistor is connected with the base electrode of the PNP transistor; the base of the PNP transistor is connected with the collector of the NPN transistor.
13. The semiconductor structure of claim 11, wherein the P-well has a second resistance; the second resistor is connected with the base electrode of the NPN transistor; the base of the NPN transistor is connected with the collector of the PNP transistor.
14. The semiconductor structure of claim 1, wherein the first P-type doped region, the third P-type doped region, the N-type well, and the first N-type doped region form a first diode; the second N-type doped region, the third N-type doped region, the P-type well and the second P-type doped region form a second diode.
15. A method of fabricating a semiconductor structure, the method comprising:
providing a substrate;
forming an N-type well and a P-type well which are adjacently arranged in the substrate;
forming a first N-type doped region and a first P-type doped region in the N-type well;
forming a third P-type doped region adjacent to the first P-type doped region in the N-type well and below the first P-type doped region through a first ion implantation process; the doping concentration of the third P-type doping region is larger than that of the first P-type doping region;
forming a second N-type doped region and a second P-type doped region in the P-type well;
forming a third N-type doped region adjacent to the second N-type doped region in the P-type well and below the second N-type doped region through a second ion implantation process; the doping concentration of the third N-type doping region is larger than that of the second N-type doping region.
16. A method of fabricating a semiconductor structure, the method comprising:
providing a substrate;
forming an N-type well and a P-type well which are adjacently arranged in the substrate;
forming a first N-type doped region in the N-type well;
forming a third P-type doped region in the N-type well through a first ion implantation process;
forming a first P-type doped region adjacent to the third P-type doped region in the N-type well and on the third P-type doped region; the doping concentration of the third P-type doping region is larger than that of the first P-type doping region;
forming a second P-type doped region in the P-type well;
forming a third N-type doped region in the P-type well through a second ion implantation process;
forming a second N-type doped region adjacent to the third N-type doped region in the P-type well and on the third N-type doped region; the doping concentration of the third N-type doping region is larger than that of the second N-type doping region.
17. The method of claim 15 or 16, wherein the first ion implantation process and the second ion implantation process are halo ion implantation processes.
CN202210917695.4A 2022-08-01 2022-08-01 Semiconductor structure and preparation method thereof Pending CN117542857A (en)

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