CN117542796A

CN117542796A - Method for forming semiconductor structure

Info

Publication number: CN117542796A
Application number: CN202311241953.2A
Authority: CN
Inventors: 郑郁陵; 林育贤; 潘姿文; 陈嘉仁
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-10-06
Filing date: 2023-09-25
Publication date: 2024-02-09

Abstract

A method for forming a semiconductor structure. An example method includes forming a first transistor structure and a second transistor structure over a substrate, wherein each transistor structure includes at least one nano-sheet. The method further includes depositing a metal over each transistor structure and around each nanoplatelet; depositing a coating on the metal; depositing a mask over the coating; the patterned mask is used to define a patterned mask, wherein the patterned mask is positioned over the masked portion of the coating and the second transistor structure, and wherein the patterned mask is not positioned over the unmasked portion of the coating and the first transistor structure. The method further includes etching the unmasked portion of the coating and the metal over the first transistor structure using a dry etching process having a process pressure of from 30 to 60 (mTorr).

Description

Method for forming semiconductor structure

Technical Field

The present invention relates to a method for forming a semiconductor structure, and more particularly to a multiple patterning gate process.

Background

The semiconductor integrated circuit (integrated circuit, IC) industry has experienced rapid growth. Technological advances in IC materials and design have resulted in multi-generation ICs, each generation having smaller, more complex circuits than the previous generation. During IC evolution, functional density (i.e., the number of interconnects per chip area) typically increases while geometry (i.e., the smallest component (or line) that can be produced using a process) decreases. This miniaturized process generally provides benefits in terms of increased production efficiency and reduced costs associated therewith. This scaling down also increases the complexity of processing and manufacturing ICs.

For example, as Integrated Circuit (IC) technology advances to smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effects (SCEs). A multi-gate device generally refers to a device in which a gate structure or a portion thereof is disposed over more than one side of a channel region. Fin-like field effect transistors (finfets) and gate-all-around (GAA) transistors (both also referred to as non-planar transistors) are examples of multi-gate devices that have become popular and promising candidates for high performance and low leakage current applications. Finfets have raised channels surrounded on more than one side by gates (e.g., gates surround the top and sidewalls of a "fin" of semiconductor material extending from a substrate). This configuration provides better channel control and significantly reduces SCE (particularly by reducing sub-critical leakage current (sub-threshold leakage) (i.e., coupling between source and drain of FinFET in "off" state)) compared to planar transistors. The GAA transistor has a gate structure that may extend partially or completely around the channel region to provide access to the channel region on two or more sides. The channel region of the GAA transistor may be formed from nanowires, nanoplates, other nanostructures, and/or other suitable structures. In some embodiments, such a channel region includes a plurality of nanowires (which extend horizontally, providing a channel in a horizontal direction) that are vertically stacked. Such GAA transistors may be referred to as vertically stacked horizontal GAA (VGAA) transistors.

Static random access memory (static random access memory, SRAM) cells have become a popular memory cell for high-speed communications, high-density storage, image processing, and system-on-chip (SOC) products. While existing SRAM cells are generally adequate for their intended purpose, they are not entirely satisfactory in all respects.

Disclosure of Invention

The present invention is directed to a method for forming a semiconductor structure, which solves at least one of the above problems.

A method of forming a semiconductor structure, comprising: forming a first transistor structure and a second transistor structure over a substrate, wherein each transistor structure includes at least one nano-sheet; depositing metal over each transistor structure and around each nanosheet; depositing a coating over the metal; depositing a mask over the coating; patterning the mask to define a patterned mask, wherein the patterned mask is located over the masked portion of the coating and the second transistor structure, and wherein the patterned mask is not located over the unmasked portion of the coating and the first transistor structure; and etching the unmasked portion of the coating and the metal over the first transistor structure using a dry etching process having a process pressure of 30-60 mTorr.

A method of forming a semiconductor structure, comprising: forming a first fully-wrapped-around gate field effect transistor structure in a first transistor region comprising at least one nano-sheet; forming a second fully-wrapped-around gate field effect transistor structure in a second transistor region comprising at least one nano-sheet, wherein the second transistor region is adjacent to the first transistor region; a success function adjustment layer formed over the first fully-wrapped gate field effect transistor structure and the second fully-wrapped gate field effect transistor structure; forming a coating layer over the work function adjusting layer; and performing an etching process to remove the coating and the work function adjustment layer from the first fully-wrapped-gate field-effect transistor structure, wherein the etching process provides the coating with an etched surface, wherein the etched surface is a maximum distance of 10 to 30 nanometers (nm) from the at least one nano-sheet in the second fully-wrapped-gate field-effect transistor structure.

A method of forming a semiconductor structure, comprising: depositing a coating over the structure; depositing a mask over the coating; patterning the coating to define a patterned mask, wherein the patterned mask is located over the masked portions of the coating over the structures, and wherein the patterned mask is not located over the unmasked portions of the coating; and etching the unmasked portion of the coating using a dry etching process to form an etched coating having an etched surface, wherein: the etched surface comprises a linear upper part and an arc lower part which are connected at the connecting point; and a bottom corner (bottom corner) of the arc-shaped lower portion extending from the intersection point to the coating; the tangent to the lower arc intersects the axis defined by the upper linear portion at an angle of 0 to 45 degrees.

Drawings

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the various features are not drawn to scale and are merely illustrative in accordance with practice standard in the industry. In fact, the dimensions of the elements may be arbitrarily expanded or reduced to improve the clarity of presentation for embodiments of the invention.

Fig. 1 is a schematic perspective view illustrating a semiconductor structure, according to some embodiments.

Fig. 2 is an X-section schematic diagram illustrating the semiconductor structure of fig. 1, in accordance with some embodiments.

Fig. 3 is a schematic Y-section diagram illustrating the semiconductor structure of fig. 1, in accordance with some embodiments.

Fig. 4 is a flow chart illustrating a method, according to some embodiments.

Fig. 5-8 are schematic Y-section views illustrating a semiconductor structure during successive stages of fabrication, in accordance with some embodiments.

Fig. 9 is a schematic Y-section diagram illustrating the semiconductor structure shown after an etching step to etch the coating and remove work function metal from selected FET regions, in accordance with some embodiments.

Fig. 10 is an enlarged view illustrating a lower portion of the etch coating in the structure of fig. 9, according to some embodiments.

The reference numerals are as follows:

100:structure

101 first region

102 second region

111:GAA-FET

112:GAA-FET

120 fin structure

121 plane surface

122 plane surface

123 vertex angle

124 midpoint(s)

125 substrate

130 isolation region

140 nanometer sheet

141 nanometer sheet

142 top edge

145 gate dielectric layer

150 gate structure

155 gate electrode layer

160 work function adjusting layer

161 bottom corner

210 coating

211 side wall

220 multiple layers

230 mask

231 cover part

232 cover part

400 method of

401-414 operations

81 plane surface

82 plane surface

85 horizontal plane

91 etching the surface

92 upper part

93 lower part

95 points (point)

98 tangent line

99 plane surface

A1 to A7 angle

D1-D3 distance

T1-T2 channel width

W1-W2 width

Detailed Description

The following disclosure provides many embodiments, or examples, for implementing different elements of the provided subject matter. Specific examples of the respective elements and their configurations are described below to simplify the explanation of the embodiments of the present invention. Of course, these are merely examples and are not intended to limit embodiments of the present invention. For example, references to a first element being formed on a second element may include embodiments in which the first and second elements are in direct contact, and may include embodiments in which additional elements are formed between the first and second elements such that they are not in direct contact. In addition, embodiments of the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Moreover, where possible, spatially relative terms such as "above" … …, "" above, "" over, "" upper, "" top, "" below "… …," "below," "under … …," "lower," "bottom," "side," and the like may be used for ease of description of the relationship between one component(s) or feature(s) and another component(s) or feature(s) in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation and the orientation depicted in the figures. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatial relative adjective used will also be interpreted in terms of the turned orientation.

When spatially relative terms such as those listed above are used to describe a first element relative to a second element, the first element may be directly on another element or intervening elements or layers may be present. When an element or layer is referred to as being "on" another element or layer, it is directly on and in contact with the other element or layer.

In certain embodiments herein, a "material layer" is a layer comprising at least 50% by weight of an identification material, such as at least 60% by weight of an identification material, or at least 75% by weight of an identification material, or at least 90% by weight of an identification material; and a film layer of "material" comprises at least 50% by weight of the identification material, such as at least 60% by weight of the identification material, at least 75% by weight of the identification material, or at least 90% by weight of the identification material. For example, in certain embodiments, each of the titanium nitride layer and the titanium nitride film is at least 50 wt%, at least 60 wt%, at least 75 wt%, or at least 90 wt% titanium nitride film.

For the sake of brevity, conventional techniques related to conventional semiconductor device fabrication may not be described in detail herein. Furthermore, the various tasks and processes described herein may be incorporated into a more comprehensive procedure or process having additional functionality not described in detail herein. In particular, various processes for semiconductor device fabrication are well known, and thus, for the sake of brevity, many conventional processes will only be briefly mentioned herein or will be omitted entirely without providing well known process details. It will be apparent to those skilled in the art from a complete reading of this disclosure that the structures disclosed herein may employ various techniques and may be incorporated into a variety of semiconductor devices and products. Further, it should be noted that the semiconductor device structure includes a different number of elements, and a single element shown in the drawings may represent a plurality of elements.

Embodiments provided herein are for forming GAA FETs, such as pull-up and pull-down (pull-down) transistors for SRAM devices. In particular, embodiments herein provide multiple patterned gate processing to improve the critical dimension uniformity of work function tuning layers. As such, for SRAM devices with better threshold voltages sigma, the pull-down transistor and pull-up transistor threshold voltages may be better balanced. Furthermore, the method provides treatment while avoiding high dielectric constant and fin or wafer damage.

In some embodiments, a high power, high flow dry etch is performed to remove work function material from the NFET structure while the work function material remains on the adjacent PFET structure. Specifically, work function material is deposited over the two FET structures, and then a coating is deposited to cover the two structures. The coating is selectively masked and then a high power, high flow dry etch is performed. The etching process maintains a sufficient distance from the PFET structure and avoids opening the coating to the PFET structure. The etching process improves the critical dimension uniformity (critical dimension uniformity, CDU) of the N/P boundary to achieve better SRAM Vt sigma.

Referring to fig. 1, a perspective schematic view of a semiconductor structure 100 is provided, in accordance with some embodiments. Fig. 2 is an X-section schematic view of the semiconductor structure of fig. 1. Specifically, fig. 2 is taken along line 2-2 in fig. 1 and includes adjacent gates not shown in fig. 1. Fig. 3 is a schematic Y-section view of the semiconductor structure of fig. 1. Specifically, FIG. 3 is taken along line 3-3 in FIG. 1. Notably, fig. 3 only shows the nanoplatelets and the material surrounding the nanoplatelets in the upper portion of the structure 100, not the gate structure, to simplify the discussion of embodiments herein.

The structure 100 of fig. 1-3 includes a first full-wrap gate FET (GAA-FET) 111 adjacent to a second full-wrap gate FET (GAA-FET) 112. In an exemplary embodiment, GAA-FETs 111 and 112 form part of a static random access memory (static random accessmemory, SRAM) device 200. In an exemplary embodiment, the first GAA-FET 111 is an n-type transistor and may be a pull-down transistor. In an exemplary embodiment, the second GAA-FET112 is a p-type transistor and may be a pull-up transistor.

Each transistor 111 and 112 is formed over a respective fin structure 120, fin structure 120 being etched from substrate 125 or formed over substrate 125. In some embodiments, the substrate 125 includes a single crystalline semiconductor layer on at least a surface portion thereof. The substrate 125 may include single crystal semiconductor materials such as, but not limited to Si, ge, siGe, gaAs, inSb, gaP, gaSb, inAlAs, inGaAs, gaSbP, gaAsSb and InP. In certain embodiments, the substrate 125 is made of crystalline Si.

Isolation regions 130, such as shallow trench isolations (shallow trench isolation, STI), are formed over the substrate 125 and between adjacent fin structures 120.

As further shown, nanowires or nanoplatelets 140 constitute the channel region and are formed of a semiconductor material. The nanoplatelets 140 are aligned parallel and perpendicular along the Z direction (normal direction of the main surface of the substrate 125). In each of the example first GAAFET 111 and second GAA FET112, semiconductor nanoplatelets 140 are formed over respective fin structures 120 protruding from the substrate 125.

Each nanoplatelet 140 is surrounded by a gate dielectric layer 145. An exemplary gate dielectric 145 is a high-k dielectric. In some embodiments, the gate dielectric layer includes an interfacial layer (interfacial layer) and a high-k dielectric layer. The gate dielectric layer 145 may also cover the underlying fin structure 120 and isolation region 130.

A metal gate structure 150 is formed over the nanoplatelets 140 and the fin structures 120. The exemplary gate structure 150 may include a gate dielectric layer 145, a gate electrode layer 155, and sidewall spacers.

Although fig. 1-3 show three semiconductor nanoplatelets 140, the number of semiconductor nanoplatelets 140 is not limited to three, and may be as small as one, or may be more than three, possibly up to fifteen (15).

In certain embodiments of the present disclosure, one or more work function adjustment layers 160 are interposed between the gate dielectric layer 145 and the gate electrode layer 155 in the second GAA FET 112. Such work function adjusting layer 160 is not present in the first GAA FET 111.

In each of the first and second GAA FETs, a source/drain epitaxial layer is disposed over the substrate 125. The source/drain epitaxial layer is in direct contact with the nanoplatelets 140 and is separated from the gate electrode layer by a dielectric layer as an internal spacer and a gate dielectric layer 145. The inter-spacer dielectric layer can be made of a low dielectric constant (specific SiO ₂ Low dielectric constant) material having a low dielectric constant. The low dielectric constant material may include SiOC, siOCN, an organic material, or a porous material, or any other suitable material.

In some embodiments, the first GAA FET 111 and the second GAA FET 112 have substantially the same structure except for the work function material 160. In some embodiments, the dimensions of the various elements of FETs 111 and 112 are different.

In an exemplary embodiment, the fin structure height in the Z direction is 50 to 70 nanometers (nm) and the fin structure width in the Y direction is 4 to 8 nanometers (nm). In an exemplary embodiment, the total metal gate height in the Z direction is 70 to 90 nanometers (nm) and the metal gate width in the X direction is 0 to 30 nanometers (nm).

Fig. 4 provides a method for fabricating the semiconductor structure 100 of fig. 1-3. Fig. 5-8 illustrate various stages of fabrication of the semiconductor structure 100 of fig. 1-3. Fig. 5-8 share the perspective of fig. 3, i.e., fig. 5-8 may be considered as taken along line 3-3 in fig. 1.

Referring cross to fig. 4-8, an exemplary method 400 includes forming alternating first and second layers of different semiconductor materials over a substrate 125 in operation 401. For example, in some embodiments, first semiconductor layers of a first composition alternate with second semiconductor layers of a second composition, wherein the first composition is different from the second composition.

In some embodiments, any of the semiconductor layers may comprise silicon. In some embodiments, any of the semiconductor layers may comprise other materials, such as germanium (Ge), compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide, alloy semiconductors such as SiGe, gaAsP, alInAs, alGaAs, inGaAs, gaInP and/or GaInAsP, or combinations thereof. In some embodiments, the first semiconductor layer may include Ge in a molar ratio of about 10% to about 70%, and the second semiconductor layer may include Si. In other embodiments, the first semiconductor layer may include Si, and the second semiconductor layer may include Ge in a molar ratio of about 10% to about 70%. In some embodiments, the first and second semiconductor layers may be undoped or substantially free of dopants (i.e., have a thickness of from about 0cm ^-3 Up to about 1X 10 ¹⁷ cm ^-3 Is a dopant concentration of (c) is an external dopant concentration). Alternatively, the second semiconductor layer may be doped. For example, the first or second semiconductor layer may be doped with P-type dopants such As boron (B), aluminum (Al), indium (In), and gallium (Ga) to form a P-type channel, or n-type dopants such As phosphorus (P), arsenic (As), and antimony (Sb) to form an n-type channel.

In the exemplary embodimentThe thickness of the first semiconductor layer may be from about 4nm to about 10nm. In some embodiments, the thickness of the first semiconductor layer may be substantially uniform. In some embodiments, the second semiconductor layer has a thickness of about 4nm to about 10nm. In some embodiments, the thickness of the second semiconductor layer is substantially uniform. For example, the growth of the stacked layers may be performed by a molecular beam epitaxy (molecular beam epitaxy, MBE) process, a metal organic chemical vapor deposition (metalorganicchemical vapor deposition, MOCVD) process, and/or other suitable epitaxial growth process. In some embodiments, the growth of the stacked layers may use a process comprising SiH ₄ 、DCS、GeH ₄ 、Si ₂ H ₆ 、PH ₃ 、HCl、GeH ₄ Or MMS (carbon source) process gas and containing N ₂ Or H ₂ Is carried out by a carrier gas of the reactor. For example, the epitaxial growth process may be performed at a process temperature in the range of about 400 ℃ to about 800 ℃ and a process pressure of less than about 50 torr.

A process may then be performed to remove either the first semiconductor layer or the second semiconductor layer using a suitable etching technique. The remaining semiconductor layer is referred to as nanoplatelets 140, for example for a fully wrap Gate (GAA) device. Such nanoplatelets may have a rectangular cross-sectional profile and may be suspended.

The method 400 further includes forming a fin structure 120 over the substrate 125 in operation 402. Fin structure 120 may be etched from substrate 125 or otherwise formed over substrate 125. In an exemplary embodiment, forming fin structure 120 includes etching through alternating semiconductor layers that are subsequently processed into a channel region over fin structure 120 and through an upper portion of substrate 125.

The example method 400 includes forming an isolation region 130, such as an STI, over the substrate 125 and between the fin structures 120 in operation 403.

Various conventional processes may then be performed, including, for example, forming a sacrificial gate over the fin structure, forming sidewall spacers around the sacrificial gate, forming source/drain regions (source/drain region(s) may be referred to as source or drain, individually or collectively, depending on the context), and removing the sacrificial gate by various deposition and etching techniques.

Such processing includes, in operation 404, removing the second layer of semiconductor material, thereby forming nanoplatelets 140 from the first layer of semiconductor material.

In operation 405, the method 400 may continue with depositing a gate dielectric layer 145 around the nanoplatelets 140 and over the surface of the fin structure 120. In an exemplary embodiment, the gate dielectric layer 145 is conformally deposited and each nanoplatelet 140 is encased in the gate dielectric 145. A gate dielectric layer 145 may also be formed over the top surface of the isolation 130 or ILD.

According to some embodiments, gate dielectric layer 145 comprises silicon oxide, silicon nitride, or a plurality of layers thereof. In some embodiments, the gate dielectric layer 145 is a high dielectric constant dielectric material, and in these embodiments, the gate dielectric layer 145 may have a dielectric constant value greater than about 7.0, and may include a metal oxide or silicate of Hf, al, zr, la, mg, ba, ti, pb and combinations thereof. The forming method of the gate dielectric layer 145 may include Molecular Beam Deposition (MBD), atomic Layer Deposition (ALD), plasma Enhanced Chemical Vapor Deposition (PECVD), etc.

The method 400 further includes depositing a film 160 over the structure 100 of fig. 5 in operation 406. The exemplary film layer 160 is a work function adjustment layer 160. An exemplary work function tuning layer 160 for a p-channel FET may be blanket deposited and may include one or more layers of conductive material. Examples of the work function tuning layer 160 of the p-channel FET include Ti, W, V, nb, nm, mo or a similar metal. In an exemplary embodiment, the film 160 has a thickness of 0.5 to 20 nanometers (nm).

Work function adjustment layer 160 may be formed by Chemical Vapor Deposition (CVD), physical Vapor Deposition (PVD) including sputtering, atomic Layer Deposition (ALD), or other suitable methods.

In the embodiment shown in fig. 5, a work function tuning layer 160 for the p-channel FET is deposited over both the first structure 111 and the second structure 112 and over the isolation region 130.

In operation 407, the method 400 continues with forming the coating 210 over the structure 100, as shown in fig. 6. An exemplary coating is bottom anti-reflective coating (BARC). The BARC may provide absorption of radiation incident to the substrate during the lithographic process, including exposure of an underlying photoresist layer (as described below).

In an exemplary embodiment, the coating 210 is formed to have a thickness of from 80 to 200 nanometers (nm).

The method 400 may also include forming a reflective Multilayer (ML) 220 over the coating 210 in operation 408. In an exemplary embodiment, the total thickness of the reflective multilayer 220 is 3 to 7 nanometers (nm).

In operation 409, the method 400 may continue with forming a photosensitive mask 230 (e.g., photoresist) over the structure 100. The photoresist 230 may be a positive-tone (positive-tone) or negative-tone (negative-tone) resist. In one embodiment, the photoresist 230 is a chemically amplified photoresist (chemical amplified photoresist, CAR). The photoresist may include polymers, photoacid generators (photoacid generator, PAGs) that provide solubility change to the developer, solvent, and/or other suitable compositions. The photoresist may be formed by processes such as coating (e.g., spin coating) and soft baking. In an exemplary embodiment, the photoresist 230 has a thickness of from 80 to 100 nanometers (nm).

The method 400 further includes patterning a photoresist mask in operation 410. For example, the method may use radiation of various and/or different wavelengths to expose an energy sensitive photoresist layer. In one embodiment, the mask is irradiated with Ultraviolet (UV) radiation or Extreme Ultraviolet (EUV) radiation. The radiation beam may additionally or alternatively include other radiation beams, such as ion beams, x-rays, extreme ultraviolet, deep ultraviolet, and other suitable radiant energies. In one example, the photoresist includes a photoacid generator (PAG) that generates an acid during the exposure process to change the solubility of the exposed/unexposed material. Lithographic processes include immersion lithography, photo development (photolithography), photolithography (optical lithography), and/or other patterning methods that can transfer a pattern onto a photosensitive layer. Patterning may also include post-exposure baking (PEB) processes. During the baking process, the photoresist layer is provided at an elevated temperature. This may allow more acid to be generated from the photoacid generator by a chemical amplification process. In addition, patterning may include developing photoresist layer 230. The developing may form a patterned photoresist layer comprising a plurality of mask features or features. In the development process, a developer is applied to the photoresist layer. In one embodiment, the photoresist material exposed to the radiation is removed by a developing solution (developer). However, a negative resist can also be implemented. The developer or developer may be a positive type developer or a negative type developer. One exemplary developer is aqueous tetramethyl ammonium hydroxide (tetramethylammonium hydroxide, TMAH).

As shown in fig. 6, the patterned mask 230 defines uncovered portions 231 of the underlying structure 100 that are not directly beneath the mask 230, and defines covered portions 232 of the underlying structure 100 that are directly beneath the mask 230.

In operation 411, the method 400 may continue with removing the multilayer 220, the BARC coating 210, and the uncovered portion 231 of the work function adjustment layer 160. Referring to fig. 7, the work function adjustment layer 160 is removed from the FET structure 111 and the isolation region 130 surrounding the FET structure 111.

In an exemplary embodiment, operation 411 is performed by a dry etching process, such as a dry high flow, high pressure etching process. In an exemplary embodiment, a dry etching process, e.g., N, is performed at a high flow rate ₂ And H ₂ May be greater than 500 standard cubic centimeters per minute (sccm). In certain embodiments, a composition comprising H ₂ 、O ₂ And N ₂ Performing a dry etching process with an etching gas of (a) a substrate; h ₂ The flow rate is 200-1500 standard cubic centimeters per minute (sccm), O ₂ The flow rate is 0-100 standard cubic centimeters per minute (sccm), N ₂ The flow rate is 0 to 100 standard cubic centimeters per minute (sccm). In addition, other gases may be used in the etching process, including Ar and He; ar flow is 0-200 standard cubic centimeters per minute (sccm), and He flow is 0-200 standard cubic centimeters per minute (sccm). In one exemplary embodiment, H ₂ The flow rate of (C) is 700 to 900sccm, N ₂ 100 to 200sccm, ar 200sccm, O ₂ The flow rate of (2) was 0sccm.

In an exemplary embodiment, the dry etching process is performed at high pressure, for example, at a pressure greater than 30 millitorr (mTorr). In an exemplary embodiment, the dry etch process is performed at a pressure of from 30 to 60 millitorr (mTorr). In certain embodiments, the use of such high pressures during the dry etching process results in etching the more vertical sidewalls 211 of the coating 210. It is believed that the high flow/high pressure process balances the C/E plasma density to provide a more vertical sidewall profile. Thus, it is ensured that the coating 210 remains covering the process window expansion of the work function adjustment layer 160 over the GAA FET 112.

In an exemplary embodiment, the dry etching process is performed at a process temperature from 35 to 70 ℃.

In operation 412, the method 400 may continue with removing the mask 230 and the underlying multilayer 220. In some embodiments, the mask 230 and the underlying multilayer 220 may be removed during the etching process of operation 411.

Further, the method 400 may include removing the remainder of the coating 210 in operation 413.

As such, the structure 100 is formed as shown in fig. 8. Specifically, the work function adjustment layer 160 remains over the GAA FET 112, while the work function adjustment layer 160 is not present around the GAA FET 111.

As shown in fig. 8, GAA FET structure 111 may be formed from nanoplatelets 140 having a critical dimension or "channel width" T1 in the Y-direction, and GAA FET structure 112 may be formed from nanoplatelets 140 having a critical dimension or "channel width" T2 in the Y-direction. In an exemplary embodiment, the sum t1+t2 is greater than or equal to 10 nanometers (nm) and less than or equal to 60 nanometers (nm). Moreover, in the exemplary embodiment, the difference between T1 and T2 is greater than or equal to 0 nanometers (nm) and less than or equal to 25 nanometers (nm). In an exemplary embodiment, the ratio of T1/T2 is greater than or equal to 1 and less than or equal to 20. For example, the minimum critical dimension may be 5 nanometers (nm) and the maximum critical dimension may be 30 nanometers (nm)). In an exemplary embodiment, the ratio of T1/T2 is closely related to Vt performance. In an exemplary GAA device, the T1/T2 ratio is 1 to 2.5.

Further, as shown in fig. 8, each stack of nanoplatelets 140 forms a respective plane defined by aligned edges of nanoplatelets 140. As shown, the plane 81 formed by the stack of nanoplates 140 in the first GAA FET 111 forms an angle A1 with the horizontal plane 85. In addition, the plane 82 formed by the stack of nanoplates 140 in the second GAA FET112 forms an angle A2 with the horizontal plane 85. In an exemplary embodiment, the sum of angles a1+a2 is greater than 154 degrees and less than 210 degrees. Furthermore, the difference in angles A1-A2 is greater than 0 degrees and less than 28 degrees. For example, the minimum angle of A2 is 77 degrees and the maximum angle of A1 is 105 degrees.

Further processing is performed at operation 414. For example, gate electrode material may be deposited over GAA FET 111 and GAA FET 112. Exemplary gate electrode materials are conductive materials including one or more layers of metallic materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), or iridium (Ir) or other metals. In other embodiments, the conductive material comprises a silicon alloy, including a titanium silicon alloy (Ti _x Si _y ) Cobalt silicon alloy (Co _x Si _y ) Nickel-silicon alloy (Ni _x Si _y ) Tungsten silicon alloy (W) _x Si _y ) Molybdenum silicon alloy (Mo _x Si _y ) Tantalum silicon alloy (Ta _x Si _y ) Or other suitable conductive material. In one embodiment, W is used. The conductive material is formed by CVD, PVD, ALD, electroplating or other suitable method.

Further processing may also include formation of interlayer dielectrics and/or intermetal dielectrics, formation of contact elements and conductive interconnects, and other back-end line processing.

Referring now to fig. 9, an exemplary embodiment of structure 100 is shown after etching that removes work function adjustment layer 160 from FET structure 111 and from isolation region 130 surrounding FET structure 111.

As shown, after the etching process, the coating 210 has an etched surface 91. As shown, the etched surface 91 is a distance D1 in the horizontal Y direction from the top edge 142 of the uppermost nanoplatelet 141. In an exemplary embodiment, D1 is 20 to 25 nanometers (nm).

Further, the point 95 on the etched surface 91 is a distance D2 in the horizontal Y direction from the top corner (topcenter) 123 of the fin structure 120. In an exemplary embodiment, D2 is 10 to 30 nanometers (nm).

In some embodiments, the increased distances D1 and D2 provide protection for the work function adjustment layer 160 from etching or damage during removal of the uncovered portions 231, thereby expanding the process window.

Further, an upper portion 92 of the etched surface 91 is substantially planar and forms an angle A3 with a horizontal Y-axis (e.g., the axis indicated by line D2). In an exemplary embodiment, angle A3 is from 70 degrees to 90 degrees. In certain embodiments, angle A3 is greater than 86 degrees.

In fig. 9, a first GAA FET 111 is formed in the first region 101 having a width W1. Likewise, a second GAA FET 112 is formed in the second region 102 having a width W2. In an exemplary embodiment, the sum of W1+W2 is greater than 15 nanometers (nm) and less than 90 nanometers (nm). Moreover, in the exemplary embodiment, the difference in W1-W2 is greater than 14.5 nanometers (nm) and less than 89.5 nanometers (nm). Further, in the exemplary embodiment, W1 is greater than or equal to W2 and the ratio of W1/W2 is greater than or equal to 1 and less than or equal to 179. In an exemplary embodiment, W1/W2 affects the Vt value. In an exemplary GAA device, the W1/W2 ratio is 1 to 1.8.

As further shown in fig. 9, the fin structure 120 for each GAA FET 111 and 112 may be formed to have a constant width or to have a width that decreases as the height of the fin structure 120 increases. As such, each fin structure 120 may be formed with an outer surface defining a plane. Specifically, fin structure 120 of GAA FET 111 may define a plane 121 intersecting the horizontal plane at an angle A4. Likewise, fin structure 120 of GAA FET 112 may define a plane 122 intersecting the horizontal plane at an angle A5. In an exemplary embodiment, the sum of angles a4+a5 is greater than 80 degrees and less than 180 degrees. Further, the difference between angles A5-A4 is greater than 0 degrees and less than 50 degrees. For example, angle A4 is at least 40 degrees and angle A5 is at most 90 degrees. In an exemplary embodiment, angles A4 and A5 may affect Vt performance. In an exemplary GAA device, the difference between A5-A4 is 0 degrees to 5 degrees.

Fig. 10 shows a focused view of the lower portion 93 of the etched surface 91. As shown, a lower portion 93 of the etched surface 91 is arcuate. The work function tuning layer 160 terminates at a bottom corner 161, the bottom corner 161 forming an interface with the isolation region 130. Further, midpoint 124 is defined as the intermediate position along the horizontal Y-direction between top corner 123 of fin structure 120 and point 95 on etched surface 91. Angle A6 is defined by a vertex at midpoint 124, a first edge terminating at point 95, and a second edge terminating at base angle 161. In an exemplary embodiment, angle A6 is from 20 degrees to 90 degrees, such as from 60 degrees to 90 degrees.

Distance D3 is defined as the bottom angle 161 from midpoint 124. In an exemplary embodiment, the distance D3 is from 15 to 20 nanometers (nm).

The arc length from point 95 to bottom angle 161 is 0.35 to 1.6 times length D3, e.g., 1 to 1.6 times length D3, e.g., 1.04 to 1.57 times length D3.

As further shown, a tangent 98 is defined by the lower portion 93 of the etched surface 91. The tangent line intersects a plane 99 defined by the upper portion 92 of the etched surface 91 at an angle A7. In an exemplary embodiment, angle A7 is from 0 degrees to 45 degrees. In the exemplary GAA device, angle A7 is from 30 degrees to 40 degrees to provide the proper Vt sigma.

As described herein, the multiple patterned gate process provides improved critical dimension uniformity for work function adjustment layer 160. As such, for SRAM devices with better threshold voltages sigma, the pull-down transistor and pull-up transistor threshold voltages may be better balanced. Furthermore, the method provides treatment while avoiding high dielectric constant and fin or wafer damage.

A method for forming a semiconductor structure is provided. An exemplary method includes: a first transistor structure and a second transistor structure are formed over a substrate, wherein each transistor structure includes at least one nano-sheet. The method further includes depositing a metal over each transistor structure and around each nanoplatelet; depositing a coating over the metal; depositing a mask over the coating; the patterned mask is used to define a patterned mask, wherein the patterned mask is located over the masked portion of the coating and the second transistor structure, and wherein the patterned mask is not located over the unmasked portion of the coating and the first transistor structure. The method further includes etching the unmasked portion of the coating and the metal over the first transistor structure using a dry etching process having a process pressure of 30-60 mTorr.

In an exemplary method, a dry etching process uses an etching gas at a flow rate greater than 500 standard cubic centimeters per minute (standard cubic centimeters per minute, sccm).

In an exemplary method, the etching process is performed at a process temperature of 35-70 ℃.

In an exemplary method, the etching process uses a gas comprising a flow of 200 to 1500 standard cubic centimeters per minute (sccm) ₂ O with flow rate of 0 to 100sccm ₂ And N with a flow rate of 0 to 100sccm ₂ Is performed by etching gas.

In an exemplary method, a dry etching process is performed using Ar at a flow rate of 0 to 200sccm and He at a flow rate of 0 to 200 sccm.

In an exemplary embodiment, the method further comprises removing the patterned mask; and removing the masked portion of the coating.

In an exemplary embodiment of the method, the unmasked portion of the coating and the metal over the first transistor structure are etched using a dry etching process, defining a remaining portion of the coating having sidewall surfaces; a portion of the sidewall surface is located at a maximum distance from the second transistor structure; and a maximum distance of 10 to 30 nanometers (nm).

In an exemplary embodiment of the method, the unmasked portion of the coating and the metal over the first transistor structure are etched using a dry etching process, defining a remaining portion of the coating having sidewall surfaces, wherein the sidewall surfaces include a lower portion and an upper portion; the lower part and the upper part are connected at a connecting point; the lower part of the side wall surface is arc-shaped; and a lower portion of the sidewall surface extends from the intersection to an interface with the isolation material.

In an exemplary embodiment of the method, the unmasked portion of the coating and the metal over the first transistor structure are etched using a dry etching process, defining a remaining portion of the coating having sidewall surfaces, wherein the sidewall surfaces include a lower portion and an upper portion; the lower part and the upper part are connected at a connecting point; defining a midpoint between the sidewall and the second transistor structure along a horizontal line; the lower part of the side wall surface is arc-shaped; a lower portion of the sidewall surface extends from the intersection to an interface with the isolation material; and defining an angle by the vertex at the midpoint, the first edge ending at the intersection point, and the second edge ending at the interface, wherein the angle is 60 to 90 degrees.

In an exemplary embodiment of the method, the unmasked portion of the coating and the metal over the first transistor structure are etched using a dry etching process, defining a remaining portion of the coating having sidewall surfaces, wherein the sidewall surfaces include a lower portion and an upper portion; the lower part and the upper part are connected at a connecting point; the lower portion is arc-shaped and extends from the junction to the interface with the isolation material; and the upper portion is linear and extends along an upper line.

In another embodiment, a method of forming a semiconductor structure includes: forming a first fully-wrapped-around gate field effect transistor structure in a first transistor region comprising at least one nano-sheet; forming a second fully-wrapped-around gate field effect transistor structure in a second transistor region comprising at least one nano-sheet, wherein the second transistor region is adjacent to the first transistor region; a success function adjustment layer formed over the first fully-wrapped gate field effect transistor structure and the second fully-wrapped gate field effect transistor structure; forming a coating layer over the work function adjusting layer; and performing an etching process to remove the coating and the work function adjustment layer from the first fully-wrapped-gate field-effect transistor structure, wherein the etching process provides the coating with an etched surface, wherein the etched surface is a maximum distance of 10 to 30 nanometers (nm) from the at least one nano-sheet in the second fully-wrapped-gate field-effect transistor structure.

In an exemplary embodiment of the method, the work function adjusting layer is titanium, tungsten, vanadium, niobium, manganese, or molybdenum.

In an exemplary embodiment of the method, the work function adjusting layer has a thickness of 0.5 to 20 nanometers (nm).

As in an exemplary embodiment of the method, the first fully-wrapped-gate field-effect transistor structure is formed in a first region having a first width, the second fully-wrapped-gate field-effect transistor structure is formed in a second region having a second width, and a sum of the first width and the second width is 15 to 90 nanometers (nm).

In an exemplary embodiment of the method, the first fully-wrapped-gate field-effect transistor structure is formed in a first region having a first width, the second fully-wrapped-gate field-effect transistor structure is formed in a second region having a second width, the first width is greater than or equal to the second width, and a ratio of the first width to the second width is 179:1 to 1:1.

In an exemplary embodiment of the method, the first fully-wrapped-gate field-effect transistor structure includes a stack of nanoplates each terminating at an edge defining a first plane; the first plane forms a first angle with the horizontal plane; the second fully-wrapped gate field effect transistor structure includes a stack of nano-sheets each terminating at an edge defining a second plane; the second plane forms a second angle with the horizontal plane; the sum of the first angle and the second angle is more than 154 degrees and less than 210 degrees; and the difference between the first angle and the second angle is greater than 0 degrees and less than 28 degrees.

In another embodiment, a method of forming a semiconductor structure includes: depositing a coating over the structure; depositing a mask over the coating; patterning the coating to define a patterned mask, wherein the patterned mask is located over the masked portions of the coating over the structures, and wherein the patterned mask is not located over the unmasked portions of the coating; and etching the unmasked portion of the coating using a dry etching process to form an etched coating having an etched surface, wherein: the etched surface comprises a linear upper part and an arc lower part which are connected at the connecting point; and a bottom corner (bottom corner) of the arc-shaped lower portion extending from the intersection point to the coating; the tangent to the lower arc intersects the axis defined by the upper linear portion at an angle of 0 to 45 degrees.

In an exemplary embodiment of the method, the axis defined by the linear upper portion intersects the horizontal plane at an angle greater than 86 degrees.

In an exemplary embodiment of the method, the maximum distance of the etched surface to the structure along the horizontal direction is 10 to 30 nanometers.

In an exemplary embodiment of the method, a minimum distance of the etched surface to the structure along the horizontal direction is defined at the bottom angle of the coating.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the embodiments of the present invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or advantages of the embodiments described herein. Those skilled in the art should also realize that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present invention.

Claims

1. A method of forming a semiconductor structure, comprising:

forming a first transistor structure and a second transistor structure over a substrate, wherein each transistor structure includes at least one nano-sheet;

depositing a metal over each transistor structure and around each nano-plate;

depositing a coating over the metal;

depositing a mask over the coating;

patterning the mask to define a patterned mask, wherein the patterned mask is over a masked portion of the coating and the second transistor structure, and wherein the patterned mask is not over an unmasked portion of the coating and the first transistor structure; and

the unmasked portion of the coating and the metal over the first transistor structure are etched using a dry etching process having a process pressure of 30-60 mTorr.

2. The method of claim 1, wherein the dry etching process uses an etching gas having a flow rate greater than 500 standard cubic centimeters per minute.

3. The method of claim 1, wherein said etching processThe process uses a flow rate of H comprising 200 to 1500 standard cubic centimeters per minute ₂ O with flow rate of 0 to 100sccm ₂ And N with a flow rate of 0 to 100sccm ₂ Is performed by etching gas.

4. The method of forming a semiconductor structure as claimed in claim 1, wherein:

etching the unmasked portion of the coating and the metal over the first transistor structure using the dry etching process, defining a remaining portion of the coating having a sidewall surface, wherein the sidewall surface includes a lower portion and an upper portion;

the lower portion and the upper portion meet at a junction;

the lower portion of the sidewall surface is arcuate; and

the lower portion of the sidewall surface extends from the intersection to an interface with an isolation material.

5. A method of forming a semiconductor structure, comprising:

forming a first fully-wrapped-gate field effect transistor structure in a first transistor region including at least one nano-sheet;

forming a second fully-wrapped-around gate field effect transistor structure in a second transistor region comprising at least one nano-sheet, wherein the second transistor region is adjacent to the first transistor region;

forming a work function adjusting layer above the first fully-wound gate field effect transistor structure and the second fully-wound gate field effect transistor structure;

forming a coating over the work function adjusting layer; and

An etching process is performed to remove the coating and the work function adjusting layer from the first fully-wrapped-gate field effect transistor structure, wherein the etching process provides the coating with an etched surface, wherein the etched surface is a maximum distance of 10 to 30 nanometers from the at least one nano-sheet in the second fully-wrapped-gate field effect transistor structure.

6. The method of claim 5, wherein said first fully-wrapped-gate field-effect transistor structure is formed in a first region having a first width, said second fully-wrapped-gate field-effect transistor structure is formed in a second region having a second width, and a sum of said first width and said second width is 15 to 90 nanometers.

7. The method of claim 5, wherein said first fully-wrapped-gate field-effect transistor structure is formed in a first region having a first width, said second fully-wrapped-gate field-effect transistor structure is formed in a second region having a second width, said first width is greater than or equal to said second width, and a ratio of said first width to said second width is 179:1 to 1:1.

8. The method of forming a semiconductor structure as claimed in claim 5, wherein:

The first fully-wrapped-gate field effect transistor structure includes a stack of nano-sheets each terminating at an edge defining a first plane;

the first plane forms a first angle with a horizontal plane;

the second fully-wrapped-gate field effect transistor structure includes a stack of nano-sheets each terminating at an edge defining a second plane;

the second plane forms a second angle with the horizontal plane;

the sum of the first angle and the second angle is more than 154 degrees and less than 210 degrees; and

a difference between the first angle and the second angle is greater than 0 degrees and less than 28 degrees.

9. A method of forming a semiconductor structure, comprising:

depositing a coating over a structure;

depositing a mask over the coating;

patterning the coating to define a patterned mask, wherein the patterned mask is located over a masked portion of the coating over the structure, and wherein the patterned mask is not located over an unmasked portion of the coating; and

etching the unmasked portion of the coating using a dry etching process to form an etched coating having an etched surface, wherein:

the etching surface comprises a linear upper part and an arc lower part which are connected at a connecting point; and

The arc-shaped lower part extends from the intersection point to a bottom corner of the coating;

a tangent line of the arcuate lower portion intersects an axis defined by the linear upper portion at an angle of 0 to 45 degrees.

10. The method of forming a semiconductor structure of claim 9, wherein the axis defined by the linear upper portion intersects a horizontal plane at an angle greater than 86 degrees.