CN117542317A - Light-emitting driving circuit and display panel - Google Patents
Light-emitting driving circuit and display panel Download PDFInfo
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- CN117542317A CN117542317A CN202311760432.8A CN202311760432A CN117542317A CN 117542317 A CN117542317 A CN 117542317A CN 202311760432 A CN202311760432 A CN 202311760432A CN 117542317 A CN117542317 A CN 117542317A
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- 230000000630 rising effect Effects 0.000 description 6
- 238000004088 simulation Methods 0.000 description 2
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
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- Theoretical Computer Science (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
The invention provides a light-emitting driving circuit and a display panel, wherein the light-emitting driving circuit comprises a plurality of driving modules, and each driving module is connected with a corresponding light-emitting driving wire; the driving module comprises a signal generating unit and a signal compensating unit; the output end of the signal generating unit is connected with the light-emitting driving line, and the signal compensating unit is connected between the signal generating unit and the light-emitting driving line. The array emission driving signals output by the signal generating units are compensated by arranging the signal compensating units, so that the starting effective duration of the array emission driving signals output by the signal generating units is consistent, the luminous duration of each OLED is consistent, and the uniformity of display is ensured.
Description
Technical Field
The present invention relates to the field of display, and in particular, to a light-emitting driving circuit and a display panel.
Background
The array emits a driving EM signal for controlling the light-emitting switch of the OLED; EOA (Emission On Array) is used for generating an EM signal according to the related signal output by the driving chip; however, there is a difference in parasitic capacitance of the wiring between different EOAs and the driving chip, so that there is a difference in waveform of EM signals output by EOAs relatively close to and far from the driving chip, and thus the light emitting time of the corresponding OLED is affected, and the light emitting time of the OLED is inconsistent, resulting in a problem of uneven display.
Disclosure of Invention
The invention mainly aims to provide a light-emitting driving circuit and a display panel, and aims to solve the problem of uneven display caused by the fact that waveforms of EM signals output by different EOAs in the prior art are different.
In order to achieve the above object, the present invention provides a light emitting driving circuit including a plurality of driving modules, each of which is connected with a corresponding light emitting driving line; the driving module comprises a signal generating unit and a signal compensating unit; the output end of the signal generating unit is connected with the light-emitting driving line, and the signal compensating unit is connected between the signal generating unit and the light-emitting driving line; wherein:
the signal generation unit is used for sending an array emission driving signal to the light emitting driving line, wherein the array emission driving signal indicates the switching device corresponding to the light emitting driving line to be conducted;
the signal compensation unit is used for compensating the starting effective duration of the array emission driving signals so as to enable the starting effective duration of the array emission driving signals corresponding to the signal generation units to be consistent.
Optionally, the signal compensation unit includes a switch subunit and a delay subunit; the switch subunit is connected between the signal generating unit and the light-emitting driving line, and the delay subunit is connected with the control end of the switch subunit; wherein:
the switch subunit is used for being conducted after the signal generating unit outputs the array emission driving signal to reach the time delay duration;
and the delay subunit is used for determining the delay time length.
Optionally, the signal generating unit includes a signal processing subunit and a first switching tube, where an output end of the signal processing subunit is connected to a control end of the first switching tube, an input end of the first switching tube is connected to a row start voltage end, and an output end of the first switching tube is connected to the light emitting driving line through the signal compensating unit.
Optionally, the switch subunit includes a second switch tube, a control end of the second switch tube is connected with a control end of the first switch tube, an input end of the second switch tube is connected with an output end of the first switch tube, an output end of the second switch tube is connected with the light-emitting driving line, and a control end of the second switch tube is further connected with the delay subunit.
Optionally, when the signal generating unit outputs the array emission driving signal, a gate-drain capacitance value and a drain-source voltage of the second switching tube in each signal compensating unit are equal.
Optionally, the delay subunit includes a first capacitor, and the first capacitor is connected between the control end of the second switching tube and the output end of the second switching tube.
Optionally, the light-emitting driving circuit further includes a driving chip, and each driving module is connected with the driving chip;
the capacitance value of the first capacitor corresponding to the first signal compensation unit is 0, wherein the first signal compensation unit is the signal compensation unit with the longest connecting line length between the first signal compensation unit and the driving chip;
the length of the connecting line between the signal compensation unit and the driving chip is inversely related to the capacitance value of the first capacitor.
Optionally, the first switching tube is a PMOS tube, the control end of the first switching tube is a gate of the PMOS tube, the input end of the first switching tube is a source of the PMOS tube, and the output end of the first switching tube is a drain of the PMOS tube;
the row starting voltage end is a starting voltage low-voltage end;
the second switching tube is a PMOS tube, the control end of the second switching tube is the grid electrode of the PMOS tube, the input end of the second switching tube is the source electrode of the PMOS tube, and the output end of the second switching tube is the drain electrode of the PMOS tube.
Optionally, the first switching tube is an NMOS tube, the control end of the first switching tube is a gate of the NMOS tube, the input end of the first switching tube is a drain of the NMOS tube, and the output end of the first switching tube is a source of the NMOS tube;
the row starting voltage end is a starting voltage high-voltage end;
the second switching tube is an NMOS tube, the control end of the second switching tube is the grid electrode of the NMOS tube, the input end of the second switching tube is the drain electrode of the NMOS tube, and the output end of the second switching tube is the source electrode of the NMOS tube.
In addition, in order to achieve the above object, the present invention also provides a display panel including light emitting driving lines and the light emitting driving circuit as described above.
The invention provides a light-emitting driving circuit and a display panel, wherein the light-emitting driving circuit comprises a plurality of driving modules, and each driving module is connected with a corresponding light-emitting driving wire; the driving module comprises a signal generating unit and a signal compensating unit; the output end of the signal generating unit is connected with the light-emitting driving line, and the signal compensating unit is connected between the signal generating unit and the light-emitting driving line; wherein: the signal generation unit is used for sending an array emission driving signal to the light emitting driving line, wherein the array emission driving signal indicates the switching device corresponding to the light emitting driving line to be conducted; the signal compensation unit is used for compensating the starting effective duration of the array emission driving signals so as to enable the starting effective duration of the array emission driving signals corresponding to the signal generation units to be consistent. The array emission driving signals output by the signal generating units are compensated by arranging the signal compensating units, so that the starting effective duration of the array emission driving signals output by the signal generating units is consistent, the luminous duration of each OLED is consistent, and the uniformity of display is ensured.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the structures shown in these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a functional block diagram of an embodiment of a light-emitting driving circuit according to the present invention;
FIG. 2 is a schematic diagram of an OLED drive circuit in one case;
FIG. 3 is a schematic diagram of a drive module in one case;
FIG. 4 is a schematic diagram of a signal compensation unit in a light-emitting driving circuit according to the present invention;
FIG. 5 is a schematic diagram of an array transmit drive signal output of a drive module;
FIG. 6 shows an array emission driving signal EM output by a driving module farthest from a driving chip in the light-emitting driving circuit of the present invention F Array emission driving signal EM output by driving module closest to driving chip C Is a simulation of the above.
The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Reference numerals illustrate:
| reference numerals | Name of the name | Reference numerals | Name of the name |
| 100 | Driving module | TD1～TD7 | First to seventh driving switching tubes |
| 110 | Signal generating unit | T1～T11 | First to eleventh switching tubes |
| 120 | Signal compensation unit | CD1 | First driving capacitor |
| 200 | Driving chip | C1～C4 | First to fourth capacitors |
Detailed Description
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that all directional indicators (such as up, down, left, right, front, and rear are used in the embodiments of the present invention) are merely for explaining the relative positional relationship, movement conditions, and the like between the components in a certain specific posture (as shown in the drawings), and if the specific posture is changed, the directional indicators are changed accordingly.
Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.
Referring to fig. 1, fig. 1 is a functional block diagram of an embodiment of a light-emitting driving circuit of the present invention. In this embodiment, the light emitting driving circuit includes a plurality of driving modules 100, each of the driving modules 100 being connected to a corresponding light emitting driving line; the driving module 100 includes a signal generating unit 110 and a signal compensating unit 120; an output end of the signal generating unit 110 is connected with the light emitting driving line, and the signal compensating unit 120 is connected between the signal generating unit 110 and the light emitting driving line; wherein:
a signal generating unit 110, configured to send an array emission driving signal to the light emitting driving line, where the array emission driving signal indicates that a switching device corresponding to the light emitting driving line is turned on;
the signal compensation unit 120 is configured to compensate for the effective starting duration of the array emission driving signal, so that the effective starting duration of the array emission driving signal corresponding to each signal generation unit 110 is consistent.
The light-emitting driving line is used for transmitting an EM signal for controlling the OLED to emit light; the light emitting drive line is connected with a switch tube in the OLED drive circuit for controlling the OLED to emit light; to further clarify the technical solution of the present embodiment, referring to fig. 2, fig. 2 is a schematic diagram of an OLED driving circuit under one condition; the OLED driving circuit is respectively connected with a Scan line Scan (n), a previous Scan line Scan (n-1), a data line Vdata, a light emitting driving line EM (n), an initialization voltage end Vint, a current high voltage end ELVDD and a current low voltage end ELVSS; the OLED driving circuit comprises an OLED, first to seventh driving switching tubes TD1 to TD7 and a first driving capacitor CD1; wherein:
the first driving switching tube TD1 is connected to the emission driving line EM (n), and the first driving switching tube TD1 is used for controlling whether the OLED emits light according to the array driving signal, specifically, when the first driving switching tube TD1 is turned off, the OLED does not emit light.
The second driving switch tube TD2 is used for controlling the magnitude of the current flowing through the OLED; the third driving switch tube TD3 is used for controlling the potential of the first driving capacitor CD1 during initialization; the fourth driving switch tube TD4 is used for compensating the conducting voltage of the second driving switch tube TD 2; the fifth driving switching tube TD5 is used for controlling ELVDD to supply power to the OLED; the sixth driving switch tube TD6 is used for controlling the data signal to charge the first driving capacitor CD 1C; the seventh driving switching transistor TD7 is used to initialize the positive voltage of the OLED.
It should be noted that the specific structure of the OLED driving circuit is only illustrated to clearly indicate the function of the light emitting line; in practical applications, the OLED driving circuit may be set based on practical needs.
The signal generating unit 110 is configured to generate an array emission driving signal; the effective starting duration of the array emission driving signal is the light emitting duration of the corresponding OLED, that is, the on duration of the first driving switching tube TD1 in a single driving period. It can be understood that, due to the influence of the parasitic capacitance of the wiring, when the array transmits the driving signal to switch between the high level and the low level, the voltage rising and falling phases exist; meanwhile, rising and falling durations of the array emission driving signals outputted from the different signal generating units 110 are different; taking the rising as an example, when the duration of the rising period is longer, the longer the output array emission driving signal reaches the conducting voltage of the first driving switch tube TD1, that is, the shorter the effective starting duration of the array emission driving signal, the shorter the conducting time of the first driving switch tube TD1, and the shorter the light emitting time of the OLED. When the effective starting time length of the array emission driving signals corresponding to different signal sounding units is different, the light emitting time length of the OLED is also different, so that uneven display is caused; and after the signal compensation unit 120 compensates the array emission driving signals, the starting effective duration of the output array emission driving signals is consistent, so that the consistent luminous duration of the OLED is ensured, and the display uniformity is ensured. It can be understood that when the signal compensation unit 120 compensates the active duration of the start of the array emission driving signal, it may be to negatively compensate the array emission driving signal with a longer active duration, so as to shorten the active duration of the start; the array emission driving signal with shorter starting effective duration can be positively compensated to prolong the starting effective duration.
In this embodiment, the signal compensation unit 120 is configured to compensate the array emission driving signals output by the signal generating units 110, so that the starting effective duration of the array emission driving signals output by each signal generating unit 110 is consistent, thereby making the light emitting duration of each OLED consistent, and ensuring uniform display.
Further, the signal compensation unit 120 includes a switch subunit and a delay subunit; the switch subunit is connected between the signal generating unit 110 and the light-emitting driving line, and the delay subunit is connected with the control end of the switch subunit; wherein:
the switch subunit is configured to be turned on after the signal generating unit 110 outputs the array emission driving signal for a delay time;
and the delay subunit is used for determining the delay time length.
The signal compensation unit 120 in the present embodiment does not adjust the structure of the signal generation unit 110; control of the active duration of activation of the array transmit drive signal is effected for the switch state of the port connected to the light-emitting drive line. Specifically, the signal generating unit 110 generates an array emission driving signal according to its own configuration and the received driving signal, and because of the blocking of the switch subunit, if the switch subunit is turned off, the array emission driving signal cannot be output to the light emitting driving line, and if the switch subunit is turned on, the array emission driving signal can be output to the light emitting driving line; it can be understood that, whether the switch sub-units are turned on or not, the voltage corresponding to the array emission driving signal can realize the processes of voltage rising, voltage holding and voltage falling based on the signal generating unit 110, so that the output of the array emission driving signal is controlled through different delay time durations of the switch sub-units, which is equivalent to intercepting a section of signal output from the array emission driving signal, and for the switch sub-units of different driving modules 100, the light emitting time durations of the OLEDs can be consistent as long as the starting effective time durations in the intercepted output array emission driving signals are consistent; specifically, there is necessarily a signal with the minimum starting effective duration in each array emission driving signal, if the starting effective duration of the signal is taken as the intercepting length, and the delay subunit is set to intercept all the array emission driving signals at the corresponding positions with the intercepting length, the starting effective duration of the array emission driving signals output by each driving module 100 can be unified to the intercepting length.
According to the embodiment, the output of the array emission driving signals with longer starting effective duration is limited, so that the corresponding OLED (organic light emitting diode) light emitting time is shortened to be compatible with the array emission driving signals with shorter starting effective duration, and the display uniformity is realized; compared with a mode of prolonging the effective starting time, the method is easy to realize, and meanwhile, no additional power supply device is needed.
Further, the signal generating unit 110 includes a signal processing subunit and a first switching tube T1, where an output end of the signal processing subunit is connected to a control end of the first switching tube T1, an input end of the first switching tube T1 is connected to a row start voltage end, and an output end of the first switching tube T1 is connected to the light emitting driving line through the signal compensating unit 120.
The specific structure of the signal generating unit 110 may be set based on the actual application scenario, and only the first switching transistor T1 for outputting the line-on voltage is focused in the present embodiment; for further clarity of the technical solution of the present application, referring to fig. 3, fig. 3 is a schematic diagram of a driving module 100 in one case; the signal generating unit 110 is connected with an open voltage low voltage end VGL, an open voltage high voltage end VGH, a first clock signal end CK, a second clock signal end XCK, and a previous EM signal end EM0; the driving module 100 comprises a first switching tube T1, a third switching tube T3 to an eleventh switching tube T11, a second capacitor C2 to a fourth capacitor C4; wherein:
the input end of the first switching tube T1 is connected with the low-voltage end of the starting voltage, the output end of the first switching tube T1 is connected with a luminous driving line through a signal compensation unit 120, the control end of the first switching tube T1 is connected with a first clock signal end through a fourth capacitor C4, and the control end of the first switching tube T1 is also connected with the control end of a third switching tube T3, the control end of a sixth switching tube T6, the output end of an eighth switching tube T8 and the output end of a ninth switching tube T9 respectively;
the input end of the third switching tube T3 is connected with the high-voltage end of the starting voltage, and the output end of the third switching tube T3 is respectively connected with the control end of the eleventh switching tube T11 and the output end of the fourth switching tube T4; the input end of the eleventh switching tube T11 is connected with the high-voltage end of the starting voltage, the output end of the eleventh switching tube T11 is connected with the light-emitting driving line, and the input end of the eleventh switching tube T11 is also connected with the control end of the eleventh switching tube T11 through a second capacitor C2;
the control end of the fourth switching tube T4 is connected with a first clock signal end, the input end of the fourth switching tube T4 is connected with the output end of the fifth switching tube T5, the input end of the fifth switching tube T5 is connected with the first clock signal end, the control end of the fifth switching tube T5 is connected with the output end of the fifth switching tube T5 through a third capacitor C3, and the control end of the fifth switching tube T5 is also respectively connected with the output end of a sixth switching tube T6, the output end of a seventh switching tube T7 and the control end of a tenth switching tube T10;
the input end of the sixth switching tube T6 is connected with the second clock signal end, the control end of the seventh switching tube T7 is connected with the second clock signal end, and the input end of the seventh switching tube T7 is connected with the starting voltage low-voltage end;
the input end of the tenth switching tube T10 is connected with the high-voltage end of the starting voltage, the output end of the tenth switching tube T10 is connected with the input end of the ninth switching tube T9, and the control end of the ninth switching tube T9 is connected with the first clock signal end; the input end of the eighth switching tube T8 is connected with the emission driving signal end of the previous array, and the control end of the eighth switching tube T8 is connected with the second clock signal end.
The low-voltage end of the starting voltage, the high-voltage end of the starting voltage, the first clock signal end and the second clock signal end are output by the driving chip 200; the first clock signal terminal and the second clock signal terminal output mutually inverted clock signals, and the front array emission driving signal terminal is the output terminal of the array emission driving signal of the driving module 100 of the previous row.
It should be noted that the above-mentioned driving module 100 is only for illustration, so as to clarify the function of the first switching tube T1; in practical applications, the driving module 100 may be set based on practical needs.
It should be noted that, if the first driving switch tube TD1 is a PMOS, the switch tubes in the driving module 100 are all PMOS tubes, and the low voltage end of the on voltage is the row on voltage end; if the first driving switching tube TD1 is an NMOS, the switching tubes in the driving module 100 are all NMOS tubes, and at this time, the high-voltage end of the turn-on voltage is the row-on voltage end, and the eleventh switching tube T11 is the first switching tube T1.
Taking PMOS as an example; when the corresponding OLED needs to be controlled to emit light, namely, when the first driving switching tube TD1 is turned on, the first switching tube T1 is turned on, and at the moment, the row starting voltage flows out through the first switching tube T1; when the corresponding OLED needs to be controlled to emit no light, that is, the first driving switching tube TD1 is turned off, the first switching tube T1 is turned off, and at this time, the row on voltage cannot be output.
Further, referring to fig. 4, the switching subunit includes a second switching tube T2, a control end of the second switching tube T2 is connected to a control end of the first switching tube T1, an input end of the second switching tube T2 is connected to an output end of the first switching tube T1, an output end of the second switching tube T2 is connected to the light emitting driving line, and a control end of the second switching tube T2 is further connected to the delay subunit.
The second switching tube T2 is in short circuit with the control end of the first switching tube T1, so that when the parameters of the first switching tube T1 and the second switching tube T2 are consistent, the first switching tube T1 and the second switching tube T2 are simultaneously turned on or turned off; the second switching tube T2 is also provided with a delay subunit, so that when the delay subunit has delay influence on the second switching tube T2, the second switching tube T2 is conducted later than the first switching tube T1; when the second switching tube T2 is turned on, the row on voltage can be output to the light emitting driving line, and when the second switching tube T2 is turned off, the row on voltage cannot be output to the light emitting driving line.
Further, when the first switching tube T1 is a PMOS tube, the second switching tube T2 is a PMOS tube, the control end of the second switching tube T2 is a gate of the PMOS tube, the input end of the second switching tube T2 is a source of the PMOS tube, and the output end of the second switching tube T2 is a drain of the PMOS tube.
Further, when the first switching tube T1 is an NMOS tube, the second switching tube T2 is an NMOS tube, the control end of the second switching tube T2 is a gate of the NMOS tube, the input end of the second switching tube T2 is a drain of the NMOS tube, and the output end of the second switching tube T2 is a source of the NMOS tube.
Further, when the signal generating unit 110 outputs the array emission driving signal, the gate-drain capacitance value and the drain-source voltage of the second switching transistor T2 in each of the signal compensating units 120 are equal.
The gate-drain capacitance value is the equivalent capacitance value between the gate and the drain of the second switching tube T2; the drain-source voltage is the voltage value between the drain and the source of the second switch tube T2.
It can be understood that the miller effect exists in the opening process of the MOS tube, and as the gate-source voltage increases, the drain current starts to increase and the drain-source voltage starts to decrease; when the gate-source voltage is increased to a certain degree, the drain current is saturated, a miller platform appears, namely the gate-source voltage is kept unchanged for a certain time, and then the gate-source voltage is continuously increased until the MOS tube is conducted; therefore, it can be known that when the duration of the miller platform is longer, the time required for conducting the MOS tube is longer, and the parasitic capacitance between the grid electrode and the drain electrode of the MOS tube needs to be charged to cause the miller platform, so that the duration of the miller platform can be adjusted by adjusting the grid-drain capacitance value of the MOS tube, and the conduction time of the MOS tube can be adjusted.
Specifically, the duration of the miller plateau is:
wherein T is m For duration of Miller platform, C gd To the gate leakage capacitance value, V ds Is drain-source voltage, I g A gate drive current; during driving, I g As a constant, therefore, when the product of the gate-drain capacitance and the drain-source voltage is determined, the duration of the miller stage can be determined, and the on-time of the second switching tube T2 can be determined.
The drain-source voltage needs to be detected and determined for the MOS transistors, and the drain-source voltages of the second switching transistors T2 in different driving modules 100 are different, so that in this embodiment, the duration of the miller platform is unified by adjusting the gate-drain capacitance value; specifically:
the delay subunit comprises a first capacitor C1, and the first capacitor C1 is connected between the control end of the second switching tube T2 and the output end of the second switching tube T2.
It can be understood that the gate-drain capacitance value refers to the magnitude of the equivalent capacitance between the gate and the drain of the second switching tube T2; parasitic capacitance exists between the grid electrode and the drain electrode of the second switching tube T2; the capacitance is externally connected between the grid electrode and the drain electrode of the second switching tube T2, so that the grid-drain capacitance value of the second switching tube T2 can be adjusted, and the duration time of the miller platform of the second switching tube T2 is adjusted.
In particular, the determination of the capacitance value of the first capacitance C1 may have the actual parameters of the second switching tube T2; if the duration of the miller stage to be set can be determined in advance based on the duration of the second switching tube T2 to be turned on, and the drain-source voltage of each second switching tube T2 is actually simulated, after the duration of each miller stage and the drain-source voltage of the second switching tube T2 are determined, the gate-drain capacitance value to be set of the second switching tube T2 is determined, and after the parasitic capacitance between the gates and the drains of the second switching tube T2 is detected, the capacitance value of the first capacitor C1 to be set can be obtained.
Further, the light-emitting driving circuit further includes a driving chip 200, and each driving module 100 is connected to the driving chip 200;
the capacitance value of the first capacitor C1 corresponding to the first signal compensation unit 120 is 0, where the first signal compensation unit 120 is the signal compensation unit 120 with the longest connection length with the driving chip 200;
the connection length between the signal compensation unit 120 and the driving chip 200 is inversely related to the capacitance of the first capacitor C1.
The driving chip 200 outputs an EOA input signal to each driving module 100, where the EOA input signal includes a low-voltage start terminal VGL, a high-voltage start terminal VGH, a first clock signal terminal CK, and a second clock signal terminal XCK.
In practical applications, since the setting positions of the different driving modules 100 are different, the lengths of the wires between the driving modules 100 and the driving chip 200 are also different, and the lengths of the wires lead to different parasitic capacitances of the wires, so that the rising and falling times of the corresponding array emission driving signals are different, see fig. 5, and fig. 5 is a schematic diagram of the array emission driving signal output of the driving module 100; the closer to the driving chip 200, i.e. the shorter the length of the connection line, the shorter the rise time of the array emission driving signal, the array emission driving signal output by the driving module 100 closest to the driving chip 200 can be regarded as a standard square wave signal; the longer the length of the connection line, the longer the rise time of the array emission driving signal, and the longer the time to reach the on voltage of the first driving switching tube TD 1.
Meanwhile, the drain-source voltage of the second switching tube T2 can also be influenced by the length of the connecting wire; specifically, the longer the wiring length, the smaller the drain-source voltage of the second switching tube T2.
Therefore, in order to ensure that the conduction time of the second switching tube T2 in different driving modules 100 is consistent, when the drain-source voltage is smaller, the capacitance value of the first capacitor C1 to be set is larger; conversely, when the drain-source voltage is larger, the capacitance value of the first capacitor C1 to be set is smaller. In particular, in an application, the first capacitor C1 may not be set for the second switching tube T2 in the driving module 100 farthest from the driving chip 200, that is, the gate-drain capacitance value in the second switching tube T2 is only parasitic capacitance between the gate and the drain of the second switching tube T2, the duration of the miller stage corresponding to the second switching tube T2 is determined based on the setting, and the durations of the miller stages corresponding to the second switching tube T2 in other driving modules 100 are unified by the capacitance value of the first capacitor C1.
Referring to fig. 6, fig. 6 shows an array emission driving signal EM outputted from the driving module 100 farthest from the driving chip 200 in the light emitting driving circuit of the present invention F An array emission driving signal EM output from the driving module 100 closest to the driving chip 200 C Is a simulation diagram of (1); as can be seen from FIG. 6, EM F For transmitting driving signals for the array identical to the output of the first switching tube T1, i.e. the first switching tube T1 and the second switching tube T2 are simultaneously turned on and off, EM C For transmitting driving signals for the array delayed by the second switching tube T2, although EM F With EM C In the driving module 100 closest to the driving chip 200, the array transmitting driving signal having a shorter fall time is elongated by the second switching tube T2, so that EM F With EM C At time t2, the on-voltage Von, EM, of the first drive switching tube TD1 is reached F With EM C The starting effective time of the OLED is the same, so that the luminous time of the OLED corresponding to the pixel rows at different positions is the same, and the display uniformity is ensured.
The invention also provides a display panel, which comprises a light emitting drive line and a light emitting drive circuit, wherein the structure of the light emitting drive circuit can refer to the above embodiment, and the description is omitted herein. It should be noted that, since the display panel of the present embodiment adopts the technical scheme of the light-emitting driving circuit, the display panel has all the beneficial effects of the light-emitting driving circuit.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or system that comprises the element. The foregoing embodiment numbers of the present invention are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.
The foregoing description is only of the preferred embodiments of the present invention, and is not intended to limit the scope of the invention, but rather is intended to cover any equivalents of the structures or equivalent processes disclosed herein or in the alternative, which may be employed directly or indirectly in other related arts.
Claims (10)
1. A light-emitting driving circuit, characterized in that the light-emitting driving circuit comprises a plurality of driving modules, each driving module is connected with a corresponding light-emitting driving wire; the driving module comprises a signal generating unit and a signal compensating unit; the output end of the signal generating unit is connected with the light-emitting driving line, and the signal compensating unit is connected between the signal generating unit and the light-emitting driving line; wherein:
the signal generation unit is used for sending an array emission driving signal to the light emitting driving line, wherein the array emission driving signal indicates the switching device corresponding to the light emitting driving line to be conducted;
the signal compensation unit is used for compensating the starting effective duration of the array emission driving signals so as to enable the starting effective duration of the array emission driving signals corresponding to the signal generation units to be consistent.
2. The light-emitting driving circuit according to claim 1, wherein the signal compensation unit includes a switching subunit and a delay subunit; the switch subunit is connected between the signal generating unit and the light-emitting driving line, and the delay subunit is connected with the control end of the switch subunit; wherein:
the switch subunit is used for being conducted after the signal generating unit outputs the array emission driving signal to reach the time delay duration;
and the delay subunit is used for determining the delay time length.
3. The light-emitting drive circuit according to claim 2, wherein the signal generating unit comprises a signal processing subunit and a first switching tube, wherein an output end of the signal processing subunit is connected to a control end of the first switching tube, an input end of the first switching tube is connected to a row on voltage end, and an output end of the first switching tube is connected to the light-emitting drive line through the signal compensating unit.
4. A light-emitting drive circuit as claimed in claim 3, characterized in that the switching sub-unit comprises a second switching tube, the control end of the second switching tube being connected to the control end of the first switching tube, the input end of the second switching tube being connected to the output end of the first switching tube, the output end of the second switching tube being connected to the light-emitting drive line, the control end of the second switching tube being further connected to the delay sub-unit.
5. The light-emitting drive circuit according to claim 4, wherein a gate-drain capacitance value and a drain-source voltage of the second switching transistor in each of the signal compensation units are equal to each other when the signal generation unit outputs the array emission drive signal.
6. The light-emitting driver circuit of claim 4, wherein the delay sub-unit comprises a first capacitor connected between the control terminal of the second switching tube and the output terminal of the second switching tube.
7. The light-emitting driver circuit of claim 6, further comprising a driver chip, each of the driver modules being coupled to the driver chip;
the capacitance value of the first capacitor corresponding to the first signal compensation unit is 0, wherein the first signal compensation unit is the signal compensation unit with the longest connecting line length between the first signal compensation unit and the driving chip;
the length of the connecting line between the signal compensation unit and the driving chip is inversely related to the capacitance value of the first capacitor.
8. The light-emitting driving circuit according to any one of claims 3 to 7, wherein the first switching tube is a PMOS tube, a control end of the first switching tube is a gate of the PMOS tube, an input end of the first switching tube is a source of the PMOS tube, and an output end of the first switching tube is a drain of the PMOS tube;
the row starting voltage end is a starting voltage low-voltage end;
the second switching tube is a PMOS tube, the control end of the second switching tube is the grid electrode of the PMOS tube, the input end of the second switching tube is the source electrode of the PMOS tube, and the output end of the second switching tube is the drain electrode of the PMOS tube.
9. The light-emitting driving circuit according to any one of claims 3 to 7, wherein the first switching tube is an NMOS tube, a control end of the first switching tube is a gate of the NMOS tube, an input end of the first switching tube is a drain of the NMOS tube, and an output end of the first switching tube is a source of the NMOS tube;
the row starting voltage end is a starting voltage high-voltage end;
the second switching tube is an NMOS tube, the control end of the second switching tube is the grid electrode of the NMOS tube, the input end of the second switching tube is the drain electrode of the NMOS tube, and the output end of the second switching tube is the source electrode of the NMOS tube.
10. A display panel comprising light emitting drive lines and a light emitting drive circuit as claimed in any one of claims 1 to 9.
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| CN202311760432.8A CN117542317B (en) | 2023-12-19 | 2023-12-19 | Light-emitting driving circuit and display panel |
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