CN117538591A

CN117538591A - Method and circuit for reducing residual error generated during rotation of Hall current

Info

Publication number: CN117538591A
Application number: CN202410026110.9A
Authority: CN
Inventors: 郁炜嘉; 牛智文
Original assignee: Saizhuo Electronic Technology Shanghai Co ltd
Current assignee: Saizhuo Electronic Technology Shanghai Co ltd
Priority date: 2024-01-09
Filing date: 2024-01-09
Publication date: 2024-02-09
Anticipated expiration: 2044-01-09
Also published as: CN117538591B

Abstract

The invention relates to a method and a circuit for reducing residual errors generated when Hall current rotates. The problem of residual error of Hall induced voltage caused by parasitic resistance or capacitance of the Hall element when the Hall current rotates is solved. The specific method comprises the following steps: when the Hall current starts to rotate the phase, a first preset voltage is applied to the induction output terminal in a preset time period, and a second preset voltage is applied to the bias input terminal, so that the voltages of the induction output terminal and the bias input terminal are quickly converted from a current steady state to a new steady state in a short time. Accordingly, the time for the initial value of the error of the hall sensing voltage to converge to zero in an exponential form is significantly reduced, so that the residual error of the hall sensing voltage is significantly reduced when the rotation of the hall current is completed. Compared with the prior art, the method can effectively and rapidly reduce the residual error of the Hall induced voltage, thereby improving the output accuracy of the Hall sensor, and is particularly suitable for the high-frequency Hall current rotation condition.

Description

Method and circuit for reducing residual error generated during rotation of Hall current

Technical Field

The invention relates to the field of Hall sensors, in particular to a method and a circuit for reducing residual errors generated during rotation of Hall current.

Background

In the hall sensor, in order to eliminate the mismatch of the hall element itself and the influence of low-frequency noise on the output of the hall sensor, a hall current rotation technology is generally adopted. This technique is to sequentially apply a hall bias voltage or bias current between opposite corners of a hall element and detect a hall induced voltage generated between other two terminals perpendicular thereto at the same time, so as to characterize the magnetic field flux density perpendicular to the hall element. The hall current rotation technique is essentially a chopper stabilization technique, and the hall current rotation frequency/chopper frequency is proportional to the bandwidth of the hall sensor. However, with the trend of the hall sensor to be faster, the rotation frequency of the hall current is also increasing, so that the delay effect caused by the parasitic resistance and parasitic capacitance of the hall element is increased.

The hall current rotation technique may employ different phase rotations (e.g., 2/4/8/16 phases), here illustrated as 2-phase rotations. Fig. 1 is a schematic diagram of a hall current rotation for 2-phase rotation. Fig. 2 is a waveform diagram of the voltages at terminals a-D on the hall element shown in fig. 1 and the voltages induced by the hall element. Wherein V is _SENSE The voltage induced by the hall element is called hall induced voltage, and the hall induced voltage is proportional to the magnetic flux density of the magnetic field perpendicular to the hall element. However, in actual case, the hall element has a parasitic resistance R and a parasitic capacitance C, which form a time constant τ=rc as shown in fig. 3. After each current rotation (switching), V _SENSE Error slave (V) _HI -V _LO -V _H ) Gradually converging to 0 in an exponential form, where V _H Is ideally a hall induced voltage. In practice, the parasitic resistance and parasitic capacitance of the hall element form a first-order low-pass network, and when the current rotates each time, the voltage of each terminal of the hall element actually presents the step response characteristic of the first-order system, and after each current rotation, the four terminals of the hall element need to take a certain time to reach a new stable state. As shown in connection with fig. 2, the gray waveform is an ideal voltage waveform, and the black is a voltage waveform in which parasitic resistance and parasitic capacitance exist, and the percentage error between the two decreases at an exp (-t/RC) speed, so that the larger the RC product, the longer it takes to converge to an ideal value. For example, when time passes 3τ, the error is reduced toAbout 5% or less; when time passes 7τ, the error is reduced to below about 0.1%.

When the hall current rotation frequency is low, there is enough time for the error to decay to a negligible range. However, as the rotation frequency of the hall current increases, at the end of one switching period, the residual error becomes larger but not negligible, which results in the problem that the residual error cannot be distinguished from the hall sensing voltage sensed by the hall element, and finally becomes an output error of the hall sensor, thereby affecting the accuracy of the output signal of the hall sensor.

Disclosure of Invention

The invention aims to solve the technical problem of providing a method and a circuit for reducing residual errors generated when a Hall current rotates, wherein the residual errors of a Hall element at the end of a current rotation switching period are reduced by introducing a first preset voltage and a second preset voltage in a preset time period.

The technical scheme for solving the technical problems is as follows: a method of reducing residual error in hall current rotation applied to a hall element, wherein the hall element includes a bias input terminal and an sense output terminal, the method comprising:

when the Hall current starts to rotate in phase, a first preset voltage is applied to the induction output terminal in a preset time period, so that the voltage of the induction output terminal is quickly converted from a first current steady-state voltage to a first new steady-state voltage; wherein the first new steady state voltage matches the first preset voltage; and is combined with

Determining a bias type of the bias input terminal, wherein when the bias type is current bias, a second preset voltage is applied to the bias input terminal in the preset time period, so that the voltage of the bias input terminal is quickly converted from a second current steady-state voltage to a second new steady-state voltage; wherein the second new steady state voltage matches the second preset voltage.

On the basis of the technical scheme, the invention can be improved as follows.

Further, the sense output terminal includes a first sense output terminal and a second sense output terminal; when the Hall current starts to rotate in phase, a first preset voltage is applied to the induction output terminal in a preset time period, so that the voltage of the induction output terminal is quickly converted from a first current steady-state voltage to a first new steady-state voltage, wherein the first new steady-state voltage is matched with the first preset voltage, and the method specifically comprises the following steps of:

if the first current steady-state voltage of the first inductive output terminal is a high steady-state voltage, and the first current steady-state voltage of the corresponding second inductive output terminal is a low steady-state voltage, when the Hall current starts to rotate the phase, the intermediate steady-state voltage is applied to the first inductive output terminal and the second inductive output terminal simultaneously in the preset time period, so that the voltage of the first inductive output terminal is quickly converted from the Gao Wentai voltage to the first new steady-state voltage, and the voltage of the second inductive output terminal is quickly converted from the low steady-state voltage to the first new steady-state voltage; wherein the first new steady state voltage matches the intermediate steady state voltage.

Further, applying an intermediate steady-state voltage to the first and second sense output terminals simultaneously, specifically includes:

and shorting the first induction output terminal and the second induction output terminal in the preset time period by adopting a first switch.

if the first current steady-state voltage of the first inductive output terminal is an intermediate steady-state voltage, and the first current steady-state voltage of the corresponding second inductive output terminal is an intermediate steady-state voltage, when the Hall current starts to rotate the phase, the high steady-state voltage is applied to the first inductive output terminal in the preset time period, and meanwhile, the low steady-state voltage is applied to the second inductive output terminal, so that the voltage of the first inductive output terminal is quickly converted from the intermediate steady-state voltage to the first new steady-state voltage, and the voltage of the second inductive output terminal is quickly converted from the intermediate steady-state voltage to the first new steady-state voltage; wherein the first new steady state voltage of the first sense output terminal matches the Gao Wentai voltage; the first new steady state voltage of the second sense output terminal matches the low steady state voltage.

Further, applying a high steady-state voltage to the first inductive output terminal and simultaneously applying a low steady-state voltage to the second inductive output terminal within the preset time period specifically includes:

in the preset time period, a second switch is adopted to jointly connect the first induction output terminal and the second induction output terminal into a preset common mode voltage;

the preset common-mode voltage is an average value of steady-state values of the Hall induced voltage of the first induction output terminal and the Hall induced voltage of the second induction output terminal in a Hall current rotation phase.

Further, the bias input terminal includes a first bias input terminal and a second bias input terminal; determining a bias type of the bias input terminal, wherein when the bias type is current bias, a second preset voltage is applied to the bias input terminal in the preset time period, so that the voltage of the bias input terminal is quickly converted from a second current steady-state voltage to a second new steady-state voltage; wherein, in the matching of the second new steady-state voltage and the second preset voltage, the method specifically includes:

if the second current steady-state voltage of the first bias input terminal is a high steady-state voltage, and the second current steady-state voltage of the corresponding second bias input terminal is a low steady-state voltage, applying an intermediate steady-state voltage to the first bias input terminal and the second bias input terminal simultaneously in the preset time period, so that the voltage of the first bias input terminal is quickly converted from the Gao Wentai voltage to the second new steady-state voltage, and the voltage of the second bias input terminal is quickly converted from the low steady-state voltage to the second new steady-state voltage; wherein the second new steady state voltage matches the intermediate steady state voltage.

Further, by simultaneously applying an intermediate steady-state voltage to the first bias input terminal and the second bias input terminal within the preset period of time, the method specifically includes:

in a preset time period, a third switch and a first voltage source are adopted to enable the first bias input terminal to be connected with an intermediate steady-state voltage; and is combined with

And connecting the second bias input terminal to an intermediate steady-state voltage by using a fourth switch and a second voltage source.

if the second current steady-state voltage of the first bias input terminal is the intermediate steady-state voltage, and the second current steady-state voltage of the corresponding second bias input terminal is the intermediate steady-state voltage, applying a high steady-state voltage to the first bias input terminal and simultaneously applying a low steady-state voltage to the second bias input terminal in the preset time period, so that the voltage of the first bias input terminal is quickly converted from the intermediate steady-state voltage to the second new steady-state voltage, and the voltage of the second bias input terminal is quickly converted from the intermediate steady-state voltage to the second new steady-state voltage; wherein said second new steady state voltage of said first bias input terminal matches said Gao Wentai voltage, said second new steady state voltage of said second bias input terminal matches said low steady state voltage.

Further, by applying a high steady-state voltage to the first bias input terminal and simultaneously applying a low steady-state voltage to the second bias input terminal within the preset time period, the method specifically includes:

in a preset time period, a fifth switch and a third voltage source are adopted to enable the first bias input terminal to be connected with high steady-state voltage; and is combined with

The second bias input terminal is connected to a low steady state voltage using a sixth switch and a fourth voltage source.

Based on the method for reducing the residual error generated during the rotation of the Hall current, the invention also provides a circuit for reducing the residual error generated during the rotation of the Hall current.

A circuit for reducing residual error generated when Hall current rotates is applied to a Hall element, wherein the Hall element comprises a bias input terminal and an induction output terminal. The circuit comprises:

the first preset voltage circuit is connected with the induction output terminal and is used for applying a first preset voltage to the induction output terminal in a preset time period when the Hall current starts to rotate the phase, so that the voltage of the induction output terminal is quickly converted from a first current steady-state voltage to a first new steady-state voltage; wherein the first new steady state voltage matches the first preset voltage;

The second preset voltage circuit is connected with the bias input terminal and is used for applying a second preset voltage to the bias input terminal in the preset time period when the bias type of the bias input terminal is current bias, so that the voltage of the bias input terminal is quickly converted from a second current steady-state voltage to a second new steady-state voltage; wherein the second new steady state voltage matches the second preset voltage.

The beneficial effects of the invention are as follows: in the method and the circuit for reducing residual errors generated when the Hall current rotates, the parasitic resistance/capacitance of the Hall element cannot be changed, but when the Hall current starts to rotate in phase, a first preset voltage is applied to an induction output terminal of the Hall element in a preset time period, so that the voltage of the induction output terminal is quickly converted from a first current steady-state voltage to a first new steady-state voltage, and the first new steady-state voltage is matched with the first preset voltage; and simultaneously, applying a second preset voltage to the bias input terminal of the Hall element, so that the voltage of the bias input terminal is quickly converted from the second current steady-state voltage to a second new steady-state voltage, and the second new steady-state voltage is matched with the second preset voltage. In addition, because the preset time period is relatively small in the Hall current rotation period, the voltage states of the induction output terminal and the bias input terminal can be converted from the current steady state to the new steady state in a short time, and then, when the preset time period is ended, the residual error initial value of the Hall induction voltage is obviously reduced, and further, when the residual error initial value of the Hall induction voltage is in an exponential form to be converged to zero in a period of time after the preset time period is ended, the time for converging to zero is correspondingly obviously reduced, so that the residual error of the Hall induction voltage is obviously reduced when the Hall current rotation period is ended, and the residual error of the Hall induction voltage is prevented from becoming the final output error of the Hall sensor. Compared with the prior art, the method can effectively and rapidly reduce the residual error of the Hall induced voltage, thereby improving the output accuracy of the Hall sensor, and is particularly suitable for the high-frequency Hall current rotation condition.

Drawings

FIG. 1 is a schematic diagram of a prior art Hall current rotation;

FIG. 2 is a waveform diagram of the voltages at terminals A-D of the Hall element shown in FIG. 1 and the voltages induced by the Hall element;

FIG. 3 is a schematic diagram of a Hall element with parasitic resistance and parasitic capacitance in the prior art;

FIG. 4 is a step diagram of a method for reducing residual error generated during Hall current rotation according to the present invention;

FIG. 5 is a waveform diagram of a Hall current rotation clock, a preset time period, voltages of A-D terminals and Hall induced voltages in a method for reducing residual errors of Hall current rotation according to the present invention;

FIG. 6 is a step S11a of the method for reducing residual error generated during rotation of the Hall current shown in FIG. 4;

FIG. 7 is a step S11a1 of the method for reducing residual error generated during rotation of the Hall current shown in FIG. 6;

FIG. 8 is a step diagram of S11 a' of the method of FIG. 4 for reducing residual error generated during rotation of the Hall current;

FIG. 9 is a step S11 a' 1 of the method of reducing residual error generated during rotation of the Hall current shown in FIG. 8;

FIG. 10 is a step S11b of the method for reducing residual error generated during rotation of the Hall current shown in FIG. 4;

FIG. 11 is a step S11b1 of the method for reducing residual error generated during rotation of the Hall current shown in FIG. 10;

FIG. 12 is a step S11 b' of the method of reducing residual error generated during rotation of the Hall current shown in FIG. 4;

FIG. 13 is a step S11 b' 1 of the method of FIG. 12 for reducing residual error in Hall current rotation;

FIG. 14 is a block diagram of a circuit for reducing residual error in Hall current rotation in accordance with the present invention;

FIG. 15 is a circuit diagram of a circuit for reducing residual error in Hall current rotation in accordance with one embodiment shown in FIG. 14;

fig. 16 is a circuit diagram of a preset time period setting circuit of a circuit for reducing residual error generated when the hall current rotates according to one embodiment shown in fig. 14.

Detailed Description

The principles and features of the present invention are described below with reference to the drawings, the examples are illustrated for the purpose of illustrating the invention and are not to be construed as limiting the scope of the invention.

As shown in connection with fig. 1 and 2, the terminal voltage of the hall element has three stable states, i.e., a high steady state, a medium steady state, and a low steady state, during the rotation of the hall current. When one terminal of the Hall element is in a high steady state, the voltage of the terminal is the high steady state voltage V _HI . When one terminal of the Hall element is in an intermediate steady state, the other terminal The voltage is the intermediate steady-state voltage V _MED . When one terminal of the Hall element is in a low steady state, the voltage of the terminal is the low steady state voltage V _LO . For each terminal of the Hall element, the voltage is switched between two stable states, i.e. at a high steady-state voltage V _HI And an intermediate steady-state voltage V _MED Switching between, or at, low steady-state voltage V _LO And an intermediate steady-state voltage V _MED Switching between. That is, in the hall current rotation technique, each terminal voltage of the hall element is flipped once every half clock period of the clock signal CLK, that is, each terminal voltage is gradually converted from the current steady-state voltage to the corresponding new steady-state voltage in every half clock period.

However, as shown in fig. 3, due to the parasitic resistance R and the parasitic capacitance C of the hall element, a corresponding residual error may be generated in each process of converting the voltage of each terminal from the current steady-state voltage to the corresponding new steady-state voltage. When the hall current rotation frequency is low, there may be enough time for the residual error to decay to a negligible range. However, as the frequency increases, the residual error becomes non-negligible at the end of a hall current rotation period, and this residual error is indistinguishable from the hall induced voltage sensed by the hall element, and eventually becomes the error of the sensor output.

Accordingly, the present invention provides a method of reducing residual error generated when a hall current is rotated, applied to a hall element including a bias input terminal and an sense output terminal. The sense output terminals include a first sense output terminal B and a second sense output terminal D. The bias input terminals include a first bias input terminal a and a second bias input terminal C.

Referring to fig. 4 and 5, CLK in fig. 5 represents a waveform diagram of a hall current rotation clock; the SET represents a change waveform diagram of a preset time period, wherein the time for which the SET is continuously at a high level is the preset time period; v (V) _B A waveform diagram representing the voltage of the first sense output terminal B, wherein the gray square wave is that the Hall element has no parasitic resistance and parasitic capacitanceUnder the condition of capacitance generation, the ideal waveform of the voltage of the first induction output terminal B, and the black line is the actual waveform of the voltage of the first induction output terminal B after the method is adopted; v (V) _D A waveform diagram representing the voltage of the second induction output terminal D, wherein the gray square wave is an ideal waveform of the voltage of the second induction output terminal D under the condition that the Hall element has no parasitic resistance and parasitic capacitance, and the black line is an actual waveform of the voltage of the second induction output terminal D after the method is adopted; v (V) _A A waveform diagram representing the voltage of the first bias input terminal A, wherein gray square waves are ideal waveforms of the voltage of the first bias input terminal A under the condition that the Hall element has no parasitic resistance and parasitic capacitance, and black lines are actual waveforms of the voltage of the first bias input terminal A after the method is adopted; v (V) _C A waveform diagram representing the voltage of the second bias input terminal C, wherein the gray square wave is an ideal waveform of the voltage of the second bias input terminal C under the condition that the Hall element has no parasitic resistance or parasitic capacitance, and the black line is an actual waveform of the voltage of the second bias input terminal C after the method is adopted; v (V) _SENSE The gray square wave is an ideal waveform of the Hall induced voltage under the condition that the Hall element does not have parasitic resistance and parasitic capacitance, and the black line is an actual waveform of the Hall induced voltage after the method is adopted.

The method comprises the following steps:

s1, when the Hall current starts to rotate the phase, applying a first preset voltage to the induction output terminal in a preset time period to enable the voltage of the induction output terminal to be quickly converted from a first current steady-state voltage to a first new steady-state voltage; wherein the first new steady state voltage matches the first preset voltage; and is combined with

The bias type of the bias input terminal is determined, and the bias type comprises current bias and voltage bias. When the bias type is current bias, applying a second preset voltage to the bias input terminal in the preset time period to quickly convert the voltage of the bias input terminal from a second current steady-state voltage to a second new steady-state voltage; wherein the second new steady state voltage matches the second preset voltage. In addition, when the bias type is voltage bias, since the bias voltage source is low-resistance, the corresponding bias input terminal can be free from applying a preset voltage.

In this embodiment, although the parasitic resistance R and the parasitic capacitance C of the hall element cannot be changed, when the hall current starts to rotate the phase, a first preset voltage is applied to the sensing output terminal of the hall element in a preset period of time, so that the voltage of the sensing output terminal is quickly converted from a first current steady-state voltage to a first new steady-state voltage, and the first new steady-state voltage is matched with the first preset voltage; and simultaneously, applying a second preset voltage to the bias input terminal of the Hall element, so that the voltage of the bias input terminal is quickly converted from the second current steady-state voltage to a second new steady-state voltage, and the second new steady-state voltage is matched with the second preset voltage. In addition, since the preset time period is relatively small in the hall current rotation period, the voltage states of the induction output terminal and the bias input terminal can be converted from the current steady state to the new steady state in a short time, and accordingly, when the preset time period is finished, the residual error initial value of the hall induction voltage is obviously reduced, and further, when the preset time period is finished, the time when the residual error initial value of the hall induction voltage gradually converges to zero in an exponential form is correspondingly obviously reduced, so that the residual error of the hall induction voltage is obviously reduced when the hall current rotation period is finished, and the residual error reduction proportion is the hall induction voltage V at the starting and ending time point of the preset time period _SENSE The ratio of the errors also prevents the residual error of the Hall sensing voltage from becoming the error of the final output of the Hall sensor. Compared with the prior art, the method can effectively and rapidly reduce the residual error of the Hall induced voltage, thereby improving the output accuracy of the Hall sensor, and is particularly suitable for the high-frequency Hall current rotation condition.

In addition, the hall current rotation may use 2/4/8/16 equal phase rotation, and for convenience of understanding, the method of the present invention is described by taking 2 phase rotation as an example, but the method of the present invention may be extended to more phase hall current rotation.

In some embodiments, when the hall current starts to rotate the phase, a first preset voltage is applied to the induction output terminal in a preset time period, so that the voltage of the induction output terminal is quickly converted from a first current steady-state voltage to a first new steady-state voltage, wherein the first new steady-state voltage is matched with the first preset voltage, and the method specifically comprises the following steps:

referring to fig. 5 and 6, step S11a is performed if the first current steady-state voltage of the first sensing output terminal B is the high steady-state voltage V _HI The first current steady-state voltage corresponding to the second induction output terminal D is a low steady-state voltage V _LO When the Hall current starts to rotate the phase, the intermediate steady-state voltage V is applied to the first induction output terminal B and the second induction output terminal D simultaneously in the preset time period _MED Causing the voltage V of the first sense output terminal B to _B From the Gao Wentai voltage V _HI Rapidly converting to the first new steady-state voltage and enabling the voltage V of the second induction output terminal D _D From the low steady state voltage V _LO Rapidly converting to the first new steady state voltage; wherein the first new steady-state voltage and the intermediate steady-state voltage V _MED Matching.

Specifically, when the clock signal CLK is high, the voltage V at the first sense output terminal B _B From a high steady-state voltage V _HI Conversion to intermediate steady-state voltage V _MED At the same time the voltage V of the second sense output terminal D _D From low steady-state voltage V _LO Conversion to intermediate steady-state voltage V _MED The method comprises the steps of carrying out a first treatment on the surface of the It can be understood that the instant at which the rising edge of the clock signal CLK comes is the current steady state, after which the clock signal CLK becomes the new steady state after passing through the high level of the half period; therefore, the first current steady-state voltage of the first induction output terminal B is a high steady-state voltage V _HI The first new steady-state voltage of the first induction output terminal B is the intermediate steady-state voltage V _MED The first current steady-state voltage of the second induction output terminal D is a low steady-state voltage V _LO A second induction output endThe first new steady-state voltage of sub-D is the intermediate steady-state voltage V _MED 。

Thus, the first preset voltage applied simultaneously to the first and second sense output terminals B and D for the preset period of time at this time is the intermediate steady-state voltage V _MED Or close to the intermediate steady-state voltage V _MED So that the voltage of the first induction output terminal B is higher than the steady-state voltage V _HI Fast conversion to intermediate steady-state voltage V _MED And the voltage of the second induction output terminal D is changed from the low steady-state voltage V _LO Fast conversion to intermediate steady-state voltage V _MED 。

In the present embodiment, as can be seen by comparing fig. 2 and 5, when the hall current starts to rotate the phase and the clock signal CLK is at a high level, the voltage V in fig. 5 _B From a high steady-state voltage V _HI Conversion to intermediate steady-state voltage V _MED Is related to the voltage V in FIG. 2 _B From a high steady-state voltage V _HI Conversion to intermediate steady-state voltage V _MED The curve of (2) is much steeper and thus the voltage V in fig. 5 _B From a high steady-state voltage V _HI Conversion to intermediate steady-state voltage V _MED Is shorter; at the same time in FIG. 5 voltage V _D From low steady-state voltage V _LO Conversion to intermediate steady-state voltage V _MED Is related to the voltage V in FIG. 2 _D From low steady-state voltage V _LO Conversion to intermediate steady-state voltage V _MED The curve of (2) is much steeper and thus the voltage V in FIG. 5 _D From low steady-state voltage V _LO Conversion to intermediate steady-state voltage V _MED Is shorter.

In some embodiments, as shown in FIG. 7, an intermediate steady state voltage V is applied to the first sense output terminal B and the second sense output terminal D simultaneously _MED Specifically, the method comprises the following steps:

step S11a1, shorting the first induction output terminal B to the second induction output terminal D in the preset time period by using a first switch K1.

In this embodiment, the first switch K1 is used to control the short circuit between the first and second sensing output terminals B and D, i.e. during the preset period of timeIn order to connect the first and second sensing output terminals B and D within a preset period of time, the first and second sensing output terminals B and D are turned off outside the preset period of time. For applying the intermediate steady-state voltage V at the same time at the first sense output terminal B and the second sense output terminal D _MED In the scheme of (a), the first induction output terminal B and the second induction output terminal D can be replaced by short-circuiting, so that the first induction output terminal B and the second induction output terminal D are connected in a preset time period to form a low-resistance path, and thus the corresponding impedance of the first induction output terminal B and the second induction output terminal D is reduced in the preset time period, and the corresponding time constant is reduced, so that compared with the prior art without forming the low-resistance path, the voltage of the first induction output terminal B and the voltage of the second induction output terminal D can be converged to be near a new steady-state voltage in a shorter time.

In addition, for a preset period of time, the starting point is the point of time when the clock signal CLK toggles; the duration between the start point and the end point of the preset time period is preferably longer than three times of the first preset time constant; wherein the first preset time constant is the product between the parasitic capacitance of the hall element and the impedance of the first switch K1.

as shown in fig. 8, in step S11 a', if the first current steady-state voltage of the first sensing output terminal B is the intermediate steady-state voltage V _MED The first current steady-state voltage corresponding to the second induction output terminal D is an intermediate steady-state voltage V _MED When the Hall current starts to rotate the phase, the high steady-state voltage V is applied to the first induction output terminal B within the preset time period _HI Simultaneously applying a low steady-state voltage V to the second sense output terminal D _LO Make the followingThe voltage V of the first induction output terminal B _B From the intermediate steady-state voltage V _MED Rapidly converting to the first new steady-state voltage and enabling the voltage V of the second induction output terminal D _D From the intermediate steady-state voltage V _MED Rapidly converting to the first new steady state voltage; wherein the first new steady-state voltage of the first sense output terminal B and the Gao Wentai voltage V _HI Matching; the first new steady-state voltage and the low steady-state voltage V of the second induction output terminal D _LO Matching.

Specifically, when the clock signal CLK is low, the voltage V at the first sense output terminal B _B From intermediate steady-state voltage V _MED Conversion to high steady-state voltage V _HI At the same time the voltage V of the second sense output terminal D _D From intermediate steady-state voltage V _MED Conversion to low steady state voltage V _LO The method comprises the steps of carrying out a first treatment on the surface of the It can be understood that the instant at which the falling edge of the clock signal CLK arrives is the current steady state, after which the clock signal CLK becomes the new steady state after passing the low level of the half period; therefore, the first current steady-state voltage of the first induction output terminal B is the intermediate steady-state voltage V _MED The first new steady-state voltage of the first inductive output terminal B is a high steady-state voltage V _HI The first current steady-state voltage of the second induction output terminal D is the intermediate steady-state voltage V _MED The first new steady-state voltage of the second induction output terminal D is a low steady-state voltage V _LO 。

Thus, the first preset voltage applied to the first induction output terminal B in the preset time period is a high steady-state voltage V _HI Or close to high steady-state voltage V _HI So that the voltage of the first sense output terminal B is from the intermediate steady-state voltage V _MED Fast conversion to high steady-state voltage V _HI The method comprises the steps of carrying out a first treatment on the surface of the At the same time, the first preset voltage applied to the second induction output terminal D is a low steady-state voltage V _LO Or close to low steady state voltage V _LO The voltage of the second induction output terminal D is led to be from the middle steady-state voltage V _MED Fast transition to low steady state voltage V _LO 。

In this embodiment, it can be seen by comparing FIGS. 2 and 5, that in the case of HallThe clock signal CLK starts rotating phase and the voltage V in FIG. 5 is low _B From intermediate steady-state voltage V _MED Conversion to high steady-state voltage V _HI Relative to the voltage V in FIG. 2 _B From intermediate steady-state voltage V _MED Conversion to high steady-state voltage V _HI The curve of (2) is much steeper and thus the voltage V in fig. 5 _B From intermediate steady-state voltage V _MED Conversion to high steady-state voltage V _HI Is shorter; at the same time in FIG. 5 voltage V _D From intermediate steady-state voltage V _MED Conversion to low steady state voltage V _LO Is related to the voltage V in FIG. 2 _D From intermediate steady-state voltage V _MED Conversion to low steady state voltage V _LO The curve of (2) is much steeper and thus the voltage V in FIG. 5 _D From low steady-state voltage V _LO Conversion to intermediate steady-state voltage V _MED Is shorter.

In some embodiments, as shown in fig. 9, a high steady-state voltage V is applied to the first sense output terminal B for the preset period of time _HI Simultaneously applying a low steady-state voltage V to the second sense output terminal D _LO Specifically, the method comprises the following steps:

step S11 a' 1, in the preset time period, connecting the first and second sensing output terminals B and D together to a preset common mode voltage V by using a second switch K2 _CM ；

Wherein the preset common-mode voltage V _CM For the Hall induced voltage V of the first induced output terminal B in the phase of Hall current rotation _sens ⁺ And the Hall induced voltage V of the second induced output terminal D _sens ^- Is a mean of steady state values of (c).

In this embodiment, a second switch K2 is used to control the first and second sensing output terminals B and D to commonly access a preset common mode voltage V _CM I.e. a preset common-mode voltage V is switched in between the first induction output terminal B and the second induction output terminal D in a preset time period _CM And the second switch K2 is controlled to be turned off outside the preset time period. Connecting two sense output terminals to a preset common for a preset period of time Mode voltage V _CM Because of the preset common-mode voltage V _CM Hall induced voltage V determining two induced output terminals _sens ⁺ And V _sens ^- In a steady state condition (a sufficient time has elapsed after one current revolution), the hall sensing voltage V at the first hall sensing terminal B _sens ⁺ With the Hall sensing voltage V on the second Hall sensing terminal D _sens ^- Almost equally, they have only a very small voltage difference caused by the Hall effect, and their average value is equal to the high steady-state voltage V at the first Hall sense terminal B _HI And a low steady state voltage V at the second hall sensing terminal D _LO Average value of (2). Connecting the two sense output terminals to the preset common mode voltage for a preset period of time may therefore enable the two sense output terminals to converge to near the steady state value in a shorter time.

In addition, for a preset period of time, the starting point is the point of time when the clock signal CLK toggles; a second preset time constant with the duration between the starting point and the ending point of the preset time period being more than three times is preferable; wherein the second preset time constant is the product between the parasitic capacitance of the hall element itself and the impedance of the second switch K2.

In some embodiments, determining a bias type of the bias input terminal, wherein when the bias type is current bias, applying a second preset voltage to the bias input terminal in the preset time period, so that the voltage of the bias input terminal is quickly converted from a second current steady-state voltage to a second new steady-state voltage; in the matching of the second new steady-state voltage and the second preset voltage, as shown in fig. 10, the method specifically includes:

Step S11b, if the second current steady-state voltage of the first bias input terminal A is the high steady-state voltage V _HI The second current steady-state voltage corresponding to the second bias input terminal C is a low steady-state voltage V _LO In this case, the intermediate steady-state voltage V is applied to the first bias input terminal a and the second bias input terminal C simultaneously for the preset period of time _MED Causing the first bias input terminal toVoltage V of A _A From the Gao Wentai voltage V _HI Rapidly switching to the second new steady state voltage and causing the voltage at the second bias input terminal C to change from the low steady state voltage V _LO Rapidly converting to the second new steady state voltage; wherein the second new steady-state voltage and the intermediate steady-state voltage V _MED Matching.

Specifically, when the clock signal CLK is low, the voltage V at the first bias input terminal A _A From a high steady-state voltage V _HI Conversion to intermediate steady-state voltage V _MED At the same time bias voltage V of input terminal C _C From low steady-state voltage V _LO Conversion to intermediate steady-state voltage V _MED The method comprises the steps of carrying out a first treatment on the surface of the It can be understood that the instant at which the rising edge of the clock signal CLK comes is the current steady state, after which the clock signal CLK becomes the new steady state after passing the low level of the half period; the second current steady state voltage of the first bias input terminal A is therefore a high steady state voltage V _HI The second new steady-state voltage of the first bias input terminal A is the intermediate steady-state voltage V _MED The second current steady state voltage of the second bias input terminal C is a low steady state voltage V _LO The second new steady-state voltage of the second bias input terminal C is the intermediate steady-state voltage V _MED 。

Thus, the present invention applies the intermediate steady-state voltage V to the first bias input terminal a and the second bias input terminal C simultaneously for a preset period of time _MED So that the voltage V of the first bias input terminal A _A From a high steady-state voltage V _HI Fast conversion to intermediate steady-state voltage V _MED And a voltage V of the second bias input terminal C _C From low steady-state voltage V _LO Fast conversion to intermediate steady-state voltage V _MED 。

In this embodiment, comparing FIGS. 2 and 5, it can be seen that the voltage V in FIG. 5 when the Hall current starts to rotate the phase and the clock signal CLK is low _A From a high steady-state voltage V _HI Conversion to intermediate steady-state voltage V _MED Relative to the voltage V in FIG. 2 _A From a high steady-state voltage V _HI Conversion to intermediate steady-state voltage V _MED The curve of (2) is much steeper and thus the electricity in figure 5Pressure V _A From a high steady-state voltage V _HI Conversion to intermediate steady-state voltage V _MED Is shorter; at the same time in FIG. 5 voltage V _C From low steady-state voltage V _LO Conversion to intermediate steady-state voltage V _MED Relative to the voltage V in FIG. 2 _C From low steady-state voltage V _LO Conversion to intermediate steady-state voltage V _MED The curve of (2) is much steeper and thus the voltage V in FIG. 5 _C From low steady-state voltage V _LO Conversion to intermediate steady-state voltage V _MED Is shorter.

In some embodiments, the intermediate steady state voltage V is applied simultaneously to the first bias input terminal a and the second bias input terminal C for the preset period of time _MED As shown in fig. 11, the method specifically includes:

step S11b1, in a preset time period, using a third switch K3 and a first voltage source V1 to connect the first bias input terminal A to the intermediate steady-state voltage V _MED The method comprises the steps of carrying out a first treatment on the surface of the And is combined with

The second bias input terminal C is connected to the middle steady-state voltage V by adopting a fourth switch K4 and a second voltage source V2 _MED 。

In this embodiment, the output voltages of the first voltage source V1 and the second voltage source V2 are both the intermediate steady-state voltage V _MED . The first voltage source V1 is connected with the first bias input terminal A through the third switch K3, the second voltage source V2 is connected with the second bias input terminal C through the fourth switch K4, and in a preset time period, the third switch K3 and the fourth switch K4 are controlled to be conducted, so that the first bias input terminal A and the second bias input terminal C can be simultaneously applied with the intermediate steady-state voltage V _MED 。

In other embodiments, there may be a voltage bias for the type of bias of the first bias input terminal a or/and the second bias input terminal C. If the bias type of the first bias input terminal a is a current bias and the bias type of the second bias input terminal C is a voltage bias, the fourth switch K4 can be always in an off state; if the bias type of the first bias input terminal a is a voltage bias and the bias type of the second bias input terminal C is a current bias, the third switch K3 can be always in an off state; if the bias type of the first bias input terminal a is a voltage bias and the bias type of the second bias input terminal C is a voltage bias, the third switch K3 and the fourth switch K4 may be always in an off state. For the bias input terminal with the bias type of voltage bias, when the Hall current starts to rotate the phase, the second preset voltage is not required to be externally connected, because the delay is generated due to RC product, the voltage source with the voltage bias is low in resistance, the low resistance means that R is small, and the generated delay is small, so that the second preset voltage is not required to be externally connected.

In addition, for a preset period of time, the starting point is the point of time when the clock signal CLK toggles; a third preset time constant with the duration between the starting point and the ending point of the preset time period being more than three times is preferable; wherein the third preset time constant is the product of the parasitic capacitance of the hall element and the impedance of the third switch K3 or the fourth switch K4.

In some embodiments, determining a bias type of the bias input terminal, wherein when the bias type is current bias, applying a second preset voltage to the bias input terminal in the preset time period, so that the voltage of the bias input terminal is quickly converted from a second current steady-state voltage to a second new steady-state voltage; in the matching of the second new steady-state voltage and the second preset voltage, as shown in fig. 12, the method specifically includes:

step S11 b', if the second current steady-state voltage of the first bias input terminal A is the intermediate steady-state voltage V _MED The second current steady-state voltage corresponding to the second bias input terminal C is an intermediate steady-state voltage V _MED When the first bias input terminal A is in the preset time period, a high steady-state voltage V is applied to the first bias input terminal A _HI At the same time, applying a low steady-state voltage V to the second bias input terminal C _LO Causing the voltage V of the first bias input terminal A to _A From the intermediate steady-state voltage V _MED Rapidly converting to the second new steady state voltage and causing the voltage V of the second bias input terminal C _C From the intermediate steady-state voltage V _MED Rapidly switching to the second new steady state voltageThe method comprises the steps of carrying out a first treatment on the surface of the Wherein the second new steady state voltage of the first bias input terminal A and the Gao Wentai voltage V _HI The second new steady state voltage of the second bias input terminal C is matched with the low steady state voltage V _LO Matching.

Specifically, when the clock signal CLK is high, the voltage V at the first bias input terminal A _A From intermediate steady-state voltage V _MED Conversion to high steady-state voltage V _HI At the same time bias voltage V of input terminal C _C From intermediate steady-state voltage V _MED Conversion to low steady state voltage V _LO The method comprises the steps of carrying out a first treatment on the surface of the It can be understood that the instant at which the rising edge of the clock signal CLK comes is the current steady state, after which the clock signal CLK becomes the new steady state after passing through the high level of the half period; the second current steady state voltage of the first bias input terminal A is thus the intermediate steady state voltage V _MED The second new steady-state voltage of the first bias input terminal A is a high steady-state voltage V _HI The second current steady-state voltage of the second bias input terminal C is the intermediate steady-state voltage V _MED The second new steady state voltage of the second bias input terminal C is a low steady state voltage V _LO 。

Thus, the second preset voltage applied to the first bias input terminal A in the preset time period is a high steady-state voltage V _HI Or close to high steady-state voltage V _HI So that the voltage V of the first bias input terminal A _A From intermediate steady-state voltage V _MED Fast conversion to high steady-state voltage V _HI The method comprises the steps of carrying out a first treatment on the surface of the At the same time, the second preset voltage applied to the second bias input terminal C is a low steady-state voltage V _LO Or close to low steady state voltage V _LO Causing the voltage V of the second bias input terminal C to _C From intermediate steady-state voltage V _MED Fast transition to low steady state voltage V _LO 。

In this embodiment, as can be seen by comparing FIGS. 2 and 5, when the Hall current starts to rotate the phase and the clock signal CLK is high, the voltage V in FIG. 5 _A From intermediate steady-state voltage V _MED Conversion to high steady-state voltage V _HI Relative to the voltage V in FIG. 2 _A From intermediate steady-state voltage V _MED TransformationIs of high steady state voltage V _HI The curve of (2) is much steeper and thus the voltage V in fig. 5 _A From intermediate steady-state voltage V _MED Conversion to high steady-state voltage V _HI Is shorter; at the same time in FIG. 5 voltage V _C From intermediate steady-state voltage V _MED Conversion to low steady state voltage V _LO Relative to the voltage V in FIG. 2 _C From intermediate steady-state voltage V _MED Conversion to low steady state voltage V _LO The curve of (2) is much steeper and thus the voltage V in FIG. 5 _C From low steady-state voltage V _LO Conversion to intermediate steady-state voltage V _MED Is shorter.

In some embodiments, the high steady-state voltage V is applied to the first bias input terminal a by applying the high steady-state voltage V for the preset period of time _HI At the same time, applying a low steady-state voltage V to the second bias input terminal C _LO As shown in fig. 13, the method specifically includes:

step S11 b' 1, in a preset time period, using a fifth switch K5 and a third voltage source V3 to connect the first bias input terminal A to the high steady-state voltage V _HI The method comprises the steps of carrying out a first treatment on the surface of the And is combined with

The second bias input terminal C is connected to the low steady-state voltage V by adopting a sixth switch K6 and a fourth voltage source V4 _LO 。

In this embodiment, the voltage output by the third voltage source V3 is a high steady-state voltage V _HI The voltages output by the fourth voltage source V4 are all low steady-state voltages V _LO . The third voltage source V3 is connected with the first bias input terminal A through the fifth switch K5, the fourth voltage source V4 is connected with the second bias input terminal C through the sixth switch K6, and in a preset time period, the fifth switch K5 and the sixth switch K6 are controlled to be conducted, so that the first bias input terminal A can be connected with the high steady-state voltage V _HI And connecting the second bias input terminal C to the low steady state voltage V _LO 。

In other embodiments, if the bias type of the first bias input terminal a is a current bias and the bias type of the second bias input terminal C is a voltage bias, the sixth switch K6 may be always in the off state; if the bias type of the first bias input terminal a is a voltage bias and the bias type of the second bias input terminal C is a current bias, the fifth switch K5 is always in an off state; if the bias type of the first bias input terminal a is a voltage bias and the bias type of the second bias input terminal C is a voltage bias, the fifth switch K5 and the sixth switch K6 may be always in an off state. For the bias input terminal with the bias type of voltage bias, when the Hall current starts to rotate the phase, the second preset voltage is not required to be externally connected, because the delay is generated due to RC product, the voltage source with the voltage bias is low in resistance, the low resistance means that R is small, and the generated delay is small, so that the second preset voltage is not required to be externally connected.

In addition, for a preset period of time, the starting point is the point of time when the clock signal CLK toggles; a fourth preset time constant, the duration between the starting point and the ending point of the preset time period of which is more than three times, is preferable; wherein the fourth preset time constant is the product of the parasitic capacitance of the hall element and the impedance of the fifth switch K5 or the sixth switch K4.

It should be noted that, in order to maintain consistency of the preset time period, all the switches adopted in the present invention are switches with equal impedance.

Comparing fig. 2 and 5, each time the clock signal CLK toggles, V is caused _A 、V _B 、V _C And V _D Exponentially changing, when the preset period SET is high, V _A 、V _B 、V _C 、V _D The change is faster than in fig. 2. Therefore, under the condition that the rotation frequency of the Hall current is higher, the voltage states of the induction output terminal and the bias input terminal can be converted from the current steady state to the new steady state in a short time, and then, the initial value of the error of the Hall induction voltage is obviously reduced when the preset time period is ended, and further, the time when the initial value of the error of the Hall induction voltage gradually converges to zero in an exponential form is correspondingly obviously reduced in a period of time after the preset time period is ended, so that the residual error of the Hall induction voltage is obviously reduced when the rotation period of the Hall current is ended, and the residual error of the Hall induction voltage is prevented from becoming the final output error of the Hall sensor. Compared with the prior art, the inventionThe invention can effectively and rapidly reduce the residual error of the Hall induced voltage, thereby improving the output accuracy of the Hall sensor, and is particularly suitable for the high-frequency Hall current rotation condition.

As shown in fig. 14, a circuit 1 for reducing residual error generated when a hall current is rotated is applied to a hall element 2, wherein the hall element 2 includes a bias input terminal 3 and an induction output terminal 4. The circuit 1 comprises:

the first preset voltage circuit 5 is connected with the induction output terminal 4 and is used for applying a first preset voltage to the induction output terminal 4 in a preset time period when the Hall current starts to rotate the phase, so that the voltage of the induction output terminal 4 is quickly converted from a first current steady-state voltage to a first new steady-state voltage; wherein the first new steady state voltage matches the first preset voltage;

a second preset voltage circuit 6, connected to the bias input terminal 3, configured to apply a second preset voltage to the bias input terminal 3 during the preset period of time when the bias type of the bias input terminal 3 is current bias, so that the voltage of the bias input terminal 3 is quickly converted from a second current steady-state voltage to a second new steady-state voltage; wherein the second new steady state voltage matches the second preset voltage.

In this embodiment, by setting the first preset voltage circuit 5, and applying the first preset voltage to the sensing output terminal 4 of the hall element 2 in a preset period of time, the voltage of the sensing output terminal 4 is quickly converted from the first current steady-state voltage to the first new steady-state voltage, and the first new steady-state voltage is matched with the first preset voltage; meanwhile, by providing a second preset voltage circuit 6 for applying a second preset voltage to the bias input terminal 3 of the Hall element 2, the voltage of the bias input terminal 3 is rapidly converted from a second current steady-state voltage to a second new steady-state voltage, and the second new steady-state voltage is matched with the second preset voltage. In addition, since the preset time period is relatively small in the hall current rotation period, the voltage states of the sensing output terminal 4 and the bias input terminal 3 can be converted from the current steady state to the new steady state in a short time, and accordingly, at the end of the preset time period, the initial value of the error of the hall sensing voltage is obviously reduced, and further, at the end of the preset time period, the time when the initial value of the error of the hall sensing voltage gradually converges to zero in an exponential form is correspondingly obviously reduced, so that the residual error of the hall sensing voltage is obviously reduced at the end of the hall current rotation period, and the reduced proportion of the residual error is the hall sensing voltage V at the starting and ending time points of the preset time period _SENSE The ratio of the errors also prevents the residual error of the Hall sensing voltage from becoming the error of the final output of the Hall sensor. Compared with the prior art, the method can effectively and rapidly reduce the residual error of the Hall induced voltage, thereby improving the output accuracy of the Hall sensor, and is particularly suitable for the high-frequency Hall current rotation condition.

As shown in fig. 15, in some embodiments, the bias input terminal 3 includes a first bias input terminal a, a second bias input terminal C. The sense output terminal 4 includes a first sense output terminal B and a second sense output terminal D.

The first preset voltage circuit 5 includes a first switch K1. The first switch K1 is connected between the first sensing output terminal B and the second sensing output terminal D, and is configured to control the first sensing output terminal B to be shorted with the second sensing output terminal D in a preset time period.

In some embodiments, the first preset voltage circuit 5 includes a second switch K2, one end of the second switch K2 is connected to the first and second sense output terminals B and D, and the other end is connected to a preset common mode voltage V _CM For controlling the first and second sense output terminals B and D to commonly access the preset common-mode voltage V within the preset time period _CM 。

In some embodiments, the second preset voltage circuit 6 includes a third switch K3 and a first voltage source V1. The first voltage source V1 is onThe third switch K3 is connected with the first bias input terminal A for controlling the first bias input terminal A to be connected with the intermediate steady-state voltage V _MED 。

In some embodiments, the second preset voltage circuit 6 includes a fourth switch K4 and a second voltage source V2. The second voltage source V2 is connected to the second bias input terminal C through the fourth switch K4 for controlling the second bias input terminal C to access the intermediate steady-state voltage V _MED 。

In some embodiments, the second preset voltage circuit 6 includes a fifth switch K5 and a third voltage source V3. The third voltage source V3 is connected to the first bias input terminal A via the fifth switch K5 for controlling the first bias input terminal A to access the high steady-state voltage V _HI 。

In some embodiments, the second preset voltage circuit 6 includes a sixth switch K6 and a fourth voltage source V4. The fourth voltage source V4 is connected to the second bias input terminal C through the sixth switch K6 for controlling the second bias input terminal C to be connected to the low steady-state voltage V _LO 。

In some embodiments, the circuit 1 further includes a preset time period setting circuit 7 connected to the first preset voltage circuit 5 and the second preset voltage circuit 6. Specifically, the preset time period setting circuit 7 is connected to the first switch K1, the second switch K2, the third switch K3, the fourth switch K4, the fifth switch K5 and the sixth switch K6, and is configured to control the first switch K1, the second switch K2, the third switch K3, the fourth switch K4, the fifth switch K5 and the sixth switch K6 to be turned on in the preset time period and turned off outside the preset time period.

Wherein the output voltages of the first voltage source V1 and the second voltage source V2 are the intermediate steady-state voltage V _MED The voltage output by the third voltage source V3 is a high steady-state voltage V _HI The voltages output by the fourth voltage source V4 are all low steady-state voltages V _LO 。

Specifically, as shown in fig. 16, M1 to M4 are transistors, C1 AND C2 are capacitors, NOT1 to NOT3 are NOT gates, AND1 AND2 are AND gates, inv1 AND inv 2 are inverters, AND OR is an OR gate; the SET lasting high time is the preset time period; and the SET signal generated by the preset time period setting circuit acts on the corresponding switch, the switch is turned on when the SET signal is at a high level, and the switch is turned on when the SET signal is at a low level.

The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the invention are intended to be included within the scope of the invention.

Claims

1. A method of reducing residual error in hall current rotation applied to a hall element, wherein the hall element includes a bias input terminal and an sense output terminal, the method comprising:

2. The method of reducing residual error in a hall current rotation of claim 1, the sense output terminals comprising a first sense output terminal and a second sense output terminal; the method is characterized in that when the Hall current starts to rotate the phase, a first preset voltage is applied to the induction output terminal in a preset time period, so that the voltage of the induction output terminal is quickly converted from a first current steady-state voltage to a first new steady-state voltage, wherein the first new steady-state voltage is matched with the first preset voltage, and the method specifically comprises the following steps of:

3. The method for reducing residual error in hall current rotation according to claim 2, wherein applying an intermediate steady-state voltage to the first and second sense output terminals simultaneously comprises:

4. The method of reducing residual error in a hall current rotation of claim 1, the sense output terminals comprising a first sense output terminal and a second sense output terminal; the method is characterized in that when the Hall current starts to rotate the phase, a first preset voltage is applied to the induction output terminal in a preset time period, so that the voltage of the induction output terminal is quickly converted from a first current steady-state voltage to a first new steady-state voltage, wherein the first new steady-state voltage is matched with the first preset voltage, and the method specifically comprises the following steps of:

5. The method of reducing residual error in hall current rotation of claim 4 wherein applying a high steady state voltage to the first sense output terminal while applying a low steady state voltage to the second sense output terminal for the predetermined period of time comprises:

6. The method of reducing residual error in a hall current rotation of claim 1, the bias input terminal comprising a first bias input terminal and a second bias input terminal; the method is characterized by comprising the steps of determining the bias type of the bias input terminal, wherein when the bias type is current bias, applying a second preset voltage to the bias input terminal in the preset time period, so that the voltage of the bias input terminal is quickly converted from a second current steady-state voltage to a second new steady-state voltage; wherein, in the matching of the second new steady-state voltage and the second preset voltage, the method specifically includes:

7. The method of reducing residual error in hall current rotation of claim 6, wherein said applying an intermediate steady state voltage to said first bias input terminal and said second bias input terminal simultaneously for said predetermined period of time comprises:

8. The method of reducing residual error in a hall current rotation of claim 1, the bias input terminal comprising a first bias input terminal and a second bias input terminal; the method is characterized by comprising the steps of determining the bias type of the bias input terminal, wherein when the bias type is current bias, applying a second preset voltage to the bias input terminal in the preset time period, so that the voltage of the bias input terminal is quickly converted from a second current steady-state voltage to a second new steady-state voltage; wherein, in the matching of the second new steady-state voltage and the second preset voltage, the method specifically includes:

9. The method of reducing residual error in hall current rotation of claim 8, wherein applying a high steady state voltage to the first bias input terminal while applying a low steady state voltage to the second bias input terminal for the preset period of time comprises:

10. A circuit for reducing residual error in rotation of a hall current applied to a hall element, wherein the hall element includes a bias input terminal and an sense output terminal, the circuit comprising: