CN117532885B - Intelligent auxiliary system, method and storage medium for 3D printing - Google Patents

Intelligent auxiliary system, method and storage medium for 3D printing Download PDF

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CN117532885B
CN117532885B CN202410037425.3A CN202410037425A CN117532885B CN 117532885 B CN117532885 B CN 117532885B CN 202410037425 A CN202410037425 A CN 202410037425A CN 117532885 B CN117532885 B CN 117532885B
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memristor
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门正兴
王阳合
高曦
王莲莲
白晶斐
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Chengdu Aeronautic Polytechnic
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Abstract

The embodiment of the application discloses a 3D printing intelligent auxiliary system, a method and a storage medium, wherein the 3D printing intelligent auxiliary system comprises: the multi-processor system-on-chip is used for acquiring real-time picture data of the 3D printing mechanical arm, initializing and training a hierarchical overrun learning machine memristor hardware network model based on hierarchical overrun learning machine memristor hardware network optimization based on the real-time picture data to acquire training tag data, carrying out randomization weight distribution based on the training tag data, and sending the acquired weight distribution data to the hierarchical overrun learning machine memristor hardware network to acquire parameter adjustment decisions of the mechanical arm based on an output result of the hierarchical overrun learning machine memristor hardware network model, thereby assisting control of the mechanical arm in 3D printing. The method solves the problems of high calculation power consumption and large delay in the prior art.

Description

Intelligent auxiliary system, method and storage medium for 3D printing
Technical Field
The application relates to the technical field of artificial intelligence auxiliary 3D printing, in particular to a 3D printing intelligent auxiliary system, a method and a storage medium.
Background
In the prior art, machine learning algorithms such as neural networks for assisting 3D printing are all run in the context of a von neumann architecture such as a CPU or GPU, where the computation and storage functions are separate, and are performed by the CPU and memory, respectively. With the development of technology, the speed and capacity of a CPU and a memory are rapidly improved, but the speed of a bus for transmitting data and instructions is limited, so that the frequent data transmission between the CPU and the memory causes a bottleneck of information processing, namely a von Neumann bottleneck; on the other hand, the memory data access speed cannot keep up with the data processing speed of the CPU, and the difference is pulled more and more, so that the memory wall phenomenon is caused, and the performance of the CPU is severely limited by the memory performance.
Therefore, the existing 3D printing intelligent auxiliary system adopting the von Neumann architecture has the problems of high calculation power consumption and large delay.
Disclosure of Invention
The embodiment of the application aims to provide a 3D printing intelligent auxiliary system, a method and a storage medium, which are used for solving the problems of high calculation power consumption and large delay existing in the prior art that a von Neumann architecture is adopted as the 3D printing intelligent auxiliary system.
To achieve the above object, an embodiment of the present application provides a 3D printing intelligent auxiliary system, including:
The multiprocessor system-on-chip and the hierarchical overrun learning machine memristor hardware network are connected, wherein,
The multiprocessor on-chip system is used for acquiring real-time picture data of the 3D printing mechanical arm, initializing and training a hierarchical overrun learning machine memristor hardware network model based on hierarchical overrun learning machine memristor hardware network optimization based on the real-time picture data to acquire training tag data, carrying out randomization weight distribution based on the training tag data, and sending the acquired weight distribution data to the hierarchical overrun learning machine memristor hardware network to acquire parameter adjustment decisions of the mechanical arm based on an output result of the hierarchical overrun learning machine memristor hardware network model, thereby assisting control of the mechanical arm in 3D printing.
Optionally, after the deriving the parameter adjustment decision for the robotic arm, the multiprocessor system-on-chip is further configured to:
and acquiring a 3D printing path code, planning a motion track of the mechanical arm based on the 3D printing path code, fusing a parameter adjustment decision of the mechanical arm, and performing parameterization adjustment on the mechanical arm so as to realize control on the mechanical arm.
Optionally, the hierarchical overrunning learner memristor hardware network includes:
a multiplexer, a generating circuit, a memristor array and an inner layer overrun learning machine memristor node, wherein,
The multiplexer is used for carrying out randomized weight distribution based on the input weight distribution data;
The generation circuit is used for generating analog direct current according to the input weight distribution data and inputting the analog direct current into the memristor array so that the memristor array copies the weight distribution data into the memristor nodes of the inner-layer overrun learning machine of each column and multiplies the weight distribution data with the random weight generated in the current mirror image array;
The memristor array is used for summing currents in the same column according to kirchhoff's law, and taking a current summation result as input of hidden layer neurons;
and the memristor node of the inner-layer overrun learning machine is used for obtaining the output result of the hidden layer neuron, completing small grid calculation, obtaining the output weight through a column scanner, and finally obtaining the output result of the memristor hardware network model of the hierarchical overrun learning machine.
Optionally, the hierarchical overrunning learner memristor hardware network further includes:
And the peak neuron circuit is used for converting the current output by the memristor array into an output result of the hidden layer neuron.
Optionally, the output result of the hierarchical overrunning learner memristor hardware network model is expressed as:
，
Wherein, Representing the output of the memristor hardware network model of the hierarchical overrunning learning machine,The hidden matrix is represented by a representation of the hidden matrix,Representing M independent hierarchical overrunning learner memristor hardware network models,Representing the output weight of all hierarchical overrun learner memristor hardware network models,Representing the output weights of M independent hierarchical overrunning learner memristor hardware network models,Representing the output weight of each independent hierarchical overrun learner memristor hardware network model, O m representing the output of the inner layer overrun learner memristor node, H m representing the hidden layer output matrix of the inner layer overrun learner memristor node,Represents the Moore-Penrose generalized inverse of the matrix,Is the sigmod activation function of the device,The object matrix is represented by a matrix of objects,Representing a given training dataset, said training dataset being formed by said real-time picture data preprocessing,AndThe random input weight and the initial bias of the memristor node of the inner layer overrun learning machine are respectively represented.
Optionally, the initializing and training the hierarchical overrun learning memristor hardware network model based on the hierarchical overrun learning memristor hardware network optimization based on the real-time picture data includes:
Minimizing the output weight parameters of the memristor hardware network model of the hierarchical overrunning learning machine in the process of training the memristor hardware network model; the method specifically comprises the following steps:
Based on the formula: And Performing convex optimization on the memristor hardware network model of the hierarchical overrun learning machine,
Wherein the method comprises the steps ofRepresenting a minimized objective functionTime output weightIs used for the value of (a) and (b),The function of the object is represented by a function of the object,Representing the constraint function(s),The representation takes the L2 norm,A training sample is represented and a sample is represented,Representing the number of training samples to be used,The constant is represented by a value that is a function of,Representing an error between the target truth value and the predicted value;
Defining an objective function for convex optimization problem augmentation: ，
Wherein the method comprises the steps of The lagrangian function is represented as such,The function of the object is represented by a function of the object,Representing the constraint function(s),The output weight is represented as a function of the output weight,The gradient constant is represented by a gradient constant,The constant is represented by a value that is a function of,The representation takes the L2 norm,Represent the firstThe gradient constant of the individual training samples is set,Represents a target true value,Representing an error between the target truth value and the predicted value;
based on the objective function, obtaining a closed solution for convex optimization and finally outputting the weight parameters: ，
Wherein the method comprises the steps of The output weight is represented as a function of the output weight,Representation ofThe order-unit matrix is used for the data processing,Representation ofThe order-unit matrix is used for the data processing,The inverse matrix is represented by a representation,The hidden layer output matrix is represented as such,Representing a transpose of the hidden layer output matrix,The constant is represented by a value that is a function of,Representing the target true value output,Representing the number of training samples to be used,And the number of memristor hidden layer nodes of the overrun learning machine is represented.
Optionally, the acquiring real-time picture data of the 3D printing mechanical arm includes:
Acquiring real-time picture data of an original image of the mechanical arm, which is acquired by a mechanical arm image acquisition device connected with the multiprocessor system-on-chip;
The obtaining the 3D printing path code, and planning the motion trail of the mechanical arm based on the 3D printing path code, includes:
And acquiring the sliced 3D printing path code input through the storage medium, converting the motion trail of the mechanical arm based on the 3D printing path code, converting the 3D printing path into the motion trail of the mechanical arm, solving the motion trail of the mechanical arm in an inversion way, and planning the motion trail of the mechanical arm by using a planning tool.
Optionally, the weight allocation data includes address and weight parameter data;
The parameter adjustment decisions of the mechanical arm comprise three parameter adjustment decisions of the speed, the acceleration and the path of the mechanical arm.
In order to achieve the above object, the present application further provides a 3D printing intelligent auxiliary method, including: acquiring real-time picture data of a 3D printing mechanical arm, and carrying out feature extraction and binarization;
initializing and training a memristor hardware network model of the hierarchical overrun learning machine based on memristor hardware network optimization based on the extracted characteristic data to obtain training tag data;
And carrying out randomized weight distribution based on the training tag data, and sending the obtained weight distribution data to the memristor hardware network of the hierarchical overrun learning machine so as to obtain a parameter adjustment decision of the mechanical arm based on an obtained output result of the memristor hardware network model of the hierarchical overrun learning machine, thereby assisting in the control of the mechanical arm in 3D printing.
To achieve the above object, the present application also provides a computer storage medium having stored thereon a computer program which, when executed by a machine, implements the steps of the method as described above.
The embodiment of the application has the following advantages:
The embodiment of the application provides a 3D printing intelligent auxiliary system, which comprises: the multi-processor system-on-chip is used for acquiring real-time picture data of the 3D printing mechanical arm, initializing and training a hierarchical overrun learning machine memristor hardware network model optimized based on the hierarchical overrun learning machine memristor hardware network based on the real-time picture data to acquire training tag data, carrying out randomized weight distribution based on the training tag data, and sending the acquired weight distribution data to the hierarchical overrun learning machine memristor hardware network to acquire parameter adjustment decisions of the mechanical arm based on an output result of the hierarchical overrun learning machine memristor hardware network model, thereby assisting control of the mechanical arm in 3D printing.
Through the system, a circuit based on the memristor is used as a hardware neural network computing unit, a multiprocessor system-on-chip is used as an auxiliary control system of the 3D printing mechanical arm, and more intelligent system assistance is provided for real-time intelligent decision making in a complex environment. As the memristor is used as a basic passive device, the memristor has nanoscale size and nonvolatile property, not only can realize continuous change of synaptic weight when simulating nerve synapses and realize integration of memory computation, but also can construct a neural network structure with higher integration level, so that the 3D printing intelligent auxiliary system adopting the hierarchical overrunning learning memristor hardware network has low calculation power consumption and small delay.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It will be apparent to those skilled in the art from this disclosure that the drawings described below are merely exemplary and that other embodiments may be derived from the drawings provided without undue effort.
FIG. 1 is a schematic diagram of a multiprocessor system-on-chip of a 3D printing intelligent auxiliary system according to an embodiment of the present application;
FIG. 2 is a schematic structural diagram of a hierarchical overrun learning machine memristor hardware network model of a 3D printing intelligent auxiliary system according to an embodiment of the present application;
FIG. 3 is a schematic structural diagram of an ELM memristor small network of a 3D printing intelligent auxiliary system provided by the embodiment of the present application;
FIG. 4 is a schematic diagram of a spiking neuron circuit of a 3D printing intelligent auxiliary system according to an embodiment of the present application;
Fig. 5 is a flowchart of a 3D printing intelligent assisting method according to an embodiment of the present application.
Detailed Description
Other advantages and advantages of the present application will become apparent to those skilled in the art from the following detailed description, which, by way of illustration, is to be read in connection with certain specific embodiments, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In addition, the technical features of the different embodiments of the present application described below may be combined with each other as long as they do not collide with each other.
An embodiment of the present application provides a 3D printing intelligent auxiliary system, including: and the multiprocessor system-on-chip and the hierarchical overrun learning machine memristor hardware network are connected.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a multiprocessor system-on-chip of a 3D printing intelligent auxiliary system provided in an embodiment of the present application, and it should be understood that the structural diagram may further include additional blocks not shown and/or blocks shown may be omitted, and the scope of the present application is not limited in this respect.
The multiprocessor system on chip (MPSOC) is used for acquiring real-time picture data of a 3D printing mechanical arm (such as a SCARA horizontal joint mechanical arm), initializing and training a hierarchical overrun learning machine memristor hardware network model (which can be simply called HELM model, HELM English is called HIERARCHICAL EXTREME LEARNING MACHINE in the following embodiment) based on the hierarchical overrun learning machine memristor hardware network optimization based on the real-time picture data to acquire training tag data, carrying out randomization weight distribution based on the training tag data, and sending the obtained weight distribution data to the hierarchical overrun learning machine memristor hardware network to obtain parameter adjustment decisions of the mechanical arm based on an output result of the hierarchical overrun learning machine memristor hardware network model, thereby assisting control of the mechanical arm in 3D printing.
Referring to fig. 1, in some embodiments, the acquiring real-time picture data of the 3D printing robot includes:
And acquiring real-time picture data of an original image of the mechanical arm, which is acquired by a mechanical arm image acquisition device (such as a camera) connected with the multiprocessor system-on-chip.
Referring to fig. 1, in some embodiments, after the deriving the parameter adjustment decisions for the robotic arm, the multiprocessor system-on-chip is further configured to:
and acquiring a 3D printing path code (such as G-code), planning a motion track of the mechanical arm based on the 3D printing path code, fusing a parameter adjustment decision of the mechanical arm, and performing parameterization adjustment on the mechanical arm so as to realize control on the mechanical arm.
Referring to fig. 1, in some embodiments, the acquiring the 3D printing path code, and performing the planning of the motion trajectory of the mechanical arm based on the 3D printing path code, includes:
And acquiring the sliced 3D printing path code input through the storage medium, converting the motion trail of the mechanical arm based on the 3D printing path code, converting the 3D printing path into the motion trail of the mechanical arm, solving the motion trail of the mechanical arm in an inversion way, and planning the motion trail of the mechanical arm by using a planning tool.
Referring to fig. 1, in particular, the inside of the multiprocessor system-on-a-chip is mainly composed of two parts, namely a PS (ARM) part and a PL (FPGA) part. The PS part is a processing system part, i.e., a central processor chip part, and the PL part is a programmable logic part, i.e., a field programmable gate array.
Specifically, the PS (ARM) part is realized by a program therein: acquiring real-time image data of an original image of the mechanical arm acquired by the mechanical arm image acquisition device, extracting features, and binarizing the extracted feature data; initializing and training HELM a model based on the extracted feature data; the resulting data (including training tag data and/or binarized feature data) is sent to the PL (FPGA) section. PL (FPGA) part is implemented by a program therein: processing the acquired training label data and configuring a randomizing weightAnd initial biasAnd performing outer-layer randomization weight distribution and inner-layer randomization weight distribution, and outputting the outer-layer randomization weight distribution and the inner-layer randomization weight distribution to a memristor hardware network of the hierarchical overrun learning machine (HELM) through address lines A <6:0> and B <6:0 >. Calculating HELM model output layers, judging model convergence, and if not, acquiring a target matrixAnd lagrange (lagrangian) function, which builds HELM models, is provided to the convex optimizer (IP kernel), consisting of a closed-form solutionObtain the optimal biasThe input update bias is returned until the model converges. After training, decision is made through a decision circuit based on the FPGA to obtain a mechanical arm parameter adjustment decision (specifically, the mechanical arm parameter adjustment decision can comprise three parameters of the speed, the acceleration and the path of the mechanical arm). Specifically, the calculation of HELM output layers is mainly a regression clustering algorithm, such as K-means, and through output weight calculation, the prediction of speed, acceleration and path is finally obtained.
Specifically, the PS (ARM) section is also realized by a program therein: acquiring a sliced 3D printing path G-code input through storage media such as an SD card, converting a mechanical arm motion track based on the 3D printing path code, converting the 3D printing path into the mechanical arm motion track, carrying out inversion solution through tools such as ROS moveit ikfast, planning the mechanical arm motion track through tools such as ROS OMPL, and fusing mechanical arm parameter adjustment decisions to carry out parameterization adjustment on the mechanical arm; the mechanical arm is controlled by ROS ActionServer or other tools.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a memristor hardware network of a 3D printing intelligent auxiliary system provided in an embodiment of the present disclosure, it should be understood that the structural diagram may further include additional blocks not shown and/or blocks shown may be omitted, and the scope of the present disclosure is not limited in this respect.
In some embodiments, as shown in fig. 2, in the hierarchical overrunning learner (HELM) memristor hardware network, the hierarchical overrunning learner memristor hardware network includes: the multi-path selector, the generating circuit, the memristor array and the memristor node of the inner-layer overrun learning machine (hereinafter, in the embodiments and the drawings, the inner-layer ELM memristor node is simply referred to as an inner-layer ELM, wherein ELM is called an Extreme LEARNING MACHINE, namely, an overrun learning machine).
Wherein the multiplexer may be a 128-way multiplexer for performing randomization weight distribution based on the input address A <6:0> and the weight parameter Data data_in1, and first calculating and simulating the random weight of the input networkMeanwhile, address A <6:0> and weight parameter data_in1 Data are demultiplexed according to the address and sent to a specific channel in the system using the serial peripheral interface. Address a <6:0> and weight parameter data_in1 Data are stored in the shift register for configuring the input current magnitude of the analog-to-digital converter in the input generation circuit (IGC, input Generting Circuit).
The IGC functions to generate analog DC current from the input address and weight parameter data and input the analog DC current into the memristor array, and copy the address and weight parameter data into the ELM memristor small network (understood as an outer neuron hidden layer) of each column by using the outer layer overrun learning machine memristor nodes (hereinafter referred to as outer layer ELM memristor nodes in the embodiments and the drawings) formed by the 1T1R memristor array) And then multiplied by the random weights generated in the 1T1R memristor array. The data processing and output modes of the inner layer ELM memristor nodes in the small ELM memristor network are the same as those of the outer layer ELM memristor nodes (the scanning modes are different, the outer layer ELM memristor nodes are scanned by columns, and the inner layer ELM memristor nodes are scanned by rows).
In fig. 1 to 3, the rn_in and clk_in signals are used to configure reset signals and clock signals of the IGC input generation circuit for resetting and refresh control of address and weight parameter data. The clk_out clock signal output by the PL (FPGA) portion clock module and the control module on the multiprocessor system-on-chip (mpssoc) drives each ELM memristor small network by column scan and stores output data into output registers C <13:0>, which are connected to the HELM output layer computation module of the PL (FPGA) portion on the multiprocessor system-on-chip (mpssoc). FIG. 3 is a schematic diagram of an ELM memristor network of a 3D printing intelligent auxiliary system according to an embodiment of the present application. In addition, the same letters a to I, which are labeled next to the arrowed lines representing data transmission in fig. 2 and 3, are used to represent the same arrowed lines in fig. 2 and 3, respectively.
Specifically, as shown in fig. 2, the currents in the same column are summed according to kirchhoff's law, and the result is taken as the input to the hidden layer neurons. The hidden layer neurons generate spike oscillations with different frequencies according to the input current, and the spike oscillations are counted by an asynchronous counter of the generation matrix. And transmitting the hidden layer neuron output result to an ELM memristor small network, completing small network calculation in the ELM memristor small network, and passing through a column scanner so as to obtain output weight. And finally obtaining and outputting the calculation result HELM.
Referring to FIG. 3, FIG. 3 is a schematic diagram of an ELM memristor small network of a 3D printing intelligent auxiliary system provided in an embodiment of the present application, it should be understood that the block diagram may further include additional blocks not shown and/or blocks shown may be omitted, and the scope of the present application is not limited in this respect.
Specifically, as shown in fig. 3, the schematic structure diagram of the ELM memristor small network in the mechanical arm 3D printing intelligent auxiliary system of the present application is shown, the Data a of the previous hidden layer is connected to the Data input end of the multiplexer through data_in2, the hierarchical node random weight C is calculated, and the Data a is connected to the address input end of the multiplexer through the input address B <6:0 >.
The input data is then used to generate analog direct current through IGC and the inner ELM memristor nodes formed by the 1T1R memristor array are used to copy the analog direct current to the hidden layers of the neurons of each row (understood as the hidden layers of the inner neurons)) Is a kind of medium. The output mode is the same as the outer layer.
Referring to fig. 2 or 3, in some embodiments, the outer layer ELM memristor node or the inner layer ELM memristor node further includes a spiking neuron circuit that functions to convert an input current into an output of the neuron.
Peak neuron circuits are used in FIGS. 2 and 3Indicating that the neu_en signal output by the clock and control modules in the PL (FPGA) section on the multiprocessor system-on-chip (mpssoc) is enabled.
Wherein the method comprises the steps ofRepresenting L spike neuron counters. The spiking neuron counter may be reset by an RN _ cnt signal output by a clock module and a control module in a PL (FPGA) portion on a multiprocessor system-on-chip (mpssoc).
The HELM framework can automatically learn and combine different single over-limit learning machine ELM memristor small networks (namely the ELM memristor small networks in fig. 2), the fusion parameters of a plurality of ELM models (over-limit learning machine models) are learned by adopting an ELM (over-limit learning machine) algorithm, and then the final result is calculated by combining the output of each single ELM model.
In some embodiments, the training process of the hierarchical overrunning learner memristor hardware network model is divided into two steps:
inputting a given training data set Target matrixTraining data set in embodiments of the applicationThe method comprises the steps of preprocessing real-time picture data acquired from a 3D printing mechanical arm, and determining the number of nodes of an inner ELM memristorNumber of outer ELM memristor nodesThe hidden layer nodes of the inner layer and the outer layer ELM memristor are the same in number。
Step one: training a single ELM memristor model, namely training of inner layer ELM memristor nodes of the hierarchical overrun learning machine memristor hardware network model, and considering the number of the inner layer ELM memristor nodes in the embodiment of the applicationEqual to the number of outer ELM memristor nodesThereby trainingAnd the hierarchical overrunning learning machine memristor hardware network model with independent nodes.
The inner layer ELM memristor node calculation steps in fig. 3 mainly include:
1. Generating random input weights for inner layer ELM memristor nodes And initial biasThe data input end of the multi-path selector is connected through the letter C line by the address A <6:0 >;
2. calculating a hidden layer output matrix H m of the inner layer ELM memristor node: ；
3. Calculating output weight of inner ELM memristor node ：；
4. Calculating the output O m of the inner ELM memristor node:
，
Wherein the method comprises the steps of The peak neuron circuit is sigmod activation function, can be any nonlinear piecewise continuous function, and meets the ELM general approximation capability theorem, and can be understood as an actual hardware activation function. Wherein the method comprises the steps ofRepresents the Moore-Penrose generalized inverse of the matrix.
Step two: based on the learning of the first step, calculating an output value of an inner ELM memristor node, and then learning fusion parameters of a plurality of ELM models; in the hierarchical overrun learning machine memristor hardware network model, cascading all inner-layer ELM memristor node outputs is used as a hidden matrix of the whole hierarchical overrun learning machine memristor hardware network model：
，
Wherein the method comprises the steps ofIs the output of the m-th inner ELM memristor node; wherein if all of the inner ELM memristor nodes have the same size, thenIs oneA rank matrix; the calculated fusion parameter is the output weight of the outer ELM memristor node,Is oneRepresenting the combined weights that M different inner layer ELM memristor nodes contribute to the final result. The outer ELM memristor node is parameterized by its parameters，，，Outer layer output weightFully defined;
the output weight of each independent hierarchical overrunning learner memristor hardware network model is expressed as:
，
output weight of each inner layer ELM memristor node Is an NxN square matrix, which represents the connection between the m-th inner ELM memristor node and the final output, and all output weightsExpressed as: ; the output result of the memristor hardware network model of the hierarchical overrun learning machine is expressed as follows:
，
It is understood that the output of the outer layer ELM memristor node is a linear combination of the outputs of the different inner layer ELM memristor nodes, where Representing the output of the memristor hardware network model of the hierarchical overrunning learning machine,The hidden matrix is represented by a representation of the hidden matrix,Representing M independent inner layer ELM memristor nodes in training step one,Representing the output weights of the hierarchical overrunning learner memristor hardware network model of all ELM models,Representing the output weights of the M independent inner layer ELM memristor nodes in training step one,Representing the output weight of each individual inner layer ELM memristor node.
It will be appreciated by those skilled in the art that HELM is a hierarchical neural network that includes a small network in each hidden node.
In some embodiments, for the parameter solving problem in HELM model training process, in addition to minimizing the network predicted value error, the output weight parameter is also minimizedThereby yielding optimization problems with regularization terms.
The application provides a method for convex optimization aiming at HELM models, which comprises the following steps:
、
wherein Representing a minimized objective functionTime output weightIs used for the value of (a) and (b),As a function of the object to be processed,In order to constrain the function of the signal,The representation takes the L2 norm,In order to train the sample,In order to train the number of samples,Is a constant value, and is used for the treatment of the skin,Is the error between the target true and predicted values.
Further, an objective function for convex optimization problem augmentation, i.e., a lagrangian function, is defined:
，
Wherein the method comprises the steps of Representing the lagrangian function, as an objective function,In order to constrain the function of the signal,As the weight of the material to be weighed,As a constant of the gradient,In order to train the sample,In order to train the number of samples,Is a constant value, and is used for the treatment of the skin,The representation takes the L2 norm,Is the firstThe gradient constant of the individual training samples is set,For the target truth value,Is the error between the target true and predicted values.
Further, from the above Lagrangian function, the optimal solution needs to meet the following form according to the KKT (Coulomb-Tak) condition:
Weighting the weight Is equal to zero, resulting in the following equation:
， （1）
to make the error between the target true value and the predicted value Is equal to zero, resulting in the following equation:， （2）
Let the gradient constant Is equal to zero, resulting in the following equation:
， （3）
Wherein the method comprises the steps of The lagrangian function is represented as such,The output weight is represented as a function of the output weight,Is the firstThe gradient constant of the individual training samples is set,As a constant of the gradient,As the error between the target true and predicted values,Is a constant value, and is used for the treatment of the skin,In order to conceal the transpose of the layer output matrix,In order to train the number of samples,The hidden layer row vectors are represented as such,Is the target true value.
Further, if a small training data set exists, the method) "Small training dataset" means that the number of training samples is (far) less than the number of ELM hidden layer nodes. Bringing formula (1) and formula (2) into formula (3) to obtain:
，
the combined type (1) and the formula (2) can be obtained:
；
further, if a big training data set exists, the method ) "Large training dataset" refers to a number of training samples that is far greater than the number of ELM hidden layer nodes. In this case, the following formulas (1) and (2) are used to indicate:
，
；
further, it is further obtainable from the formula (3):
， （4）
； （5）
Further, the simultaneous formula (4) and the formula (5) can be obtained:
；
further, obtaining a closed solution of the final output weight of the convex optimization;
，
Wherein the method comprises the steps of The output weight is represented as a function of the output weight,Representation ofThe order-unit matrix is used for the data processing,Representation ofThe order-unit matrix is used for the data processing,The inverse matrix is represented by a representation,Represents the Moore-Penrose generalized inverse of the matrix,In order to hide the layer output matrix,In order to conceal the transpose of the layer output matrix,Is a constant value, and is used for the treatment of the skin,For the target true value output,In order to train the number of samples,The number of nodes of the hidden layer of the memristor for the inner layer and the outer layer is increased.
Closed-form solution of output weights by convex optimizerRandomly inputting weightsOptimal bias of memristor hardware network model of hierarchical overrun learning machine is reversely calculatedWhereinThe inverse of the activation function is represented sigmod,Closed solution for expressing convex optimization output weightMoore-Penrose generalized inverse,A set of training data is represented and,Representing the target matrix. To the obtained optimal biasStoring may be used to update the initial biasAccelerating model training convergence and matching with random input weightAnd finishing the new training.
Those skilled in the art will appreciate that by 1T1R is meant a structure in which one transistor is connected in series with one memristor or resistance change cell. And the transistor is used for realizing the gating of the memristor unit, so that the crosstalk phenomenon caused by the leakage current problem is avoided.
Referring to fig. 4, fig. 4 is a schematic diagram of a spiking neuron circuit of a 3D printing intelligent assistance system provided in an embodiment of the application, it being understood that the schematic diagram may also include additional blocks not shown and/or blocks shown may be omitted, the scope of the application being not limited in this respect.
In FIG. 4The tube represents the subthreshold transistor of the spiking neuron circuit,Representing the feedback capacitor(s),An input voltage signal representing a spiking neuron circuit,Representing the storage voltage of the input parasitic storage capacitance,Representing the input parasitic storage capacitance,Representing the reference voltage of the operational amplifier,An output voltage signal representing the spiking neuron circuit.
Specifically, the spiking neuron circuit functions to convert an input current into an output of the neuron. After the input circuit is built, to simulate the neuron behavior, the input current is equivalent to the input of each neuron, and the output of each neuron can be regarded as the following spike rate formula:
，
Wherein, Is the sampling period of the output signal,Representing the maximum number of spikes in a cycle,Is a hervelacts step function,Indicating the leakage current is indicated by the fact that,Representing the input current. If the input current is less than the leakage current, the leakage current will not allow the neuron to spike.
In some embodiments, the spiking neuron output may be used for counter clocking, thus at a certain sampling timeIn, if each neuronProduction ofThe secondary spike can then treat the counter output asIs a quantization case of (2). Then, in the second stage, the calculation is continued to obtain。
The field of additive manufacturing is expanding rapidly and new materials, techniques and solutions are emerging. Artificial intelligence assisted 3D printing is playing its unique role from determining the best material for a job to improving the build quality of a product by eliminating human error.
Since memristors are used as electronic synaptic devices, the migration of ions in memristors is very similar to the diffusion process of neurotransmitters in nerve synapses, so that the use of memristors to simulate synapses in a nerve network is a great trend, and the memristors are widely used in the nerve network to store synaptic weights. Numerous experiments have demonstrated that simulating synapses in a neural network with memristors would have great potential advantages.
The memristor is used as a basic passive device, has nanoscale size and nonvolatile property, can realize continuous change of synaptic weight when simulating nerve synapses, realizes integration of memory and calculation, and can construct a neural network structure with higher integration level, so that the artificial neural network has learning and memory capabilities, and meanwhile, the functions of the artificial neural network are diversified.
Therefore, the memristor network optimization-based mechanical arm 3D printing intelligent auxiliary system provided by the application adopts the memristor RRAM circuit as a hardware neural network computing unit, and the MPSOC multiprocessor system-on-chip is used as a control system of the 3D printing mechanical arm, so that more intelligent system assistance is provided for environments requiring high stability, such as biological 3D printing requiring in-situ printing, cultural relic repairing 3D printing and the like, aiming at real-time intelligent decisions requiring complex environments. Meanwhile, the memristor hardware network is adopted as a 3D printing intelligent auxiliary system, and the method has the advantages of low calculation power consumption and small delay.
The embodiment of the application also provides a 3D printing intelligent auxiliary method, which comprises the following steps:
Acquiring real-time picture data of a 3D printing mechanical arm, and carrying out feature extraction and binarization;
initializing and training a hierarchical overrun learning machine memristor hardware network model based on hierarchical overrun learning machine memristor hardware network optimization based on the extracted feature data to acquire training tag data;
And carrying out randomized weight distribution based on the training tag data, and sending the obtained weight distribution data to the memristor hardware network of the hierarchical overrun learning machine so as to obtain a parameter adjustment decision of the mechanical arm based on an obtained output result of the memristor hardware network model of the hierarchical overrun learning machine, thereby assisting in the control of the mechanical arm in 3D printing.
In particular, referring to fig. 5, fig. 5 is a flowchart of a 3D printing intelligent assistance method provided in an embodiment of the present application, it should be understood that the flowchart may also include additional blocks not shown and/or blocks shown may be omitted, the scope of the present application being not limited in this respect.
As shown in fig. 5, the method includes the steps of firstly, executing left side flow, firstly, acquiring real-time video of a 3D printing process through a camera beside a mechanical arm, secondly, acquiring real-time image data, extracting features, binarizing, thirdly, training a HELM model based on memristor hardware network optimization, fourthly, calibrating a printing position, adjusting mechanical arm speed, acceleration and path point time parameterization through a decision circuit based on an FPGA, adjusting a spray head flow rate, and fifthly, adjusting the spray head flow rate through a 3D printing nozzle controller.
Then executing right side flow, firstly, inputting a printing file G-code path, secondly, converting the 3D printing path into a mechanical arm movement track, such as MOVJ joint movement, MOVL linear movement and MOVC arc movement, thirdly, planning the mechanical arm movement track based on a Ruckig time optimal track generation algorithm in an ROS open source movement planning library OMPL, acquiring speed, acceleration and path in left side flow, performing parameter adjustment, fourthly, converting the planned joint angle into a control signal of a mechanical arm motor through a ActionServer action server, and fifthly, controlling an entity mechanical arm.
The specific implementation method refers to the foregoing system embodiment, and is not repeated here.
The present application may be a method, apparatus, system, and/or computer program product. The computer program product may include a computer readable storage medium having computer readable program instructions embodied thereon for performing various aspects of the present application.
The computer readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium would include the following: portable computer disks, hard disks, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static Random Access Memory (SRAM), portable compact disk read-only memory (CD-ROM), digital Versatile Disks (DVD), memory sticks, floppy disks, mechanical coding devices, punch cards or in-groove structures such as punch cards or grooves having instructions stored thereon, and any suitable combination of the foregoing. Computer-readable storage media, as used herein, are not to be construed as transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., optical pulses through fiber optic cables), or electrical signals transmitted through wires.
The computer readable program instructions described herein may be downloaded from a computer readable storage medium to a respective computing/processing device or to an external computer or external storage device over a network, such as the internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmissions, wireless transmissions, routers, firewalls, switches, gateway computers and/or edge servers. The network interface card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium in the respective computing/processing device.
Computer program instructions for carrying out operations of the present application may be assembly instructions, instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages, including an object oriented programming language such as SMALLTALK, C ++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions may be executed entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, aspects of the present application are implemented by personalizing electronic circuitry, such as programmable logic circuitry, field Programmable Gate Arrays (FPGAs), or Programmable Logic Arrays (PLAs), with state information for computer readable program instructions, which can execute the computer readable program instructions.
Various aspects of the present application are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.
These computer readable program instructions may be provided to a processing unit of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processing unit of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable medium having the instructions stored therein includes an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.
The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
Note that all features disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic set of equivalent or similar features. Where used, further, preferably, still further and preferably, the brief description of the other embodiment is provided on the basis of the foregoing embodiment, and further, preferably, further or more preferably, the combination of the contents of the rear band with the foregoing embodiment is provided as a complete construct of the other embodiment. A further embodiment is composed of several further, preferably, still further or preferably arrangements of the strips after the same embodiment, which may be combined arbitrarily.
While the application has been described in detail in the foregoing general description and specific examples, it will be apparent to those skilled in the art that modifications and improvements can be made thereto. Accordingly, such modifications or improvements may be made without departing from the spirit of the application and are intended to be within the scope of the application as claimed.

Claims (9)

1. A 3D printing intelligent assistance system, comprising: the multiprocessor system-on-chip and the hierarchical overrun learning machine memristor hardware network are connected, wherein,
The multi-processor on-chip system is used for acquiring real-time picture data of the 3D printing mechanical arm, initializing and training a hierarchical overrun learning machine memristor hardware network model based on hierarchical overrun learning machine memristor hardware network optimization based on the real-time picture data to acquire training tag data, carrying out randomized weight distribution based on the training tag data, and sending the obtained weight distribution data to the hierarchical overrun learning machine memristor hardware network to obtain parameter adjustment decisions of the mechanical arm based on an output result of the hierarchical overrun learning machine memristor hardware network model, thereby assisting control of the mechanical arm in 3D printing;
the hierarchical overrun learning machine memristor hardware network model comprises: a multiplexer, a generating circuit, a memristor array and an inner layer overrun learning machine memristor node, wherein,
The multiplexer is used for carrying out randomized weight distribution based on the input weight distribution data;
The generation circuit is used for generating analog direct current according to the input weight distribution data and inputting the analog direct current into the memristor array so that the memristor array copies the weight distribution data into memristor nodes of the inner-layer overrun learning machine of each column and multiplies the weight distribution data with random weights generated in the current mirror image array;
The memristor array is used for summing currents in the same column according to kirchhoff's law, and taking a current summation result as input of hidden layer neurons;
The memristor nodes of the inner-layer overrun learning machine are used for obtaining the output result of the hidden layer neurons, completing small grid calculation, obtaining output weights through a column scanner, and finally obtaining the output result of the memristor hardware network model of the hierarchical overrun learning machine.
2. The 3D printing intelligent assistance system of claim 1, wherein after deriving the parameter adjustment decisions for the robotic arm, the multiprocessor system-on-a-chip is further configured to:
And acquiring a 3D printing path code, planning the motion trail of the mechanical arm based on the 3D printing path code, fusing the parameter adjustment decision of the mechanical arm, and performing parameterization adjustment on the mechanical arm so as to realize control on the mechanical arm.
3. The 3D printing intelligent assistance system of claim 1, wherein the hierarchical overrunning learner memristor hardware network further comprises:
And the peak neuron circuit is used for converting the current output by the memristor array into an output result of the hidden layer neuron.
4. The 3D printing intelligent assistance system of claim 1, wherein the output result of the hierarchical overrun learner memristor hardware network model is expressed as:
wherein O represents the output of a memristor hardware network model of the hierarchical overrun learning machine,
H G denotes a hidden matrix and,
O 1～OM represents M independent inner layer overrun learner memristor nodes,
Gamma represents the output weight of the hierarchical overrun learner memristor hardware network model of the overall overrun learner model,
Gamma 1～γM denotes the output weights of M independent inner layer overrun learner memristor nodes,
Gamma m denotes the output weight of each individual inner layer overrun learner memristor node,
O m represents the output of the memristor node of the inner-layer overrun learning machine, H m represents the hidden-layer output matrix of the memristor node of the inner-layer overrun learning machine,
(. Cndot.) + represents the Moore-Penrose generalized inverse of the matrix,
Sigma (·) is sigmod activation functions,
T represents the matrix of the object and,
X denotes a given training data set, which is composed of real-time picture data preprocessing,
W m and b m represent the random input weight and initial bias, respectively, of the inner layer overrun learner memristor node.
5. The 3D printing intelligent assistance system of claim 4, wherein initializing and training a hierarchical overrun learner memristor hardware network model based on hierarchical overrun learner memristor hardware network optimization based on real-time picture data comprises:
Minimizing the output weight parameters of the memristor hardware network model of the hierarchical overrun learning machine in the process of training the memristor hardware network model; the method specifically comprises the following steps:
Based on the formula: And s.t.g (β) =h (x i)β-ti-ξi =0, i=1, …, N), convex optimization of the hierarchical overrun learner memristor hardware network model,
Wherein the method comprises the steps ofThe method comprises the steps of representing the value of an output weight beta when a target function f (beta) is minimized, wherein f (beta) is the target function, g (beta) represents a constraint function, I, I 2 represents taking an L2 norm, i represents training samples, N represents the number of the training samples, C represents a constant, and xi i represents an error between a target true value and a predicted value;
Defining an objective function for convex optimization problem augmentation:
Where L (β, α) represents a lagrangian function, f (β) represents an objective function, g (β) represents a constraint function, β represents an output weight, α represents a gradient constant, C represents a constant, |·| 2 represents taking the L2 norm, α i represents a gradient constant of the ith training sample, t i represents a target true value, ζ i represents an error between the target true value and the predicted value;
Based on the objective function, obtaining a closed solution of the final output weight parameter of convex optimization:
Wherein β represents the output weight, I N represents the N-order identity matrix, I L represents the L-order identity matrix, (·) -1 represents the inversion matrix, H represents the hidden layer output matrix, H T represents the transpose of the hidden layer output matrix, C represents the constant, t represents the target true value output, N represents the number of training samples, and L represents the number of hidden layer nodes of the memristor of the overrun learning machine.
6. The intelligent 3D printing support system according to claim 2, wherein,
Acquiring real-time picture data of a 3D printing mechanical arm, comprising:
Acquiring real-time picture data of an original image of a mechanical arm, which is acquired by a mechanical arm image acquisition device connected with a multiprocessor system-on-chip;
Acquiring a 3D printing path code, and planning a motion trail of the mechanical arm based on the 3D printing path code, wherein the method comprises the following steps:
acquiring a sliced 3D printing path code input through a storage medium, converting the motion trail of the mechanical arm based on the 3D printing path code, converting the 3D printing path into the motion trail of the mechanical arm, solving the motion trail of the mechanical arm in an inversion way, and planning the motion trail of the mechanical arm by using a planning tool.
7. The intelligent 3D printing support system according to claim 1, wherein,
The weight allocation data comprises address and weight parameter data;
The parameter adjustment decisions of the mechanical arm comprise three parameter adjustment decisions of the speed, the acceleration and the path of the mechanical arm.
8. A 3D printing intelligent assistance method, characterized by comprising:
using the 3D printing intelligent assistance system of claim 1:
Acquiring real-time picture data of a 3D printing mechanical arm, and carrying out feature extraction and binarization;
initializing and training a hierarchical overrun learning machine memristor hardware network model based on hierarchical overrun learning machine memristor hardware network optimization based on the extracted feature data to acquire training tag data;
And carrying out randomized weight distribution based on the training tag data, and sending the obtained weight distribution data to a hierarchical overrun learning machine memristor hardware network so as to obtain a parameter adjustment decision of the mechanical arm based on an output result of the acquired hierarchical overrun learning machine memristor hardware network model, thereby assisting in the control of the mechanical arm in 3D printing.
9. A computer storage medium having stored thereon a computer program, which when executed by a machine performs the steps of the method according to claim 8.
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