CN117529801A

CN117529801A - Chip packaging structure, packaging method thereof and communication device

Info

Publication number: CN117529801A
Application number: CN202180099627.5A
Authority: CN
Inventors: 郭晨鸣
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-09-28
Filing date: 2021-09-28
Publication date: 2024-02-06
Also published as: WO2023050093A1

Abstract

The embodiment of the application provides a chip packaging structure, a packaging method thereof and a communication device, relates to the technical field of semiconductors, and is used for solving the problem of failure of the chip packaging structure. A chip package structure, comprising: packaging a substrate; the chip structure comprises a plurality of bumps positioned on the surface; the chip structure is arranged on the packaging substrate, and the salient points are electrically connected with the packaging substrate; a plastic layer at least wrapping the side surface of the chip structure; the outer side of the bottom of the plastic layer, which is close to the packaging substrate, is provided with a chamfer; and the underfill is used for wrapping the salient points and at least part of chamfer faces of the chamfer.

Description

Chip packaging structure, packaging method thereof and communication device

Technical Field

The present disclosure relates to the field of semiconductor technologies, and in particular, to a chip packaging structure, a packaging method thereof, and a communication device.

Background

With the development of electronic technology, the communication device has continuous and rich and comprehensive functions, so that the evolution iteration requirement of the higher-order chip is increased, the integration level of the chip is continuously increased, and the multi-chip integrated package is a trend. As the number of stacked chips increases, the size of the chip package structure increases. However, oversized chip packages present significant stress and process challenges.

After bonding between the high-density bumps of the chip structure and the package substrate in the chip package structure, due to a large thermal expansion coefficient (coefficient of thermal expansion, CTE) difference between the chip structure and the package substrate, warpage (stress) and stress are easily generated between the package substrate and the chip structure when the temperature is changed during use. In order to protect the bumps and improve the stability of the chip structure and the package substrate, underfill (underfill) is formed between the chip structure and the package substrate. However, on the one hand, the difference in thermal expansion coefficient between the chip structure and the package substrate is large during the package bonding process, and the chip structure corner (die corner) carries a large risk of stress to the underfill. On the other hand, in the subsequent use process, the temperature is continuously changed during the use of the chip packaging structure, so that the chip packaging structure is repeatedly warped, the situation of repeated extrusion between the corners of the chip structure and the underfill is caused, the repeated extrusion between the corners of the chip structure with high modulus and the underfill with low modulus is caused by internal stress, expansion, shrinkage and other reasons, the underfill is broken, and the chip packaging structure is invalid.

The above problem is further emphasized by the increasing size of the chip structure sealed with the package substrate, which results in a gradual increase in the ratio of the size of the chip structure to the size of the package substrate (die-substrate size ratio).

Disclosure of Invention

The embodiment of the application provides a chip packaging structure, a packaging method thereof and a communication device, which are used for solving the problem of failure of the chip packaging structure.

In order to achieve the above purpose, the present application adopts the following technical scheme:

in a first aspect of the embodiments of the present application, a chip package structure is provided, where the chip package structure includes a package substrate, a chip structure disposed on the package substrate, a molding layer (molding) at least wrapping a side surface of the chip structure, and an underfill. The chip structure comprises a plurality of protruding points positioned on the surface, and the protruding points are electrically connected with the packaging substrate; the plastic layer wraps the side surface of the chip structure or also wraps the top surface of the chip structure, but does not wrap the salient points; the outer side of the bottom of the plastic layer, which is close to the packaging substrate, is provided with a chamfer; the underfill encapsulates the bumps and at least a portion of the chamfer faces of the chamfer.

The embodiment of the application provides a chip structure in a chip packaging structure, which is not required to be provided with a chamfer, a wider cutting channel area on a wafer is not required to be reserved, and the actual size of the chip structure is similar to the size of a functional area of the chip structure, so that the problems of chip structure damage, wafer waste and the like caused by the chamfer on the chip structure can be avoided, and the cost of the chip structure is reduced. Moreover, the chamfer on the plastic sealing layer can not generate the influence of cracks and the like on the chip structure, a sintering groove is not required to be arranged on the plastic sealing layer, a safe distance is not required to be reserved, and a cutting channel area can be reduced. Therefore, the size of the plastic layer is not required to be excessively large, and the size of the chip packaging structure is not excessively increased. That is, after the chamfer on the chip structure is transferred to the plastic sealing layer, the concentrated stress between the sharp corner of the chip structure and the underfill can be relieved, and the problem that the underfill is cracked due to the concentrated stress can be avoided. The cost of the chip package structure can also be reduced, and a series of problems caused by cutting the chip structure can be solved. The limit of the chip structure under the chip package with large size and high area occupation ratio is overcome, the problem of stress concentration of the corners of the chip structure under the chip package with large size is solved, and the failure of the chip package structure under high temperature is avoided.

In some embodiments, a side of the chamfered chamfer surface near the bottom of the molding layer has a spacing from the chip structure. The corner of chip structure is wrapped up by the plastic envelope, and plastic envelope and underfill direct contact can avoid the corner of chip structure and underfill direct contact to cause split or warpage. Meanwhile, when cutting is carried out along the cutting path, the problem that the chip structure is broken due to the fact that the chip structure is cut due to cutting offset can be avoided.

In some embodiments, the underfill overflows from the bottom of the molding layer, over the chamfer and wraps around the sides of the molding layer. The higher the side height of the underfill coating plastic envelope, the greater the stress that the underfill can withstand and the more resistant the risk of stress.

In some embodiments, the material of the plastic layer comprises an epoxy. The plastic sealing layer is used as a stress transition layer between the chip structure and the underfill, the hardness of the epoxy resin is smaller than that of the chip structure, and the chamfer is formed on the epoxy resin more easily than that on the chip structure, and the loss to a cutter is low.

In some embodiments, the chip structure is: and the chip is provided with bumps. The chip structure is not limited, and the application range is wide.

In some embodiments, a chip structure includes: an interconnection switching layer; a plurality of via holes penetrating through the interconnection switching layer; the chip is arranged on the interconnection switching layer and is electrically connected with one end of the through hole; and the other end of the through hole is provided with a bump. The chip structure is not limited, and the application range is wide.

In a second aspect of the embodiments of the present application, a packaging method of a chip packaging structure is provided, where the chip packaging method includes: forming a plastic packaging film on a carrier plate provided with a plurality of chip modules; the surface of the chip module with a plurality of contacts faces the carrier plate, and the plastic packaging film at least wraps the side surface of the chip module; removing the carrier plate to expose the contacts; forming a bump on the contact, the bump being electrically connected with the contact; forming a plurality of chamfer grooves on the bottom surface of the plastic packaging film, which is close to the convex points, wherein the chamfer grooves are positioned at the gaps of the chip module; cutting along the cutting path; the cutting channel is positioned at the gap of the chip module, and the position of the chamfer groove coincides with the position of the cutting channel; electrically connecting the assembly structure obtained by cutting with the packaging substrate through the convex points; and forming underfill between the assembly structure and the packaging substrate, wherein the underfill is wrapped on the periphery of the plastic packaging film.

According to the packaging method of the chip packaging structure, the periphery of the chip structure without forming the chamfer is wrapped with the plastic packaging film, and then the plastic packaging film is cut to form the structure of wrapping the periphery of the chip structure with the plastic packaging film. Because the chip structure does not need to be chamfered, a wider cutting channel area does not need to be reserved on the wafer, and the actual size of the finally formed chip structure is similar to the size of the functional area of the chip structure. Therefore, the problems of chip structure damage, wafer waste and the like caused by forming the chamfer on the chip structure can be avoided, and the preparation cost of the chip structure is reduced. Moreover, the chamfer groove is cut on the plastic sealing layer so as to form a chamfer, and the chip structure is not affected by cracks and the like. The sintering groove is not required to be formed on the plastic sealing layer, the safety distance is not required to be reserved, and the cutting channel area can be reduced. Therefore, the assembled structure of the plastic sealing layer wrapped on the periphery of the finally formed chip structure has little difference with the size of the chip structure, and the size of the chip packaging structure is not excessively increased. That is, after the chamfer on the chip structure is transferred to the plastic sealing layer, the concentrated stress between the sharp corner of the chip structure and the underfill can be relieved, and the problem that the underfill is cracked due to the concentrated stress can be avoided. The cost of the chip packaging structure can be reduced, and a series of problems caused by cutting the chip structure can be solved. The limit of the chip structure under the chip package with large size and high area occupation ratio is overcome, the problem of stress concentration of the corners of the chip structure under the chip package with large size is solved, and the failure of the chip package structure under high temperature is avoided.

A third aspect of embodiments of the present application provides a communication device, including a printed wiring board and the chip package structure of any one of the first aspects; the chip packaging structure is arranged on the printed circuit board and is coupled with the printed circuit board.

The communication device provided in the third aspect of the embodiments of the present application includes the chip packaging structure of any one of the first aspect, and the beneficial effects of the chip packaging structure are the same as those of the chip packaging structure, and are not repeated here.

Drawings

Fig. 1 is a schematic structural diagram of a base station according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a chip package structure according to an embodiment of the present application carried on a PCB;

fig. 3A is a schematic structural diagram of a chip package structure according to an embodiment of the present application;

fig. 3B is a schematic structural diagram of a chip structure according to an embodiment of the present application;

fig. 3C is a schematic structural diagram of another chip structure according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of another chip package structure according to an embodiment of the present disclosure;

fig. 5 is a flow chart of a packaging method of a chip packaging structure according to an embodiment of the present application;

fig. 6A-6P are schematic diagrams illustrating a packaging process of a chip packaging structure according to an embodiment of the present application;

Fig. 7A is a schematic structural diagram of another chip package structure according to an embodiment of the present disclosure;

fig. 7B is a schematic structural diagram of another chip structure according to an embodiment of the present disclosure;

fig. 7C is a schematic structural diagram of another chip structure according to an embodiment of the present disclosure;

fig. 7D is a schematic structural diagram of another chip structure according to an embodiment of the present disclosure;

fig. 8A is a schematic structural diagram of another chip structure according to an embodiment of the present disclosure;

fig. 8B is a schematic structural diagram of another chip structure according to an embodiment of the present disclosure;

fig. 9A is a schematic structural diagram of still another chip package structure according to an embodiment of the present disclosure;

fig. 9B is a schematic structural diagram of another chip package structure according to an embodiment of the present disclosure;

fig. 9C is a schematic structural diagram of another chip package structure according to an embodiment of the present disclosure;

fig. 9D is a schematic structural diagram of another chip package structure according to an embodiment of the present disclosure;

fig. 9E is a schematic structural diagram of another chip package structure according to an embodiment of the present disclosure;

fig. 10A is a schematic structural diagram of another chip package structure according to an embodiment of the present disclosure;

fig. 10B is a schematic structural diagram of another chip package structure according to an embodiment of the present application.

Reference numerals:

1-a communication device; a 2-antenna; 3-radio frequency units; 4-memory; a 5-processor; 100-chip packaging structure; 10-wafer; 20-sealing rings; 30-a sintering groove; 40-chamfer grooves; 11-packaging a substrate; 12-chip structure; 12' -chip module; 12 "-assembled structure; 121-bump; 122-contacts; 123-an interconnection switching layer; 124-via holes; 125-chip; 13-plastic sealing layer; 13' -plastic packaging film; 131-chamfering; a-chamfer surface; 14-underfill; 21-a carrier plate; 22-connection layer.

Detailed Description

The following description of the technical solutions in the embodiments of the present application will be made with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments.

Hereinafter, in the embodiments of the present application, the terms "first", "second", and the like are used for descriptive convenience only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", etc. may explicitly or implicitly include one or more such feature. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.

In the embodiments of the present application, "upper", "lower", "left" and "right" are not limited to the orientation in which the components are schematically disposed in the drawings, and it should be understood that these directional terms may be relative concepts, which are used in relation to the description and clarity, which may be varied accordingly to the orientation in which the components are disposed in the drawings.

In the present embodiments, the term "comprising" is to be interpreted as an open, inclusive meaning, i.e. "comprising, but not limited to", throughout the specification and claims, unless the context requires otherwise. In the description of the present specification, the terms "one embodiment," "some embodiments," "example embodiments," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

In describing some embodiments, expressions of "coupled" and "connected" and their derivatives may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, the term "coupled" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact. However, the term "coupled" may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited to the disclosure herein.

In the embodiment of the present application, "and/or" is merely an association relationship describing an association object, and indicates that three relationships may exist, for example, a and/or B may indicate: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.

Exemplary implementations are described in the examples herein with reference to cross-sectional and/or plan views and/or equivalent circuit diagrams as idealized exemplary figures. In the drawings, the thickness of layers and regions are exaggerated for clarity. Thus, variations from the shape of the drawings due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.

The embodiment of the application provides a communication device, which can be a terminal device, a processor and a server in a data center, or a network device.

The terminal device is used for providing one or more of voice service and data connectivity service for users, and the terminal is an entity on the user side for receiving signals or transmitting signals or receiving signals and transmitting signals. A terminal device can also be called a User Equipment (UE), an access terminal, a subscriber unit, a subscriber station, a mobile station, a remote terminal, a mobile device, a user terminal, a wireless communication device, a user agent, or a user equipment. The terminal device may be a Mobile Station (MS), a subscriber unit (subscriber unit), an unmanned aerial vehicle, an internet of things (internet of things, ioT) device, a Station (ST) in a wireless local area network (wireless local area networks, WLAN), a cellular phone (cellular phone), a smart phone (smart phone), a cordless phone, a wireless data card, a tablet, a session initiation protocol (session initiation protocol) phone, a wireless local loop (wireless local loop, WLL) station, a personal digital assistant (personal digital assistant, PDA) device, a laptop (machine type communication, MTC) terminal, a handheld device with wireless communication capabilities, a computing device or other processing device connected to a wireless modem, a vehicle-mounted device, a wearable device (which may also be referred to as a wearable smart device). The terminal device may also be a terminal in a next generation communication system, e.g. a terminal device in a future evolved public land mobile network (public land mobile network, PLMN), a terminal device in a New Radio (NR) communication system, etc.

A network device is an entity on the network side that sends signals or receives signals or both. The network device may be a means deployed in a radio access network (radio access network, RAN) for providing wireless communication functionality for the terminal, e.g. a base station. The network device may be a macro base station, a micro base station (also called a small station), a relay station, an Access Point (AP), etc. in various forms, and may also include various forms of control nodes, such as a network controller. The control node can be connected with a plurality of base stations and can configure resources for a plurality of terminals covered by the plurality of base stations. In systems employing different radio access technologies, the names of base station capable devices may vary. For example, a global system for mobile communications (global system for mobile communication, GSM) or code division multiple access (code division multiple access, CDMA) network may be referred to as a base transceiver station (base transceiver station, BTS), a wideband code division multiple access (wideband code division multiple access, WCDMA) network may be referred to as a base station (NodeB), an evolved NodeB (eNB or eNodeB) in an LTE system, and a next generation base station node (next generation node base station, gNB) in an NR communication system, the specific names of the base stations are not limited in this application. The network device may also be a radio controller in the context of a cloud radio access network (cloud radio access network, CRAN), a network device in a future evolved public land mobile network, a transmission receiving node (transmission and reception point, TRP), etc.

Example a network device architecture as shown in fig. 1, the network device 1 may comprise one or more radio frequency units, such as a remote radio frequency unit (remote radio unit, RRU) and one or more baseband units (BBU) (also referred to as Digital Units (DUs)).

The RRU may be referred to as a transceiver unit, transceiver circuitry, or transceiver, etc., which may include at least one antenna 2 and a radio frequency unit 3. The RRU portion is mainly used for receiving and transmitting a radio frequency signal and converting the radio frequency signal to a baseband signal, for example, for transmitting the first indication information in the above method embodiment. The RRU and BBU may be physically located together or may be physically separate, e.g., a distributed base station.

The BBU is a control center of a network device, and may also be referred to as a processing unit, and is mainly used for performing baseband processing functions, such as channel coding, multiplexing, modulation, spreading, and so on.

In some embodiments, the BBU may be formed by one or more single boards, where the multiple single boards may support a single access indicated radio access network (e.g., an LTE network), or may support radio access networks of different access schemes (e.g., an LTE network, a 5G network, or other networks) respectively. The BBU further comprises a memory 4 and a processor 5, the memory 4 being arranged to store necessary instructions and data. The processor 5 is arranged to control the network device to perform the necessary actions. The memory 4 and the processor 5 may serve one or more boards. That is, the memory and the processor may be separately provided on each board. It is also possible that multiple boards share the same memory and processor. In addition, each single board can be provided with necessary circuits. The necessary circuits such as the memory 4 and the processor 5 are packaged on a single board as a chip package structure. Wherein the single board may be, for example, a printed circuit board (printed circuit board, PCB).

As shown in fig. 2, the chip package structure 100 is carried on a PCB. In general, the chip structure 12 with the functional circuit is electrically connected to the package substrate 11, and then electrically connected to the PCB through the package substrate 11.

In the electrical connection between the chip structure 12 and the package substrate 11, for example, flip chip package (flip chip), the flip chip package is a package form in which the chip structure 12 and the package substrate 11 are soldered together by performing flip chip process to face the bump 121 toward the package substrate 11, aligning the bump 121 with a pad on the package substrate 11, and then performing solder processes such as reflow soldering. While the high-density bumps 121 and the package substrate 11 are tightly bonded by soldering, there is a mismatch in thermal expansion coefficient between the chip structure 12 and the package substrate 11. The combination structure with stronger mismatch of thermal expansion coefficients can generate warping change or internal stress in the temperature change process of the subsequent thermal process.

In order to protect the bump 121 structure and the insulating barrier (SR) structure on the surface of the package substrate 11 during the high temperature process (e.g., ball-mounting reflow, upper board reflow) in the subsequent packaging process, an underfill 14 is formed between the chip structure 12 and the package substrate 11 as shown in fig. 2. The encapsulated chip structure 12 is protected from failure during reliability testing and high temperature processing by the surrounding protection of the underfill 14.

However, the underfill 14 in the above-described chip package structure 100 can alleviate the problem caused by warpage of the chip structure 12 and the package substrate 11. However, since the computing power of high-performance devices such as servers, high-performance processors (CPUs), and network interconnection switches on core chips is continuously improved, the development speed of advanced nodes is relatively slow, which requires that the critical chip size be increased to achieve a higher computing power. As the ratio of the size of the chip structure to the size of the package substrate (die-substrate size ratio) increases, the corners of the chip structure 12 carry a greater risk of stress to the underfill 14. In the use process of the chip packaging structure, repeated warping caused by continuous temperature change occurs between sharp corners with high modulus at corners of the chip structure 12 and the softer underfill 14, repeated extrusion and pulling due to internal stress, expansion, shrinkage and other reasons occur, and the underfill 14 is finally broken and failed. The greater the area of the chip structure 12, the higher the risk of such failure.

Based on this, in order to solve the problem of stress and crack of the chip package structure 100, in some embodiments, as shown in fig. 3A, a chip package structure 100 is provided, which mainly includes a package carrier 11, a chip structure 12 and an underfill 14, wherein a surface of the chip structure 12 near the package substrate 11 has a sintering groove (far laser) 30, and a bottom side of the chip structure 12 has a chamfer 131.

In this chip package structure 100, with the chamfer 131 structure cut at the chip corner (die corner), the apex angle in contact with the underfill 14 is changed from sharp angle to chamfer, and after the apex angle of the chip structure 12 is smoothed, the concentrated stress between the chip structure corner and the underfill 14 can be relieved, and the problem that the underfill 14 has cracks due to the concentrated stress can be avoided.

However, the chip structure 12 with chamfer can alleviate the problems of stress and crack, but a new problem is caused in the process of manufacturing the chip structure 12.

As shown in fig. 3B, the process of preparing the chip structure 12 includes: forming a wafer (wafer) 10 including a plurality of chip structures 12, the plurality of chip structures 12 being separated by scribe line spaces; then, a sealing ring (20) and a sintering groove (30) are formed on the wafer (10), wherein the sintering groove (30) is positioned in a cutting channel area and is positioned at the periphery of the sealing ring (20); then forming auxiliary grooves between adjacent sintering grooves 30 (i.e., at intermediate positions of the scribe line regions); then forming a chamfer groove 40 at the auxiliary groove with a cutter; a dicing blade is then used to cut through the wafer 10 at the middle of the chamfer groove 40 to form the chip structure 12.

However, in the process of manufacturing the chip structure 12, in order to prevent cracks generated during the chamfer groove cutting (chamfer cut) from expanding to the seal ring 20 and the logic region within the seal ring 20, a sintering groove 30 needs to be formed between the seal ring 20 and the region where the chamfer groove 40 is to be formed. Among these, a safety distance of about 12 μm is required between the sintering groove 30 and the chamfering groove 40, and a safety distance of about 25 μm is required between the sintering groove 30 and the seal ring 20 in consideration of the process and the like. The width of the sintering groove 30 is about 30. Mu.m. According to the different chamfering angles on the chip structure 12, the chamfering groove also needs to be reserved with a certain width. For example, a 45 ° chamfer requires a width of about 100 μm to be reserved. This results in a dicing street having a width of not less than 234 μm, which wastes more wafers 10, resulting in an increase in the manufacturing cost of the chip structure 12 and thus an increase in the cost of the chip package structure 100.

Moreover, because of the relatively high hardness of the wafer 10 (e.g., si), the logic region of the wafer 10 typically includes an extremely low dielectric constant material (ELK). The porous structure of the very low dielectric constant material results in cracks forming on the surface of the chamfer groove 40 during the formation of the chamfer groove 40. During the formation of the sintering groove 30, a heat affected zone (hat affected zone, HAZ) is formed around the sintering groove 30, as shown in fig. 3C, which causes an irregular topography on the surface of the sintering groove 30 with an unknown risk of stress. In addition, since the metal of the metal layer in the wafer 10 adheres to the surface of the dicing blade during dicing, the dicing blade cannot directly contact with the wafer 10 during dicing, which affects the dicing effect and results in cracking of the wafer 10. In addition, the introduction of the sintering groove 30 does not completely avoid the risk of cracking when forming the chamfer groove 40 on the wafer 10.

On the one hand, the chamfer cut out on the wafer 10 is uneven and brings about the problem of local stress concentration, and on the other hand, in order to keep the chamfer angle stable, the chamfer cutter can generate larger abrasion in the process of cutting the chamfer, so that the service life of the cutter is shortened.

Based on this, in order to solve the problem of high manufacturing cost of the chip packaging structure, the embodiment of the present application further provides a chip packaging structure, as shown in fig. 4, the chip packaging structure 100 mainly includes a packaging substrate 11, a chip structure 12, a plastic sealing layer 13, and an underfill 14, and a chamfer 131 is provided on the bottom outer side of the plastic sealing layer 13.

As shown in fig. 5, an embodiment of the present application provides a packaging method of a chip packaging structure, including:

s1, as shown in fig. 6A, a plurality of chip modules 12' are placed on the carrier plate 21.

It is to be noted here that, as shown in fig. 4, the chip module 12' refers to a structure before the bump 121 is not formed on the chip structure 12. That is, after the bump 12 is formed on the chip module 12', the chip structure 12 shown in fig. 4 can be obtained.

Illustratively, a plurality of chip modules 12' are arranged on the carrier plate 21 at intervals. For example, a plurality of chip modules 12' are arrayed on the carrier plate 21.

As shown in fig. 6B, fig. 6B is a cross-sectional view taken along A1-A2 in fig. 6A, the bottom surface of the chip module 12 'has a plurality of contacts 122, and signals of an external structure are transmitted to the inside of the chip module 12' through the contacts 122. The chip module 12' has a bottom surface of the plurality of contacts 122 facing the carrier plate 21.

As shown in fig. 6A, the carrier 21 is used to carry a plurality of chip modules 12', and the material of the carrier 21 is not limited in the embodiment of the present application. Illustratively, the material forming carrier plate 21 may include silicon, silicon oxide, glass, ceramic, polymer, metal, or other materials having similar functions and compatible with subsequent packaging processes. In addition, the shape of the carrier 21 may be a wafer shape, a square shape, or any other shape, and the shape of the carrier 21 in fig. 6A is only one illustration.

In some embodiments, before the chip module 12' is placed on the carrier 21, the carrier 21 is cleaned to remove impurities on the surface of the carrier 21, so as to improve the adhesion and coplanarity of the carrier 21.

In some embodiments, the chip module 12 'is placed on the carrier plate 21 and is fixedly connected to the carrier plate 21, so that the chip module 12' does not move on the carrier plate 21 in the subsequent process.

As shown in fig. 6B, the chip module 12' and the carrier plate 21 are connected by a connection layer 22.

Based on this, as shown in fig. 6C, before the chip module 12' is placed on the carrier 21, the connection layer 22 is formed on the carrier 21.

Regarding the material of the tie layer 22, in some embodiments, the tie layer 22 is an adhesive layer film (adhesive layer).

That is, the chip module 12' is bonded to the carrier plate 21. For example, the material of the connection layer 22 may be an Ultraviolet (UV) curable adhesive or an adhesive (LTHC) material.

For example, as shown in fig. 6C, the connection layer 22 is first adhered to the carrier 21. The chip modules 12 'are then adhered to the connection layer 22 to effect a fixed placement of the plurality of chip modules 12' on the carrier plate 21.

In other embodiments, the connection layer 22 is a sacrificial layer film (sacrificial layer).

In still other embodiments, the connection layer 22 is a buffer layer film (buffer layer).

In still other embodiments, the connection layer 22 is a dielectric layer film (dielectric layer).

The material of the connection layer 22 is not limited in this embodiment, and may be any material with any performance and any function. Materials that are capable of connecting the chip module 12' to the carrier plate 21 and compatible with subsequent packaging processes are applicable to the present application.

It should be understood that in case the chip module 12 'can be directly obtained, the obtained chip module 12' can be directly put on the carrier plate 21. In the event that the chip module 12 'cannot be directly accessed, the wafer including the plurality of chip modules 12' also needs to be diced.

As illustrated in fig. 6D, a wafer obtained from a wafer factory, which is not bumped, is diced by standard wafer thinning (backside grinding, BG), laser groove sintering (LG), dicing (die saw, DS), and the like, to obtain a chip module 12'.

S2, as shown in fig. 6E, a plastic sealing film 13 'is formed on the carrier plate 21 on which the plurality of chip modules 12' are placed.

It is explained herein that the plastic sealing layer 13 'can be obtained after dicing the plastic sealing film 13' in the chip package structure 100 shown in fig. 4.

The embodiment of the present application does not limit the forming process and the forming material of the plastic sealing film 13 ', and exemplary, the plastic sealing film 13' is formed on the carrier plate 21 by using an injection molding process. The material forming the plastic sealing film 13' may include epoxy resin, for example: the plastic sealing film 13' is made of epoxy plastic sealing material (epoxy molding compound, EMC), underfill (UF), chip adhesive (adhesive material, AD), heat conducting medium material (thermal interface material, TIM) or the like.

The structure of the plastic packaging film 13 'is not limited, the formed plastic packaging film 13' is arranged on the carrier plate 21, and the thickness of the plastic packaging film 13 'is reasonably set according to the layout of the chip module 12', so that the plastic packaging film 13 'at least wraps the side face of the chip module 12'. Here, whether the plastic sealing film 13 'covers the top surface of the chip module 12' is not limited.

In some embodiments, as shown in fig. 6E, the plastic film 13 'wraps around the side of the chip module 12', exposing the top surface of the chip module 12 '(disposed opposite the bottom surface with contacts 122) to facilitate heat dissipation from the surface of the chip module 12'.

As for the method of forming the plastic sealing film 13 'shown in fig. 6E, for example, as shown in fig. 6E, the plastic sealing film 13' exposing the top surface of the chip module 12 'is formed directly on the carrier plate 21 and the chip module 12'.

The mode of directly forming the plastic packaging film 13 'has few process steps and high preparation efficiency, and is beneficial to heat dissipation of the surface of the chip module 12'.

Alternatively, as shown in fig. 6F, a plastic sealing film 13 'may be formed on the surfaces of the carrier plate 21 and the chip module 12', the plastic sealing film 13 'may wrap the side surfaces and the top surface of the chip module 12', and then the surface of the plastic sealing film 13 'away from the carrier plate 21 may be subjected to a polishing (polishing) process to expose the top surface of the chip module 12'.

The plastic sealing film 13' may be polished by, for example, chemical mechanical planarization (chemical mechanical polishing, CMP) process.

In other embodiments, as shown in fig. 6G, the plastic encapsulation film 13 'wraps the side and top surfaces of the chip module 12'.

Thus, the plastic sealing film 13' does not need to be ground by a CMP process, and the process steps can be reduced.

S3, as shown in fig. 6H, the carrier 21 is removed, and the contacts 122 are exposed.

Illustratively, the carrier plate 21 may be removed by a grinding process or a thinning process to expose the contacts 122 on the bottom surface of the chip module 12'. For example, the carrier plate 21 may be removed by mechanical grinding, chemical mechanical planarization process, wet etching, or dry etching.

Alternatively, the carrier plate 21 may be removed, illustratively, by removing the connection layer 22 between the carrier plate 21 and the chip module 12 'to expose the contacts 122 of the chip module 12' surface.

S4, as shown in fig. 6I, bumps 121 are formed on the contacts 122.

The bump 121 is electrically connected to the contact 122, so as to obtain the chip structure 12. It is understood that the contacts 122 of the chip module 12' surface correspond to the under ball metal layer (under bump metalization, UBM).

The bump 121 may be a structure made of metal solder such as solder ball (solder ball), bump (bump), copper pillar (Cu ballast), and controlled collapse chip connection bump (controlled collapse chip connection bump, C4 bump). Of course, the material and shape of the bump 121 in the embodiment of the present application are not limited, and the manufacturing process of the bump 121 is different according to the different structures of the bump 121.

For example, when the bump 121 is a solder ball, it may be prepared by coating, exposing, developing, printing with solder paste, implanting balls, and the like.

Alternatively, when the bump 121 is a copper pillar, it may be formed by coating, exposing, developing, curing, sputtering, electroplating, etching, reflow, or the like.

Different manufacturing processes may be selected as needed to form the bumps 121 of different structures.

S5, as shown in fig. 6J, a plurality of chamfer grooves 40 are formed on the bottom surface of the plastic sealing film 13' near the bump 121.

Wherein the chamfer 40 is located at the gap of the chip structure 12, i.e. the dicing street. The process of forming the chamfer groove 40 may be to cut on the bottom surface of the plastic sealing film 13' near the bump 121 using a cutter having an inclined side surface to form the chamfer groove 40. In addition, if necessary, an auxiliary groove may be formed before the chamfer groove 40 is formed, so as to reduce loss of the cutting blade.

Cutting knives of different shapes and angles can be selected as required to form chamfer grooves 40 of different shapes, so that chamfers 131 of different shapes are obtained.

The walls of the chamfer 40 may be straight or curved, for example. That is, the chamfer surface to be finally formed may be a straight surface or a curved surface.

By way of example, the angular extent of the chamfer 40 may be 30 ° -70 °, for example: the chamfer groove 40 may be at an angle of 45 °, 60 ° or 63 °, corresponding to the side inclination angle of the cutter.

The number and length of the chamfer grooves are not limited in the embodiment of the application. The chamfer groove 40 formed on the plastic sealing film 13' is different in structure according to the chamfer to be included in the plastic sealing film 13 to be formed.

Illustratively, as shown in fig. 6K, chamfer grooves 40 are formed throughout the entire row at the gaps of the multi-row chip structure 12. Wherein each column of chip structures 12 is arranged in sequence along a first direction X.

Thus, the resulting partial molding layer 13 has a chamfer on only one side (e.g., molding layer 13 surrounding chip structure 12-1 in fig. 6K), and partial molding layer 13 has a chamfer on both sides (e.g., molding layer 13 surrounding chip structure 12-2 in fig. 6K).

Illustratively, as shown in fig. 6L, chamfer grooves 40 extending through the entire row and column are formed at the gaps of the multi-column chip structure 12 and at the gaps of the multi-row chip structure 12. Wherein each row of chip structures 12 is arranged in sequence along the second direction Y.

Thus, the resulting partial molding layer 13 has chamfers only on three sides (e.g., molding layer 13 surrounding chip structure 12-3 in fig. 6L), and partial molding layer 13 has chamfers on four sides (e.g., molding layer 13 surrounding chip structure 12-4 in fig. 6L).

It will be appreciated that if it is desired to have chamfers on four sides of each molding layer 13, it is only necessary to ensure that the periphery of each chip structure 12 is formed with a chamfer 40. That is, it is desirable that the molding layer 13 has a chamfer on several sides, and the chip structure 12 has a chamfer groove 40 formed on several sides, and the chamfer on the molding layer 13 corresponds to the chamfer groove 40 on the molding film 13'.

S6, as shown in FIG. 6M, cutting is carried out along the cutting path to form an assembly structure 12".

It should be noted that the assembly structure 12″ includes the chip structure 12, the molding layer 13 and the bump 121, the bump 121 is electrically connected to the contact 122, and a chamfer 131 is formed on a surface of the molding layer 13 adjacent to the bump 121.

Wherein, the cutting lines which are staggered transversely and longitudinally are positioned at the gap of the chip structure 12, and the positions of the chamfer grooves 40 are coincident with the positions of the cutting lines. That is, it is understood that the cutting is performed centering on the intersection line of the two groove walls of the chamfer groove 40.

For example, a plurality of mutually separated assembled structures 12 "are formed by cutting along the dicing streets shown in fig. 6N using a dicing blade.

It should be noted that, in the embodiment of the present application, the order of S4 is not limited, and S4 may be executed first, and then S5 and S6 may be executed. S5 may be performed first, and S4 and S6 may be performed later.

S7, as shown in fig. 6N, the assembly structure 12″ obtained by dicing is electrically connected to the package substrate 11 through the bump 121.

The structure of the package substrate 11 is not limited in this embodiment, and the package substrate 11 may be capable of transmitting signals from the upper surface to the lower surface. For example, the package substrate 11 includes a plurality of signal line layers, an insulating layer is disposed between adjacent signal line layers, and the adjacent signal line layers are coupled through vias on the insulating layer to realize signal transmission.

According to the different structures of the bumps 121, the bonding manner of the bumps 121 and the package substrate 11 to achieve electrical connection is also different, which is not limited in the embodiment of the present application, and the electrical connection between the bumps 121 and the package substrate 11 may be achieved.

S8, as shown in fig. 6O, an underfill 14 is formed between the package structure 12″ and the package substrate 11.

Filling underfill glue (underfill) between the assembly structure 12 'and the package substrate 11 to form underfill glue 14, wherein the underfill glue 14 is arranged between the assembly structure 12' and the package substrate 11 to wrap the bumps 121; and overflows from the bottom of the assembled structure 12", wrapping around at least part of the chamfer face a of the chamfer 131.

Alternatively, the underfill 14 is disposed between the package structure 12″ and the package substrate 11, and is wrapped around the periphery of the plastic layer 13. The extent to which the underfill 14 covers the periphery of the molding layer 13 is not limited in this embodiment, and may be set as needed.

Illustratively, as shown in fig. 6O, the underfill 14 is applied to the chamfer surface a of the chamfer 131 on the molding layer 13.

Thus, the preparation process time is short, and the productivity is improved.

Alternatively, as illustrated in fig. 6P, the underfill 14 overflows from the bottom of the molding layer 13, over the chamfer 131 and wraps around the side b of the molding layer 13.

The underfill 14 may be wrapped to half the height of the side b of the plastic layer 13, or may be wrapped to all the side b of the plastic layer 13, or may be wrapped to any height of the side b of the plastic layer 13.

It is understood that the side b of the molding layer 13 refers to a face intersecting the top face c (a face away from the package substrate 11) of the molding layer 13. The side surface and the bottom surface d of the plastic layer 13 do not directly intersect, and a chamfer surface a is arranged between the side surface b and the bottom surface d. That is, in the embodiment of the present application, the chamfer a is not a part of the side face b of the molding layer 13. Since the higher the side b of the underfill 14 that encapsulates the molding layer 13, the greater the stress that the underfill 14 can withstand, the more resistant the risk of stress. Therefore, the underfill 14 is wrapped to the side b of the plastic layer 13 in the embodiment of the present application, so that the stress resistance risk of the underfill 14 can be increased.

The above packaging method provided by the embodiment of the application is not limited by any step sequence, and can be reasonably adjusted according to the needs.

In addition, the steps S1 to S8 may be omitted as needed, and are not limited to the steps. Some steps may be added as needed, and the steps are not limited to the above steps.

According to the packaging method of the chip packaging structure, the periphery of the chip structure 12 without forming a chamfer is wrapped with the plastic packaging film 13 ', and then the plastic packaging film 13' is cut to form a structure that the periphery of the chip structure 12 is wrapped with the plastic packaging film 13. Since no chamfer is required to be formed on the chip structure 12, a wider dicing street area is not required to be reserved on the wafer 10, and the actual size of the finally formed chip structure 12 is similar to the size of the functional area of the chip structure 12. Therefore, the problems of damage to the chip structure 12, waste of the wafer 10, and the like caused by forming the chamfer on the chip structure 12 can be avoided, and the manufacturing cost of the chip structure 12 can be reduced. In addition, the process of cutting the chamfer groove 40 on the molding layer 13 to form the chamfer 131 does not have any influence on the chip structure 12 such as cracks. The sintering groove 30 is not required to be formed on the plastic sealing layer 13, the safety distance is not required to be reserved, and the cutting path area can be reduced. Therefore, the assembled structure 12″ of the finally formed chip structure 12 surrounding the plastic layer 13 is not greatly different from the size of the chip structure 12, and the size of the chip package structure is not excessively increased. That is, after the chamfer on the chip structure 12 is transferred to the plastic sealing layer 13, the concentrated stress between the sharp corner of the chip structure 12 and the underfill 14 can be relieved, and the problem that the underfill 14 is cracked due to the concentrated stress can be avoided. The cost of the chip package structure can also be reduced and a series of problems caused by the need to cut the chip structure 12 can be solved. The limit of the chip structure under the large-size chip package is overcome, the problem of stress concentration of the corners of the chip structure 12 under the large-size and high-area-ratio chip package is solved, and the failure of the chip package structure under the high temperature is avoided.

In addition, the molding layer 13 wraps around the periphery of the chip structure 12, and the molding layer 13 is directly contacted with the underfill 14. The difference in thermal expansion coefficient between the molding compound forming the molding layer 13 and the underfill 14, and the difference in thermal expansion coefficient between the chip structure 12 and the molding layer 13 are smaller than the difference in thermal expansion coefficient between the chip structure 12 and the underfill 14. Therefore, the plastic layer 13 is used as a stress transition layer, so that the stress caused in the thermal expansion and contraction process between the chip structure 12 and the underfill 14 can be improved, and the concentrated stress of the corners of the chip structure 12 to the underfill 14 is reduced, thereby avoiding the problem that the chip packaging structure fails due to the fact that the underfill 14 is broken by the concentrated stress, and realizing the release of the stress in the chip packaging structure 100.

In addition, the material of the plastic layer 13 is softer and is easier to cut than the material of the wafer 10, so that the formed chamfer surface a is smoother, and local stress concentration caused by the uneven chamfer surface a is avoided. And the loss to the cutter in the process of forming the chamfer 131 is also small, the service life of the cutter is prolonged, and the preparation cost is further reduced.

Furthermore, the chip packaging method provided by the embodiment of the application can be applied to flip chip ball grid array packages (flip chip ball grid array, FCBGA), flip chip grid array packages (flip chip land grid array, FCLGA) and flip chip pin grid array packages (flip chip pin grid array, FCPGA), and has a wide application range. In addition, the preparation process can be realized by using the existing chip structure reorganization process, injection molding process and chamfer groove cutting process, and has the advantages of simple flow, low cost and mature technology.

The following embodiments illustrate the chip packaging structure provided in the embodiments of the present application, where the chip packaging structure may be prepared by using the packaging method of the chip packaging structure.

Based on this, as shown in fig. 7A, the chip package structure 100 includes: package substrate 11, chip structure 12, plastic layer 13, and underfill 14.

The chip structure 12 includes a plurality of bumps 121 on a surface (near a bottom surface of the package substrate 11), the chip structure 12 is disposed on the package substrate 11, and the bumps 121 are electrically connected to the package substrate 11 to electrically connect the chip structure 12 and the package substrate 11.

The specific structure of the chip structure 12 is not limited, and the chip structure 12 includes a chip, and the chip and the package substrate 11 can be electrically connected.

As shown in fig. 7B, the chip structure 12 mainly includes a chip module 12' and bumps 121.

In some embodiments, the chip module 12' includes an interconnect interposer (e.g., as may be understood as an interposer) 123, a plurality of vias 124, and a chip 125.

A plurality of via holes 124 penetrate through the interconnection transit layer 123, and illustratively, the end surfaces of the via holes 124 are flush with the surface of the interconnection transit layer 123.

The material of the interconnection switching layer 123 is not limited in this embodiment, and may be, for example, an inorganic nonmetallic material.

In some embodiments, the material of the interconnection layer 123 may be, for example, silicon, and the chip structure 12 may be understood as a through-silicon via-on-wafer-on-substrate (CoWoS) structure.

In other embodiments, the material of the interconnection via layer 123 may be glass, for example, and the chip structure 12 may be understood as a glass via interposer 2.5D package (cooos) structure.

In still other embodiments, the interconnect interposer material may be ceramic, for example, and the resulting chip structure 12 may be understood as a ceramic through-hole interposer 2.5D package (cos) structure.

In addition, the material of the via hole 124 is not limited in the embodiment of the present application, and the via hole 124 may be any conductive material. The via 124 may be fabricated, for example, by a through silicon via (through silicon via, TSV) technique, or an electroplating process.

As shown in fig. 7B, the chip 125 is disposed on the interconnection switching layer 123 (e.g., on the first surface) and electrically connected to the first end of the via 124. The bump 121 is also disposed on the interconnection switching layer 123 (on a second surface opposite to the first surface) and electrically connected to the second end of the via 124.

In this case, the second end of the via 124 may be understood as the contact 122 of the chip structure 12.

In some embodiments, to simplify the manner in which the chip 125 is electrically connected to the interconnection switching layer 123, as shown in fig. 7B, the active surface of the chip 125 is disposed toward the interconnection switching layer 123.

The structure of the transfer point exposed to the active surface of the chip 125 is different according to the structure of the chip 125. Illustratively, the transfer points exposed to the active side of the chip 125 are pads (pads). Alternatively, the transfer points exposed to the active side of the chip 125 are illustratively conductive pillars (bumps). Alternatively, the transfer points exposed to the active surface of the die 125 are solder balls, for example. Based on this, the embodiment of the present application does not limit the manner in which the chip 125 is electrically connected to the first end of the via 124. For example, the two may be electrically connected by bonding.

The number of chips 125 included in the chip structure 12 is not limited in the embodiments of the present application, and in some embodiments, the chip structure 12 includes one chip 125.

In other embodiments, as shown in fig. 7C, the chip structure 12 includes a plurality of chips 125.

For example, as shown in fig. 7C, a plurality of chips 125 are arranged side by side on the interconnection transit layer 123.

Alternatively, as illustrated in fig. 7D, a plurality of chips 125 are stacked and then disposed on the interconnection transit layer 123.

The structure of the chip 125 included in the chip structure 12 is not limited in the embodiments of the present application, and in some embodiments, the chip 125 may be a bare chip (may also be referred to as a die or a particle) (die). It can be understood that the dicing of the wafer results in a die.

In other embodiments, the chip 125 may be a packaged chip obtained by packaging a bare chip.

It is understood that in the case where the chip structure 12 includes a plurality of chips 125, the plurality of chips 125 may all be bare chips; the plurality of chips 125 may be all packaged chips; the plurality of chips 125 may also be partially bare chips and partially packaged chips.

Regarding the structure of the bump 121, the embodiment of the present application does not limit the structure and the material of the bump 121.

In some embodiments, bumps 121 may be solder balls (solder balls), bumps (bumps), copper pillars (Cu bumps), and controlled collapse chip connection bumps (controlled collapse chip connection bump, C4 bumps) or the like.

The bumps 121 with different structures can be obtained by adjusting the process of step S4 in the method for manufacturing the package structure.

With respect to the structure of the chip structure 12, in another embodiment, as shown in fig. 8A, the chip module 12' includes a chip 125 and bumps 121.

The number of chips 125 included in the chip structure 12 is not limited in this embodiment, and the chip structure 12 includes one chip 125 as illustrated in fig. 8A.

Alternatively, as illustrated in fig. 8B, the chip structure 12 includes a plurality of chips 125 arranged in a stack.

The chip 125 may be a bare chip or a packaged chip, which is not limited in the embodiment of the present application.

Bumps 121 are disposed on die 125, e.g., bumps 121 are disposed on the active side of die 125, and pads exposed to the active side of die 125 serve as contacts 122 in die structure 12, electrically connected to bumps 121.

The bump 121 may be, for example, a solder ball, bump, copper pillar, or C4 metal solder.

The chip module 12 'in fig. 7B-7D and fig. 8A and 8B is the chip module 12' placed on the carrier plate 21 in step S1 of the method for manufacturing the chip package structure. After the bump 121 is formed on the chip module 12', the chip structure 12 in the embodiment of the present application can be obtained.

Regarding the plastic layer 13 in the chip package structure 100, as shown in fig. 7A, the plastic layer 13 wraps at least the side of the chip structure 12 and exposes the bumps 121.

In some embodiments, as shown in fig. 7A, the molding layer 13 wraps around the sides of the chip structure 12 and covers the top surface of the chip structure 12 (the surface remote from the package substrate 11).

Thus, the preparation process is simple and the efficiency is high.

In other embodiments, as shown in fig. 9A, the molding layer 13 wraps around the sides of the chip structure 12 and exposes the top surface of the chip structure 12.

Thus, the surface heat dissipation of the chip structure 12 is facilitated.

The plastic layer 13 with different wrapping degrees can be obtained by adjusting the process of step S2 in the preparation method of the package structure.

On this basis, as shown in fig. 9A, the bottom outer side of the molding layer 13 has a chamfer 131.

Regarding the structure of the chamfer 131, in some embodiments, as shown in fig. 9A, the chamfer face a of the chamfer 131 is planar.

In other embodiments, as shown in fig. 9B, the chamfer surface a of the chamfer 131 is a curved surface.

The embodiment of the application is not limited to this, and can be reasonably arranged according to the needs.

In addition, the embodiment of the present application does not limit the size of the angle α of the chamfer 131, and the range of the chamfer angle α may be 30 ° to 70 °. For example: the chamfer angle α may be 45 °, 60 °, or 63 °. The chamfer angle α is understood to be the angle between the chamfer a and the bottom surface of the plastic layer 13.

In the process of executing the above step S5, the chamfer 131 with different structures can be prepared by setting the inclination angle of the side surface of the cutter and the shape of the side surface.

In some embodiments, as shown in fig. 9C, in the molding layer 13, a side of the chamfered chamfer surface a near the bottom of the molding layer 13 (a side near the package substrate 11) has no space from the chip structure 12.

Thus, the size of the molding layer 13 is smaller, and the size of the chip package structure 100 can be reduced.

In other embodiments, as shown in fig. 9A, a side of the chamfered chamfer surface a near the bottom of the molding layer 13 (near the package substrate 11 side) has a space (or understood as a horizontal margin) h1 from the chip structure 12; the chamfer surface a of the chamfer is close to the top of the plastic sealing layer 13 (the side far away from the package substrate 11) and has a distance (or understood as a vertical allowance) h2 from the chip structure 12.

That is, the chamfer 131 of the molding layer 13 has a horizontal distance from the chip structure 12, and the chamfer 131 is not cut directly to the edge of the chip structure 12.

In other embodiments, as shown in fig. 9D, a space h1 is provided between the side of the chamfered chamfer surface a near the bottom of the molding layer 13 (the side near the package substrate 11) and the chip structure 12, and the side of the chamfered chamfer surface a near the top of the molding layer 13 is directly contacted with the top of the molding layer 13 without a space.

By having a certain horizontal distance h1 between the chamfer 131 of the plastic layer 13 and the chip structure 12, the corners of the chip structure 12 can be wrapped by the plastic layer 13, and the plastic layer 13 is in direct contact with the underfill 14. In this way, cracking or warping caused by direct contact of the corners of the chip structure 12 with the underfill 14 can be avoided. Meanwhile, in the process of executing the above step S6, when dicing is performed along dicing streets, the problem of breakage of the chip structure 12 due to dicing of the chip structure 12 caused by dicing offset can be avoided.

Regarding the placement position of the chamfer 131, in some embodiments, as shown in fig. 10A, the chamfer 131 is placed only at four corners of the bottom of the molding layer 13.

Since the stress applied to the underfill 14 is greatest at the four corners of the bottom of the molding layer 13, the chamfers 131 are formed at the four corners of the bottom of the molding layer 13, so that the stress applied to the underfill 14 by the molding layer 13 can be reduced, and the risk of cracking of the underfill 14 can be reduced.

In other embodiments, as shown in fig. 10B, chamfer 131 is provided around the bottom outside of plastic layer 13.

Thus, the preparation process is simple and easy to realize.

The chamfer 131 arranged at different positions can be obtained by adjusting the process of the step S5 in the preparation method of the packaging structure.

The material of the plastic sealing layer 13 is not limited in this embodiment, and the plastic sealing layer 13 serves as a stress transition layer between the chip structure 12 and the underfill 14. Therefore, the stress applied by the molding layer 13 to the underfill 14 may be smaller than the stress applied by the chip structure 12 to the underfill 14.

For example, the hardness of the molding layer 13 is less than the hardness of the chip structure 12. For example, the modulus of the molding layer 13 is less than the modulus of the chip structure 12, but is close to the modulus of the underfill 14.

For example, the material of the plastic layer 13 uses epoxy resin as a substrate, and is doped to obtain a required material.

The material of the plastic layer 13 may be, for example, epoxy plastic, underfill, adhesive, or a heat conductive medium material.

As shown in fig. 7A, the underfill 14 in the chip package structure 100 is disposed on the package substrate 11, and is electrically connected to the package substrate 11 through the bumps 121. There is a gap between the chip structure 12 and the package substrate 11, and the underfill 14 is disposed at the gap between the chip structure 12 and the package substrate 11 and wraps around the periphery of the plastic layer 13.

The packaging degree of the underfill 14 on the plastic sealing layer 13 is not limited, and the packaging degree is reasonably set according to the process and the requirements.

In some embodiments, as shown in fig. 9A, an underfill 14 is applied to side b of the molding layer 13.

The underfill 14 may be wrapped to half the height of the side b of the plastic layer 13, or may wrap all the side b of the plastic layer 13, or may wrap any height of the side b of the plastic layer 13.

The higher the side height of the underfill 14 that encapsulates the molding layer 13, the greater the stress that the underfill 14 can withstand and the more resistant to the risk of stress. Therefore, the underfill 14 is wrapped to the side b of the plastic layer 13 in the embodiment of the present application, so that the stress resistance risk of the underfill 14 can be increased. In other embodiments, as shown in fig. 9E, the underfill 14 is wrapped to the chamfer face a of the chamfer 131.

The underfill 14 wraps the chamfer surface a of the chamfer 131, so that the bump 121 can be protected and the chip structure 12 can be stabilized. The preparation process time is short, and the productivity is improved.

The underfill 14 with different packaging degrees can be obtained by adjusting the process of step S8 in the preparation method of the package structure.

The chip packaging structure provided by the embodiment of the application comprises a packaging substrate 11, a chip structure 12 arranged on the packaging substrate 11, a plastic layer 13 at least wrapping the side surface of the chip structure 12, and underfill 14 arranged between the chip structure 12 and the packaging substrate 11 and wrapping the periphery of the plastic layer 13. The chip structure 12 includes a plurality of bumps 121 on a surface, and the bumps 121 are electrically connected with the package substrate 11; the plastic layer 13 wraps the side surface of the chip structure 12, the protruding points 121 are exposed, and a chamfer 131 is arranged on the outer side of the bottom of the plastic layer 13, which is close to the package substrate 11. Since the chip structure 12 with the chamfer is not needed, a wider cutting channel area on the wafer 10 is not needed to be reserved, and the actual size of the chip structure 12 is similar to the size of the functional area of the chip structure 12, the problems of damage to the chip structure 12, waste of the wafer 10 and the like caused by the chamfer on the chip structure 12 can be avoided, and the cost of the chip structure 12 is reduced.

Moreover, the chamfer 131 on the plastic sealing layer 13 does not have any influence on the chip structure 12, such as cracks, and the plastic sealing layer 13 does not need to be provided with the sintering groove 30, and a safe distance is not required to be reserved, so that the cutting path area can be reduced. Therefore, the size of the molding layer 13 does not need to be excessively large, and the size of the chip package structure is not excessively increased. That is, after the chamfer on the chip structure 12 is transferred to the plastic sealing layer 13, the concentrated stress between the sharp corner of the chip structure 12 and the underfill 14 can be relieved, and the problem that the underfill 14 is cracked due to the concentrated stress can be avoided. The cost of the chip package structure can also be reduced and a series of problems caused by dicing the chip structure 12 can be solved. The limit of the chip structure under the large-size chip package is overcome, the problem of stress concentration of the corners of the chip structure 12 under the large-size and high-area-ratio chip package is solved, and the failure of the chip package structure under the high temperature is avoided.

The molding layer 13 encapsulates the periphery of the chip structure 12, and the molding layer 13 is in direct contact with the underfill 14. The difference in thermal expansion coefficient between the molding compound forming the molding layer 13 and the underfill 14, and the difference in thermal expansion coefficient between the chip structure 12 and the molding layer 13 are smaller than the difference in thermal expansion coefficient between the chip structure 12 and the underfill 14. Therefore, the plastic layer 13 is used as a stress transition layer, so that the stress caused in the thermal expansion and contraction process between the chip structure 12 and the underfill 14 can be improved, and the concentrated stress of the corners of the chip structure 12 to the underfill 14 is reduced, thereby avoiding the problem that the chip packaging structure fails due to the fact that the underfill 14 is broken by the concentrated stress, and realizing the release of the stress in the chip packaging structure 100.

In addition, the material of the plastic layer 13 is softer and is easier to cut than the material of the wafer 10, so that the formed chamfer surface is smoother, and local stress concentration caused by uneven chamfer surface is avoided.

The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

A chip package structure, comprising:

packaging a substrate;

the chip structure comprises a plurality of bumps positioned on the surface; the chip structure is arranged on the packaging substrate, and the salient points are electrically connected with the packaging substrate;

a molding layer (molding) that wraps at least the sides of the chip structure; the outer side of the bottom of the plastic layer, which is close to the packaging substrate, is provided with a chamfer;

and the underfill is used for wrapping the convex points and at least part of chamfer surfaces of the chamfer angles.
The chip package structure of claim 1, wherein a side of the chamfered surface near the bottom of the molding layer has a spacing from the chip structure.
The chip package structure according to claim 1 or 2, wherein the underfill overflows from the bottom of the molding layer, flows over the chamfer and wraps around the sides of the molding layer.
A chip package structure according to any one of claims 1-3, wherein the material of the plastic layer comprises an epoxy resin.
The chip package structure according to any one of claims 1 to 4, wherein the chip structure is:

and the chip is provided with the convex points.
The chip package structure according to any one of claims 1 to 4, wherein the chip structure comprises:

an interconnection switching layer;

a plurality of via holes penetrating through the interconnection switching layer;

the chip is arranged on the interconnection switching layer and is electrically connected with one end of the through hole; the other end of the via hole is provided with the convex point.
A packaging method of a chip packaging structure, comprising:

forming a plastic packaging film on a carrier plate provided with a plurality of chip modules; the surface of the chip module with a plurality of contacts faces the carrier plate, and the plastic packaging film at least wraps the side surface of the chip module;

Removing the carrier plate to expose the contacts;

forming a bump on the contact, wherein the bump is electrically connected with the contact;

forming a plurality of chamfer grooves on the bottom surface of the plastic packaging film, which is close to the convex points, wherein the chamfer grooves are positioned at the gaps of the chip module;

cutting along the cutting path; the cutting channel is positioned at the gap of the chip module, and the position of the chamfer groove coincides with the position of the cutting channel;

electrically connecting the assembly structure obtained by cutting with the packaging substrate through the convex points;

and an underfill is formed between the assembly structure and the packaging substrate, and the underfill is wrapped on the periphery of the plastic packaging film.
A communication device comprising a printed wiring board and the chip package structure of any one of claims 1-6; the chip packaging structure is arranged on the printed circuit board and is coupled with the printed circuit board.