CN117527120A - PTP switch and implementation method thereof - Google Patents
PTP switch and implementation method thereof Download PDFInfo
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- CN117527120A CN117527120A CN202311451662.6A CN202311451662A CN117527120A CN 117527120 A CN117527120 A CN 117527120A CN 202311451662 A CN202311451662 A CN 202311451662A CN 117527120 A CN117527120 A CN 117527120A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
- H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays
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Abstract
The application discloses a PTP switch and an implementation method thereof, which are applied to a preset switch which does not support PTP clock synchronization and are used for solving the technical problems that the prior switch which does not support PTP needs to develop corresponding switch equipment aiming at time synchronization precision requirements and application scenes at the beginning of design if PTP function upgrading is to be realized. The method comprises the following steps: determining an appointed equipment optical port used for connecting a PHY chip in a preset exchanger; for the optical port of the appointed equipment, a recovered clock corresponding to the PHY chip connected to the optical port of the appointed equipment is accessed into a preset clock chip, so that the PTP clock and the recovered clock which are output to the exchange chip by the clock chip under the first application mode are homologous; and configuring the crystal oscillator in the clock chip to enable the clock chip to output a forward biased clock through the crystal oscillator, so that the SerDes clock corresponding to the exchange chip in the second application mode can be forward biased under the action of the forward biased clock.
Description
Technical Field
The application relates to the technical field of switches, in particular to a PTP switch and an implementation method thereof.
Background
The precision clock synchronization protocol (Precision Time Protocol, PTP) is a protocol for achieving network clock synchronization and is a protocol for time and frequency synchronization of standard ethernet end devices, which defines a method for achieving synchronization between network devices by transmitting time synchronization messages over the network. The protocol can realize sub microsecond time synchronization precision, and has important significance for communication systems, industrial control and test systems and the like which need high-precision time synchronization. For example, in a communication system, time synchronization is critical to ensure reliability and availability of data transmission; in industrial control, accurate time synchronization can ensure coordinated operation of the production process; in a test system, time synchronization can help ensure accuracy and consistency of test results.
The PTP is used for improving timing synchronization capability of the network system, and the PTP supporting equipment needs to confirm the architecture and single board design scheme of the system, and designs the special PTP supporting equipment aiming at the requirement of synchronization precision and application scene. Because PTP only needs to rely on software and hardware to cooperate to realize time synchronization, just so need to develop corresponding switch equipment to time synchronization precision requirement and application scenario at the beginning of the design, need just invest a large amount of manpower, material resources and time cost in the earlier design stage of equipment, the cost is higher.
Disclosure of Invention
In order to solve the above problems, the present application proposes a method for implementing a PTP switch, which is applied to a preset switch that does not support PTP clock synchronization, and the method includes:
determining an appointed equipment optical port used for connecting a PHY chip in the preset exchanger;
accessing a recovery clock corresponding to a PHY chip connected to the optical port of the specified equipment into a preset clock chip aiming at the optical port of the specified equipment, so that the PTP clock output to the exchange chip by the clock chip is homologous to the recovery clock in a first application mode;
and configuring the crystal oscillator in the clock chip so that the clock chip outputs a forward biased clock through the crystal oscillator, and enabling the SerDes clock corresponding to the exchange chip to forward bias under the action of the forward biased clock in a second application mode.
In one implementation manner of the present application, configuring the crystal oscillator in the clock chip specifically includes:
replacing the crystal oscillator in the clock chip with a forward-bias crystal oscillator capable of forward bias; wherein, the frequency corresponding to the forward bias crystal oscillator is 48MHz, and the frequency stability is 25ppm.
In one implementation of the present application, the clock chip is an Au5325B chip.
In one implementation of the present application, the type of the forward bias crystal oscillator is XO32-YAGRC-48.0012MHz.
In one implementation of the present application, the first application mode is required to be compatible with PTP synchronization requirements and SyncE synchronization requirements, and the second application mode is not required to be compatible with the PTP synchronization requirements and the SyncE synchronization requirements.
The embodiment of the application provides a PTP switch, which comprises a switching chip, a clock chip and a designated equipment optical port for connecting a PHY chip;
the clock chip is used for accessing a recovered clock corresponding to the PHY chip connected to the optical port of the appointed equipment so that the PTP clock output to the exchange chip in the first application mode is homologous to the recovered clock;
and outputting a forward bias clock through the configured crystal oscillator, so that the SerDes clock corresponding to the exchange chip in the second application mode can be forward biased under the action of the forward bias clock.
In one implementation manner of the present application, the crystal oscillator in the clock chip is a forward bias crystal oscillator capable of forward bias; wherein, the frequency corresponding to the forward bias crystal oscillator is 48MHz, and the frequency stability is 25ppm.
In one implementation of the present application, the clock chip is an Au5325B chip.
In one implementation of the present application, the type of the forward bias crystal oscillator is XO32-YAGRC-48.0012MHz.
In one implementation of the present application, the first application mode is required to be compatible with PTP synchronization requirements and SyncE synchronization requirements, and the second application mode is not required to be compatible with the PTP synchronization requirements and the SyncE synchronization requirements.
The PTP switch implementation method provided by the application can bring the following beneficial effects:
the recovered clock in the PHY chip connected with the preset switch is connected to the clock chip, so that the PTP clock output by the clock chip can keep the same with the recovered clock, and the PTP and SyncE functions can be realized by using part of interfaces in the preset switch which do not support the PTP clock synchronization function originally under the condition of not changing the board. Meanwhile, the crystal oscillator of the clock chip is configured, so that the clock forward bias requirement of the switching chip can be met in a second application mode of non-PTP+SyncE. The modified PTP exchanger can be compatible with two application scenes, and a board is not required to be changed when the PTP function is realized, so that the cost is greatly reduced, and the time precision can be improved to nanosecond level by means of the improvement of SyncE on the precision.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:
fig. 1 is a flow chart of a method for implementing a PTP switch according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of a PTP switch according to an embodiment of the present application.
Detailed Description
For the purposes, technical solutions and advantages of the present application, the technical solutions of the present application will be clearly and completely described below with reference to specific embodiments of the present application and corresponding drawings. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
The following describes in detail the technical solutions provided by the embodiments of the present application with reference to the accompanying drawings.
As shown in fig. 1, the implementation method of a PTP switch provided in the embodiment of the present application is applied to a preset switch that does not support PTP clock synchronization, and the method includes:
s101: and determining an appointed equipment optical port used for connecting the PHY chip in the preset switch.
The port physical layer (Port Physical Layer, PHY) is a common abbreviation for the OSI model physical layer, which is capable of connecting a device (MAC) of a data link layer to a physical medium such as an optical fiber or copper cable. PHY is capable of providing PTP time synchronization functions, requiring proper configuration of PTP parameters when in use to ensure proper transmission of data in the physical layer and protocol stack. Meanwhile, the PHY also supports a SyncE function, and the SyncE is mainly used for carrying out frequency synchronization among Ethernet devices, and the devices supporting the SyncE extract clock signals from a received serial data stream from an upstream Ethernet device, wherein the clock signal extraction work is carried out in a PHY chip, such as a digital phase-locked loop. The extracted clock signal can be output through an interface, and can also be continuously transmitted to downstream equipment through Ethernet data.
An ethernet PHY is a chip that can send and receive ethernet data frames. PHY chips differ from switching chips in that switching chips implement network switching by forwarding data packets between different ports, while PHY chips are electrical signals required to convert data from or to a physical medium for communication at the physical layer. The switch chip is typically mounted on the motherboard of the switch or router, while the PHY chip is typically mounted on a port of the switch or router, with some of the PHYs being integrated into the switch chip.
The preset switch equipment optical ports are of two types, as shown in a schematic architecture of a PTP switch shown in fig. 2, the PTP switch includes two equipment optical ports, namely an optical module a and an optical module B, wherein a PHY of the optical module B is integrated in a switch chip, and the optical module a is used for separately accessing the PHY chip. Considering that the existing device does not perform special processing on the clock of the PHY chip, the optical port of the device of the type of the optical module a is mainly designed for the embodiment of the application.
S102: and accessing a recovered clock corresponding to the PHY chip connected to the optical port of the specified equipment into a preset clock chip aiming at the optical port of the specified equipment, so that the PTP clock output from the clock chip to the exchange chip is homologous to the recovered clock in the first application mode.
After determining the optical port of the designated device for connecting the PHY chip, for the independent PHY, if the time synchronization of the switch is to be realized, the recovered clock of the PHY needs to be separately connected, the parameter clock of the PHY needs to be homologous to the PTP clock of the switching chip, and the higher the phase noise is, the better the accuracy is.
As shown in fig. 2, in the embodiment of the present application, an Au5325B chip is used as a clock chip, an original connection pin R1 on the Au5325B chip is disconnected, the clock chip is connected with a switch chip by soldering R2, and then a recovered clock corresponding to a PHY chip connected to an optical port of a specified device is accessed into a preset clock chip, so that, in a first application mode that needs to be compatible with PTP synchronization requirements and SyncE synchronization requirements, a PTP clock output by the clock chip into the switch chip can keep homology with the recovered clock, and thus, the preset switch that does not currently support PTP functions can realize clock synchronization by the PTP clock.
S103: and configuring the crystal oscillator in the clock chip to enable the clock chip to output a forward biased clock through the crystal oscillator, so that the SerDes clock corresponding to the exchange chip in the second application mode can be forward biased under the action of the forward biased clock.
The preset switch can also meet the data exchange function in a non-PTP scene on the basis of supporting the PTP+SyncE function, but the Serdes Clock of the switch chip in the scene without SyncE+PTP needs to be forward biased, otherwise, error codes can occur, and therefore the switch chip of the preset switch is required to be compatible with the synchronous requirement of PTP+SyncE and the forward biased requirement of Serdes Clock in the scene without PTP+SyncE.
The switching chip is used for configuring the crystal oscillator in the clock chip under the condition that the clock configuration is not changed, so that the clock chip outputs a forward biased clock through the crystal oscillator, and the SerDes clock corresponding to the switching chip in the second application mode can be forward biased under the action of the forward biased clock.
The frequency corresponding to the crystal oscillator of the original clock chip is 48MHz, but the crystal oscillator does not have a forward bias function, so that the crystal oscillator in the clock chip is replaced by a forward bias crystal oscillator capable of forward bias. The model of the forward-biased crystal oscillator is XO32-YAGRC-48.0012MHz, the corresponding frequency of the forward-biased crystal oscillator is 48MHz, and the frequency stability is 25ppm. The frequency stability is used for measuring the frequency deviation parameter of the crystal oscillator in the working temperature range, the crystal oscillator corresponding to the clock chip is replaced by the forward-biased crystal oscillator with 25ppm, and the clock chip can output the forward-biased clock along with the crystal oscillator under the second application mode without the need of being compatible with PTP synchronization requirement and SyncE synchronization requirement.
The recovered clock in the PHY chip connected with the preset switch is connected to the clock chip, so that the PTP clock output by the clock chip can keep the same with the recovered clock, and the PTP and SyncE functions can be realized by using part of interfaces in the preset switch which do not support the PTP clock synchronization function originally under the condition of not changing the board. Meanwhile, the crystal oscillator of the clock chip is configured, so that the clock forward bias requirement of the switching chip can be met in a second application mode of non-PTP+SyncE. The modified PTP exchanger can be compatible with two application scenes, and a board is not required to be changed when the PTP function is realized, so that the cost is greatly reduced, and the time precision can be improved to nanosecond level by means of the improvement of SyncE on the precision.
The foregoing is a method embodiment presented herein. Based on the same inventive concept, the embodiment of the application also provides a PTP switch, and a schematic structure diagram of the PTP switch is shown in fig. 2.
The embodiment of the application provides a PTP switch, which comprises a switch chip, a clock chip and a designated equipment optical port for connecting with a PHY chip.
The clock chip is used for accessing a recovered clock corresponding to the PHY chip connected to the optical port of the designated equipment so as to enable the PTP clock output to the switching chip under the first application mode to be homologous to the recovered clock;
and outputting a forward bias clock through the configured crystal oscillator, so that the SerDes clock corresponding to the exchange chip in the second application mode can be forward biased under the action of the forward bias clock. The first application mode is required to be compatible with the PTP synchronization requirement and the Sync E synchronization requirement, and the second application mode is required to be compatible with the PTP synchronization requirement and the Sync E synchronization requirement.
The crystal oscillator in the clock chip is a forward bias crystal oscillator capable of forward bias; wherein, the frequency corresponding to the forward bias crystal oscillator is 48MHz, and the frequency stability is 25ppm. The clock chip is an Au5325B chip. The model of the forward bias crystal oscillator is XO32-YAGRC-48.0012MHz.
All embodiments in the application are described in a progressive manner, and identical and similar parts of all embodiments are mutually referred, so that each embodiment mainly describes differences from other embodiments. In particular, for the apparatus and medium embodiments, the description is relatively simple, as it is substantially similar to the method embodiments, with reference to the section of the method embodiments being relevant.
The devices and media provided in the embodiments of the present application are in one-to-one correspondence with the methods, so that the devices and media also have similar beneficial technical effects as the corresponding methods, and since the beneficial technical effects of the methods have been described in detail above, the beneficial technical effects of the devices and media are not described in detail herein.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In one typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
The memory may include volatile memory in a computer-readable medium, random Access Memory (RAM) and/or nonvolatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of computer-readable media.
Computer readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device. Computer-readable media, as defined herein, does not include transitory computer-readable media (transmission media), such as modulated data signals and carrier waves.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.
The foregoing is merely exemplary of the present application and is not intended to limit the present application. Various modifications and changes may be made to the present application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. which are within the spirit and principles of the present application are intended to be included within the scope of the claims of the present application.
Claims (10)
1. The implementation method of the PTP switch is characterized by being applied to a preset switch which does not support PTP clock synchronization, and comprises the following steps:
determining an appointed equipment optical port used for connecting a PHY chip in the preset exchanger;
accessing a recovery clock corresponding to a PHY chip connected to the optical port of the specified equipment into a preset clock chip aiming at the optical port of the specified equipment, so that the PTP clock output to the exchange chip by the clock chip is homologous to the recovery clock in a first application mode;
and configuring the crystal oscillator in the clock chip so that the clock chip outputs a forward biased clock through the crystal oscillator, and enabling the SerDes clock corresponding to the exchange chip to forward bias under the action of the forward biased clock in a second application mode.
2. The method for implementing a PTP switch according to claim 1, wherein configuring the crystal oscillator in the clock chip specifically includes:
replacing the crystal oscillator in the clock chip with a forward-bias crystal oscillator capable of forward bias; wherein, the frequency corresponding to the forward bias crystal oscillator is 48MHz, and the frequency stability is 25ppm.
3. The method according to claim 1, wherein the clock chip is an Au5325B chip.
4. The method according to claim 2, wherein the positive bias crystal oscillator is of the type XO 32-yacrc-48.0012 MHz.
5. The method according to claim 1, wherein the first application mode is compatible with PTP synchronization requirements and SyncE synchronization requirements, and the second application mode is not compatible with the PTP synchronization requirements and the SyncE synchronization requirements.
6. The PTP switch is characterized by comprising a switching chip, a clock chip and a designated equipment optical port for connecting with a PHY chip;
the clock chip is used for accessing a recovered clock corresponding to the PHY chip connected to the optical port of the appointed equipment so that the PTP clock output to the exchange chip in the first application mode is homologous to the recovered clock;
and outputting a forward bias clock through the configured crystal oscillator, so that the SerDes clock corresponding to the exchange chip in the second application mode can be forward biased under the action of the forward bias clock.
7. The PTP switch of claim 6, wherein the crystal oscillator in the clock chip is a forward biased crystal oscillator capable of forward biasing; wherein, the frequency corresponding to the forward bias crystal oscillator is 48MHz, and the frequency stability is 25ppm.
8. The PTP switch of claim 6, wherein the clock chip is an Au5325B chip.
9. The PTP switch of claim 7, wherein the forward biased crystal oscillator is model XO 32-yacrc-48.0012 MHz.
10. The PTP switch of claim 6, wherein the first application mode is compatible with PTP and SyncE synchronization requirements, and wherein the second application mode is not compatible with the PTP and SyncE synchronization requirements.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202311451662.6A CN117527120A (en) | 2023-11-02 | 2023-11-02 | PTP switch and implementation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311451662.6A CN117527120A (en) | 2023-11-02 | 2023-11-02 | PTP switch and implementation method thereof |
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| CN117527120A true CN117527120A (en) | 2024-02-06 |
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| CN202311451662.6A Pending CN117527120A (en) | 2023-11-02 | 2023-11-02 | PTP switch and implementation method thereof |
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