CN117526916A - Driving circuit and method for insulated gate bipolar transistor - Google Patents
Driving circuit and method for insulated gate bipolar transistor Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/567—Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
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Abstract
The application provides a drive circuit and a drive method of an insulated gate bipolar transistor, which relate to the technical field of drive circuits, wherein a drive module responds to a control instruction to generate a first signal, a first narrow wave circuit generates a first narrow wave signal according to the first signal, a second narrow wave circuit generates a second narrow wave signal according to the first signal, and a synthesis module synthesizes the first narrow wave signal and the second narrow wave signal into a control signal, so that the insulated gate bipolar transistor is turned on or turned off in response to the control signal, the on and off of the insulated gate bipolar transistor are controlled, a level transfer chip is not required to be added, the cost is reduced, and the problem that the cost is increased due to the fact that the level transfer chip is added in the prior art is solved. In addition, the zero temperature coefficient first resistor and the zero temperature coefficient second resistor in the driving circuit can improve the stability of the control signal.
Description
Technical Field
The application belongs to the technical field of driving circuits, and particularly relates to a driving circuit and a driving method of an insulated gate bipolar transistor.
Background
Insulated gate bipolar transistors (IGBTs, insulated gate bipolar transistor) are widely used in applications such as industrial electric motors, domestic small-capacity motors, converters (inverters), stroboscopes for cameras, induction heating rice cookers, and the like. In order to realize control of turning on and off of the insulated gate bipolar transistor, a driving circuit of the insulated gate bipolar transistor is required.
In the prior art, a low-voltage domain control signal output by a driving chip is converted into a high-voltage domain control signal suitable for a high-voltage domain where an insulated gate bipolar transistor is located through a level shifting chip, so that the on and off of the insulated gate bipolar transistor are controlled.
The application range of the IGBT is generally above 600V, the current is above 10A, and the frequency is above 1kHz, and the control signal output by the driving chip is generally a pulse width modulation (PWM, pulse width modulation wave) signal with 3.3V or 5V and the frequency less than 100 kHz.
In implementing the present application, the inventors found that at least the following problems exist in the prior art: the low-voltage domain control signal output by the driving chip is converted into a high-voltage domain control signal suitable for the high-voltage domain where the insulated gate bipolar transistor is located through the level transfer chip, so that the on and off of the insulated gate bipolar transistor are controlled, the level transfer chip is required to be added, and the cost is increased.
Disclosure of Invention
The application aims to provide a drive circuit and a drive method of an insulated gate bipolar transistor, which at least solve the problem that in the prior art, as a level transfer chip is used for converting a low-voltage domain control signal output by the drive chip into a high-voltage domain control signal suitable for a high-voltage domain where the insulated gate bipolar transistor is located, so as to control the on and off of the insulated gate bipolar transistor, the level transfer chip is required to be added, and the cost is increased.
In order to solve the technical problems, the application is realized as follows:
in a first aspect, embodiments of the present application provide a driving circuit of an insulated gate bipolar transistor, including: the device comprises a driving module, a first narrow-wave circuit, a second narrow-wave circuit, a synthesis module and an insulated gate bipolar transistor; the driving module is respectively and electrically connected with the first narrow-wave circuit and the second narrow-wave circuit, and the synthesizing module is respectively and electrically connected with the first narrow-wave circuit, the second narrow-wave circuit and the insulated gate bipolar transistor;
the driving module is used for responding to the control instruction and generating a first signal; the first narrow-wave circuit is used for generating a first narrow-wave signal according to the first signal; the second narrow wave circuit is used for generating a second narrow wave signal according to the first signal; the synthesis module is used for synthesizing the first narrow-wave signal and the second narrow-wave signal into control signals; the insulated gate bipolar transistor is used for being turned on or turned off in response to the control signal;
Wherein the first narrow wave circuit comprises a first resistor with a zero temperature coefficient, and the second narrow wave circuit comprises a second resistor with a zero temperature coefficient; the narrow wave width of the first narrow wave signal is positively correlated with the resistance value of the first resistor, and the narrow wave width of the second narrow wave signal is positively correlated with the resistance value of the second resistor.
In a second aspect, embodiments of the present application provide a driving method of an insulated gate bipolar transistor, the method including:
generating a first signal in response to a control instruction;
generating a first narrow-wave signal according to the first signal, and generating a second narrow-wave signal according to the first signal;
synthesizing the first narrow-wave signal and the second narrow-wave signal into control signals;
in response to the control signal, controlling the insulated gate bipolar transistor to be turned on or off;
the narrow wave width of the first narrow wave signal is controlled through a first resistor with a zero temperature coefficient, and the narrow wave width of the second narrow wave signal is controlled through a second resistor with a zero temperature coefficient; the narrow wave width of the first narrow wave signal is positively correlated with the resistance value of the first resistor, and the narrow wave width of the second narrow wave signal is positively correlated with the resistance value of the second resistor.
In the embodiment of the application, the driving module responds to the control instruction to generate the first signal, the first narrow-wave circuit generates the first narrow-wave signal according to the first signal, the second narrow-wave circuit generates the second narrow-wave signal according to the first signal, and the synthesizing module synthesizes the first narrow-wave signal and the second narrow-wave signal into the control signal, so that the insulated gate bipolar transistor is turned on or off in response to the control signal, the control on and off of the insulated gate bipolar transistor is realized, a level transfer chip is not needed to be added, the cost is reduced, and the problem that in the prior art, because the level transfer chip is used, the low-voltage domain control signal output by the driving chip is converted into the high-voltage domain control signal suitable for the high-voltage domain where the insulated gate bipolar transistor is located, the control on and off of the insulated gate bipolar transistor is realized, and the level transfer chip is needed to be added, and the cost is increased is solved. In addition, since the narrow width of the first narrow signal is positively correlated with the resistance value of the first resistor of zero temperature coefficient, the narrow width of the second narrow signal is positively correlated with the resistance value of the second resistor of zero temperature coefficient, and the resistance value of the first resistor of zero temperature coefficient and the resistance value of the second resistor of zero temperature coefficient change less with temperature, the narrow width of the first narrow signal and the narrow width stability of the second narrow signal can be improved, and the stability of the control signal can be further improved, so that the control stability of the insulated gate bipolar transistor can be improved.
Drawings
Fig. 1 is a schematic diagram of a driving circuit of an insulated gate bipolar transistor according to an embodiment of the present application;
fig. 2 is a step flowchart of a driving method of an insulated gate bipolar transistor according to an embodiment of the present application;
fig. 3 is a schematic diagram of a driving circuit of an insulated gate bipolar transistor according to an embodiment of the present application;
fig. 4 is a schematic waveform diagram of a driving circuit of an insulated gate bipolar transistor according to an embodiment of the present application;
FIG. 5 is a schematic diagram showing a temperature coefficient of resistance according to a temperature change curve provided in an embodiment of the present application;
FIG. 6 is a schematic diagram of experimental data for narrow wave widths provided in an embodiment of the present application;
fig. 7 is a schematic structural diagram of a zero temperature coefficient resistor according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
The terms first, second and the like in the description and in the claims, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present application may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type and not limited to the number of objects, e.g., the first object may be one or more. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means that the associated object is an "or" relationship.
Referring to fig. 1, an embodiment of the present application provides a driving circuit of an insulated gate bipolar transistor 50, including: a driving module 10, a first narrow-wave circuit 20, a second narrow-wave circuit 30, a synthesizing module 40, and an insulated gate bipolar transistor 50; the driving module 10 is electrically connected to the first narrow-wave circuit 20 and the second narrow-wave circuit 30, and the synthesizing module 40 is electrically connected to the first narrow-wave circuit 20, the second narrow-wave circuit 30, and the insulated gate bipolar transistor 50;
The driving module 10 is used for responding to the control instruction and generating a first signal; the first narrow-wave circuit 20 is configured to generate a first narrow-wave signal according to the first signal; the second narrow-wave circuit 30 is configured to generate a second narrow-wave signal according to the first signal; the synthesizing module 40 is configured to synthesize the first narrow-wave signal and the second narrow-wave signal into a control signal; the insulated gate bipolar transistor 50 is configured to be turned on or off in response to the control signal;
wherein the first narrow-wave circuit 20 includes a first resistor R1 with a zero temperature coefficient, and the second narrow-wave circuit 30 includes a second resistor R2 with a zero temperature coefficient; the narrow wave width of the first narrow wave signal is positively correlated with the resistance value of the first resistor R1, and the narrow wave width of the second narrow wave signal is positively correlated with the resistance value of the second resistor R2.
It should be noted that, the first signal is a PWM square wave signal in a low voltage domain, the low voltage domain may be 3.3V or 5V, and the frequency is less than 100kHz, for example, the first signal may be a PWM square wave signal in 3.3V or 5V, and the frequency is less than 100 kHz; the control signal is a PWM square wave signal in a high voltage region where the insulated gate bipolar transistor 50 is located, and the high voltage region may be a region with a withstand voltage of 600V or more, a current of 10A or more, and a frequency of 1kHz or more; the period of the control signal is the same as that of the first signal, the duty ratio of the control signal is the same as that of the first signal, that is, the control signal is high when the first signal is high, and the control signal is low when the first signal is low, so as to convert the first signal in the low voltage domain output by the driving module 10 into a control signal suitable for the high voltage domain where the insulated gate bipolar transistor 50 is located, wherein the duty ratio is the ratio of the signal width (the signal existence duration) of the high level to the period in one period of the signal.
The insulated gate bipolar transistor 50 is turned on when the control signal is high, and the insulated gate bipolar transistor 50 is turned off when the control signal is low.
The first narrow-wave signal and the second narrow-wave signal are both narrow-pulse square waves, the narrow-pulse square waves are square waves in which the width of a signal at a high level (signal existence duration) in each period is smaller than the width of a signal at a low level, and the pulse width of a signal at a high level in each period of the narrow-pulse square waves is called a narrow-wave width.
Specifically, in some embodiments, the period and the narrow wave width of the first narrow wave signal and the second narrow wave signal are the same.
The zero-temperature-coefficient first resistor R1 and the zero-temperature-coefficient second resistor R2 are both zero-temperature-coefficient resistors, and the resistance value of the zero-temperature-coefficient resistor changes less with temperature than that of a normal resistor (positive-temperature-coefficient resistor or negative-temperature-coefficient resistor). The resistance value of the zero temperature coefficient resistor can be approximately regarded as being constant with temperature change.
Specifically, referring to fig. 5, in some embodiments, the first resistor R1 and the second resistor R2 are the same resistor, in fig. 5, the ordinate axis P is the temperature coefficient of the resistor, the abscissa axis t is the temperature (in degrees celsius), the curve X1 is the curve of the temperature coefficient of the first resistor R1 with the temperature change in the embodiment of the application, the curve X2 is the curve of the temperature coefficient of the resistor with the negative temperature coefficient with the temperature change, and the temperature coefficient of the first resistor R1 with the temperature change is smaller, approximately unchanged, compared with the resistance with the negative temperature coefficient in the embodiment of the application, and since the temperature coefficient of the first resistor R1 is close to the zero temperature coefficient in the embodiment of the application, the first resistor R1 can be regarded as the resistance with the zero temperature coefficient in the embodiment of the application. It should be noted that, the smaller the absolute value of the temperature coefficient, the smaller the resistance value of the resistor changes with temperature, the more stable the resistance value of the resistor, and the resistance value of the resistor with zero temperature coefficient is more stable relative to the common resistor, and the resistance values of the first resistor R1 and the second resistor R2 in the embodiment of the present application are both more stable than the resistance value of the common resistor.
The following table (table 1) is experimental data of a first scheme and a second scheme, wherein the first scheme is a driving circuit of the insulated gate bipolar transistor 50 obtained by replacing the first resistor R1 and the second resistor R2 in the embodiment of the present application with common resistors, and the second scheme is a driving circuit of the insulated gate bipolar transistor 50 provided in the embodiment of the present application.
TABLE 1
The narrow-wave width of the narrow-wave signal (Z2 in fig. 6) generated by the driving circuit of the insulated gate bipolar transistor 50 of the first embodiment is 222 ns at the ambient temperature of 25 degrees celsius, the narrow-wave width of the narrow-wave signal (Z1 in fig. 6) generated by the driving circuit of the insulated gate bipolar transistor 50 of the first embodiment is 164 ns at the ambient temperature of-40 degrees celsius, the deviation from 222 ns at 25 degrees celsius is-26.13%, the narrow-wave width of the narrow-wave signal (Z3 in fig. 6) generated by the driving circuit of the insulated gate bipolar transistor 50 of the first embodiment is 317 ns at the ambient temperature of 125 degrees celsius, and the deviation from 222 ns at 25 degrees celsius is 42.79%.
At an ambient temperature of 25 degrees celsius, the narrow-wave width of the narrow-wave signal (including the first narrow-wave signal and the second narrow-wave signal, as in Z5 in fig. 6) generated by the drive circuit of the insulated gate bipolar transistor 50 of the second embodiment is 98 nanoseconds, at an ambient temperature of-40 degrees celsius, the narrow-wave width of the narrow-wave signal (as in Z4 in fig. 6) generated by the drive circuit of the insulated gate bipolar transistor 50 of the second embodiment is 97 nanoseconds, the deviation from 98 nanoseconds at 25 degrees celsius is-1.02%, and at an ambient temperature of 125 degrees celsius, the narrow-wave width of the narrow-wave signal (as in Z6 in fig. 6) generated by the drive circuit of the insulated gate bipolar transistor 50 of the second embodiment is 112 nanoseconds, the deviation from 98 nanoseconds at 25 degrees celsius is 14.29%.
Therefore, compared to the driving circuit of the first insulated gate bipolar transistor 50, the driving circuit of the second insulated gate bipolar transistor 50 (i.e., the driving circuit of the insulated gate bipolar transistor 50 provided in the embodiment of the present application) generates a more stable narrow wave signal, and the driving circuit of the second insulated gate bipolar transistor 50 generates a narrower narrow wave width, so that the driving circuit of the second insulated gate bipolar transistor 50 consumes less energy.
The zero temperature coefficient of resistance may be a combination of a plurality of sub-resistances.
Specifically, in some embodiments, referring to the (a) diagram in fig. 7, the zero temperature coefficient resistor may be a first sub-resistor Rp1 and a second sub-resistor Rn1 connected in series, where the first sub-resistor Rp1 is a positive temperature coefficient resistor and the second sub-resistor Rn1 is a negative temperature coefficient resistor;
in some embodiments, referring to the (b) diagram in fig. 7, the zero temperature coefficient resistor includes a third sub-resistor Rp2, a fourth sub-resistor Rp3, and a fifth sub-resistor Rn2, the third sub-resistor Rp2 and the fourth sub-resistor Rp3 are connected in parallel, the third sub-resistor Rp2 and the fifth sub-resistor Rn2 are connected in series, the fourth sub-resistor Rp3 and the fifth sub-resistor Rn2 are connected in series, wherein the third sub-resistor Rp2 and the fourth sub-resistor Rp3 are both positive temperature coefficient resistors, and the fifth sub-resistor Rn2 is a negative temperature coefficient resistor;
In some embodiments, referring to the (c) diagram in fig. 7, the zero temperature coefficient resistor includes a sixth sub-resistor Rp4, a seventh sub-resistor Rn3, an eighth sub-resistor Rn4, the seventh sub-resistor Rn3 and the eighth sub-resistor Rn4 are connected in parallel, the seventh sub-resistor Rn3 and the sixth sub-resistor Rp4 are connected in series, the eighth sub-resistor Rn4 and the sixth sub-resistor Rp4 are connected in series, wherein the sixth sub-resistor Rp4 is a positive temperature coefficient resistor, and the seventh sub-resistor Rn3 and the eighth sub-resistor Rn4 are both negative temperature coefficient resistors;
in some embodiments, referring to the (d) diagram in fig. 7, the zero temperature coefficient resistor includes a ninth sub-resistor Rp5, a tenth sub-resistor Rp6, an eleventh sub-resistor Rn5, a twelfth sub-resistor Rn6, the ninth sub-resistor Rp5 and the tenth sub-resistor Rp6 being connected in parallel, the eleventh sub-resistor Rn5 and the twelfth sub-resistor Rn6 being connected in parallel, the parallel combination of the ninth sub-resistor Rp5 and the tenth sub-resistor Rp6 and the parallel combination of the eleventh sub-resistor Rn5 and the twelfth sub-resistor Rn6 being connected in series, wherein the ninth sub-resistor Rp5 and the tenth sub-resistor Rp6 are both positive temperature coefficient resistors, and the eleventh sub-resistor Rn5 and the twelfth sub-resistor Rn6 are both negative temperature coefficient resistors.
In the embodiment of the application, the driving module responds to the control instruction to generate the first signal, the first narrow-wave circuit generates the first narrow-wave signal according to the first signal, the second narrow-wave circuit generates the second narrow-wave signal according to the first signal, and the synthesizing module synthesizes the first narrow-wave signal and the second narrow-wave signal into the control signal, so that the insulated gate bipolar transistor is turned on or off in response to the control signal, the control on and off of the insulated gate bipolar transistor is realized, a level transfer chip is not needed to be added, the cost is reduced, and the problem that in the prior art, because the level transfer chip is used, the low-voltage domain control signal output by the driving chip is converted into the high-voltage domain control signal suitable for the high-voltage domain where the insulated gate bipolar transistor is located, the control on and off of the insulated gate bipolar transistor is realized, and the level transfer chip is needed to be added, and the cost is increased is solved.
In addition, since the narrow width of the first narrow signal is positively correlated with the resistance value of the first resistor of the zero temperature coefficient and the narrow width of the second narrow signal is positively correlated with the resistance value of the second resistor of the zero temperature coefficient, and the resistance value of the first resistor of the zero temperature coefficient and the resistance value of the second resistor of the zero temperature coefficient are less varied with temperature than the normal resistor, so that the narrow width of the first narrow signal and the narrow width of the second narrow signal are less varied with temperature, it is possible to improve the stability of the narrow width of the first narrow signal and the stability of the narrow width of the second narrow signal, and further improve the stability of the control signal synthesized by the first narrow signal and the second narrow signal, to improve the stability of the drive of the insulated gate bipolar transistor by the control signal.
Optionally, referring to fig. 3, in some embodiments, the first narrow-wave circuit 20 includes a first inverter F1, a first delay sub-circuit 21, a first nor gate unit 22, and a first MOS transistor M1, and the second narrow-wave circuit 30 includes a second delay sub-circuit 31, a second nor gate unit 32, and a second MOS transistor M2; wherein the first delay sub-circuit 21 comprises the first resistor R1 and the second delay sub-circuit 31 comprises the second resistor R2;
The output end of the driving module 10 is electrically connected to the input end of the first inverter F1, the input end of the second delay sub-circuit 31, and the first input end of the second nor gate unit 32, the output end of the first inverter F1 is electrically connected to the input end of the first delay sub-circuit 21 and the first input end of the first nor gate unit 22, the output end of the first delay sub-circuit 21 is electrically connected to the second input end of the first nor gate unit 22, and the output end of the first nor gate unit 22 is electrically connected to the gate of the first MOS transistor M1;
the output end of the second delay sub-circuit 31 is electrically connected with the second input end of the second nor gate unit 32, and the output end of the second nor gate unit 32 is electrically connected with the gate of the second MOS transistor M2; the first input end of the synthesis module 40 is electrically connected to the drain electrode of the first MOS transistor M1, the second input end of the synthesis module 40 is electrically connected to the drain electrode of the second MOS transistor M2, and the output end of the synthesis module 40 is electrically connected to the gate electrode of the insulated gate bipolar transistor 50.
In this embodiment of the present application, the first inverter F1 and the second inverter F2 are both inverters, where the inverters are components that invert the phase of the signal input to the inverters by 180 degrees and output the signal, and when the signal input to the inverters is at a high level, the signal output by the inverters is at a low level, and when the signal input to the inverters is at a low level, the signal output by the inverters is at a high level.
The first nor gate unit 22 and the second nor gate unit 32 are nor gate devices, each of the nor gate devices includes two input terminals and one output terminal, and when signals input to the two input terminals of each nor gate device are both low-level signals, the output terminal of each nor gate device outputs a high-level signal, when signals input to one input terminal of each nor gate device are high-level signals, when signals input to the other input terminal of each nor gate device are low-level signals, the output terminal of each nor gate device outputs a low-level signal, and when signals input to the two input terminals of each nor gate device are both high-level signals, the output terminal of each nor gate device outputs a low-level signal.
The first MOS transistor M1 and the second MOS transistor M2 are both MOS transistors (Metal-Oxide-Semiconductor Field-Effect Transistor, metal-Oxide Semiconductor field effect transistors), and the MOS transistors include PMOS transistors (positive channel Metal Oxide Semiconductor ) and NMOS transistors (Negative channel Metal Oxide Semiconductor).
The first inverter F1, the first delay sub-circuit 21, the first nor gate unit 22, the second delay sub-circuit 31, and the second nor gate unit 32 are in a low voltage domain, and the first MOS transistor M1 and the second MOS transistor M2 are in a high voltage domain.
Specifically, in some embodiments, the first inverter F1 and the second inverter F2 are the same, the first delay sub-circuit 21 and the second delay sub-circuit 31 are the same, the first nor gate unit 22 and the second nor gate unit 32 are the same, the first resistor R1 and the second resistor R2 are the same, the first MOS transistor M1 and the second MOS transistor M2 are the same, and the first MOS transistor M1 and the second MOS transistor M2 are NMOS transistors.
Optionally, in some embodiments, the first inverter F1 is configured to invert the first signal to generate a second signal; the first delay sub-circuit 21 is configured to delay the second signal to generate a third signal; the first nor gate unit 22 is configured to generate a first initial narrow-wave signal according to the second signal and the third signal; the first MOS transistor M1 is configured to convert the first initial narrow-wave signal into the first narrow-wave signal; the second delay sub-circuit 31 is configured to delay the first signal to generate a fourth signal; the second nor gate unit 32 is configured to generate a second initial narrow-wave signal according to the first signal and the fourth signal; the second MOS transistor M2 is configured to convert the second initial narrow-wave signal into the second narrow-wave signal.
The second signal, the third signal, the fourth signal, the first initial narrow-wave signal, and the second initial narrow-wave signal are all signals in a low-voltage domain, and the first narrow-wave signal is a signal in a high-voltage domain.
The third signal is delayed from the second signal by a preset time period, and the fourth signal is delayed from the first signal by a preset time period.
Specifically, referring to fig. 4, the ordinate axis Y is the waveform of the signal, the abscissa axis T is the time, in some embodiments, the waveform Y1 is the waveform of the second signal, the waveform Y2 is the waveform of the third signal, the waveform Y3 is the waveform of the first initial narrow-wave signal, the waveform Y4 is the waveform of the first signal, the waveform Y5 is the waveform of the fourth signal, and the waveform Y6 is the waveform of the second initial narrow-wave signal.
The second signal is low when the first signal is high, and is high when the first signal is low; the first initial narrow-wave signal is low when the second signal is high and the third signal is low, the first initial narrow-wave signal is low when the second signal is low and the third signal is high, the first initial narrow-wave signal is low when both the second signal and the third signal are high, and the first initial narrow-wave signal is high when both the second signal and the third signal are low; the first initial narrow-wave signal is at a high level when the first initial narrow-wave signal is at a high level, and the first narrow-wave signal is at a low level when the first initial narrow-wave signal is at a low level.
The first initial narrow-wave signal is low when the first signal is high and the fourth signal is low, the second initial narrow-wave signal is low when the first signal is low and the fourth signal is high, the second initial narrow-wave signal is low when both the first signal and the fourth signal are high, and the second initial narrow-wave signal is high when both the first signal and the fourth signal are low; the second initial narrow-wave signal is at a high level when the second initial narrow-wave signal is at a high level, and the second narrow-wave signal is at a low level when the second initial narrow-wave signal is at a low level.
In the embodiment of the application, the first signal is inverted through the first inverter F1 to generate the second signal, the second signal is delayed through the first delay sub-circuit 21 to generate the third signal, then the first initial narrow-wave signal is generated through the first nor gate unit 22 according to the second signal and the third signal, and then the first initial narrow-wave signal is converted into the first narrow-wave signal through the first MOS transistor M1, so that the first signal in the low-voltage domain is converted into the first narrow-wave signal in the high-voltage domain; the first signal is delayed by the second delay sub-circuit 31 to generate a fourth signal, then a second initial narrow-wave signal is generated by the second nor gate unit 32 according to the first signal and the fourth signal, and then the second initial narrow-wave signal is converted into a second narrow-wave signal by the second MOS transistor M2, so as to convert the first signal in the low-voltage domain into the second narrow-wave signal in the high-voltage domain.
Optionally, referring to fig. 3, in some embodiments, the driving circuit of the insulated gate bipolar transistor 50 further includes a first power supply 60; the first delay sub-circuit 21 includes a third MOS transistor M3, a fourth MOS transistor M4, the first resistor R1, a first capacitor C1, a first schmitt trigger S1, and a second inverter F2; the output end of the first inverter F1 is electrically connected to the gate of the third MOS transistor M3 and the gate of the fourth MOS transistor M4, the drain of the third MOS transistor M3 is electrically connected to the first power supply 60, the source of the third MOS transistor M3 is electrically connected to the first end of the first resistor R1, the second end of the first resistor R1 is electrically connected to the drain of the fourth MOS transistor M4, and the source of the fourth MOS transistor M4 is grounded; the first end of the first capacitor C1 is electrically connected with the second end of the first resistor R1, and the second end of the first capacitor C1 is grounded; the second end of the first resistor R1 is electrically connected to the input end of the first schmitt trigger S1, the output end of the first schmitt trigger S1 is electrically connected to the input end of the second inverter F2, and the output end of the second inverter F2 is electrically connected to the second input end of the first nor gate unit 22.
In this embodiment of the present application, the third MOS transistor M3, the fourth MOS transistor M4, the first resistor R1, and the first capacitor C1 cooperate with the first schmitt trigger S1 to delay the second signal, generate an initial third signal, and the second inverter F2 is configured to invert the initial third signal to generate a third signal, where the third signal is a signal that is inverted from the initial third signal, the third signal is at a low level when the initial third signal is at a high level, and the third signal is at a high level when the initial third signal is at a low level.
Optionally, in some embodiments, the third MOS transistor M3 is a PMOS transistor, and the fourth MOS transistor M4 is an NMOS transistor.
In this embodiment of the present application, since the third MOS transistor M3 is a PMOS transistor, the fourth MOS transistor M4 is an NMOS transistor, the third MOS transistor M3 is turned off, the fourth MOS transistor M4 is turned on, and the third MOS transistor M3 is turned on, and the fourth MOS transistor M4 is turned off, when the second signal is at a low level.
The first schmitt trigger S1 is a schmitt trigger, and the schmitt trigger has a low voltage threshold and a high voltage threshold, wherein an absolute value of the low voltage threshold (which is a negative number) may be equal to an absolute value of the high voltage threshold (which is a positive number), and the absolute value of the low voltage threshold and the absolute value of the high voltage threshold are collectively referred to as a voltage threshold of the schmitt trigger. The schmitt trigger is used for outputting a high-level signal when the voltage of an input low-level signal is lower than a low-voltage threshold value, outputting a low-level signal when the voltage of the input high-level signal is higher than the high-voltage threshold value, performing waveform shaping on the input signal, and outputting a shaped square wave signal.
Specifically, in some embodiments, the initial third signal is delayed from the second signal by a length of timeThe expression (i.e., the length of time that the third signal is delayed from the second signal) is:
wherein,is the resistance value of the first resistor R1 (because the resistance value of the third MOS tube M3 and the resistance value of the fourth MOS tube M4 are far smaller than the resistance value of the resistor of the first resistor R1, the influence of the resistance value of the third MOS tube M3 and the resistance value of the fourth MOS tube M4 can be ignored), the resistance value is improved>For the capacitance value of the first capacitance C1, < >>For the voltage value of the first power supply 60, +.>Is the voltage threshold of the first schmitt trigger S1.
For example, when=0.5×/>When (I)>。
The first initial narrow-wave signal has a narrow-wave width equal to the length of time that the initial third signal is delayed from the second signalSince the initial third signal is delayed by a length of time of +.>Resistance value +.>Positive correlation, the narrow-wave width of the first initial narrow-wave signal is correlated with the resistance value of the first resistor R1>Positive correlation, and the narrow width of the first narrow signal is positively correlated with the narrow width of the first initial narrow signal, so that the narrow width of the first narrow signal is positively correlated with the resistance value of the first resistor R1Positive correlation.
Optionally, in some embodiments, the driving circuit of the insulated gate bipolar transistor 50 further includes a first power supply 60; the second delay sub-circuit 31 includes a fifth MOS transistor M5, a sixth MOS transistor M6, a second resistor R2, a second capacitor C2, a second schmitt trigger S2, and a third inverter F3;
The output end of the driving module 10 is electrically connected with the gate of the fifth MOS transistor M5 and the gate of the sixth MOS transistor M6, the drain of the fifth MOS transistor M5 is electrically connected with the first power supply 60, the source of the fifth MOS transistor M5 is electrically connected with the first end of the second resistor R2, the second end of the second resistor R2 is electrically connected with the drain of the sixth MOS transistor M6, and the source of the sixth MOS transistor M6 is grounded; the first end of the second capacitor C2 is electrically connected with the second end of the second resistor R2, and the second end of the second capacitor C2 is grounded;
the second end of the second resistor R2 is electrically connected to the input end of the second schmitt trigger S2, the output end of the second schmitt trigger S2 is electrically connected to the input end of the third inverter F3, and the output end of the third inverter F3 is electrically connected to the second input end of the second nor gate unit 32.
In this embodiment of the present application, the fifth MOS transistor M5, the sixth MOS transistor M6, the second resistor R2, the second capacitor C2, and the second schmitt trigger S2 cooperate to delay the first signal, generate an initial fourth signal, the second inverter F2 is configured to invert the initial fourth signal, generate a fourth signal, the fourth signal is a signal inverted from the initial fourth signal, the fourth signal is a low level when the initial fourth signal is a high level, and the fourth signal is a high level when the initial fourth signal is a low level.
Optionally, in some embodiments, the fifth MOS transistor M5 is a PMOS transistor, and the sixth MOS transistor M6 is an NMOS transistor.
In this embodiment of the present application, since the fifth MOS transistor M5 is a PMOS transistor and the sixth MOS transistor M6 is an NMOS transistor, the fifth MOS transistor M5 is turned off and the sixth MOS transistor M6 is turned on under the condition that the first signal is at a high level, and the fifth MOS transistor M5 is turned on and the sixth MOS transistor M6 is turned off under the condition that the first signal is at a low level.
The second schmitt trigger S2 is a schmitt trigger.
Specifically, in some embodiments, the initial fourth signal is delayed from the first signal by a length of timeThe expression (i.e., the length of time that the third signal is delayed from the second signal) is:
wherein,is the resistance value of the second resistor R2 (because the resistance value of the fifth MOS tube M5 and the resistance value of the sixth MOS tube M6 are far smaller than the resistance value of the resistance of the second resistor R2, the influence of the resistance value of the fifth MOS tube M5 and the resistance value of the sixth MOS tube M6 can be ignored), the resistance value is improved>Is the capacitance value of the second capacitor C2, < >>Is the voltage value of the second power supply 70, +.>Is the voltage threshold of the second schmitt trigger S2.
The narrow wave width of the second initial narrow wave signal is equal to the time length of the delay of the initial fourth signal compared with the first signal Since the fourth signal is delayed by a length of time which is +.>Resistance value +.>Positive correlation, the narrow-wave width of the second initial narrow-wave signal and the resistance value of the second resistor R2>Positive correlation, and the narrow-wave width of the second narrow-wave signal is positive-correlated with the narrow-wave width of the second initial narrow-wave signal, therefore, the narrow-wave width of the second narrow-wave signal is positive-correlated with the resistance value of the second resistor R2>Positive correlation.
Optionally, in some embodiments, the first nor gate unit 22 includes a first nor gate element H1, a fourth inverter F4, and a fifth inverter F5; the second nor gate unit 32 includes a second nor gate element H2, a sixth inverter F6, and a seventh inverter F7;
a first input end of the first nor gate element H1 is electrically connected to an output end of the first inverter F1, a second input end of the first nor gate element H1 is electrically connected to an output end of the first delay sub-circuit 21, an output end of the first nor gate element H1 is electrically connected to an input end of the fourth inverter F4, an output end of the fourth inverter F4 is electrically connected to an input end of the fifth inverter F5, and an output end of the fifth inverter F5 is electrically connected to a gate of the first MOS transistor M1;
The first input end of the second nor gate element H2 is electrically connected to the output end of the driving module 10, the second input end of the second nor gate element H2 is electrically connected to the output end of the second delay sub-circuit 31, the output end of the second nor gate element H2 is electrically connected to the input end of the sixth inverter F6, the output end of the sixth inverter F6 is electrically connected to the input end of the seventh inverter F7, and the output end of the seventh inverter F7 is electrically connected to the gate of the second MOS transistor M2.
In this embodiment of the present application, the first nor gate element H1 is configured to generate a first output signal according to the second signal and the third signal, the fourth inverter F4 and the fifth inverter F5 have a signal waveform shaping effect, the fourth inverter F4 is configured to invert the first output signal to generate a second output signal, and the fifth inverter F5 is configured to invert the second output signal to generate a first initial narrow-wave signal. When the first output signal is at a high level, the second output signal is at a low level, when the first output signal is at a low level, the second output signal is at a high level, when the second output signal is at a high level, the first initial narrow-wave signal is at a low level, and when the second output signal is at a low level, the first initial narrow-wave signal is at a high level.
The second nor gate element H2 is configured to generate a third output signal according to the first signal and the fourth signal, the sixth inverter F6 and the seventh inverter F7 have signal waveform shaping effects, the sixth inverter F6 is configured to invert the third output signal to generate a fourth output signal, and the seventh inverter F7 is configured to invert the fourth output signal to generate a second initial narrow-wave signal. When the third output signal is at a high level, the fourth output signal is at a low level, when the third output signal is at a low level, the fourth output signal is at a high level, when the fourth output signal is at a high level, the second initial narrow-wave signal is at a low level, and when the fourth output signal is at a low level, the second initial narrow-wave signal is at a high level.
Optionally, referring to fig. 3, in some embodiments, the driving circuit of the insulated gate bipolar transistor 50 further includes a second power supply 70; the first narrow-wave circuit 20 further includes a third resistor R3, and the second narrow-wave circuit 30 further includes a fourth resistor R4; the second power supply 70 is electrically connected with the first end of the third resistor R3, the second end of the third resistor R3 is connected with the drain electrode of the first MOS transistor M1, and the source electrode of the first MOS transistor M1 is grounded; the second power supply 70 is electrically connected to the first end of the fourth resistor R4, the second end of the fourth resistor R4 is connected to the drain of the second MOS transistor M2, and the source of the second MOS transistor M2 is grounded.
In this embodiment, the third resistor R3 is a current limiting resistor, the fourth resistor R4 is a current limiting resistor, and the second power supply 70 is configured to supply power to the first MOS transistor M1 and the second MOS transistor M2.
Specifically, in some embodiments, the resistance value of the third resistor R3 is the same as the resistance value of the fourth resistor R4.
When the first MOS tube is started, the current passing through the first MOS tube isWherein, the method comprises the steps of, wherein,pulse current for the first narrow-wave signal, +.>The voltage value of the second power supply is R is the resistance value of the third resistor; similarly, the current passing through the first MOS transistor is calculated in a similar manner to that described above, and will not be described here again.
Because the narrow wave width of the first narrow wave signal provided by the embodiment of the application is stable, the current of the first narrow wave signalThe current passing through the first MOS tube is more stable>The power consumption (positively correlated with the current) of the first MOS transistor is thus more stable. When the narrow wave width of the first narrow wave signal provided by the embodiment of the application is smaller, the power consumption of the first MOS tube is smaller; similarly, the power consumption analysis of the second MOS transistor is similar to the above, and will not be repeated here.
Optionally, referring to fig. 3, in some embodiments, the first MOS transistor M1 is an NMOS transistor, the second MOS transistor M2 is an NMOS transistor, the first narrow-wave circuit 20 further includes a first diode D1, and the second narrow-wave circuit 30 further includes a second diode D2; the positive electrode of the first diode D1 is electrically connected with the drain electrode of the first MOS transistor M1, and the negative electrode of the first diode D1 is electrically connected with the second power supply 70; the anode of the second diode D2 is electrically connected to the drain of the second MOS transistor M2, and the cathode of the second diode D2 is electrically connected to the second power supply 70.
In this embodiment of the present application, since the first MOS transistor M1 is an NMOS transistor, the first MOS transistor M1 is turned on when the first initial narrow-wave signal is at a high level, and the first MOS transistor M1 is turned off when the first initial narrow-wave signal is at a low level. Because the second MOS transistor M2 is an NMOS transistor, the second MOS transistor M2 is turned on when the second initial narrow-wave signal is at a high level, and the second MOS transistor M2 is turned off when the second initial narrow-wave signal is at a low level. The first diode D1 and the second diode D2 are used to reduce the possibility of the voltage spike breakdown of the combining module 40.
Optionally, referring to fig. 3, in some embodiments, the driving module 10 includes a driving chip 11, an eighth inverter F8; the output end of the driving chip 11 is connected to the input end of the eighth inverter F8, and the output end of the eighth inverter F8 is electrically connected to the input end of the first narrow-wave circuit 20 and the input end of the second narrow-wave circuit 30, respectively.
In this embodiment of the present application, the driving chip 11 is configured to generate an initial first signal in response to a control instruction, the eighth inverter F8 has a waveform shaping function of a signal, and the eighth inverter F8 is configured to invert the initial first signal to generate a first signal, where the first signal is low when the initial first signal is high, and the first signal is high when the initial first signal is low.
In summary, in this embodiment of the present application, the driving module is configured to generate the first signal in response to the control instruction, then generate the first narrow-wave signal according to the first signal by using the first narrow-wave circuit, and generate the second narrow-wave signal according to the first signal by using the second narrow-wave circuit, and then synthesize the first narrow-wave signal and the second narrow-wave signal into the control signal by using the synthesizing module, so that the insulated gate bipolar transistor is turned on or off in response to the control signal, so as to control the on or off of the insulated gate bipolar transistor, and a level transfer chip is not required to be added, thereby reducing the cost, and solving the problem in the prior art that the level transfer chip is required to be added to convert the low-voltage domain control signal output by the driving chip into the high-voltage domain control signal suitable for the high-voltage domain where the insulated gate bipolar transistor is located, so as to control the on or off of the insulated gate bipolar transistor.
In addition, since the narrow width of the first narrow signal is positively correlated with the resistance value of the first resistor of the zero temperature coefficient and the narrow width of the second narrow signal is positively correlated with the resistance value of the second resistor of the zero temperature coefficient, and the resistance value of the first resistor of the zero temperature coefficient and the resistance value of the second resistor of the zero temperature coefficient are less varied with temperature than the normal resistor, so that the narrow width of the first narrow signal and the narrow width of the second narrow signal are less varied with temperature, it is possible to improve the stability of the narrow width of the first narrow signal and the stability of the narrow width of the second narrow signal, and further improve the stability of the control signal synthesized by the first narrow signal and the second narrow signal, to improve the stability of the drive of the insulated gate bipolar transistor by the control signal.
Fig. 2 is a flowchart of steps of a driving method of an insulated gate bipolar transistor according to an embodiment of the present application, as shown in fig. 1, the method may include:
step 101, responding to a control instruction, and generating a first signal.
In the embodiment of the application, the first signal is generated in response to the control instruction, and then the first narrow-wave signal is generated according to the first signal, and the second narrow-wave signal is generated according to the first signal.
Step 102, generating a first narrow-wave signal according to the first signal, and generating a second narrow-wave signal according to the first signal.
In the embodiment of the application, the first narrow-wave signal is generated according to the first signal, the second narrow-wave signal is generated according to the first signal, and the first narrow-wave signal and the second narrow-wave signal are further synthesized into the control signal.
Step 103, synthesizing the first narrow-wave signal and the second narrow-wave signal into a control signal.
In the embodiment of the application, the first narrow-wave signal and the second narrow-wave signal are synthesized into the control signal, so that the insulated gate bipolar transistor is controlled to be turned on or off in response to the control signal.
Step 104, in response to the control signal, the insulated gate bipolar transistor is controlled to be turned on or off.
The narrow wave width of the first narrow wave signal is controlled through a first resistor with a zero temperature coefficient, and the narrow wave width of the second narrow wave signal is controlled through a second resistor with a zero temperature coefficient; the narrow wave width of the first narrow wave signal is positively correlated with the resistance value of the first resistor, and the narrow wave width of the second narrow wave signal is positively correlated with the resistance value of the second resistor.
In the embodiment of the application, the drive control of the insulated gate bipolar transistor is realized by controlling the insulated gate bipolar transistor to be turned on or off in response to the control signal.
The specific implementation process of the driving method of the insulated gate bipolar transistor is similar to that described above, and will not be repeated here.
In the embodiment of the application, the first signal is generated by responding to the control instruction, the first narrow-wave signal is generated according to the first signal, the second narrow-wave signal is generated according to the first signal, the first narrow-wave signal and the second narrow-wave signal are synthesized into the control signal, and then the turn-on or turn-off of the insulated gate bipolar transistor is controlled by responding to the control signal, so that the turn-on and turn-off of the insulated gate bipolar transistor are controlled, a level transfer chip is not needed to be added, the cost is reduced, and the problem that the cost is increased because the low-voltage domain control signal output by the driving chip is converted into the high-voltage domain control signal suitable for the high-voltage domain where the insulated gate bipolar transistor is located by the level transfer chip in the prior art is solved, so that the turn-on and turn-off of the insulated gate bipolar transistor are controlled, and the level transfer chip is needed to be added.
In addition, since the narrow width of the first narrow signal is positively correlated with the resistance value of the first resistor of the zero temperature coefficient and the narrow width of the second narrow signal is positively correlated with the resistance value of the second resistor of the zero temperature coefficient, and the resistance value of the first resistor of the zero temperature coefficient and the resistance value of the second resistor of the zero temperature coefficient are less varied with temperature than the normal resistor, so that the narrow width of the first narrow signal and the narrow width of the second narrow signal are less varied with temperature, it is possible to improve the stability of the narrow width of the first narrow signal and the stability of the narrow width of the second narrow signal, and further improve the stability of the control signal synthesized by the first narrow signal and the second narrow signal, to improve the stability of the drive of the insulated gate bipolar transistor by the control signal.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. Furthermore, it should be noted that the scope of the methods and apparatus in the embodiments of the present application is not limited to performing the functions in the order shown or discussed, but may also include performing the functions in a substantially simultaneous manner or in an opposite order depending on the functions involved, e.g., the described methods may be performed in an order different from that described, and various steps may also be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.
The embodiments of the present application have been described above with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those of ordinary skill in the art without departing from the spirit of the present application and the scope of the claims, which are also within the protection of the present application.
Claims (12)
1. A drive circuit of an insulated gate bipolar transistor, comprising: the device comprises a driving module, a first narrow-wave circuit, a second narrow-wave circuit, a synthesis module and an insulated gate bipolar transistor; the driving module is respectively and electrically connected with the first narrow-wave circuit and the second narrow-wave circuit, and the synthesizing module is respectively and electrically connected with the first narrow-wave circuit, the second narrow-wave circuit and the insulated gate bipolar transistor;
the driving module is used for responding to the control instruction and generating a first signal; the first narrow-wave circuit is used for generating a first narrow-wave signal according to the first signal; the second narrow wave circuit is used for generating a second narrow wave signal according to the first signal; the synthesis module is used for synthesizing the first narrow-wave signal and the second narrow-wave signal into control signals; the insulated gate bipolar transistor is used for being turned on or turned off in response to the control signal;
Wherein the first narrow wave circuit comprises a first resistor with a zero temperature coefficient, and the second narrow wave circuit comprises a second resistor with a zero temperature coefficient; the narrow wave width of the first narrow wave signal is positively correlated with the resistance value of the first resistor, and the narrow wave width of the second narrow wave signal is positively correlated with the resistance value of the second resistor.
2. The drive circuit of an insulated gate bipolar transistor according to claim 1, wherein the first narrow-wave circuit comprises a first inverter, a first delay sub-circuit, a first nor gate unit and a first MOS transistor, and the second narrow-wave circuit comprises a second delay sub-circuit, a second nor gate unit and a second MOS transistor; wherein the first delay sub-circuit comprises the first resistor and the second delay sub-circuit comprises the second resistor;
the output end of the driving module is electrically connected with the input end of the first inverter, the input end of the second delay sub-circuit and the first input end of the second NOR gate unit respectively, the output end of the first inverter is electrically connected with the input end of the first delay sub-circuit and the first input end of the first NOR gate unit respectively, the output end of the first delay sub-circuit is electrically connected with the second input end of the first NOR gate unit, and the output end of the first NOR gate unit is electrically connected with the grid electrode of the first MOS tube;
The output end of the second delay subcircuit is electrically connected with the second input end of the second NOR gate unit, and the output end of the second NOR gate unit is electrically connected with the grid electrode of the second MOS tube; the first input end of the synthesis module is electrically connected with the drain electrode of the first MOS tube, the second input end of the synthesis module is electrically connected with the drain electrode of the second MOS tube, and the output end of the synthesis module is electrically connected with the grid electrode of the insulated gate bipolar transistor.
3. The drive circuit of an insulated gate bipolar transistor according to claim 2, wherein the first inverter is configured to invert the first signal to generate a second signal; the first delay sub-circuit is used for delaying the second signal to generate a third signal; the first NOR gate unit is used for generating a first initial narrow wave signal according to the second signal and the third signal; the first MOS tube is used for converting the first initial narrow-wave signal into the first narrow-wave signal;
the second delay sub-circuit is used for delaying the first signal to generate a fourth signal; the second NOR gate unit is used for generating a second initial narrow wave signal according to the first signal and the fourth signal; the second MOS tube is used for converting the second initial narrow-wave signal into the second narrow-wave signal.
4. The drive circuit of an insulated gate bipolar transistor according to claim 2, wherein the drive circuit of an insulated gate bipolar transistor further comprises a first power supply; the first delay subcircuit comprises a third MOS tube, a fourth MOS tube, the first resistor, a first capacitor, a first Schmidt trigger and a second inverter;
the output end of the first inverter is electrically connected with the grid electrode of the third MOS tube and the grid electrode of the fourth MOS tube respectively, the drain electrode of the third MOS tube is electrically connected with the first power supply, the source electrode of the third MOS tube is electrically connected with the first end of the first resistor, the second end of the first resistor is electrically connected with the drain electrode of the fourth MOS tube, and the source electrode of the fourth MOS tube is grounded; a first end of the first capacitor is electrically connected with a second end of the first resistor, and a second end of the first capacitor is grounded;
the second end of the first resistor is electrically connected with the input end of the first schmitt trigger, the output end of the first schmitt trigger is electrically connected with the input end of the second inverter, and the output end of the second inverter is electrically connected with the second input end of the first nor gate unit.
5. The drive circuit of an insulated gate bipolar transistor according to claim 4, wherein the third MOS transistor is a PMOS transistor and the fourth MOS transistor is an NMOS transistor.
6. The drive circuit of an insulated gate bipolar transistor according to claim 2, wherein the drive circuit of an insulated gate bipolar transistor further comprises a first power supply; the second delay subcircuit comprises a fifth MOS tube, a sixth MOS tube, a second resistor, a second capacitor, a second Schmitt trigger and a third inverter;
the output end of the driving module is electrically connected with the grid electrode of the fifth MOS tube and the grid electrode of the sixth MOS tube respectively, the drain electrode of the fifth MOS tube is electrically connected with the first power supply, the source electrode of the fifth MOS tube is electrically connected with the first end of the second resistor, the second end of the second resistor is electrically connected with the drain electrode of the sixth MOS tube, and the source electrode of the sixth MOS tube is grounded; the first end of the second capacitor is electrically connected with the second end of the second resistor, and the second end of the second capacitor is grounded;
the second end of the second resistor is electrically connected with the input end of the second schmitt trigger, the output end of the second schmitt trigger is electrically connected with the input end of the third inverter, and the output end of the third inverter is electrically connected with the second input end of the second nor gate unit.
7. The drive circuit of an insulated gate bipolar transistor according to claim 6, wherein the fifth MOS transistor is a PMOS transistor and the sixth MOS transistor is an NMOS transistor.
8. The drive circuit of an insulated gate bipolar transistor according to claim 2, wherein the first nor gate unit includes a first nor gate element, a fourth inverter, and a fifth inverter; the second NOR gate unit comprises a second NOR gate element, a sixth inverter and a seventh inverter;
the first input end of the first NOR gate element is electrically connected with the output end of the first inverter, the second input end of the first NOR gate element is electrically connected with the output end of the first delay subcircuit, the output end of the first NOR gate element is electrically connected with the input end of the fourth inverter, the output end of the fourth inverter is electrically connected with the input end of the fifth inverter, and the output end of the fifth inverter is electrically connected with the grid electrode of the first MOS tube;
the first input end of the second nor gate element is electrically connected with the output end of the driving module, the second input end of the second nor gate element is electrically connected with the output end of the second delay sub-circuit, the output end of the second nor gate element is electrically connected with the input end of the sixth inverter, the output end of the sixth inverter is electrically connected with the input end of the seventh inverter, and the output end of the seventh inverter is electrically connected with the grid electrode of the second MOS tube.
9. The drive circuit of an insulated gate bipolar transistor according to claim 2, wherein the drive circuit of an insulated gate bipolar transistor further comprises a second power supply; the first narrow-wave circuit further comprises a third resistor, and the second narrow-wave circuit further comprises a fourth resistor;
the second power supply is electrically connected with the first end of the third resistor, the second end of the third resistor is connected with the drain electrode of the first MOS tube, and the source electrode of the first MOS tube is grounded;
the second power supply is electrically connected with the first end of the fourth resistor, the second end of the fourth resistor is electrically connected with the drain electrode of the second MOS tube, and the source electrode of the second MOS tube is grounded.
10. The drive circuit of an insulated gate bipolar transistor according to claim 9, wherein the first MOS transistor is an NMOS transistor, the second MOS transistor is an NMOS transistor, the first narrow-wave circuit further comprises a first diode, and the second narrow-wave circuit further comprises a second diode;
the anode of the first diode is electrically connected with the drain electrode of the first MOS tube, and the cathode of the first diode is electrically connected with the second power supply;
the anode of the second diode is electrically connected with the drain electrode of the second MOS tube, and the cathode of the second diode is electrically connected with the second power supply.
11. The drive circuit of an insulated gate bipolar transistor according to claim 1, wherein the drive module comprises a drive chip, an eighth inverter;
the output end of the driving chip is connected with the input end of the eighth inverter, and the output end of the eighth inverter is electrically connected with the input end of the first narrow-wave circuit and the input end of the second narrow-wave circuit respectively.
12. A method of driving an insulated gate bipolar transistor, the method comprising:
generating a first signal in response to a control instruction;
generating a first narrow-wave signal according to the first signal, and generating a second narrow-wave signal according to the first signal;
synthesizing the first narrow-wave signal and the second narrow-wave signal into control signals;
in response to the control signal, controlling the insulated gate bipolar transistor to be turned on or off;
the narrow wave width of the first narrow wave signal is controlled through a first resistor with a zero temperature coefficient, and the narrow wave width of the second narrow wave signal is controlled through a second resistor with a zero temperature coefficient; the narrow wave width of the first narrow wave signal is positively correlated with the resistance value of the first resistor, and the narrow wave width of the second narrow wave signal is positively correlated with the resistance value of the second resistor.
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