CN117526683A - High-voltage direct-current converter system and synchronous start-stop fault processing method - Google Patents
High-voltage direct-current converter system and synchronous start-stop fault processing method Download PDFInfo
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- CN117526683A CN117526683A CN202410005081.8A CN202410005081A CN117526683A CN 117526683 A CN117526683 A CN 117526683A CN 202410005081 A CN202410005081 A CN 202410005081A CN 117526683 A CN117526683 A CN 117526683A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
- H02M1/007—Plural converter units in cascade
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
- G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J1/00—Circuit arrangements for dc mains or dc distribution networks
- H02J1/10—Parallel operation of dc sources
- H02J1/102—Parallel operation of dc sources being switching converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
- H02M1/0074—Plural converter units whose inputs are connected in series
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/36—Means for starting or stopping converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/60—Arrangements for transfer of electric power between AC networks or generators via a high voltage DC link [HVCD]
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Abstract
The invention provides a high-voltage direct-current converter system and a synchronous start-stop fault processing method, wherein a single cascading power conversion module comprises a second processor, a first communication circuit, a second communication circuit, a hardware bus component, a power processing component and a second memory; the main control module comprises a first processor, a third communication circuit, a fourth communication circuit, a first memory and a fifth communication circuit; the first communication circuit in the power conversion module is connected with the hardware synchronous bus; the second communication circuit in the power conversion module is connected with the internal communication bus; the third communication circuit in the main control module is connected with the hardware synchronous bus; the fourth communication circuit in the main control module is connected with the internal communication bus; the fifth communication circuit in the main control module is connected with an external communication bus. The invention enables the synchronous start and stop of each level of power conversion module, realizes fault protection, and has higher real-time performance and high reliability.
Description
Technical Field
The invention belongs to the technical field of high-voltage direct-current converter systems, and particularly relates to a high-voltage direct-current converter system and a synchronous start-stop fault processing method.
Background
At present, ocean resources have huge development potential and research value, and ocean resource development is an emerging field with profound significance. The submarine observation network has become one of the important approaches of the ocean research in the 21 st century, the submarine power supply system is a key related to the submarine observation network, and the submarine high-voltage direct-current converter is used as a key device in the submarine observation network, and can convert a shore-based high-voltage power supply into hundreds of medium-voltage direct currents required by a submarine observation platform by transmitting high-voltage direct currents of more than kilovolts through a submarine cable of hundreds of kilometers. There are two possible implementations of current subsea-powered high-voltage high-frequency converters, namely multi-power tube series (single-stage topology) and cascaded power conversion module converters (ISOPs). The modular converter has the advantages of redundant operation capability, standard modular operation, flexibility of power expansion and the like. The load influence of large LRC parasitic parameters and large dynamic change characteristics of the submarine remote power transmission submarine cable is considered, and the submarine remote power transmission submarine cable runs reliably for a long time, so that the stability, the real-time response speed and the reliability of the module power converter are required to be improved.
The ISOP system can enable the switching tube with lower rated voltage to be applied to high-input voltage and low-output voltage and high-current occasions. The input side equalizing and the output side equalizing are guaranteed to be the most basic operation requirements of the stable working system. Not only is stable operation required to ensure the voltage equalizing of the input sides of all modules, but also the voltage equalizing or instant shutdown between all modules is required to realize protection when the machine is started, stopped and fails.
The start-up and stop of the modules in the ISOP system are asynchronous, and the system can be caused to be faulty. 1) If the delay exists in the starting between the modules, the voltage of the input side is not balanced, and if the voltage is severe, the voltage-sharing loop between the modules oscillates and even exceeds the safe working interval of the device, so that irreversible faults occur; 2) The inter-module shutdown has larger delay (the module blocks PWM signals to realize shutdown), the impedance of the input side of the module which is stopped first is far greater than that of other modules, the input voltage partial pressure of the module is far greater than that of other modules, so that the power device in the module bears larger voltage and even exceeds the safe working interval of the module, and irreversible faults occur.
In addition, a single module in the ISOP system has short circuit fault on the input side or the output side, so that the module has uneven voltage or uneven current. If the single module in the ISOP system triggers fault protection (PWM signal is blocked or the input bypass switch is opened), the protection signal can not be timely sent to all modules to block the PWM signal to realize synchronous shutdown, the input current of the failed module rapidly rises and exceeds the safe working threshold of the device, and the whole system causes permanent faults when serious.
The prior synchronous start-stop or fault processing method generally adopts a communication bus or a plurality of parallel start-stop control lines. For example, the CAN communication bus CAN support long-distance transmission (communication speed and distance are in negative correlation), and the reliability of transmission data is high. However, the transmission of the CAN communication bus needs to be carried out according to a special protocol, and the one-to-many transmission speed cannot reach the response of a rapid ns level, so that the CAN communication bus does not have the characteristic of rapid synchronous start and stop of transmission. In addition, the functions of quick start-up and shutdown and fault protection can be realized by a plurality of parallel control lines, but the wiring is complex (the control lines with the same number as the modules are required to be configured), and the method or the technology of the parallel control lines is difficult to apply in the field in consideration of the environment of high isolation and voltage resistance, limited space and strong electromagnetic interference of the high-voltage direct-current converter.
Disclosure of Invention
The embodiment of the invention provides a high-voltage direct-current converter system, which aims to solve the problems that in the prior art, each module of a cascade power conversion module (ISOP input serial output parallel connection type) high-voltage direct-current converter is poor in protection synchronism and instantaneity during start-up and shutdown and faults, and the reliability of the existing bus control technology method is poor, so that each module is input with no voltage equalizing or overshoot current occurs, overvoltage breakdown occurs on power MOS (metal oxide semiconductor) tubes in the module, breakdown of all modules is more serious, and finally the whole high-voltage direct-current converter system breaks down.
In a first aspect, an embodiment of the present invention provides a hvdc converter system including: the device comprises a hardware synchronous bus, an external communication bus, an internal communication bus, a main control module and a plurality of cascade power conversion modules; each power conversion module is connected in a mode of input series connection and output parallel connection;
the single power conversion module comprises a second processor, a first communication circuit, a second communication circuit, a hardware bus component, a power processing component and a second memory; the second processor is respectively connected with the first communication circuit, the second communication circuit, the hardware bus component, the power processing component and the second memory; the first communication circuit is connected with the hardware synchronous bus; the second communication circuit is connected with the internal communication bus;
The main control module comprises a first processor, a third communication circuit, a fourth communication circuit, a first memory and a fifth communication circuit; the first processor is respectively connected with the third communication circuit, the fourth communication circuit, the first memory and the fifth communication circuit; the third communication circuit is connected with the hardware synchronous bus; the fourth communication circuit is connected with the internal communication bus; the fifth communication circuit is connected with the external communication bus;
the first processor is configured to: after the high-voltage input power supply voltage is established, a bus reset signal is sent to a hardware synchronous bus through a third communication circuit, and delay processing is carried out; sending a start command to an internal communication bus through a fourth communication circuit; transmitting a start pulse or a stop signal to the hardware synchronous bus through a third communication circuit;
each second processor is configured to: starting timing after receiving a start command of an internal communication bus through a second communication circuit; judging whether a pulse signal sent by a third communication circuit to a hardware synchronous bus is received or not in the timing time, and controlling a corresponding power conversion module to synchronously start up at the moment of the falling edge of the pulse signal to output a medium-voltage power supply; and when a fault signal or a shutdown signal sent by the hardware synchronous bus is received, controlling all the power conversion modules working to synchronously shutdown so as to shut down the medium-voltage power supply.
Further, the HVDC converter system also comprises an upper computer terminal; the upper computer terminal is connected with the main control module through the external communication bus and is used for configuring the working mode of the high-voltage direct-current converter system, sending a start-stop control command and monitoring the running state of the high-voltage direct-current converter system; and the external communication bus is used for uploading the internal data and the state of the high-voltage direct-current converter system to an upper computer terminal.
Further, the third communication circuit in the main control module is connected with the first communication circuit in the power conversion module through the hardware synchronous bus, and is used for sending the start-stop signal and the fault signal of the main control module to a plurality of cascaded power conversion modules;
the fourth communication circuit in the main control module is connected with the second communication circuit in the power conversion module through the internal communication bus and is used for the main control module to issue control instructions and inquire the internal operation state and working data of the cascade power conversion module.
Further, the first communication circuit is configured to output a pulse signal or a level signal of the hardware synchronization bus to the second processor, so as to send an on/off command or a fault protection signal;
The second communication circuit is used for uploading the running state and running data of the power conversion module and the fault information of the second memory;
the hardware bus component is used for enabling or resetting a hardware synchronous bus signal; the second memory is used for storing the internal parameters of the power conversion module and fault information of the power conversion module.
Further, the first memory is used for storing internal fault information or configuration parameters of the main control module.
In a second aspect, an embodiment of the present invention provides a synchronous start-stop fault processing method, where the synchronous start-stop fault processing method is applied to the hvdc converter system, and the method includes:
after the high-voltage input power supply voltage is established, a first processor in the main control module sends a bus reset signal to the hardware synchronous bus through a third communication circuit and performs delay processing;
a first processor in the main control module sends a start instruction to an internal communication bus through a fourth communication circuit;
after receiving a start command of the internal communication bus through a second communication circuit, a second processor in the power conversion module starts timing;
judging whether pulse signals sent to the hardware synchronous bus by the main control module through the third communication circuit are received by a second processor in all the power conversion modules in a timing time, and synchronously starting all the power conversion modules in normal states at the time of descending delay of the pulse signals to output a medium-voltage power supply;
When the second processor in all the power conversion modules receives the hardware synchronous bus fault or shutdown signal, controlling all the power conversion modules working to synchronously shutdown, and simultaneously storing the fault signal in a second memory;
the main control module receives the fault or stop signal of the hardware synchronous bus, stores the fault signal triggered by the main control module in the first memory, reads the fault information of all power conversion modules through the internal communication bus, and stores the fault information of all power conversion modules in the first memory.
Further, the second processor in all the power conversion modules judges whether a pulse signal sent by the main control module to the hardware synchronous bus through the third communication circuit is received in a timing time, and when the pulse signal drops and delays, all the power conversion modules in normal states synchronously start up, and the step of outputting the medium-voltage power supply comprises the following steps:
the second processors in all the power conversion modules judge whether the received hardware synchronous bus pulse signals exceed the timing time or not;
if not, the first processor in the main control module sends a pulse signal to the hardware synchronous bus through the third communication circuit;
And the second processors in all the working power conversion modules synchronously start up at the moment of receiving the falling edge of the pulse signal, and output a medium-voltage power supply.
Further, when the second processor in the all power conversion modules receives the hardware synchronous bus fault or shutdown signal, the step of controlling all power conversion modules working to synchronously shutdown and simultaneously storing the fault signal in the second memory includes:
the second processor in each power conversion module judges whether the hardware synchronous bus fault or shutdown signal is received;
when the hardware synchronous bus fault or shutdown signal is received, each second processor judges whether each power conversion module operates normally or not;
if not, synchronously stopping all the power conversion modules which are working, and storing fault signals in a second memory.
Further, the method further comprises:
the main control module uploads fault information in the first memory and the second memory to an upper computer terminal through an external communication bus;
the upper computer terminal sets the working mode of the high-voltage direct-current converter system as a debugging mode;
Under the condition that the HVDC converter system is configured into a debugging mode, the upper computer terminal sends a start command to the main control module through the fifth communication circuit;
and under the condition that the HVDC converter system is configured to be in a non-debugging mode, the upper computer terminal sends a shutdown command to the main control module through the fifth communication circuit.
The invention has the beneficial effects that: in the invention, a bus is adopted to realize a method for realizing time-sharing transmission pulse and level to realize start-stop fault protection, and a first processor is used for: after the high-voltage input power supply voltage is established, a bus reset signal is sent to a hardware synchronous bus through a third communication circuit, and delay processing is carried out; sending a start command to an internal communication bus through a fourth communication circuit; each second processor is configured to: starting timing after receiving a start command of an internal communication bus through a second communication circuit; judging whether a pulse signal sent by a third communication circuit to a hardware synchronous bus is received or not in the timing time, and controlling a corresponding power conversion module to synchronously start up at the moment of the falling edge of the pulse signal to output a medium-voltage power supply; when a fault signal or a shutdown signal sent by a hardware synchronous bus is received, controlling all the power conversion modules working synchronously to shutdown; the bus transmission speed is high, so that the synchronism of all cascaded power conversion modules is high; the bus structure is simplified, and the bus is convenient to carry out isolation transmission; the method has the advantages that the method combines the hardware synchronous bus with the internal communication bus, and the effects of quick and reliable start-up and fault protection are realized by utilizing the characteristic of quick transmission of the hardware synchronous bus and the characteristic of reliable transmission data of the internal communication bus, so that the situation that the cascade power conversion module is not balanced in the transient start-up and fault protection process is avoided; the bus in the form of another differential twisted pair is also adopted, so that the redundant application is easy, and the reliability of the whole machine is improved. The invention not only realizes higher real-time performance of synchronous start-stop and fault protection of each cascade power conversion module, but also rapidly stores and restores fault information into a fault real state, and simultaneously meets the requirements of high isolation voltage resistance, high anti-interference performance and high reliability.
Drawings
Fig. 1 is a schematic structural diagram of a hvdc converter system according to an embodiment of the present invention;
FIG. 2 is a flowchart of a synchronous start-stop fault handling method provided by an embodiment of the present invention;
FIG. 3 is a timing chart of a synchronous start-stop fault handling method according to an embodiment of the present invention when a power-on is started;
FIG. 4 is a timing chart of a synchronous start-stop fault handling method provided by an embodiment of the present invention when a start-up is unsuccessful;
FIG. 5 is a timing diagram of a synchronous start-stop fault handling method provided by an embodiment of the present invention at shutdown;
fig. 6 is a schematic structural diagram of another hvdc converter system according to an embodiment of the present invention;
fig. 7 is an interactive flowchart of a synchronous start-stop fault handling method according to an embodiment of the present invention.
Wherein, 100, the HVDC converter system; 110. a power conversion module; 120. a main control module; 131. a hardware synchronization bus; 132. an internal communication bus; 133. an external communication bus; 111. a second processor; 112. a first communication circuit; 113. a second communication circuit; 114. a hardware bus component; 115. a power processing component; 116. a second memory; 121. a first processor; 122. a third communication circuit; 123. a fourth communication circuit; 124. a first memory; 125. a fifth communication circuit; 000. and the upper computer terminal.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the prior art, because each module in the cascade module (ISOP input series output parallel type) high-voltage direct-current converter in the prior art has poor synchronization of start-up and shutdown and fault protection, poor real-time performance and poor reliability of the prior bus control technical method, the input of each module is uneven or overshoot current occurs, overvoltage breakdown occurs on power MOS tubes in the modules, more serious breakdown even all modules occurs, and finally the whole high-voltage direct-current converter system breaks down and the like.
In the present invention, the first processor is configured to: after the high-voltage input power supply voltage is established, a bus reset signal is sent to a hardware synchronous bus through a third communication circuit, and delay processing is carried out; sending a start command to an internal communication bus through a fourth communication circuit; each second processor is configured to: starting timing after receiving a start command of an internal communication bus through a second communication circuit; judging whether a pulse signal sent by a third communication circuit to a hardware synchronous bus is received or not in the timing time, and controlling a corresponding power conversion module to synchronously start up at the moment of the falling edge of the pulse signal to output a medium-voltage power supply; when a fault signal or a shutdown signal sent by a hardware synchronous bus is received, controlling all the power conversion modules working synchronously to shutdown; the third communication circuit in the main control module is connected with the first communication circuit in the power conversion module through a hardware synchronous bus and is used for sending a start-stop signal and a fault signal of the main control module to a plurality of cascade power conversion modules; the fourth communication circuit in the main control module is connected with the second communication circuit in the power conversion module through an internal communication bus and is used for the main control module to issue control instructions and inquire the internal operation state and working data of the cascade power conversion module; the upper computer terminal is connected with the main control module through an external communication bus and is used for configuring the working mode of the high-voltage direct-current converter system, sending a start-stop control command and monitoring the running state of the high-voltage direct-current converter system. The invention not only realizes higher real-time performance of synchronous start-stop and fault protection of each cascade power conversion module and fast stores and restores fault information to the real fault state, but also meets the requirements of high isolation voltage resistance, high anti-interference performance and high reliability.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a hvdc converter system according to an embodiment of the present invention. The hvdc converter system 100 includes: a hardware synchronous bus 131, an external communication bus 133, an internal communication bus 132, a main control module 120 and a plurality of cascade power conversion modules 110; each cascade power conversion module 110 is connected in a mode of input series connection and output parallel connection;
included in the single cascaded power conversion module 110 are a second processor 111, a first communication circuit 112, a second communication circuit 113, a hardware bus component 114, a power processing component 115, and a second memory 116. The second processor 111 is connected to the first communication circuit 112, the second communication circuit 113, the hardware bus component 114, the power processing component 115, and the second memory 116, respectively. The first communication circuit 112 is connected to the hardware synchronization bus 131; the second communication circuit 113 is connected to the internal communication bus 132.
The main control module 120 includes a first processor 121, a third communication circuit 122, a fourth communication circuit 123, a first memory 124, and a fifth communication circuit 125. The first processor 121 is connected to the third communication circuit 122, the fourth communication circuit 123, the first memory 124, and the fifth communication circuit 125, respectively. The third communication circuit 122 is connected to the hardware synchronization bus 131; the fourth communication circuit 123 is connected to the internal communication bus 132; the fifth communication circuit 125 is connected to the external communication bus 133.
The first processor 121 is configured to: after the high-voltage input power supply voltage is established, a bus reset signal is sent to the hardware synchronous bus 131 through the third communication circuit 122, and delay processing is performed; sending an startup instruction to the internal communication bus 132 through the fourth communication circuit 123; transmitting a start pulse or a stop signal to the hardware synchronization bus 131 through the third communication circuit 122;
each second processor 111 is configured to: after receiving the start-up instruction of the internal communication bus 132 through the second communication circuit 113, start up timing; judging whether a pulse signal sent by the third communication circuit 122 to the hardware synchronous bus 131 is received or not in the timing time, and controlling the corresponding power conversion module 110 to synchronously start up at the time of the falling edge of the pulse signal to output a medium-voltage power supply; upon receiving the fault signal or shutdown signal sent by the hardware synchronization bus 131, all the power conversion modules 110 that are operating are controlled to shutdown synchronously to shut down the medium voltage power supply.
Wherein, the medium voltage power supply is DC375V or DC600V.
Referring to fig. 1, the number of the power conversion modules 110 in the present invention is N, which is a first power conversion module, a second power conversion module, … …, and an nth power conversion module, where N is greater than or equal to 2, and N is an integer.
Further, referring to fig. 6, fig. 6 is a schematic structural diagram of another dc-dc converter system according to an embodiment of the present invention; fig. 6 is different from fig. 1 in that fig. 1 adopts a self-start mode without participation of the upper computer terminal 000, and fig. 6 adopts a debug mode with participation of the upper computer terminal 000. The upper computer terminal 000 is connected to the main control module 120 through the external communication bus 133, and is used for configuring the working mode of the hvdc converter system, sending start-stop control commands, and monitoring the running state of the hvdc converter system.
Specifically, the hvdc converter system 100 further comprises an upper computer terminal 000; the upper computer terminal 000 is connected to the main control module 120 through the external communication bus 133, and is used for configuring the working mode of the hvdc converter system 100, sending a start-stop control command, and monitoring the running state of the hvdc converter system 100; the external communication bus 133 is used for uploading the internal data and status of the hvdc converter system 100 to the upper computer terminal 000.
Further, the third communication circuit 122 in the main control module 120 is connected to the first communication circuit 112 in the power conversion module 110 through the hardware synchronous bus 131, and is used for sending the start-stop signal and the fault signal of the main control module 120 to the plurality of cascaded power conversion modules 110;
Further, the fourth communication circuit 123 in the main control module 120 is connected to the second communication circuit 113 in the power conversion module 110 through the internal communication bus 132, so that the main control module 120 issues a control command and queries the internal operation state and the working data of the cascaded power conversion module 110.
The internal communication bus 132 may be a CAN communication bus, or may be an RS-485 or RS-232 communication bus, etc.
Further, the second processor 111 in the power conversion module 110 is connected to the first communication circuit 112, and the first communication circuit 112 is configured to output a pulse signal or a level signal (high level) of the hardware synchronization bus 131 to the second processor 111 in the power conversion module 110, and send out a start-stop command or a fault protection signal; the second processor 111 is connected to the second communication circuit 113, and the second communication circuit 113 is used for uploading the operation state and operation data of the power conversion module 110 and fault information of the second memory 116; the second processor 111 is connected to the hardware bus component 114 for enabling or resetting the hardware synchronization bus 131 signal; the second processor 111 is connected to the power processing component 115 for sampling and enabling or resetting control of the power processing component 115; the second processor 111 is connected to a second memory 116, and the second memory 116 is used for storing parameters inside the power conversion module 110 and fault information of the power conversion module 110.
Further, the hardware bus component 114 is connected to the first communication circuit 112, and is used for transmitting a fault bus signal generated inside the power conversion module 110 to the hardware synchronous bus 131 through the first communication circuit 112; the hardware bus component 114 is coupled to the power processing component 115 for converting a fault generated by the power conversion module 110 into a fault bus signal.
The second memory 116 may be implemented by various types of volatile or nonvolatile memory devices or combinations thereof, such as an electrically erasable programmable read-only memory (EEPROM), an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a magnetic memory, a Flash, or an optical disk.
Further, the first processor 121 is connected to the first memory 124, and is configured to store internal fault information or configuration parameters of the main control module 120.
Further, the first processor 121 is connected to the fourth communication circuit 123, and is configured to upload, by the first processor 121 in the main control module, the operation state and operation data of the main control module 120 and fault information of the first memory 124; the first processor 121 is connected to the fifth communication circuit 125, and is configured to send the system state information of the hvdc converter to the external communication bus 133 through the fifth communication circuit 125 by the first processor 121 in the main control module 120.
The first memory 124 may be implemented by various types of volatile or nonvolatile memory devices or combinations thereof, such as an electrically erasable programmable read-only memory (EEPROM), an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a magnetic memory, a Flash, or an optical disk.
Specifically, under the default condition, the high-voltage direct-current converter system works in a self-starting mode, and the upper computer terminal sets and selects a working mode.
The invention adopts a hardware synchronous bus time-sharing multiplexing mode, one bus realizes a method for realizing time-sharing transmission pulse and level and realizing start-stop and fault protection, and the bus transmission speed is high, so that the synchronization of all cascade power conversion modules is high; the bus structure is simplified, and the bus is convenient to carry out isolation transmission; the method has the advantages that the method combines the hardware synchronous bus with the internal communication bus, and the effects of quick and reliable start-up and fault protection are realized by utilizing the characteristic of quick transmission of the hardware synchronous bus and the characteristic of reliable transmission data of the internal communication bus, so that the situation that the power devices of the cascade power conversion modules are not balanced in the transient start-up and fault protection process is avoided; the bus in the form of another differential twisted pair is also adopted, so that the redundant application is easy, and the reliability of the whole machine is improved. The invention not only realizes higher real-time performance of synchronous start-stop and fault protection of each cascade power conversion module and fast stores and restores fault information to the real fault state, but also meets the requirements of high isolation voltage resistance, high anti-interference performance and high reliability.
Referring to fig. 2-5, fig. 2 is a flowchart of a synchronous start-stop fault processing method according to an embodiment of the present invention; FIG. 3 is a timing chart of a synchronous start-stop fault handling method according to an embodiment of the present invention when a power-on is started; FIG. 4 is a timing chart of a synchronous start-stop fault handling method provided by an embodiment of the present invention when a start-up is unsuccessful; fig. 5 is a timing chart of a synchronous start-stop fault handling method provided by an embodiment of the present invention during a stop.
The synchronous start-stop fault processing method is applied to the high-voltage direct-current converter system shown in fig. 1, and comprises the following steps:
201. after the high-voltage input power supply voltage is established, a first processor in the main control module sends a bus reset signal to the hardware synchronous bus through a third communication circuit and performs delay processing.
Under the condition that the first processor 121 in the main control module 120 is set to operate in the automatic operation mode by default, the first processor 121 sends a bus reset signal to the hardware synchronous bus 131 through the third communication circuit 122, and the level is pulled down to realize bus reset, and the first processor 121 delays according to a set delay time length, for example, delay time is 1s; the first processor 121 may be a Microcontroller (MCU) or a Digital Signal Processor (DSP).
202. The first processor in the main control module sends a start instruction to the internal communication bus through the fourth communication circuit.
The fourth communication circuit 123 may be an RS-484 or CAN communication interface circuit.
203. And after the second processor in the power conversion module receives a start instruction of the internal communication bus through the second communication circuit, starting timing.
Wherein, the cascade power conversion modules have N power conversion modules 110 in total, N is more than or equal to 2, N is an integer, and the N power conversion modules 110 are connected in a mode of input series connection and output parallel connection; the second processor 111 may be a Micro Controller Unit (MCU) or a Digital Signal Processor (DSP), and the first processor 121 starts up at a timing of 100ms when receiving a start-up instruction from the first processor 121 through the internal communication bus 132.
204. And the second processors in all the power conversion modules judge whether pulse signals sent to the hardware synchronous bus by the main control module through the third communication circuit are received in the timing time, and all the power conversion modules in normal states synchronously start up to output a medium-voltage power supply at the time of the falling delay of the pulse signals.
The second processor 111 in the power conversion module 110 determines whether the pulse signal of the receiving hardware synchronization bus 131 exceeds 100ms.
Further, the second processor 111 in the power conversion module 110 receives the pulse signal sent by the main control module 120 to the hardware synchronous bus 131 through the first communication circuit 112 within 100ms, and the power processing component 115 enables normal operation.
Further, after the second processor 111 in the power conversion module 110 receives the falling edge of the pulse signal, the power processing component 115 is enabled, and the power conversion module 110 outputs the medium voltage +375V.
Specifically, the power conversion module 110 converts the high voltage input voltage to a medium voltage +375V output.
Further, the second processor 111 in the power conversion module 110 is not enabled by the power processing component 115, i.e. the power conversion module 110 is not operated, regardless of whether the pulse signal sent by the main control module 120 to the hardware synchronization bus 131 through the first communication circuit 112 is received or not received outside the timing of 100ms. At this time, the second processor 111 generates a fault signal to pull up the hardware synchronization bus 131 through the first communication circuit 112.
Specifically, determining whether the power conversion module 110 is operating properly is determined by the second processor 111 in the power conversion module 110.
Further, if the second processor 111 in the power conversion module 110 determines that the power conversion module 110 is not operating properly, the fault information is sent to the hardware synchronization bus 131.
205. And when the second processor in all the power conversion modules receives the hardware synchronous bus fault or shutdown signal, controlling all the power conversion modules working to synchronously shutdown, and simultaneously storing the fault signal in a second memory.
Wherein the hardware synchronous bus fault signal is a fault generated by one of the cascaded power conversion modules 110 and is sent to the hardware synchronous bus 131 through the hardware bus component 114 and the first communication circuit 112 of the power conversion module 110; the shutdown signal is sent to the hardware synchronization bus 131 by the main control module 120 through the first processor 121 and the third communication circuit 122.
206. The main control module receives the fault or stop signal of the hardware synchronous bus, stores the fault signal triggered by the main control module in the first memory, reads the fault information of all the power conversion modules through the internal communication bus, and stores the fault information of all the power conversion modules in the first memory.
Further, the second processor in all the power conversion modules judges whether a pulse signal sent by the main control module to the hardware synchronous bus through the third communication circuit is received in a timing time, and when the pulse signal drops and delays, all the power conversion modules in normal states synchronously start up, and the step of outputting the medium-voltage power supply comprises the following steps:
The second processors in all the power conversion modules judge whether the received hardware synchronous bus pulse signals exceed the timing time or not;
if not, the first processor in the main control module sends a pulse signal to the hardware synchronous bus through the third communication circuit;
and the second processors in all the working power conversion modules synchronously start up at the moment of receiving the falling edge of the pulse signal, and output a medium-voltage power supply.
The second processor 111 in the power conversion module 110 receives the pulse signal of the hardware synchronous bus 131 for more than a timing time, and receives or fails to receive the pulse signal sent by the main control module 120 to the hardware synchronous bus 131 through the first communication circuit 112, so that the power processing component 115 is not enabled, and the power conversion module 110 does not work.
Further, when the second processor in the all power conversion modules receives the hardware synchronous bus fault or shutdown signal, the step of controlling all power conversion modules working to synchronously shutdown and simultaneously storing the fault signal in the second memory includes:
the second processor in each power conversion module judges whether the hardware synchronous bus fault or shutdown signal is received;
When the hardware synchronous bus fault or shutdown signal is received, each second processor judges whether each power conversion module operates normally or not;
if not, synchronously stopping all the power conversion modules which are working, and storing fault signals in a second memory.
Wherein, the second processor 111 in the power conversion module 110 determines whether the power conversion module 110 is operating normally; the second processor 111 in the power conversion module 110 determines that the power conversion module 110 is not operating properly, and sends fault information to the hardware synchronization bus 131.
Further, the method further comprises:
207. the main control module uploads fault information in the first memory and the second memory to the upper computer terminal through an external communication bus; the first processor 121 in the main control module 120 sends the system status information of the hvdc converter to the external communication bus 133 through the fifth communication circuit 125. Further, the main control module 120 performs data interaction with the upper computer terminal 000 on the premise that the external communication bus 133 is connected with the upper computer terminal 000;
208. the upper computer terminal sets the working mode of the high-voltage direct-current converter system as a debugging mode;
209. Under the condition that the high-voltage direct-current converter system is configured into a debugging mode, the upper computer terminal sends a start command to the main control module through a fifth communication circuit;
210. and under the condition that the HVDC converter system is configured to be in a non-debugging mode, the upper computer terminal sends a shutdown command to the main control module through the fifth communication circuit.
Referring to fig. 7, fig. 7 is an interactive flowchart of a synchronous start-stop fault processing method provided by an embodiment of the present invention; as shown in fig. 7, the synchronous start-stop fault processing method includes the following steps:
701. the default operating mode of the hvdc converter system is a self-starting mode.
702. A first processor in the main control module sends a reset instruction to a hardware synchronous bus through a third communication circuit; the hardware synchronization bus is pulled low, enabling a bus reset.
Wherein the bus reset is a low level reset.
703. Reset is delayed for 1s.
Wherein the first processor in the main control module delays for 1s.
704. And the first processor in the main control module sends a start instruction to the internal communication bus through the fourth communication circuit.
705. The first processor in the main control module delays for 10ms.
706. And after receiving the start-up instruction, a second processor in the power conversion module is timed for 100ms.
707. The first processor in the main control module sends a 10ms pulse signal to the hardware synchronous bus through the third communication circuit.
708. Determine if timing exceeds 100ms?
Wherein a second processor in the power conversion module determines whether the received hardware synchronization bus pulse signal exceeds 100ms.
If not, execution 709: and after the second processors in all the power conversion modules receive the falling edges of the pulse signals, enabling the power processing assembly, and outputting medium-voltage +375V by the power conversion modules.
Wherein the power conversion module converts the high voltage input voltage to a medium voltage +375V output.
If yes, execute 710: a second processor in the power conversion module triggers a start-up failure flag.
711. Determine if the power conversion module is operating properly?
Wherein the determination is made by a second processor in the power conversion module.
If not, execution 712: the first communication circuit in the power conversion module sends a fault signal to the hardware synchronous bus.
And if the second processor in the power conversion module judges that the module is not normally operated, fault information is sent to the hardware synchronous bus.
If yes, execution 713: the second processor in the power conversion module transmits power conversion module status information to the internal communication via the second communication circuit.
714. Determine whether the power conversion module start-up state is normal?
The first processor in the main control module judges whether the power conversion module works normally or not.
If yes, execution 715: the first processor in the main control module sends the state information of the high-voltage direct-current converter to the external communication bus through the fifth communication circuit.
On the premise that the external communication bus is connected with the upper computer terminal, the main control module performs data interaction with the upper computer terminal.
If not, execution 716: the upper computer terminal sets the working mode of the high-voltage direct-current converter system as a debugging mode.
Under the default condition, the HVDC converter system works in a self-starting mode, and the upper computer terminal sets and selects a working mode.
717. And the upper computer terminal sends a start command to the main control module through the fifth communication circuit.
Under the condition that the HVDC converter system is configured into a debugging mode, an upper computer terminal sends a start command to a main control module.
718. And the upper computer terminal sends a shutdown command to the main control module through the fifth communication circuit.
And under the condition that the HVDC converter system is configured into a non-debugging mode, the upper computer terminal sends a shutdown command to the main control module.
The embodiments of the present invention also provide a storage medium containing computer executable instructions, where the computer executable instructions are not limited to the method operations described above, but may also perform related operations in the synchronous start-stop fault handling method provided by any of the embodiments of the present invention.
It is noted that the terms "comprising" and "having" and any variations thereof in the description of the invention and the claims and drawings are intended to cover a non-exclusive inclusion. The terms first, second and the like in the description and in the claims or drawings are used for distinguishing between different objects and not for describing a particular sequential order. Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the invention. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (9)
1. A hvdc converter system comprising: the device comprises a hardware synchronous bus, an external communication bus, an internal communication bus, a main control module and a plurality of cascade power conversion modules; each power conversion module is connected in a mode of input series connection and output parallel connection;
the single power conversion module comprises a second processor, a first communication circuit, a second communication circuit, a hardware bus component, a power processing component and a second memory; the second processor is respectively connected with the first communication circuit, the second communication circuit, the hardware bus component, the power processing component and the second memory; the first communication circuit is connected with the hardware synchronous bus; the second communication circuit is connected with the internal communication bus;
the main control module comprises a first processor, a third communication circuit, a fourth communication circuit, a first memory and a fifth communication circuit; the first processor is respectively connected with the third communication circuit, the fourth communication circuit, the first memory and the fifth communication circuit; the third communication circuit is connected with the hardware synchronous bus; the fourth communication circuit is connected with the internal communication bus; the fifth communication circuit is connected with the external communication bus;
the first processor is configured to: after the high-voltage input power supply voltage is established, a bus reset signal is sent to a hardware synchronous bus through a third communication circuit, and delay processing is carried out; sending a start command to an internal communication bus through a fourth communication circuit; transmitting a start pulse or a stop signal to the hardware synchronous bus through a third communication circuit;
The second processor is configured to: starting timing after receiving a start command of an internal communication bus through a second communication circuit; judging whether a pulse signal sent by a third communication circuit to a hardware synchronous bus is received or not in the timing time, and controlling a corresponding power conversion module to synchronously start up at the moment of the falling edge of the pulse signal to output a medium-voltage power supply; and when a fault signal or a shutdown signal sent by the hardware synchronous bus is received, controlling all the power conversion modules working to synchronously shutdown so as to shut down the medium-voltage power supply.
2. The hvdc converter system in accordance with claim 1, further comprising an upper computer terminal; the upper computer terminal is connected with the main control module through the external communication bus and is used for configuring the working mode of the high-voltage direct-current converter system, sending a start-stop control command and monitoring the running state of the high-voltage direct-current converter system; and the external communication bus is used for uploading the internal data and the state of the high-voltage direct-current converter system to an upper computer terminal.
3. The hvdc converter system in accordance with claim 2 wherein said third communication circuit in said main control module is connected to said first communication circuit in said power conversion module via said hardware synchronization bus for transmitting said main control module start-stop signal and fault signal to a plurality of cascaded power conversion modules;
The fourth communication circuit in the main control module is connected with the second communication circuit in the power conversion module through the internal communication bus and is used for the main control module to issue control instructions and inquire the internal operation state and working data of the cascade power conversion module.
4. The hvdc converter system in accordance with claim 3 wherein said first communication circuit is operative to output a pulse signal or a level signal of said hardware synchronization bus to said second processor for issuing a start-stop command or a failsafe signal;
the second communication circuit is used for uploading the running state and running data of the power conversion module and the fault information of the second memory;
the second processor is used for enabling or resetting the hardware synchronous bus signal through the hardware bus component; the second processor is also used for sampling and enabling or resetting control of the power processing component; the second memory is used for storing the internal parameters of the power conversion module and fault information of the power conversion module.
5. The hvdc converter system in accordance with claim 4 wherein said first memory is for storing fault information or configuration parameters internal to said main control module.
6. A synchronous start-stop fault handling method, wherein the synchronous start-stop fault handling method is applied to the high voltage dc converter system provided in any one of claims 1 to 5, the method comprising:
after the high-voltage input power supply voltage is established, a first processor in the main control module sends a bus reset signal to the hardware synchronous bus through a third communication circuit and performs delay processing;
a first processor in the main control module sends a start instruction to an internal communication bus through a fourth communication circuit;
after receiving a start command of the internal communication bus through a second communication circuit, a second processor in the power conversion module starts timing;
judging whether pulse signals sent to the hardware synchronous bus by the main control module through the third communication circuit are received by a second processor in all the power conversion modules in a timing time, and synchronously starting all the power conversion modules in normal states at the time of descending delay of the pulse signals to output a medium-voltage power supply;
when the second processor in all the power conversion modules receives the hardware synchronous bus fault or shutdown signal, controlling all the power conversion modules working to synchronously shutdown, and simultaneously storing the fault signal in a second memory;
The main control module receives the fault or stop signal of the hardware synchronous bus, stores the fault signal triggered by the main control module in the first memory, reads the fault information of all power conversion modules through the internal communication bus, and stores the fault information of all power conversion modules in the first memory.
7. The method of claim 6, wherein the second processor in all power conversion modules determines whether a pulse signal sent by the main control module to the hardware synchronous bus through the third communication circuit is received in a timing time, and at a time of a falling delay of the pulse signal, all power conversion modules in normal states start up synchronously, and the step of outputting the medium voltage power supply comprises:
the second processors in all the power conversion modules judge whether the received hardware synchronous bus pulse signals exceed the timing time or not;
if not, the first processor in the main control module sends a pulse signal to the hardware synchronous bus through the third communication circuit;
and the second processors in all the working power conversion modules synchronously start up at the moment of receiving the falling edge of the pulse signal, and output a medium-voltage power supply.
8. The method of claim 7, wherein when the second processor of all power conversion modules receives the hardware synchronous bus fault or stall signal, the step of controlling all power conversion modules that are operating to stall synchronously while storing the fault signal in the second memory comprises:
the second processor in each power conversion module judges whether the hardware synchronous bus fault or shutdown signal is received;
when the hardware synchronous bus fault or shutdown signal is received, each second processor judges whether each power conversion module operates normally or not;
if not, synchronously stopping all the power conversion modules which are working, and storing fault signals in a second memory.
9. The method of claim 8, wherein the method further comprises:
the main control module uploads fault information in the first memory and the second memory to an upper computer terminal through an external communication bus;
the upper computer terminal sets the working mode of the high-voltage direct-current converter system as a debugging mode;
under the condition that the HVDC converter system is configured into a debugging mode, the upper computer terminal sends a start command to the main control module through the fifth communication circuit;
And under the condition that the HVDC converter system is configured to be in a non-debugging mode, the upper computer terminal sends a shutdown command to the main control module through the fifth communication circuit.
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