CN117525127A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN117525127A
CN117525127A CN202210911075.XA CN202210911075A CN117525127A CN 117525127 A CN117525127 A CN 117525127A CN 202210911075 A CN202210911075 A CN 202210911075A CN 117525127 A CN117525127 A CN 117525127A
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region
layer
work function
forming
semiconductor structure
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王艳霞
何海杰
吴汉洙
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Priority to CN202210911075.XA priority Critical patent/CN117525127A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET

Abstract

A semiconductor structure and a method for forming the semiconductor structure, the structure includes: a substrate comprising a first region, a second region, and a third region; a transition layer located over the first region, over the second region, and over the third region; the gate dielectric layer is positioned on the transition layer, the electric dipole concentration of the transition layer interface on the second area is larger than that of the transition layer interface on the first area, and the electric dipole concentration of the transition layer interface on the third area is larger than that of the transition layer interface on the second area; and the work function layers are positioned on the gate dielectric layer, and the trend of regulating the voltage of the work function layers on the first region, the second region and the third region is changed in a gradient manner. The voltage diversity capability of the semiconductor structure is improved.

Description

Semiconductor structure and forming method thereof
Technical Field
The present disclosure relates to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the semiconductor structure.
Background
Nanowires or nanoplatelet structures are considered to be one of the most promising structures to replace finfets due to their superior dc performance and better short channel control performance. When various devices require different voltages, the device voltage is typically adjusted by adjusting the thickness of the work function layer metal,
however, in stacked nanowire or nanoplatelet structures, inter-nanowire (inter-nanoplatelet) spacing is limited by the current technology node and the range of thickness tuning of the work function layer metal is limited.
Therefore, there is a need to propose a better solution for regulating the device voltage to meet the requirement of device voltage diversity.
Disclosure of Invention
The invention solves the technical problem of providing a semiconductor structure and a method for forming the semiconductor structure so as to meet the requirement of device voltage diversity.
In order to solve the above technical problems, the present invention provides a semiconductor structure, including: a substrate comprising a first region, a second region, and a third region; a transition layer located over the first region, over the second region, and over the third region; the gate dielectric layer is positioned on the transition layer, the electric dipole concentration of the transition layer interface on the second area is larger than that of the transition layer interface on the first area, and the electric dipole concentration of the transition layer interface on the third area is larger than that of the transition layer interface on the second area; and the work function layers are positioned on the gate dielectric layer, and the trend of regulating the voltage of the work function layers on the first region, the second region and the third region is changed in a gradient manner.
Optionally, the conductivity type of the work function layer includes an N-type or a P-type, the N-type work function material includes titanium aluminum, and the P-type work function material includes titanium nitride or tantalum nitride.
Optionally, when the conductivity type of the work function layer includes N-type, a tuning voltage of the work function layer on the first region is greater than a tuning voltage of the work function layer on the second region, and the tuning voltage of the work function layer on the second region is greater than the tuning voltage of the work function layer on the third region.
Optionally, when the conductivity type of the work function layer includes P-type, a tuning voltage of the work function layer on the first region is smaller than a tuning voltage of the work function layer on the second region, and the tuning voltage of the work function layer on the second region is smaller than the tuning voltage of the work function layer on the third region.
Optionally, the material of the gate dielectric layer includes a dielectric material with a dielectric constant greater than 3.9, and the dielectric material includes aluminum oxide or hafnium oxide.
Optionally, the material of the transition layer includes silicon oxide.
Optionally, the method further comprises: a gate layer over the work function layer.
Optionally, the substrate includes: a substrate; and the gate layer spans the fin structure.
Optionally, the fin structure includes: and the channel layers are stacked along the direction perpendicular to the surface of the substrate, spaces are reserved between the channel layers and the substrate and between adjacent channel layers, the transition layers are positioned on the surface of the channel layers, and the gate layers encircle the channel layers.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate comprises a first region, a second region and a third region; forming a transition layer on the first region, the second region and the third region; forming a gate dielectric layer on the transition layer; forming a barrier layer on the gate dielectric layer of the first region; forming a diffusion layer on the gate dielectric layer on the second region and the third region, wherein the diffusion layer is used for generating an electric dipole; carrying out first annealing treatment on the diffusion layers on the second region and the third region, so that the electric dipole concentration of the transition layer interface on the second region is larger than that of the transition layer interface on the first region; after the diffusion layers on the second region and the third region are subjected to first annealing treatment, removing the diffusion layers on the second region; after removing the diffusion layer on the second region, carrying out second annealing treatment on the diffusion layer on the third region, so that the electric dipole concentration of the transition layer interface on the third region is larger than that of the transition layer interface on the second region; removing the diffusion layer and the barrier layer after carrying out second annealing treatment on the diffusion layer on the third region; and after the diffusion layer and the blocking layer are removed, forming work function layers on the gate dielectric layers on the first region, the second region and the third region, wherein the trend of the work function layers on the first region, the second region and the third region for regulating the voltage is in gradient change.
Optionally, the conductivity type of the work function layer includes an N-type or a P-type, the N-type work function material includes titanium aluminum, and the P-type work function material includes titanium nitride or tantalum nitride.
Optionally, when the conductivity type of the work function layer includes N-type, a tuning voltage of the work function layer on the first region is greater than a tuning voltage of the work function layer on the second region, and the tuning voltage of the work function layer on the second region is greater than the tuning voltage of the work function layer on the third region.
Optionally, when the conductivity type of the work function layer includes P-type, a tuning voltage of the work function layer on the first region is smaller than a tuning voltage of the work function layer on the second region, and the tuning voltage of the work function layer on the second region is smaller than the tuning voltage of the work function layer on the third region.
Optionally, the method for forming the barrier layer on the gate dielectric layer of the first region includes: forming an initial barrier layer on the gate dielectric layer of the first region, the gate dielectric layer of the second region and the gate dielectric layer of the third region; and removing the initial barrier layers on the second region and the third region, and forming a barrier layer on the gate dielectric layer of the first region.
Optionally, the method for forming a diffusion layer on the gate dielectric layer on the second region and the third region includes: after forming a barrier layer on the gate dielectric layer of the first region, a diffusion layer is formed on the barrier layer of the first region, on the gate dielectric layer of the second region and on the gate dielectric layer of the third region.
Optionally, the process parameters of the first annealing treatment of the diffusion layer on the second region and the third region include: the temperature range is 400-1000 ℃.
Optionally, the process parameters of performing the second annealing treatment on the diffusion layer on the third region include: the temperature range is 400-1000 ℃.
Optionally, the material of the diffusion layer includes a rare earth element-containing compound, and the material of the diffusion layer includes: scandium oxide, lanthanum oxide, erbium oxide or strontium oxide.
Optionally, the material of the gate dielectric layer includes a dielectric material with a dielectric constant greater than 3.9, and the dielectric material includes aluminum oxide or hafnium oxide.
Optionally, the material of the transition layer includes silicon oxide.
Optionally, the material of the barrier layer includes a metal nitride, and the metal nitride includes titanium nitride.
Optionally, after forming the work function layer, the method further includes: a gate layer is formed over the work function layer.
Optionally, the substrate includes: a substrate; and the gate layer spans the fin structure.
Optionally, the fin structure includes: and the channel layers are stacked along the direction perpendicular to the surface of the substrate, spaces are reserved between the channel layers and the substrate and between adjacent channel layers, the transition layers are positioned on the surface of the channel layers, and the gate layers encircle the channel layers.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
according to the technical scheme, the diffusion layers on the second area and the third area are subjected to first annealing treatment, so that the electric dipole concentration of the transition layer interface on the second area is larger than that of the transition layer interface on the first area, and then the diffusion layers on the third area are subjected to second annealing treatment, so that the electric dipole concentration of the transition layer interface on the third area is larger than that of the transition layer interface on the second area. The greater the electric dipole concentration is, the greater the degree of the voltage offset towards the negative direction is, so that the voltage adjusting capability of the work function layer formed subsequently can be influenced by adjusting the electric dipole concentration in the first region, the second region and the third region, and the requirement of device voltage diversity is further met.
Drawings
Fig. 1 to 5 are schematic views illustrating a semiconductor structure forming process according to an embodiment of the present invention.
Detailed Description
As described in the background, there is a need to propose a better solution for adjusting the device voltage to meet the requirement of device voltage diversity.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 to 5 are schematic views illustrating a semiconductor structure forming process according to an embodiment of the present invention.
Referring to fig. 1, a substrate 100 is provided, the substrate 100 including a first region I, a second region II, and a third region III.
In this embodiment, the substrate 100 includes: a base (not shown); fin structures (not shown) located on the substrate.
The fin structure includes: and a plurality of channel layers stacked along the direction vertical to the surface of the substrate, wherein a space is reserved between the channel layers and the substrate and between adjacent channel layers.
In this embodiment, the material of the substrate 100 is silicon.
In other embodiments, the material of the substrate comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). Wherein the iii-v element comprising multi-component semiconductor material comprises InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP.
In other embodiments, the substrate is a planar substrate.
In other embodiments, the fin structure does not have several channel layers.
With continued reference to fig. 1, a transition layer 101 is formed over the first region I, over the second region II, and over the third region III.
In this embodiment, the transition layer 101 is located on the surface of the channel layer. The transition layer 101 is used to increase adhesion between the subsequently formed high-K gate dielectric layer and the substrate 100, so as to perform interface transition between the substrate 100 and the high-K gate dielectric layer.
In this embodiment, the material of the transition layer 101 includes silicon oxide.
In other embodiments, the transition layer is located on the fin structure surface or the substrate surface.
With continued reference to fig. 1, a gate dielectric layer 102 is formed on the transition layer 101.
The material of the gate dielectric layer 102 includes a dielectric material having a dielectric constant greater than 3.9, and the dielectric material includes aluminum oxide or hafnium oxide.
In this embodiment, the material of the gate dielectric layer 102 includes hafnium oxide.
Referring to fig. 2, a barrier layer 103 is formed on the gate dielectric layer 102 in the first region I.
The method for forming the barrier layer 103 on the gate dielectric layer 102 of the first region I includes: forming an initial barrier layer (not shown) on the gate dielectric layer 102 of the first region I, the gate dielectric layer 102 of the second region II, and the gate dielectric layer 102 of the third region III; and removing the initial barrier layers on the second region II and the third region III, and forming a barrier layer 103 on the gate dielectric layer 102 of the first region I.
The blocking layer 103 is used for blocking electric dipoles generated by the subsequent diffusion layers from diffusing into the gate dielectric layer 102 and the transition layer 101.
The material of the barrier layer 103 comprises a metal nitride comprising titanium nitride.
Referring to fig. 3, a diffusion layer 104 is formed on the gate dielectric layer 102 on the second region II and the third region III, and the diffusion layer 104 is used to generate an electric dipole.
The method for forming the diffusion layer 104 on the gate dielectric layer 102 on the second region II and the third region III includes: a diffusion layer 104 is formed on the barrier layer 103 of the first region I, on the gate dielectric layer 102 of the second region II, and on the gate dielectric layer 102 of the third region III.
The material of the diffusion layer 104 includes a rare earth element-containing compound, and the material of the diffusion layer 104 includes: scandium oxide (ScOx), lanthanum oxide (LaOx), erbium oxide (ErOx), strontium oxide (SrOx), or the like. The rare earth element-containing diffusion layer 104 generates an electric dipole under the effect of high temperature to shift the voltage of the work function layer formed later.
In this embodiment, the material of the diffusion layer 104 includes lanthanum oxide.
With continued reference to fig. 3, the diffusion layer 104 on the second region II and the third region III is subjected to a first annealing treatment, so that the electric dipole concentration of the interface of the transition layer 101 on the second region II is greater than the electric dipole concentration of the interface of the transition layer 101 on the first region I.
After the high-temperature annealing, the rare earth element lanthanum in the diffusion layer diffuses into the transition layer 101 to form silicate. Thus, the rare earth element lanthanum forms a highly polar lanthanum-oxygen (La-O) bond, providing an electric dipole. At this time, there are two main electric dipoles in the transition layer 101: (1) hafnium-oxygen (Hf-O) bonds directed to the transition layer 101; (2) lanthanum-oxygen (La-O) bonds directed toward gate dielectric layer 102. The net dipole moment vector of the electric dipoles in two different directions is directed from the transition layer 101 to the gate dielectric layer 102, so that the work function of the metal formed later is shifted, even if the voltage is shifted to the negative direction, that is, the coverage of the diffusion layer 104 can reduce the voltage of the NMOS and increase the voltage of the PMOS. The more rare earth element is dosed, the greater the net electric dipole concentration produced, and the greater the extent to which the voltage is shifted in the negative direction.
The dosage of rare earth elements can be modulated by the number of anneals, thereby changing the interfacial electric dipole concentration.
In this embodiment, the diffusion layers 104 on the second region II and the third region III are subjected to a first annealing treatment, and the first region I has a barrier layer 103 to block diffusion of the rare earth element into the transition layer 101 of the first region I, so that the electric dipole concentration of the interface of the transition layer 101 on the first region I is smaller, and the electric dipole concentration of the interface of the transition layer 101 on the second region II and the third region III is greater than the electric dipole concentration of the interface of the transition layer 101 on the first region I.
The process parameters of the first annealing treatment of the diffusion layer 104 on the second region II and the third region III include: the temperature range is 400-1000 ℃.
Referring to fig. 4, after the first annealing treatment is performed on the diffusion layer 104 on the second region II and the third region III, the diffusion layer 104 on the second region II is removed; after removing the diffusion layer 104 on the second region II, performing a second annealing treatment on the diffusion layer 104 on the third region III, so that the electric dipole concentration of the interface of the transition layer 101 on the third region III is greater than the electric dipole concentration of the interface of the transition layer 101 on the second region II.
The diffusion layer 104 on the third region III is annealed twice, the diffusion layer 104 on the second region II is annealed once, and the barrier layer 103 on the first region I blocks the rare earth element from diffusing into the transition layer 101 on the first region I, so that the electric dipole concentration of the interface of the transition layer 101 on the third region III is greater than that of the interface of the transition layer 101 on the second region II, and the electric dipole concentration of the interface of the transition layer 101 on the second region II and the third region III is greater than that of the interface of the transition layer 101 on the first region I.
The greater the dosage of rare earth elements, the greater the net electric dipole concentration generated, the greater the degree to which the voltage is shifted in the negative direction, which reduces the voltage of the NMOS and increases the voltage of the PMOS. Therefore, when the work function layer formed on the gate dielectric layer 102 on the first region I, the second region II and the third region III is P-type, the voltage on the third region III is greater than the voltage on the second region II, and the voltage on the second region II is greater than the voltage of the first region I; when the work function layer is of an N type, the voltage on the third region III is smaller than the voltage on the second region II, and the voltage on the second region II is smaller than the voltage of the first region I.
Therefore, the electric dipole concentration of the interface of the transition layer 101 can be controlled by adjusting the annealing times and controlling whether the rare earth element diffuses into the transition layer 101, so that the voltage adjusting capability of the work function layer formed subsequently is affected, and the requirement of voltage diversity is met.
In this embodiment, the process parameters of performing the second annealing treatment on the diffusion layer 104 on the third region III include: the temperature range is 400-1000 ℃.
Referring to fig. 5, after the second annealing treatment is performed on the diffusion layer 104 on the third region III, the diffusion layer 104 and the barrier layer 103 are removed; after the diffusion layer 104 and the barrier layer 103 are removed, a work function layer 105 is formed on the gate dielectric layer 102 on the first region I, the second region II and the third region III, and the trend of the work function layer 105 on the first region I, the second region II and the third region III for adjusting the voltage is gradient.
The conductivity type of the work function layer 105 includes an N-type or a P-type, the N-type work function material includes titanium aluminum, and the P-type work function material includes titanium nitride or tantalum nitride.
When the conductivity type of the work function layer is N-type, the tuning voltage of the work function layer 105 on the first region I is greater than the tuning voltage of the work function layer 105 on the second region II, and the tuning voltage of the work function layer 105 on the second region II is greater than the tuning voltage of the work function layer 105 on the third region III.
When the conductivity type of the work function layer 105 is P-type, the tuning voltage of the work function layer 105 on the first region I is smaller than the tuning voltage of the work function layer 105 on the second region II, and the tuning voltage of the work function layer 105 on the second region II is smaller than the tuning voltage of the work function layer 105 on the third region III.
In this embodiment, after forming the work function layer 105, further including: a gate layer (not shown) is formed on the work function layer 105. In this embodiment, the gate layer surrounds the channel layer.
In other embodiments, the gate layer spans the fin structure.
Accordingly, an embodiment of the present invention further provides a semiconductor structure, please continue to refer to fig. 5, including:
a substrate 100, the substrate 100 comprising a first region I, a second region II and a third region III;
a transition layer 101 located on the first region I, the second region II and the third region III;
the gate dielectric layer 102 is located on the transition layer 101, the electric dipole concentration of the transition layer 101 interface on the second region II is greater than that of the transition layer 101 interface on the first region I, and the electric dipole concentration of the transition layer 101 interface on the third region III is greater than that of the transition layer 101 interface on the second region II;
and the work function layer 105 is positioned on the gate dielectric layer 102, and the trend of the work function layer 105 on the first region I, the second region II and the third region III for regulating the voltage is changed in a gradient manner.
In this embodiment, the conductivity type of the work function layer 105 includes N-type or P-type, the N-type work function material includes titanium aluminum, and the P-type work function material includes titanium nitride or tantalum nitride.
In this embodiment, when the conductivity type of the work function layer 105 includes N-type, the tuning voltage of the work function layer 105 on the first region I is greater than the tuning voltage of the work function layer 105 on the second region II, and the tuning voltage of the work function layer 105 on the second region II is greater than the tuning voltage of the work function layer 105 on the third region III.
In this embodiment, when the conductivity type of the work function layer 105 includes P-type, the tuning voltage of the work function layer 105 on the first region I is smaller than the tuning voltage of the work function layer 105 on the second region II, and the tuning voltage of the work function layer 105 on the second region II is smaller than the tuning voltage of the work function layer 105 on the third region III.
In this embodiment, the material of the gate dielectric layer 102 includes a dielectric material having a dielectric constant greater than 3.9, and the dielectric material includes aluminum oxide or hafnium oxide.
In this embodiment, the material of the transition layer 101 includes silicon oxide.
In this embodiment, further comprising: a gate layer located on the work function layer 105.
In this embodiment, the substrate 100 includes: a substrate; and the transition layer 101 is positioned on the surface of the fin structure, and the grid electrode layer spans across the fin structure.
In this embodiment, the fin structure includes: and a plurality of channel layers stacked along the direction vertical to the surface of the substrate, wherein the channel layers and the substrate are provided with intervals, and the adjacent channel layers are provided with the transition layer 101 on the surface of the channel layer, and the gate layer surrounds the channel layer.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (24)

1. A semiconductor structure, comprising:
a substrate comprising a first region, a second region, and a third region;
a transition layer located over the first region, over the second region, and over the third region;
the gate dielectric layer is positioned on the transition layer, the electric dipole concentration of the transition layer interface on the second area is larger than that of the transition layer interface on the first area, and the electric dipole concentration of the transition layer interface on the third area is larger than that of the transition layer interface on the second area;
and the work function layers are positioned on the gate dielectric layer, and the trend of regulating the voltage of the work function layers on the first region, the second region and the third region is changed in a gradient manner.
2. The semiconductor structure of claim 1, wherein the conductivity type of the work function layer comprises an N-type or a P-type, the N-type work function material comprises titanium aluminum, and the P-type work function material comprises titanium nitride or tantalum nitride.
3. The semiconductor structure of claim 2, wherein when the conductivity type of the work function layer comprises an N-type, a tuning voltage of the work function layer on the first region is greater than a tuning voltage of the work function layer on the second region, and the tuning voltage of the work function layer on the second region is greater than the tuning voltage of the work function layer on the third region.
4. The semiconductor structure of claim 2, wherein when the conductivity type of the work function layer comprises a P-type, a tuning voltage of the work function layer on the first region is less than a tuning voltage of the work function layer on the second region, and the tuning voltage of the work function layer on the second region is less than the tuning voltage of the work function layer on the third region.
5. The semiconductor structure of claim 1, wherein the material of the gate dielectric layer comprises a dielectric material having a dielectric constant greater than 3.9, the dielectric material comprising aluminum oxide or hafnium oxide.
6. The semiconductor structure of claim 1, wherein a material of the transition layer comprises silicon oxide.
7. The semiconductor structure of claim 1, further comprising: a gate layer over the work function layer.
8. The semiconductor structure of claim 7, wherein the substrate comprises: a substrate; and the gate layer spans the fin structure.
9. The semiconductor structure of claim 8, wherein the fin structure comprises: and the channel layers are stacked along the direction perpendicular to the surface of the substrate, spaces are reserved between the channel layers and the substrate and between adjacent channel layers, the transition layers are positioned on the surface of the channel layers, and the gate layers encircle the channel layers.
10. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a first region, a second region and a third region;
forming a transition layer on the first region, the second region and the third region;
forming a gate dielectric layer on the transition layer;
forming a barrier layer on the gate dielectric layer of the first region;
forming a diffusion layer on the gate dielectric layer on the second region and the third region, wherein the diffusion layer is used for generating an electric dipole;
carrying out first annealing treatment on the diffusion layers on the second region and the third region, so that the electric dipole concentration of the transition layer interface on the second region is larger than that of the transition layer interface on the first region;
after the diffusion layers on the second region and the third region are subjected to first annealing treatment, removing the diffusion layers on the second region;
after removing the diffusion layer on the second region, carrying out second annealing treatment on the diffusion layer on the third region, so that the electric dipole concentration of the transition layer interface on the third region is larger than that of the transition layer interface on the second region;
removing the diffusion layer and the barrier layer after carrying out second annealing treatment on the diffusion layer on the third region;
and after the diffusion layer and the blocking layer are removed, forming work function layers on the gate dielectric layers on the first region, the second region and the third region, wherein the trend of the work function layers on the first region, the second region and the third region for regulating the voltage is in gradient change.
11. The method of forming a semiconductor structure of claim 10, wherein the conductivity type of the work function layer comprises an N-type or a P-type, the N-type work function material comprises titanium aluminum, and the P-type work function material comprises titanium nitride or tantalum nitride.
12. The method of forming a semiconductor structure of claim 11, wherein when the conductivity type of the work function layer comprises an N-type, a tuning voltage of the work function layer on the first region is greater than a tuning voltage of the work function layer on the second region, and the tuning voltage of the work function layer on the second region is greater than the tuning voltage of the work function layer on the third region.
13. The method of forming a semiconductor structure of claim 11, wherein when the conductivity type of the work function layer comprises a P-type, a tuning voltage of the work function layer on the first region is less than a tuning voltage of the work function layer on the second region, and the tuning voltage of the work function layer on the second region is less than the tuning voltage of the work function layer on the third region.
14. The method of forming a semiconductor structure of claim 10, wherein forming a barrier layer over the gate dielectric layer of the first region comprises: forming an initial barrier layer on the gate dielectric layer of the first region, the gate dielectric layer of the second region and the gate dielectric layer of the third region; and removing the initial barrier layers on the second region and the third region, and forming a barrier layer on the gate dielectric layer of the first region.
15. The method of forming a semiconductor structure of claim 10, wherein forming a diffusion layer over the gate dielectric layer over the second region and over the third region comprises: after forming a barrier layer on the gate dielectric layer of the first region, a diffusion layer is formed on the barrier layer of the first region, on the gate dielectric layer of the second region and on the gate dielectric layer of the third region.
16. The method of forming a semiconductor structure of claim 10, wherein the process parameters of the first annealing the diffusion layer on the second region and on the third region comprise: the temperature range is 400-1000 ℃.
17. The method of forming a semiconductor structure of claim 10, wherein the process parameters of performing a second anneal process on the diffusion layer over the third region comprise: the temperature range is 400-1000 ℃.
18. The method of forming a semiconductor structure of claim 10, wherein the material of the diffusion layer comprises a rare earth element-containing compound, the material of the diffusion layer comprising: scandium oxide, lanthanum oxide, erbium oxide or strontium oxide.
19. The method of forming a semiconductor structure of claim 10, wherein the material of the gate dielectric layer comprises a dielectric material having a dielectric constant greater than 3.9, the dielectric material comprising aluminum oxide or hafnium oxide.
20. The method of forming a semiconductor structure of claim 10, wherein the material of the transition layer comprises silicon oxide.
21. The method of forming a semiconductor structure of claim 10, wherein the material of the barrier layer comprises a metal nitride comprising titanium nitride.
22. The method of forming a semiconductor structure of claim 10, further comprising, after forming the work function layer: a gate layer is formed over the work function layer.
23. The method of forming a semiconductor structure of claim 22, wherein the substrate comprises: a substrate; and the gate layer spans the fin structure.
24. The method of forming a semiconductor structure of claim 23, wherein the fin structure comprises: and the channel layers are stacked along the direction perpendicular to the surface of the substrate, spaces are reserved between the channel layers and the substrate and between adjacent channel layers, the transition layers are positioned on the surface of the channel layers, and the gate layers encircle the channel layers.
CN202210911075.XA 2022-07-29 2022-07-29 Semiconductor structure and forming method thereof Pending CN117525127A (en)

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