CN117524630A

CN117524630A - Circuit board integrated inductor, inductor and electronic equipment

Info

Publication number: CN117524630A
Application number: CN202210900744.3A
Authority: CN
Inventors: 陈奕君
Original assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Current assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Priority date: 2022-07-28
Filing date: 2022-07-28
Publication date: 2024-02-06

Abstract

The application provides a circuit board integrated inductor, an inductor and electronic equipment. The circuit board integrated inductor comprises: the circuit board comprises a substrate and a coil, wherein the coil is embedded in the substrate and comprises at least two parallel wire layers; and a magnetic layer carried on the circuit board and at least partially overlapping the coil. The integrated inductor of the circuit board integrates the inductor in the circuit board, is more ultrathin and miniaturized, improves the packaging efficiency, can reduce the alternating current resistance of the coil, and reduces the alternating current copper loss of the coil under high frequency.

Description

Circuit board integrated inductor, inductor and electronic equipment

Technical Field

The application relates to the field of electronics, in particular to a circuit board integrated inductor, an inductor and electronic equipment.

Background

With the trend of miniaturization and high density of electronic hardware, the surface area of a circuit board is drastically reduced, but there is a growing need for electronic components to be mounted on a board surface. The inductor is an indispensable component of electronic equipment, and most of the current inductors are firstly prepared into inductors and then mounted on a circuit board, so that the area of the circuit board is occupied, discrete mounting is needed, and the packaging efficiency is reduced.

Disclosure of Invention

To the above-mentioned problem, this application embodiment provides a circuit board integrated inductance, and it is with inductance integration in the circuit board, more ultra-thin, miniaturized, has improved packaging efficiency, and can reduce the alternating current resistance of coil, reduces the alternating current copper loss of coil under the high frequency.

The embodiment of the application provides a circuit board integrated inductor, which comprises:

the circuit board comprises a substrate and a coil, wherein the coil is embedded in the substrate and comprises at least two parallel wire layers; and

and the magnetic layer is carried on the circuit board and at least partially overlapped with the coil.

The embodiment of the application also provides a circuit board integrated inductor, which comprises:

the circuit board comprises a substrate and a coil, and the coil is embedded in the substrate; and

the magnetic film layer is borne on the substrate, the magnetic film layer comprises a first magnetic film sub-layer, a second magnetic film sub-layer and a third magnetic film sub-layer, the first magnetic film sub-layer and the second magnetic film sub-layer are respectively arranged on two opposite sides of the coil, the third magnetic film sub-layer penetrates through the substrate and is positioned on the periphery of the coil, and the third magnetic film sub-layer is respectively connected with the first magnetic film sub-layer and the second magnetic film sub-layer.

The embodiment of the application also provides an inductor, which comprises:

the coil layer comprises a coil, and the coil comprises at least two parallel wire layers; and

and the magnetic layer is arranged on one side of the coil layer.

The embodiment of the application provides electronic equipment, which comprises the circuit board integrated inductor; alternatively, the inductor described herein.

The integrated inductor of the circuit board comprises a circuit board and a magnetic layer; the circuit board comprises a substrate and a coil, wherein the coil is embedded in the substrate, and the coil comprises at least two parallel wire layers. Thus, under the condition that the total thickness or total cross-sectional area of the wires forming the coil is the same, the thickness of the single-layer wire layer can be thinner, the utilization rate of the cross-sectional area of each wire layer can be improved, the alternating current resistance of the whole coil is reduced, the alternating current copper loss caused by the skin effect of the coil under high frequency is reduced, and the inductance efficiency of the integrated inductor of the circuit board is improved. In addition, the circuit board integrated inductor of this embodiment is with the inductance integration on the circuit board, when being applied to electronic equipment, can make electronic equipment miniaturized, ultra-thin more, and inductance and circuit board are prepared together, do not need independent mounting, have improved encapsulation efficiency. In addition, the inductor is integrated in the circuit board, and the position of the circuit board corresponding to the inductor can be saved for mounting other components, so that the area on the circuit board is saved, and the wiring and piece distribution capacity of the circuit board is enhanced.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic structural diagram of a circuit board integrated inductor according to an embodiment of the first aspect of the present application.

Fig. 2 is a schematic diagram of a partial exploded structure of a circuit board integrated inductor according to an embodiment of the first aspect of the present application.

Fig. 3 is a schematic cross-sectional view of the integrated inductor of the circuit board according to the embodiment of the first aspect of the present application along A-A in fig. 1.

Fig. 4 is a schematic structural view of a coil according to an embodiment of the first aspect of the present application.

Fig. 5 is a schematic view of a partial exploded structure of a coil according to an embodiment of the first aspect of the present application.

Fig. 6 is a schematic structural view of a coil according to still another embodiment of the first aspect of the present application.

Fig. 7 is a schematic view of a partial exploded structure of a circuit board integrated inductor according to yet another embodiment of the first aspect of the present application.

Fig. 8 is a schematic view of a partial exploded structure of a circuit board according to still another embodiment of the first aspect of the present application.

Fig. 9 is a circuit block diagram of a circuit board integrated inductor of an embodiment of the first aspect of the present application.

Fig. 10 is a schematic structural diagram of a circuit board integrated inductor according to another embodiment of the first aspect of the present application.

Fig. 11 is a schematic structural diagram of a circuit board integrated inductor according to another embodiment of the first aspect of the present application.

Fig. 12 is a schematic structural diagram of a circuit board integrated inductor according to another embodiment of the first aspect of the present application.

Fig. 13 is a top view of a circuit board integrated inductor according to an embodiment of the first aspect of the present application.

FIG. 14 is a top view of a magnetic film layer according to an embodiment of the first aspect of the present application.

Fig. 15 is a schematic structural diagram of a circuit board integrated inductor according to an embodiment of the first aspect of the present application.

Fig. 16 is a schematic structural diagram of a circuit board integrated inductor according to another embodiment of the present Shen Di.

Fig. 17 is a schematic structural diagram of a circuit board integrated inductor according to an embodiment of the second aspect of the present application.

Fig. 18 is a schematic view of a partial exploded structure of a circuit board integrated inductor according to an embodiment of the second aspect of the present application.

Fig. 19 is a schematic cross-sectional structure view of a circuit board according to an embodiment of the second aspect of the present application along the direction B-B in fig. 17.

Fig. 20 is a schematic structural view of a coil according to still another embodiment of the second aspect of the present application.

Fig. 21 is a schematic structural diagram of a circuit board integrated inductor according to another embodiment of the second aspect of the present application.

Fig. 22 is a magnetic induction density distribution diagram of the side of the circuit board integrated inductor corresponding to the inductor portion in embodiment 4 of the present application.

Fig. 23 is a graph showing the magnetic induction intensity distribution of the side of the circuit board integrated inductor corresponding to the inductor portion of comparative example 2 of the present application.

Fig. 24 is a schematic diagram of a partial perspective structure of a circuit board integrated inductor according to an embodiment of a third aspect of the present application.

Fig. 25 is a schematic view of a partial perspective structure of a circuit board according to an embodiment of a third aspect of the present application.

Fig. 26 is a schematic structural view of a coil according to an embodiment of the third aspect of the present application.

Fig. 27 is a schematic structural view of a coil according to an embodiment of the third aspect of the present application.

Fig. 28 is a partial perspective view of the circuit board integrated inductor of embodiment 4 of the present application.

Fig. 29 is a partial perspective view of the circuit board integrated inductor of comparative example 5 of the present application.

Fig. 30 is a partial perspective view of the circuit board integrated inductor of comparative example 6 of the present application.

Fig. 31 is a schematic structural diagram of an inductor according to an embodiment of the fourth aspect of the present application.

Fig. 32 is a schematic structural diagram of an inductor according to a further embodiment of the fourth aspect of the present application.

Fig. 33 is a schematic structural diagram of an inductor according to a further embodiment of the fourth aspect of the present application.

Fig. 34 is a schematic structural diagram of an inductor according to a further embodiment of the fourth aspect of the present application.

Fig. 35 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Fig. 36 is a circuit block diagram of an electronic device of an embodiment of the present application.

Reference numerals illustrate:

the inductor is integrated by a 100-circuit board, 10-circuit board, 11-substrate, 111-insulating layer, 113-supporting layer, 13-coil, 131-main body part, 131 a-first side, 131 b-second side, 131 c-third side, 131 d-fourth side, 13 a-sub-coil, 13a 1-first sub-coil, 13a 2-second sub-coil, 133-first lead, 135-second lead, 1311-lead layer, 1301-opening, 1303-first end, 1305-second end, 15-processor, 17-memory, 30-magnetic layer, 31-magnetic film layer, 311-first magnetic film sub-layer, 313-second magnetic film sub-layer, 315-third magnetic film sub-layer, 3151-magnetic film part, 33-magnetic glue layer, 35-medium layer, 200-inductor, 210-coil layer, 300-electronic device and 310-display screen.

Detailed Description

In order to make the present application solution better understood by those skilled in the art, the following description will clearly and completely describe the technical solution in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

The terms first, second and the like in the description and in the claims of the present application and in the above-described figures, are used for distinguishing between different objects and not for describing a particular sequential order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings. It should be noted that, for convenience of explanation, in the embodiments of the present application, like reference numerals denote like components, and for brevity, detailed explanation of the like components is omitted in different embodiments.

The inductor is composed of a coil and a magnetic piece, and when alternating current passes through the coil, alternating magnetic flux is generated inside and around the coil, so that the inductor has the functions of storing and releasing energy. In electronic circuit, the inductor has current limiting effect on AC, and it can form high-pass filter or low-pass filter, phase shifting circuit and resonant circuit with resistor or capacitor, so that it is widely used in various instruments and equipment.

The inductance device occupies a larger area on the circuit board, for example, in a power module, the inductance device occupies more than 40% of the surface of the power panel, which is not only unfavorable for miniaturization and high density of the product; and most of the inductance devices need to be separately mounted, so that the packaging efficiency is reduced.

In the design of circuit board integrated inductors (PCB integrated inductors), copper losses of the coil (wire) tend to occupy a significant portion of the total losses of the inductive device. With the development of the high frequency of the future power supply module, the skin effect of the wire is more and more obvious, and with the increase of the working frequency, the total impedance is increased. When the thickness of the wire is greater than twice the skin depth of the wire at its operating frequency, the portion of the wire near the center conducts little current, so that the portion of the wire near the center is wasted. In addition, for the integrated inductor of the circuit board, the coil is formed by etching the conductive layer in the preparation process of the circuit board, the thicker the conductive layer is, the longer the conductive layer needs to be etched, the more lateral etching is performed, therefore, when the conductive layer is thicker, the larger the line distance of the formed coil is, which means that the smaller the number of turns of the coil in the same area is, the improvement of the inductance value is not facilitated, the upper limit of the increase of the line thickness is limited, and the process difficulty for preparing the lead with larger thickness is increased.

The embodiment of the application provides an integrated inductor of circuit board, it can be applied to electronic equipment such as cell-phone, panel computer, and the electronic equipment of this application uses the cell-phone to illustrate as the example, should not understand the restriction to this application protection scope.

Referring to fig. 1 to 3, an embodiment of a first aspect of the present application provides a circuit board integrated inductor 100, which includes: the circuit board 10 and the magnetic layer 30. The circuit board 10 includes a substrate 11 and a coil 13, the coil 13 is embedded in the substrate 11, and the coil 13 includes at least two parallel conductive wire layers 1311. A magnetic layer 30, the magnetic layer 30 is carried on the circuit board 10 and at least partially overlaps the coil 13.

Alternatively, the circuit board 10 may be a flexible circuit board 10 (FPC) or a printed circuit board 10 (PCB), which is not particularly limited in this application.

The number of the coils 13 on the circuit board 10 may be one or more, for example, but not limited to, 1, 2, 3, etc., and the specific number of the coils 13 may be set according to the actual application requirements, which is not specifically limited in this application. The plurality of fingers is more than two or equal to or more than two. It is understood that each coil 13 may be, but is not limited to being, a portion of one turn coil 13 (e.g., half turn coil 13, 0.3 turn coil 13, etc.), one turn coil 13, two turn coils 13, three turn coils 13, four turn coils 13, five turn coils 13, etc. The more the number of turns of the coil 13 is, the larger the inductance value is under the condition that other conditions are not changed, and therefore, the number of turns of the coil 13 can be designed according to the application scene, the inductance value to be achieved, and the like, and the present application is not particularly limited.

The coil 13 is embedded in the substrate 11, and may be that a part of the coil 13 is wrapped by the substrate 11 and a part of the coil is exposed out of the substrate 11; the coil 13 may be wrapped in the substrate 11.

The magnetic layer 30 at least partially overlaps the coil 13, it being understood that the magnetic layer 30 is at least partially disposed directly opposite the coil 13; it will also be appreciated that the front projection of the magnetic layer 30 onto the substrate 11 at least partially overlaps the front projection of the coil 13 onto the substrate 11. The magnetic layer 30 at least partially overlaps the coil 13, and may be that the front projection of the magnetic layer 30 on the substrate 11 partially overlaps the front projection of the coil 13 on the substrate 11; the front projection of the magnetic layer 30 on the substrate 11 may also fall within the range of the front projection of the coil 13 on the substrate 11; it is also possible that the front projection of the coil 13 onto the substrate 11 falls within the range of the front projection of the magnetic layer 30 onto the substrate 11.

The circuit board integrated inductor 100 of the first embodiment of the present application includes a circuit board 10 and a magnetic layer 30; the circuit board 10 includes a substrate 11 and a coil 13, the coil 13 is embedded in the substrate 11, and the coil 13 includes at least two parallel conductive wire layers 1311. In this way, under the condition that the total thickness or total cross-sectional area of the wires forming the coil 13 (i.e., the total cross-sectional area of the wires) is the same, the thickness of the single-layer wire layer 1311 can be made thinner, the utilization rate of the cross-sectional area of each wire layer 1311 can be improved, the alternating current resistance of the whole coil 13 is reduced, the alternating current copper loss caused by the skin effect of the coil 13 at high frequency is reduced, and the inductance efficiency of the circuit board integrated inductor 100 is improved. In addition, the circuit board integrated inductor 100 of the embodiment integrates the inductor on the circuit board 10, so that the electronic equipment can be miniaturized and ultrathin when the inductor is applied to the electronic equipment, and the inductor and the circuit board 10 are prepared together without independent mounting, thereby improving the packaging efficiency. In addition, the inductor is integrated in the circuit board 10, so that the position of the circuit board 10 corresponding to the inductor can be saved for mounting other components, the area on the circuit board 10 is saved, and the wiring and piece distribution capacity of the circuit board 10 is enhanced.

Optionally, on the circuit board integrated inductor 100, the size of the inductor portion may be: a rectangular structure with a length ranging from 0.4mm to 4mm, a width ranging from 0.4mm to 4mm and a height ranging from 0.1mm to 1.5 mm. The size of the inductance part is overlarge, which is not beneficial to the miniaturization of the inductance part, and the application value of the integrated inductance is not high; when the size of the inductance section is too small, the existing technology is difficult to realize.

Optionally, the coil 13 comprises at least one layer of sub-coils 13a. As shown in fig. 3, when the coil 13 includes at least two layers of sub-coils 13a, the at least two layers of sub-coils 13a are sequentially stacked and spaced apart, and each of the sub-coils 13a includes at least two wire layers 1311 connected in parallel. Each of the sub-coils 13a includes at least two conductive wire layers 1311 connected in parallel, and it is understood that each of the sub-coils 13a is formed by at least two conductive wire layers 1311 connected in parallel, and any two adjacent sub-coils 13a are electrically connected in sequence. Each sub-coil 13a comprises at least two parallel wire layers 1311, so that the utilization rate of the cross-sectional area of each wire layer 1311 can be better improved, the alternating current resistance of the coil 13 is reduced, the alternating current copper loss caused by the skin effect of the coil 13 at high frequency is reduced, and the inductance efficiency of the circuit board integrated inductor 100 is improved.

Alternatively, the coil 13 may include, but is not limited to, one layer of sub-coil 13a, two layers of sub-coils 13a, three layers of sub-coils 13a, four layers of sub-coils 13a, five layers of sub-coils 13a, six layers of sub-coils 13a, seven layers of sub-coils 13a, eight layers of sub-coils 13a, and the like.

Alternatively, each of the sub-coils 13a may include, but is not limited to, two wire layers 1311 in parallel, three wire layers 1311 in parallel, four wire layers 1311 in parallel, five wire layers 1311 in parallel, six wire layers 1311 in parallel, and the like.

Referring to fig. 4 and 5, in some embodiments, the coil 13 includes a main body 131, a first lead 133, and a second lead 135. The main body 131 includes at least one layer of sub-coils 13a, and when the main body 131 includes at least two layers of sub-coils 13a, the at least two layers of sub-coils 13a are sequentially arranged at intervals and are sequentially electrically connected; the first lead wire 133 and the second lead wire 135 are electrically connected to both end portions of the body portion 131, respectively, and the first lead wire 133 and the second lead wire 135 are spaced apart from each other on the same side of the body portion 131. In other embodiments of the present application, the first lead 133 and the second lead 135 may also be located on two opposite sides or adjacent two sides of the main body 131, and when the first lead 133 and the second lead 135 are located on the same side of the main body 131, the coil 13 may have a greater length when the inductance device area of the circuit board integrated inductor 100 is the same and the number of layers of the coil 13 is the same, so that the inductance value of the circuit board integrated inductor 100 may be higher, compared to when the first lead 133 and the second lead 135 are located on two opposite sides or adjacent two sides of the main body 131.

Specifically, when the main body 131 includes one layer of sub-coils 13a, both end portions of the main body 131 are located at the same layer, and when the main body 131 includes at least two layers of sub-coils 13a stacked in order, one end portion of the main body 131 is located at the uppermost layer of sub-coils 13a, and the other end portion is located at the lowermost layer of sub-coils 13a.

In some embodiments, the main body 131 includes at least two layers of sub-coils 13a, where the at least two layers of sub-coils 13a are sequentially stacked and electrically connected, each layer of sub-coil 13a has an opening 1301, the openings 1301 of the at least two layers of sub-coils 13a are staggered, and along the stacking direction of the at least two layers of sub-coils 13a, the at least two layers of sub-coils 13a overlap except for the portion of the opening 1301 corresponding to each layer of sub-coil 13a. When the main body 131 includes at least two layers of sub-coils 13a, if the at least two layers of sub-coils 13a are arranged in a staggered manner, a part of the magnetic field generated by one layer of sub-coil 13a may be offset by the magnetic field generated by the other layer of sub-coil 13a in the adjacent two layers of sub-coils 13a, so that the magnetic field intensity of the whole coil 13 is weakened, and when the at least two layers of sub-coils 13a are overlapped, the weakening effect between the layers of the adjacent sub-coils 13a is weakened as much as possible, so that the area of the inductor is utilized to the maximum extent, and the synergistic strengthening effect of the adjacent sub-coils 13a is realized to the maximum extent.

It will be appreciated that at least two layers of sub-coils 13a of the main body portion 131 are translated in the stacking direction, but the openings 1301 of each layer of sub-coils 13a are arranged offset.

In some embodiments, each layer of the sub-coil 13a includes a first end 1303 and a second end 1305, the first end 1303 and the second end 1305 are disposed opposite to each other, and the first end 1303 and the second end 1305 define the opening 1301. The first end 1303 and the second end 1305 of each layer of sub-coils 13a are arranged opposite each other, such that no other partial coil 13 is present between any two opposite parts of the sub-coils 13a in the same layer of sub-coils 13 a. In this way, the existence of another part of the coil 13, for example, the coil 13 with an e-shaped structure, between two opposite parts of the sub-coil 13a in the same layer of sub-coil 13a can be better avoided, and the mutual cancellation between magnetic fields generated by different parts of the sub-coil 13a after the coil 13 is electrified can be better avoided, so that the integrated inductor 100 of the circuit board has a higher inductance value.

Alternatively, the shape of the main body portion 131 may be a rectangular structure or an annular structure like a rectangular structure. In other words, the body portion 131 is shaped like a square-shaped structure. "rectangular-like structure" means a structure in which the entire outline is rectangular, with chamfers at four corners of the rectangle, or a portion of the rectangle has the shape of the opening 1301, or the like.

Referring to fig. 6, in an embodiment, the main body 131 includes a first edge 131a, a second edge 131b, a third edge 131c, and a fourth edge 131d, and the opening 1301, the first lead 133, and the second lead 135 are all located on the first edge 131a of the main body 131.

Optionally, the first lead 133 and the second lead 135 also each include at least two wire layers 1311 in parallel. Alternatively, the two wire layers 1311 of the sub-coil 13a disposed in the same layer as the first lead 133 (i.e., the sub-coil 13a electrically connected to the first lead 133) may be electrically connected at the lead-out via. The two wire layers 1311 of the sub-coil 13a disposed in the same layer as the second lead 135 (i.e., the sub-coil 13a electrically connected to the second lead 135) may be electrically connected at the lead exit via.

In some embodiments, the thickness of each of the wire layers 1311 is less than or equal to 2 times the skin depth of the wire layers 1311 at the operating frequency of the circuit board integrated inductor 100 along the stacking direction of the at least two wire layers 1311. In other words, the thickness of each of the conductive layers 1311 is less than 2 times the skin depth of the conductive layer 1311 at the operating frequency of the circuit board integrated inductor 100 along the lamination direction of the circuit board 10 and the magnetic layer 30. Therefore, the whole cross-sectional area of the wire layer 1311 can be enabled to conduct current effectively, the utilization rate of wires is improved, the current is distributed more uniformly in the wire layer 1311, the alternating current resistance of the coil 13 is reduced, the alternating current copper loss caused by the skin effect of the coil 13 under high frequency is reduced, and the inductance efficiency of the circuit board integrated inductor 100 is improved.

Alternatively, the circuit board integrated inductor 100 of the present application may be adapted to operate at a frequency of 2MHz to 50MHz. Specifically, it may be, but is not limited to, 2MHz, 5MHz, 10MHz, 15MHz, 20MHz, 25MHz, 30MHz, 35MHz, 40MHz, 45MHz, 50MHz, etc. The higher the operating frequency of the circuit board integrated inductor 100, the smaller the skin depth of the wire layer 1311, and the more pronounced the reduction in ac copper loss due to skin effects with the scheme of the embodiments of the present application.

In the embodiments of the present application, when reference is made to the numerical ranges a to b, it means that the numerical value may be any numerical value between a to b, including the end point value a, and including the end point value b, unless otherwise specified.

It should be noted that, the integrated circuit board inductor 100 according to the embodiment of the present application is also suitable for the case that the operating frequency is less than 2MHz, but when the operating frequency is less than 2MHz, the skin depth of the conductive wire layer 1311 of the integrated circuit board inductor 100 is larger, the effect of the skin effect of the conductive wire layer 1311 on the loss is not obvious, and the effect of reducing the loss is limited by adopting the method, however, the difficulty of depositing a single layer of conductive material (such as copper), particularly the difficulty of depositing the conductive wire layer 1311 (such as copper layer) with a thicker thickness can still be reduced.

In some embodiments, the thickness d1 of each of the wire layers 1311 along the stacking direction of the at least two wire layers 1311 ranges from: d1 is less than or equal to 5 mu m and less than or equal to 94 mu m. Further, the thickness d1 of each of the wiring layers 1311 is in the range of 10 μm.ltoreq.d1.ltoreq.50μm. Specifically, the thickness of each of the wire layers 1311 may be, but is not limited to, 5 μm, 8 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, 55 μm, 60 μm, 65 μm, 70 μm, 75 μm, 80 μm, 85 μm, 90 μm, 94 μm, etc. The thickness of the wire layer 1311 is too thin to reach the required thickness of the sub-coil 13a, and more wire layers 1311 are required, so that the process steps for preparing the sub-coil 13a are added, and the preparation cost of the integrated inductor 100 of the circuit board is increased; the thickness of the conductive layer 1311 is too thick, which may exceed twice the skin depth of the conductive layer 1311 with a higher operating frequency, so that the current is mainly distributed on the surface of the conductive layer 1311, and the current distribution in the central portion of the conductive layer 1311 is less, thereby wasting the cross-sectional area of the conductive layer 1311, improving the total impedance, and increasing the difficulty of conductive material deposition due to the too thick conductive layer 1311.

Alternatively, the material of the coil 13 may be, but is not limited to, at least one of copper, silver, and other conductive metals or alloys. Each of the conductor layers 1311 of each of the sub-coils 13a may be formed on both sides of the support layer by conventional PCB process steps of exposure, development, etching, film removal, etc., and at least two of the conductor layers 1311 are connected in parallel to at least two of the conductor layers 1311 of each of the sub-coils 13a by steps of via holes, deposition of conductive material, etc., and at least two of the sub-coils 13a are connected electrically (in series) in sequence by steps of via holes, deposition of conductive material, etc. The via holes of the adjacent two layers of sub-coils 13a are not easy to be oversized, the impedance of the coils 13 can be increased due to oversized via holes, and the implementation of the process is not facilitated due to undersize via holes.

In some embodiments, when the coil 13 is a copper coil 13, each of the wire layers 1311 is a copper wire layer 1311, and when the operating frequency of the circuit board integrated inductor 100 is 2MHz to 50MHz, the skin depth of the wire layer 1311 is 9 μm to 47 μm, and in this case, the thickness of the wire layer 1311 may be 18 μm to 94 μm. For example, when the operating frequency of the integrated circuit board inductor 100 is 2MHz and the skin depth of the copper wire layer 1311 is 47 μm, the thickness of the wire layer 1311 may be 94 μm or less. Also for example, when the operating frequency of the integrated circuit board inductor 100 is 50MHz and the skin depth of the copper wire layer 1311 is 9 μm, the thickness of the wire layer 1311 may be less than or equal to 18 μm.

Referring to fig. 7, in some embodiments, a distance w1 between an outer contour of the front projection of the main body 131 on the surface of the substrate 11 and an outer contour of the front projection of the magnetic layer 30 (i.e. an outer contour of the integrated inductor corresponding to the integrated inductor of the circuit board) on the surface of the substrate 11 is in a range of: w1 is less than or equal to 30 mu m and less than or equal to 300 mu m. Further, a distance w1 between an outer contour of the orthographic projection of the main body 131 on the surface of the substrate 11 and an outer contour of the orthographic projection of the magnetic layer 30 on the surface of the substrate 11 is in a range of: w1 is less than or equal to 50 mu m and less than or equal to 200 mu m. Further, a distance w1 between an outer contour of the orthographic projection of the main body 131 on the surface of the substrate 11 and an outer contour of the orthographic projection of the magnetic layer 30 on the surface of the substrate 11 is in a range of: w1 is more than or equal to 80 mu m and less than or equal to 160 mu m. Specifically, the distance w1 between the outer contour of the orthographic projection of the main body portion 131 on the surface of the substrate 11 and the outer contour of the orthographic projection of the magnetic layer 30 on the surface of the substrate 11 may be, but is not limited to, 30 μm, 50 μm, 80 μm, 100 μm, 120 μm, 150 μm, 180 μm, 200 μm, 230 μm, 250 μm, 280 μm, 300 μm, etc.

The distance w1 between the front projected outline of the main body 131 on the surface of the substrate 11 and the front projected outline of the magnetic layer 30 on the surface of the substrate 11 is too large or too small, which affects the inductance value of the integrated circuit board inductor 100. When the coil 13 is supplied with current, magnetic lines of force in the loop of the body 131 of the coil 13 and magnetic lines of force outside the loop form a closed loop. The area in the loop of the main body 131 is proportional to the magnetic resistance of the coil 13, and when the inductance size (the size of the magnetic layer 30) is fixed, the larger the coil 13, the larger the area in the loop, the larger the magnetic resistance in the loop, the smaller the area outside the loop and the smaller the magnetic resistance outside the loop; the size of the ring of the main body 131 also affects the length of the ring-shaped outer magnetic circuit, and the larger the ring is, the longer the effective length side of the coil 13 is, and the inductance value of the inductance can be increased, but the longer the center of the ring-shaped outer region is, the longer the distance side from the center of the ring to the center of the ring is, the larger the ring-shaped outer magnetic circuit is, and the ring-shaped outer magnetic resistance is increased, so that the size of the coil 13 needs to be balanced between the two. When w1 is too small, the inductance value of the integrated circuit board inductor 100 is reduced, and when w1 is too large, the effective length of the coil 13 is shortened, and the inductance value of the integrated circuit board inductor 100 is also reduced. When 80 μm.ltoreq.w1.ltoreq.160 μm may enable the inductance value of the circuit board integrated inductor 100 to have a higher inductance value in the case where the size of the magnetic layer 30 is fixed.

In the present embodiment, the surface of the substrate 11 refers to the surface of the substrate 11 on which related components such as a processor, a memory, and the like are mounted.

Referring to fig. 7 and 8, in one embodiment, the substrate 11 includes an insulating layer 111, and the insulating layer 111 is disposed between any two adjacent conductive wire layers 1311; the thickness d2 of each of the insulating layers 111 in the stacking direction of the at least two wiring layers 1311 ranges from: d2 is more than or equal to 50 μm and less than or equal to 500 μm. In other words, the interval between the adjacent two wire layers 1311 of the coil 13 ranges from 50 μm to 500 μm. Further, in the stacking direction of the at least two wire layers 1311, the thickness d2 of each insulating layer 111 ranges from: d2 is less than or equal to 100 mu m and less than or equal to 250 mu m. Specifically, the thickness d2 of each of the insulating layers 111 may be, but is not limited to, 50 μm, 80 μm, 100 μm, 120 μm, 150 μm, 180 μm, 200 μm, 220 μm, 250 μm, 280 μm, 300 μm, 320 μm, 350 μm, 380 μm, 400 μm, 420 μm, 450 μm, 480 μm, 500 μm, etc. Although the coil 13 is formed by using at least two wire layers 1311 connected in parallel, the skin effect of each wire layer 1311 is reduced, the ac impedance may still be large due to the proximity effect between the adjacent two wire layers 1311, and thus the thickness of the insulating layer 111 cannot be too thin. When the thickness of the insulating layer 111 is too thick, the thickness of the inductor in the integrated inductor 100 of the circuit board is increased, the space of the circuit board 10 is occupied, and the difficulty of the via hole (i.e. the difficulty of the opening) of the insulating layer 111 is increased.

It will be appreciated that any two adjacent wire layers 1311 are insulated from each other by the insulating layer 111. Optionally, two wire layers 1311 on opposite sides of insulating layer 111 are electrically connected by punching vias in insulating layer 111, depositing a conductive metal (e.g., copper).

Alternatively, the insulating layer 111 may include, but is not limited to, at least one including a Polyimide (PI) layer, a polypropylene layer (PP), and the like.

In some embodiments, the substrate 11 further includes a supporting layer 113, where the supporting layer 113 is insulating, and the supporting layer 113 is used to support the coil 13, and when the coil 13 includes at least two layers of sub-coils 13a, the supporting layer 113 is disposed between any two adjacent layers of sub-coils 13 a. Alternatively, the two sub-coils 13a on opposite sides of the support layer 113 are electrically connected by punching vias in the support layer 113, depositing a conductive metal (e.g., copper).

Alternatively, the thickness of each support layer 113 is 10 μm to 60 μm; specifically, it may be, but is not limited to, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, 55 μm, 60 μm, etc. When the thickness of the supporting layer 113 is too small, for example, less than 10 μm, the mechanical properties of the supporting layer 113 are limited, and it is difficult to effectively support the sub-coil 13 a; since the permeability of the supporting layer 113 is low, when the thickness of the supporting layer 113 is too large, for example, more than 60 μm, the length of the magnetic circuit is increased, so that the magnetic resistance is increased, which is disadvantageous for the performance of the resulting inductor.

Alternatively, the support layer 113 may include, but is not limited to, at least one including a Polyimide (PI) layer, a glass fiber/epoxy composite board (Prepreg), and the like.

Referring to fig. 9, in some embodiments, the circuit board 10 further includes a processor 15 and a memory 17, where the processor 15 and the memory 17 are both carried on the surface of the substrate 11, and the processor 15 is electrically connected to the memory 17 and the coil 13, respectively. The processor 15 is used for controlling the magnitude and direction of the current flowing through the coil 13. The memory 17 is used to store program code required for the operation of the processor 15.

Alternatively, the processor 15 comprises one or more general-purpose processors, which may be any type of device capable of processing electronic instructions, including a central processing unit (Central Processing Unit, CPU), microprocessor, microcontroller, main processor, controller, ASIC, and so forth. The processor 15 is operative to execute various types of digitally stored instructions, such as software or firmware programs stored in the memory 17, which enable the computing device to provide a wide variety of services.

Alternatively, the Memory 17 may include a Volatile Memory (RAM), such as a random access Memory (Random Access Memory); the Memory 17 may also include a nonvolatile Memory (Non-VolatileMemory, NVM), such as a Read-Only Memory (ROM), a Flash Memory (FM), a Hard Disk (HDD), or a Solid State Drive (SSD). The memory 17 may also comprise a combination of memories of the kind described above.

Referring to fig. 10, in some embodiments, the magnetic layer 30 includes a magnetic film layer 31. The magnetic film layer 31 is disposed on one side of the substrate 11, and the coils 13 are at least partially overlapped. "magnetic film" refers to a film layer of magnetic material deposited continuously without breaks in between.

Alternatively, the magnetic film layer 31 may be a soft magnetic layer. The soft magnetic has high magnetic permeability, low remanence, low coercivity, low magnetic resistance, small hysteresis loss, and is easy to be magnetized.

Alternatively, the magnetic film layer 31 may be, but is not limited to being, at least one of a magnetic metal, a magnetic alloy, and the like. Optionally, the magnetic metal comprises at least one of iron, cobalt, nickel, and the like. The magnetic alloy may include, but is not limited to including, at least one of an iron-based crystalline alloy, an iron-based amorphous alloy, a cobalt-based amorphous alloy, and the like. The iron-based crystalline alloy includes at least one of FeNi alloy, feCo alloy, feAl alloy, feSiAl alloy, feNiMo alloy, feC alloy, and the like. The iron-based amorphous alloy includes at least one of FeSiB alloy, feB alloy, feNiPB alloy, feNiMoB alloy, and the like. The cobalt-based amorphous alloy includes at least one of CoFeSiB alloy, cofecrsibb alloy, coNiFeSiB alloy, and the like.

The cobalt-based amorphous alloy has higher magnetic permeability than the iron-based crystalline alloy and the iron-based amorphous alloy, and thus, when the magnetic layer 30 requires higher magnetic permeability, at least one of the cobalt-based amorphous alloys may be used for the magnetic film layer 31. Compared with cobalt-based amorphous alloy, the iron-based crystalline alloy and the iron-based amorphous alloy have higher saturation magnetic properties, and when the magnetic layer 30 requires higher saturation magnetic properties, the magnetic film layer 31 may be at least one of the iron-based crystalline alloy and the iron-based amorphous alloy. Compared with the iron-based crystalline alloy, the iron-based amorphous alloy and the cobalt-based amorphous alloy have lower coercive force, and when the magnetic layer 30 requires lower coercive force, the magnetic film layer 31 can be made of the iron-based amorphous alloy and the cobalt-based amorphous alloy. The coercivity (coercive force) refers to the fact that after the magnetic material is saturated and magnetized, when the external magnetic field returns to zero, the magnetic induction intensity B does not return to zero, and the magnetic induction intensity can return to zero only by adding a magnetic field with a certain size in the opposite direction of the original magnetizing field, and the magnetic field is called coercive field, which is also called coercive force.

Alternatively, the thickness of the magnetic film layer 31 is in the range of 0.1 μm to 30 μm along the lamination direction of the substrate 11 and the magnetic film layer 31. Specifically, the thickness of the magnetic film layer 31 may be, but is not limited to, 0.1 μm, 0.5 μm, 1 μm, 2 μm, 4 μm, 6 μm, 8 μm, 10 μm, 13 μm, 15 μm, 18 μm, 20 μm, 23 μm, 25 μm, 28 μm, 30 μm, etc. When the thickness of the magnetic film 31 is too small, the contribution of the magnetic film 31 is limited, which affects the effective permeability of the magnetic layer 30 and the inductance value of the inductor and the saturation current; when the thickness of the magnetic film 31 is too large, the eddy current loss in the magnetic film is large and the deposition difficulty becomes large.

Alternatively, the magnetic film 31 may be formed by Physical Vapor Deposition (PVD) or electrodeposition, and the magnetic film 31 formed by physical vapor deposition has good appearance but is easily detached; the magnetic film 31 produced by the electrodeposition method has good peeling resistance, is not easily peeled off, but has a poor surface morphology. Therefore, when the thickness of the magnetic film layer 31 is less than 1 μm, it can be prepared by a physical vapor deposition method; when the thickness of the magnetic film layer 31 is 1 μm or more, it can be prepared by an electrodeposition method.

Referring to fig. 11, in other embodiments, the magnetic film layer 31 includes a first magnetic film sub-layer 311 and a second magnetic film sub-layer 313, and the first magnetic film sub-layer 311 and the second magnetic film sub-layer 313 are respectively disposed on opposite sides of the coil 13. In other words, the first magnetic film sub-layer 311 and the second magnetic film sub-layer 313 are respectively disposed on opposite sides of the circuit board 10, and at least partially face the coil 13. Compared with the magnetic film layer 31 arranged on one side of the coil 13, the first magnetic film sub-layer 311 and the second magnetic film sub-layer 313 are respectively arranged on the opposite sides of the coil 13, so that the magnetic resistance can be better reduced, and the inductance value of the integrated circuit board inductor 100 can be improved.

Alternatively, the first magnetic film sub-layer 311 may be, but is not limited to being, at least one of a magnetic metal, a magnetic alloy, and the like. The second magnetic film sub-layer 313 may be, but is not limited to being, at least one of a magnetic metal, a magnetic alloy, and the like. For a detailed description of the magnetic metal and the magnetic alloy, please refer to the description of the corresponding parts above, and the detailed description is omitted herein.

Alternatively, the thickness of the first magnetic film sub-layer 311 is in the range of 0.1 μm to 30 μm along the lamination direction of the first magnetic film sub-layer 311, the substrate 11, and the second magnetic film sub-layer 313. Specifically, the thickness of the first magnetic film sub-layer 311 may be, but is not limited to, 0.1 μm, 0.5 μm, 1 μm, 2 μm, 4 μm, 6 μm, 8 μm, 10 μm, 13 μm, 15 μm, 18 μm, 20 μm, 23 μm, 25 μm, 28 μm, 30 μm, etc. When the thickness of the first magnetic film sub-layer 311 is too small, the contribution of the first magnetic film sub-layer 311 is limited, which affects the effective permeability of the magnetic layer 30 and the inductance value of the inductor and the saturation current; when the thickness of the first magnetic film sub-layer 311 is too large, the first magnetic film sub-layer 311 may cause eddy current loss in the magnetic film to be large, and the deposition difficulty to be large.

Alternatively, the thickness of the second magnetic film sub-layer 313 is in the range of 0.1 μm to 30 μm along the lamination direction of the first magnetic film sub-layer 311, the substrate 11, and the second magnetic film sub-layer 313. Specifically, the thickness of the second magnetic film sub-layer 313 may be, but is not limited to, 0.1 μm, 0.5 μm, 1 μm, 2 μm, 4 μm, 6 μm, 8 μm, 10 μm, 13 μm, 15 μm, 18 μm, 20 μm, 23 μm, 25 μm, 28 μm, 30 μm, etc. When the thickness of the second magnetic film sub-layer 313 is too small, the contribution of the second magnetic film sub-layer 313 is limited, affecting the effective permeability of the magnetic layer 30 and the inductance value of the inductor and the saturation current; when the thickness of the second magnetic film sub-layer 313 is too large, the second magnetic film sub-layer 313 may cause eddy current loss in the magnetic film to be large, and deposition difficulty to be large.

Referring to fig. 12, in other embodiments, the magnetic film layer 31 further includes a third magnetic film sub-layer 315, where the third magnetic film sub-layer 315 is disposed through the substrate 11 and is located at the periphery of the coil 13, and the third magnetic film sub-layer 315 is connected to the first magnetic film sub-layer 311 and the second magnetic film sub-layer 313 respectively. The first magnetic film sub-layer 311 and the second magnetic film sub-layer 313 are respectively disposed on opposite sides of the circuit board 10, the middle is insulated by the substrate 11, the substrate 11 is insulated, the magnetic permeability is generally 1, the magnetic resistance is relatively large, and the third magnetic film sub-layer 315 is disposed to communicate the first magnetic film sub-layer 311 with the second magnetic film sub-layer 313, so as to form a closed magnetic loop, reduce the magnetic resistance of the magnetic film layer 31, and improve the inductance value (i.e., inductance value) of the integrated circuit board inductor 100. In addition, the third magnetic film sub-layer 315 is disposed on the side of the coil 13, so as to reduce the magnetic leakage phenomenon of the integrated inductor 100 of the circuit board and improve the electromagnetic interference (EMI) performance.

It will be appreciated that a third magnetic film sub-layer 315 is deposited in the holes at a location on the substrate 11 surrounding the outer circumference of the coil 13 and corresponding to the outer circumferences of the first magnetic film sub-layer 311 and the second magnetic film sub-layer 313 to connect the first magnetic film sub-layer 311 with the second magnetic film sub-layer 313.

Referring to fig. 13, optionally, the third magnetic film sub-layer 315 may further include a plurality of magnetic film portions 3151 disposed around the periphery of the coil 13 at intervals, each of the magnetic film portions 3151 is connected to the first magnetic film sub-layer 311 and the second magnetic film sub-layer 313, and the plurality of magnetic film portions 3151 are insulated from each other by the substrate 11.

Referring to fig. 14, the third magnetic film sub-layer 315 may be a continuous magnetic film portion 3151 around the periphery of the coil 13; in other words, the third magnetic film sub-layer 315 is continuously disposed around the outer circumference of the coil 13.

Compared with the plurality of magnetic film portions 3151, when the third magnetic film sub-layer 315 is the continuous magnetic film portion 3151, the magnetic resistance of the integrated circuit board inductor 100 is smaller, the inductance value is higher, and the magnetic leakage phenomenon can be better reduced, but the support of the substrate 11 to the inductance portion is weakened, and the mechanical property of the integrated circuit board inductor 100 is reduced. When the third magnetic film sub-layer 315 is a plurality of magnetic film portions 3151 arranged at intervals, the coil 13 can be better supported, and the situation that the coil 13 cannot be effectively supported after the multiple surfaces of the substrate 11 surrounding the coil 13 are broken is avoided. "plurality" means two or more.

In some embodiments, the ratio of the length L1 of the third magnetic film sub-layer 315 to the peripheral length L2 of the magnetic film layer 31 ranges from: L1/L2 is less than or equal to 1/20 and less than or equal to 3/4. The length of the third magnetic film sub-layer 315 is not too large or too small, and when the length of the third magnetic film sub-layer 315 is too small, the length of the position where the first magnetic film sub-layer 311 is connected to the second magnetic film sub-layer 313 is too small, so that the effect of improving the inductance value cannot be achieved; when the length of the third magnetic film sub-layer 315 is too large, the length of the substrate 11 corresponding to the interruption of the periphery of the coil 13 is too long, which cannot support the inductor well, and affects the mechanical performance of the integrated inductor 100.

It will be appreciated that when the third magnetic film sub-layer 315 is a continuous magnetic film portion 3151, the length of the third magnetic film sub-layer 315 is the length of the magnetic film portion 3151 around the coil 13, and when the third magnetic film sub-layer 315 is a plurality of magnetic film portions 3151 arranged at intervals, the length of the third magnetic film sub-layer 315 refers to the sum of the lengths of each magnetic film portion 3151 in the direction around the coil 13.

"the length L1 of the third magnetic film sub-layer 315" refers to the length of the third magnetic film sub-layer 315 in the direction surrounding the coil 13.

For example, as shown in fig. 14, in the embodiment of fig. 14, the first magnetic film sub-layer 311 overlaps the second magnetic film sub-layer 313, the length L1 of the third magnetic film sub-layer 315 is the sum of the lengths L0 of the three magnetic film portions 3151 along the outer circumference of the first magnetic film sub-layer, and the outer circumference length L2 of the magnetic film layer 31 is the circumference of the first magnetic film sub-layer 311.

Specifically, the ratio of the length L1 of the third magnetic film sub-layer 315 to the peripheral length L2 of the magnetic film layer 31 may be, but is not limited to, 1/20, 1/18, 1/16, 1/14, 1/12, 1/10, 1/8, 1/6, 1/4, 1/2, 3/4, etc.

In some embodiments, the third magnetic film sub-layer 315 is located on the other peripheral side of the main body portion 131 except the peripheral side on which the first and second leads 133 and 135 are provided, as shown in fig. 12. If the magnetic field strength of the first lead 133 and the second lead 135 of the coil 13 is large, and the third magnetic film sub-layer 315 is disposed too close to the first lead 133 and the second lead 135, magnetic saturation is likely to occur at the position of the third magnetic film sub-layer 315 close to the first lead 133 and the second lead 135, which is not beneficial to the improvement of the inductance value of the integrated circuit board inductor 100.

In one embodiment, the main body 131 includes a first edge 131a, a second edge 131b, a third edge 131c and a fourth edge 131d (as shown in fig. 6), and the first lead 133 and the second lead 135 are both located on the first edge 131a of the main body 131. The third magnetic film sub-layer 315 is disposed on at least one or at least two or all of the second side 131b, the third side 131c and the fourth side 131 d.

In some embodiments, the shortest distance s1 between the first lead 133 and the third magnetic film sub-layer 315 is greater than or equal to 0.5mm, and the shortest distance s2 between the second lead 135 and the third magnetic film sub-layer 315 is greater than or equal to 0.5mm. If the magnetic field strength of the first lead 133 and the second lead 135 of the coil 13 is large, and the third magnetic film sub-layer 315 is disposed too close to the first lead 133 and the second lead 135, magnetic saturation is likely to occur at the position of the third magnetic film sub-layer 315 close to the first lead 133 and the second lead 135, which is not beneficial to the improvement of the inductance value of the integrated circuit board inductor 100. When the shortest distance between the third magnetic film sub-layer 315 and the first lead 133 and the second lead 135 is greater than or equal to 0.5mm, the magnetic saturation phenomenon of the third magnetic film sub-layer 315 can be better avoided.

Further, the shortest distance s1 between the first lead 133 and the third magnetic film sub-layer 315 ranges from: s1 is more than or equal to 0.5mm and less than or equal to 1.5mm; specifically, the shortest distance s1 between the first lead 133 and the third magnetic film sub-layer 315 may be, but is not limited to, 0.5mm, 0.6mm, 0.7mm, 0.8mm, 0.9mm, 1.0mm, 1.1mm, 1.2mm, 1.3mm, 1.4mm, 1.5mm, etc. If the third magnetic film sub-layer 315 is disposed too close to the first lead 133 and the second lead 135, magnetic saturation is likely to occur at the position of the third magnetic film sub-layer 315 close to the first lead 133 and the second lead 135, which is not beneficial to the improvement of the inductance value of the integrated circuit board inductor 100. If the shortest distance between the third magnetic film sub-layer 315 and the first lead 133 and the second lead 135 is too far, the length of the third magnetic film sub-layer 315 will be reduced, and the inductance value is limited or even cannot be increased.

Further, the shortest distance s2 between the second lead 135 and the third magnetic film sub-layer 315 ranges from: s2 is more than or equal to 0.5mm and less than or equal to 1.5mm; specifically, the shortest distance s2 between the second lead 135 and the third magnetic film sub-layer 315 may be, but is not limited to, 0.5mm, 0.6mm, 0.7mm, 0.8mm, 0.9mm, 1.0mm, 1.1mm, 1.2mm, 1.3mm, 1.4mm, 1.5mm, etc. If the third magnetic film sub-layer 315 is disposed too close to the first lead 133 and the second lead 135, magnetic saturation is likely to occur at the position of the third magnetic film sub-layer 315 close to the first lead 133 and the second lead 135, which is not beneficial to the improvement of the inductance value of the integrated circuit board inductor 100. If the shortest distance between the third magnetic film sub-layer 315 and the first lead 133 and the second lead 135 is too far, the length of the third magnetic film sub-layer 315 will be reduced, and the inductance value is limited or even cannot be increased.

Alternatively, third magnetic film sub-layer 315 may be, but is not limited to being, at least one of a magnetic metal, a magnetic alloy, and the like. For a detailed description of the magnetic metal and the magnetic alloy, please refer to the description of the corresponding parts above, and the detailed description is omitted herein.

Referring to fig. 15, in some embodiments, the magnetic layer 30 further includes a magnetic glue layer 33, and the magnetic glue layer 33 is disposed between the coil 13 and the magnetic film layer 31. The magnetic glue layer 33 is arranged between the coil 13 and the magnetic film layer 31, so that the magnetic permeability and the inductance value of the inductor in the circuit board integrated inductor 100 can be improved, and the coil 13 and the magnetic film layer 31 can be arranged in an insulating manner.

It should be noted that, when the magnetic film layer 31 includes the first magnetic film sub-layer 311 and the second magnetic film sub-layer 313, the magnetic glue layer 33 is disposed between the coil 13 and the first magnetic film sub-layer 311, and between the coil 13 and the second magnetic film sub-layer 313. When the magnetic film layer 31 further includes the third magnetic film sub-layer 315, the magnetic glue layer 33 is not disposed between the third magnetic film sub-layer 315 and the coil 13.

In some embodiments, when the coil 13 includes at least two layers of sub-coils 13a, a via hole may be formed in at least one of the insulating layer 111 and the supporting layer 113 to allow the magnetic glue to penetrate into the inside of the coil 13 and between the adjacent two layers of sub-coils 13 a.

Optionally, the magnetic glue layer 33 comprises a resin and magnetic particles (not shown) dispersed in the resin. The magnetic glue layer 33 may be formed by dispersing magnetic particles in a liquid resin to form a magnetic paste, and then coating or printing the magnetic paste on the surface of the circuit board 10, and curing (e.g., uv light curing). The magnetic glue layer 33 refers to a film layer comprising a discontinuous distribution of magnetic material therein, with breaks between the magnetic materials.

Optionally, in the magnetic glue layer 33, the weight fraction of magnetic particles ranges from 30% to 90%; specifically, it may be, but is not limited to, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, etc. When the weight fraction of the magnetic particles in the magnetic glue layer 33 is less than 30%, it is difficult to achieve the effect of improving the magnetic permeability of the inductor in the integrated circuit board inductor 100, and the cost of the integrated circuit board inductor 100 is increased; when the weight fraction of the magnetic particles in the magnetic glue layer 33 is greater than 90%, the magnetic particles in the magnetic paste are difficult to disperse and have insufficient fluidity, and when coating or printing is performed, the gaps of the coils 13 on the surface of the circuit board 10 are difficult to be filled, so that the air gaps between the magnetic glue layer 33 and the coils 13 are excessive, the magnetic resistance becomes large, and the magnetic permeability is reduced.

Alternatively, the average particle diameter D of the magnetic particles is in the range of 5 μm.ltoreq.D.ltoreq.50 μm; specifically, it may be, but is not limited to, 5 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, etc. When the magnetic particles are small, eddy currents are limited to a small extent, and as the magnetic particles increase, the area through which power can flow becomes large, thereby increasing eddy current loss. When the average particle diameter of the magnetic particles is smaller than 5 μm, not only the cost of the magnetic particles is increased, but also the permeability of the magnetic glue layer 33 is reduced, and the meaning of improving the permeability by the magnetic glue layer 33 is lost. When the average particle diameter of the magnetic particles is larger than 50 μm, the eddy current loss is too large, which is detrimental to the performance of the circuit board integrated inductor 100.

Alternatively, the magnetic particles are soft magnetic particles. The soft magnetic has high magnetic permeability, low remanence, low coercivity, low magnetic resistance, small hysteresis loss, and is easy to be magnetized. Optionally, the magnetic particles comprise at least one of ferrite particles, magnetic metal particles, magnetic alloy particles. Ferrite particles have better electrical insulation and lower loss, and magnetic metal particles or magnetic alloy particles have higher magnetic permeability and magnetic saturation induction strength. Therefore, ferrite particles may be selected as the magnetic particles when the flux layer 33 is required to have better electrical insulation and lower loss, and magnetic metal particles or magnetic alloy particles may be selected as the magnetic particles when the flux layer 33 is required to have higher magnetic permeability and magnetic saturation induction strength. Optionally, the ferrite particles comprise at least one of MnZn ferrite, niZn ferrite, and the like. Optionally, the magnetic metal particles comprise at least one of iron, cobalt, nickel, and the like. Optionally, the magnetic alloy particles comprise at least one of an iron-based crystalline alloy, an iron-based amorphous alloy, a cobalt-based amorphous alloy, and the like. The iron-based crystalline alloy includes at least one of FeNi alloy, feCo alloy, feAl alloy, feSiAl alloy, feNiMo alloy, feC alloy, and the like. The iron-based amorphous alloy includes at least one of FeSiB alloy, feB alloy, feNiPB alloy, feNiMoB alloy, and the like. The cobalt-based amorphous alloy includes at least one of CoFeSiB alloy, cofecrsibb alloy, coNiFeSiB alloy, and the like.

The cobalt-based amorphous alloy has higher magnetic permeability than the iron-based crystalline alloy and the iron-based amorphous alloy, and therefore, when the magnetic glue layer 33 requires higher magnetic permeability, the magnetic particles may adopt at least one of the cobalt-based amorphous alloys. Compared with cobalt-based amorphous alloy, the iron-based crystalline alloy and the iron-based amorphous alloy have higher saturation magnetic properties, and when the magnetic glue layer 33 requires higher saturation magnetic properties, the magnetic particles can be at least one of the iron-based crystalline alloy and the iron-based amorphous alloy. Compared with the iron-based crystalline alloy, the iron-based amorphous alloy and the cobalt-based amorphous alloy have lower coercive force, and when the magnetic glue layer 33 requires lower coercive force, the iron-based amorphous alloy and the cobalt-based amorphous alloy can be selected as the magnetic particles.

When the magnetic particles are magnetic alloy particles, the surfaces of the magnetic alloy particles have a passivation layer, which is an insulating layer 111, in other words, the passivation layer is insulating. In some embodiments, a layer of organic resin may be coated on the surface of the magnetic alloy particles to make the magnetic alloy particles insulating. In other embodiments, the magnetic alloy particles may be passivated with phosphoric acid to form a non-conductive passivation layer on the surface of the magnetic alloy particles.

Optionally, the resin comprises at least one of epoxy, polyurethane, acrylate, and the like. In a specific embodiment, when the insulating layer 111 of the circuit board 10 is a glass fiber/epoxy composite board, the resin of the magnetic glue layer 33 may be epoxy, so that the magnetic glue layer 33 has better bonding performance with the circuit board 10 and can be better attached to the circuit board 10.

Alternatively, the magnetic adhesive layer 33 may be formed by: the magnetic paste is formed by dispersing magnetic particles in liquid resin, then a magnetic paste layer is formed on the surface of the circuit board 10 by coating, printing and the like, and then the circuit board is placed under ultraviolet light such as an LED lamp or a mercury lamp to enable the liquid resin to be photo-cured to form solid resin, so that the magnetic glue layer 33 is obtained. In other embodiments, the magnetic slurry layer may also be cured by thermal curing, which is not particularly limited in this application.

Referring to fig. 16, in some embodiments, the circuit board integrated inductor 100 further includes a dielectric layer 35, where the dielectric layer 35 is located between the coil 13 and the magnetic film layer 31, and is used to insulate the coil 13 from the magnetic film layer 31. While ensuring the insulation performance, the higher the permeability of the dielectric layer 35 is, and the higher the inductance value of the manufactured circuit board integrated inductor 100 is.

In some embodiments, dielectric layer 35 is at least one of fiberglass/epoxy composite board, polyimide, polypropylene, polytetrafluoroethylene, and the like. Alternatively, the dielectric layer 35 may be laminated on at least one of the two opposite surfaces of the substrate 11, and laminated so that the dielectric layer 35 is attached to the substrate 11 and covers at least the coil 13.

Alternatively, the thickness of the dielectric layer 35 is in the range of 5 μm to 200 μm in the lamination direction of the substrate 11, the dielectric layer 35, and the magnetic film layer 31 (or in the lamination direction of the first magnetic film sub-layer 311, the dielectric layer 35, the substrate 11, the dielectric layer 35, and the second magnetic film sub-layer 313); specifically, it may be, but is not limited to, 5 μm, 10 μm, 30 μm, 50 μm, 80 μm, 100 μm, 120 μm, 140 μm, 160 μm, 180 μm, 200 μm, etc. The dielectric layer 35 is typically prepared by laminating a ready-made film onto the surface of the circuit board 10, with few dielectric layers 35 currently below 5 μm and at a high cost. When the thickness of the dielectric layer 35 is too thick, the magnetic resistance of the dielectric layer 35 is too large, so that the inductance value of the manufactured circuit board integrated inductor 100 is reduced.

The circuit board integrated inductor 100 of the first aspect of the present application is further described below by way of specific embodiments.

Example 1

The circuit board integrated inductor 100 of the embodiment includes a circuit board 10 and a magnetic layer 30, the circuit board 10 includes a substrate 11 and a coil 13, the coil 13 is embedded in the substrate 11, the coil 13 includes two layers of sub-coils 13a electrically connected, a supporting layer 113 is disposed between two adjacent layers of sub-coils 13a, the thickness of the supporting layer 113 is 12.5 μm, each layer of sub-coils 13a includes two parallel layers of wire layers 1311, the two layers of wire layers 1311 are disposed at intervals through an insulating layer 111, the thickness of each layer of wire layer 1311 is 35 μm, the thickness of the middle insulating layer 111 is 250 μm, the coil 13 is a copper coil 13, the line width of the copper coil 13 is 440 μm, and the line distance is 880 μm; the magnetic layer 30 is a magnetic adhesive layer 33, the magnetic adhesive layer 33 covers two opposite surfaces of the circuit board 10 opposite to the coil 13, the length of the magnetic adhesive layer 33 on each surface of the circuit board 10 is 2.5mm, the width is 1.6mm, the thickness is 50 μm, and the relative magnetic permeability of the magnetic adhesive layer 33 is 12.

Comparative example 1

The circuit board integrated inductor 100 of this comparative example comprises a circuit board 10 and a magnetic layer 30, the circuit board 10 comprises a substrate 11 and a coil 13, the coil 13 is embedded in the substrate 11, the coil 13 comprises two layers of sub-coils 13a electrically connected, a supporting layer 113 is arranged between the two adjacent layers of sub-coils 13a, the thickness of the supporting layer 113 is 12.5 μm, each layer of sub-coils 13a comprises a layer of wire layer 1311, the thickness of each layer of wire layer 1311 is 70 μm, the coil 13 is a copper coil 13, the wire width of the copper coil 13 is 440 μm, and the wire distance is 880 μm; the magnetic layer 30 is a magnetic adhesive layer 33, the magnetic adhesive layer 33 covers two opposite surfaces of the circuit board 10 opposite to the coil 13, the length of the magnetic adhesive layer 33 on each surface of the circuit board 10 is 2.5mm, the width is 1.6mm, the thickness is 50 μm, and the relative magnetic permeability of the magnetic adhesive layer 33 is 12.

The integrated circuit board inductors 100 of example 1 and comparative example 1 were tested for inductance and ac resistance at an operating frequency of 25MHz according to standard GB/T8554-1998 by simulation, and the test results are shown in table 1 below.

Table 1 simulation test data for the circuit board integrated inductor 100 of example 1 and comparative example 1

Example	Example 1	Comparative example 1
			Operating frequency MHz	25	25
Inductance value (nH)	10.2	10.2
			AC resistor (mΩ)	11.4	14.4

As can be seen from the simulation calculation results in table 1, when the total thickness of the sub-coils 13a is the same, the inductance value is equal when each sub-coil 13a includes a single wire layer 1311 and each sub-coil 13a includes two wire layers 1311 connected in parallel, but the ac resistance is significantly reduced when each sub-coil 13a includes two wire layers 1311 connected in parallel, compared to when each sub-coil 13a includes only one wire layer 1311.

The circuit board integrated inductors 100 of example 1 and comparative example 1 were tested for inductance and ac resistance at different operating frequencies according to the standard GB/T8554-1998 by performing simulation calculations, and the test results are shown in table 2 below.

Table 2 simulation test data for the circuit board integrated inductor 100 of example 1 and comparative example 1 at different operating frequencies

As can be seen from the test data in table 2, the greater the operating frequency of the integrated circuit board inductor 100, the more significant the effect of reducing the ac resistance when each sub-coil 13a includes two parallel conductive layers 1311, compared to only one conductive layer 1311 for each sub-coil 13 a.

Example 2

The circuit board integrated inductor 100 of the embodiment includes a circuit board 10 and a magnetic layer 30, the circuit board 10 includes a substrate 11 and a coil 13, the coil 13 is embedded in the substrate 11, the coil 13 includes two electrically connected sub-coils 13a, a supporting layer 113 is disposed between two adjacent sub-coils 13a, the thickness of the supporting layer 113 is 12.5 μm, each sub-coil 13a includes two parallel wire layers 1311, the two wire layers 1311 are disposed at intervals through an insulating layer 111, the thickness of each wire layer 1311 is 35 μm, the thickness of the middle insulating layer 111 is 100 μm, the coil 13 is a copper coil 13, the line width of the copper coil 13 is 440 μm, and the line distance is 880 μm; the magnetic layer 30 is a magnetic adhesive layer 33, the magnetic adhesive layer 33 covers two opposite surfaces of the circuit board 10 opposite to the coil 13, the length of the magnetic adhesive layer 33 on each surface of the circuit board 10 is 2.5mm, the width is 1.6mm, the thickness is 50 μm, and the relative magnetic permeability of the magnetic adhesive layer 33 is 12.

Example 3

The circuit board integrated inductor 100 of the embodiment includes a circuit board 10 and a magnetic layer 30, the circuit board 10 includes a substrate 11 and a coil 13, the coil 13 is embedded in the substrate 11, the coil 13 includes two electrically connected sub-coils 13a, a supporting layer 113 is disposed between two adjacent sub-coils 13a, the thickness of the supporting layer 113 is 12.5 μm, each sub-coil 13a includes two parallel wire layers 1311, the two wire layers 1311 are disposed at intervals through an insulating layer 111, the thickness of each wire layer 1311 is 35 μm, the thickness of the middle insulating layer 111 is 400 μm, the coil 13 is a copper coil 13, the line width of the copper coil 13 is 440 μm, and the line distance is 880 μm; the magnetic layer 30 is a magnetic adhesive layer 33, the magnetic adhesive layer 33 covers two opposite surfaces of the circuit board 10 opposite to the coil 13, the length of the magnetic adhesive layer 33 on each surface of the circuit board 10 is 2.5mm, the width is 1.6mm, the thickness is 50 μm, and the relative magnetic permeability of the magnetic adhesive layer 33 is 12.

The circuit board integrated inductors 100 of examples 1 to 3 were tested for inductance and ac resistance at an operating frequency of 25MHz according to the standard GB/T8554-1998 by performing simulation calculations, and the test results are shown in table 3 below.

Table 3 simulation test data of the circuit board integrated inductor 100 of examples 1 to 3

Example	Example 2	Example 1	Example 3
				Operating frequency MHz	25	25	25
Thickness of insulating layer(μm)	100	250	400
				AC resistor (mΩ)	16.9	11.4	9.5

As can be seen from the test results of table 3, the ac resistance of the circuit board integrated inductor 100 gradually decreases with the increase in the thickness of the insulating layer 111 at the same frequency. Therefore, the thickness of the insulating layer 111 cannot be too small, otherwise the ac resistance of the circuit board integrated inductor 100 will still be large due to the proximity effect.

When the circuit board and the inductor are integrated into a whole, the coil is embedded in the substrate, the magnetic film layers cover the two opposite surfaces of the coil, the magnetic film layers on the two opposite surfaces of the coil are separated by the supporting layer or the insulating layer of the circuit board, the magnetic permeability of the supporting layer or the insulating layer is close to 1, the magnetic film layers on the two opposite surfaces of the coil are used as a large magnetic resistance string to be connected into the whole magnetic circuit, so that the total magnetic resistance of the magnetic circuit is increased, and the inductance of the lower inductor is caused.

Referring to fig. 17 to 19, an embodiment of a second aspect of the present application provides a circuit board integrated inductor 100, which includes a circuit board 10 and a magnetic film layer 31, wherein the circuit board 10 includes a substrate 11 and a coil 13, and the coil 13 is embedded in the substrate 11; the magnetic film layer 31 is carried on the substrate 11, the magnetic film layer 31 includes a first magnetic film sub-layer 311, a second magnetic film sub-layer 313 and a third magnetic film sub-layer 315, the first magnetic film sub-layer 311 and the second magnetic film sub-layer 313 are respectively disposed on opposite sides of the coil 13, the third magnetic film sub-layer 315 is disposed on the substrate 11 in a penetrating manner and is disposed on the periphery of the coil 13, and the third magnetic film sub-layer 315 is respectively connected with the first magnetic film sub-layer 311 and the second magnetic film sub-layer 313.

The circuit board integrated inductor 100 of the second embodiment of the present application includes a circuit board 10 and a magnetic film layer 31, the circuit board 10 includes a substrate 11 and a coil 13, and the coil 13 is embedded in the substrate 11; the magnetic film layer 31 is carried on the substrate 11, the magnetic film layer 31 includes a first magnetic film sub-layer 311, a second magnetic film sub-layer 313 and a third magnetic film sub-layer 315, the first magnetic film sub-layer 311 and the second magnetic film sub-layer 313 are respectively disposed on opposite sides of the coil 13, the third magnetic film sub-layer 315 is disposed on the substrate 11 in a penetrating manner and is disposed on the periphery of the coil 13, and the third magnetic film sub-layer 315 is respectively connected with the first magnetic film sub-layer 311 and the second magnetic film sub-layer 313. The first magnetic film sub-layer 311 and the second magnetic film sub-layer 313 are respectively disposed on opposite sides of the circuit board 10, the middle is insulated by the substrate 11, the substrate 11 is insulated, the magnetic permeability is generally 1, the magnetic resistance is relatively large, and the third magnetic film sub-layer 315 is disposed to communicate the first magnetic film sub-layer 311 with the second magnetic film sub-layer 313, so as to form a closed magnetic loop, reduce the magnetic resistance of the magnetic film layer 31, and improve the inductance value (i.e., inductance) of the integrated inductor 100 of the circuit board. In addition, the third magnetic film sub-layer 315 is disposed on the side of the coil 13, so as to reduce the magnetic leakage phenomenon of the integrated inductor 100 of the circuit board and improve the electromagnetic interference (EMI) performance.

Referring to fig. 20, in some embodiments, the coil 13 includes a main body 131, a first lead 133 and a second lead 135, the first lead 133 and the second lead 135 are electrically connected to two ends of the main body 131, respectively, and the first lead 133 and the second lead 135 are spaced apart from each other on the same side of the main body 131. In other embodiments of the present application, the first lead 133 and the second lead 135 may also be located on two opposite sides or adjacent two sides of the main body 131, and when the first lead 133 and the second lead 135 are located on the same side of the main body 131, the coil 13 may have a greater length under the condition that the same area and the number of layers of the coil 13 are the same, so that the inductance value of the circuit board integrated inductor 100 may be higher, compared to the case that the first lead 133 and the second lead 135 are located on two opposite sides or adjacent two sides of the main body 131.

In some embodiments, the main body 131 includes at least one layer of sub-coils 13a, and when the main body 131 includes at least two layers of sub-coils 13a, the at least two layers of sub-coils 13a are sequentially spaced apart and sequentially electrically connected.

Referring again to fig. 4 and 5, optionally, each of the sub-coils 13a includes at least two wire layers 1311 connected in parallel. In this way, under the condition that the total thickness or total cross-sectional area of each layer of sub-coil 13a (i.e. the total cross-sectional area of the wires) is the same, the thickness of the single-layer wire layer 1311 can be made thinner, the utilization rate of the cross-sectional area of each layer of wire layer 1311 can be improved, the alternating current resistance of the whole coil 13 can be reduced, the alternating current copper loss caused by the skin effect of the coil 13 at high frequency can be reduced, and the inductance efficiency of the circuit board integrated inductor 100 can be improved.

In some embodiments, the thickness d1 of each of the wire layers 1311 along the stacking direction of the at least two wire layers 1311 ranges from: d1 is less than or equal to 5 mu m and less than or equal to 94 mu m.

Referring to fig. 7 and 8 again, in some embodiments, the substrate 11 includes an insulating layer 111, and the insulating layer 111 is disposed between any two adjacent conductive wire layers 1311; the thickness d2 of each of the insulating layers 111 in the stacking direction of the at least two wiring layers 1311 ranges from: d2 is more than or equal to 50 μm and less than or equal to 500 μm. Although the coil 13 is formed by using at least two wire layers 1311 connected in parallel, the skin effect of each wire layer 1311 is reduced, the ac impedance may still be large due to the proximity effect between the adjacent two wire layers 1311, and thus the thickness of the insulating layer 111 cannot be too thin. When the thickness of the insulating layer 111 is too thick, the thickness of the inductor in the integrated inductor 100 of the circuit board is increased, the space of the circuit board 10 is occupied, and the difficulty of the via hole (i.e. the difficulty of the opening) of the insulating layer 111 is increased.

Referring to fig. 9 again, in some embodiments, the circuit board 10 further includes a processor 15 and a memory 17, the processor 15 and the memory 17 are both carried on the surface of the substrate 11, and the processor 15 is electrically connected to the memory 17 and the coil 13, respectively. The processor 15 is used for controlling the magnitude and direction of the current flowing through the coil 13. The memory 17 is used to store program code required for the operation of the processor 15.

In some embodiments, the distance w1 between the front projected outer contour of the main body 131 on the surface of the substrate 11 and the front projected outer contour of the magnetic film 31 on the surface of the substrate 11 is in the range of: w1 is less than or equal to 30 mu m and less than or equal to 300 mu m. The distance w1 between the front projection outer contour of the main body 131 on the surface of the substrate 11 and the front projection outer contour of the magnetic layer 30 on the surface of the substrate 11 is too large or too small, which affects the inductance value of the integrated circuit board inductance 100, when w1 is too small, the inductance value of the integrated circuit board inductance 100 is reduced, and when w1 is too large, the effective length of the coil 13 is shortened, which also reduces the inductance value of the integrated circuit board inductance 100.

It should be noted that, each layer of sub-coil 13a of coil 13 of circuit board integrated inductor 100 according to the second embodiment of the present application may include at least two parallel wire layers 1311, or may include only a single wire layer 1311. For the description of other aspects of the substrate 11 and the coil 13, please refer to the description of the corresponding parts of the embodiments of the first aspect, and the description is omitted here.

Referring to fig. 13 again, optionally, the third magnetic film sub-layer 315 may further include a plurality of magnetic film portions 3151 disposed around the periphery of the coil 13 at intervals, each of the magnetic film portions 3151 being connected to the first magnetic film sub-layer 311 and the second magnetic film sub-layer 313, and the plurality of magnetic film portions 3151 being disposed through the substrate 11 in an insulating manner.

Referring again to fig. 14, the third magnetic film sub-layer 315 may alternatively be a continuous magnetic film portion 3151 around the periphery of the coil 13.

Compared with the plurality of magnetic film portions 3151, when the third magnetic film sub-layer 315 is the continuous magnetic film portion 3151, the magnetic resistance of the integrated circuit board inductor 100 is smaller, the inductance value is higher, and the magnetic leakage phenomenon can be better reduced, but the support of the substrate 11 to the inductance portion is weakened, and the mechanical property of the integrated circuit board inductor 100 is reduced. When the third magnetic film sub-layer 315 is a plurality of magnetic film portions 3151 arranged at intervals, the coil 13 can be better supported, and the situation that the coil 13 cannot be effectively supported after the multiple surfaces of the substrate 11 surrounding the coil 13 are broken is avoided.

In some embodiments, the ratio of the length L1 of the third magnetic film sub-layer 315 to the peripheral length L2 of the magnetic film layer 31 ranges from: L1/L2 is less than or equal to 1/20 and less than or equal to 3/4. Specifically, the ratio of the length L1 of the third magnetic film sub-layer 315 to the peripheral length L2 of the magnetic film layer 31 may be, but is not limited to, 1/20, 1/18, 1/16, 1/14, 1/12, 1/10, 1/8, 1/6, 1/4, 1/2, 3/4, etc. The length of the third magnetic film sub-layer 315 is not too large or too small, and when the length of the third magnetic film sub-layer 315 is too small, the length of the position where the first magnetic film sub-layer 311 is connected to the second magnetic film sub-layer 313 is too small, so that the effect of improving the inductance value cannot be achieved; when the length of the third magnetic film sub-layer 315 is too large, the length of the substrate 11 corresponding to the interruption of the periphery of the coil 13 is too long, which cannot support the inductor well, and affects the mechanical performance of the integrated inductor 100.

In some embodiments, the third magnetic film sub-layer 315 is located on the other peripheral side of the body portion 131 than the peripheral side on which the first and second leads 133, 135 are located. If the magnetic field strength of the first lead 133 and the second lead 135 of the coil 13 is large, and the third magnetic film sub-layer 315 is disposed too close to the first lead 133 and the second lead 135, magnetic saturation is likely to occur at the position of the third magnetic film sub-layer 315 close to the first lead 133 and the second lead 135, which is not beneficial to the improvement of the inductance value of the integrated circuit board inductor 100.

Further, the shortest distance s1 between the first lead 133 and the third magnetic film sub-layer 315 ranges from: s1 is more than or equal to 0.5mm and less than or equal to 1.5mm; further, the shortest distance s2 between the second lead 135 and the third magnetic film sub-layer 315 ranges from: s2 is more than or equal to 0.5mm and less than or equal to 1.5mm.

For a detailed description of the magnetic film layer 31, the first magnetic film sub-layer 311, the second magnetic film sub-layer 313, and the third magnetic film sub-layer 315, and other parts that are the same as those described in the first embodiment, please refer to the description of the first embodiment of the present application, and the detailed description is omitted herein.

Referring again to fig. 18, in some embodiments, the circuit board integrated inductor 100 of the present embodiment further includes a magnetic glue layer 33, where the magnetic glue layer 33 is disposed between the coil 13 and the first magnetic film sub-layer 311, and between the coil 13 and the second magnetic film sub-layer 313.

It will be appreciated that no flux layer 33 is provided between the third flux sublayer 315 and the coil 13. For a detailed description of other parts of the magnetic glue layer 33 that are the same as the above-mentioned embodiments of the first aspect, please refer to the description of the embodiments of the first aspect of the present application, and a detailed description is omitted herein.

For a detailed description of other parts of the magnetic glue layer 33 that are the same as the above-mentioned embodiments of the first aspect, please refer to the description of the embodiments of the first aspect of the present application, and a detailed description is omitted herein.

Referring to fig. 21, in some embodiments, the circuit board integrated inductor 100 of the present embodiment further includes a dielectric layer 35, where the dielectric layer 35 is located between the coil 13 and the magnetic film layer 31, for insulating the coil 13 from the magnetic film layer 31. While ensuring the insulation performance, the higher the permeability of the dielectric layer 35 is, and the higher the inductance value of the manufactured circuit board integrated inductor 100 is. For a detailed description of the other portions of the dielectric layer 35 that are the same as the embodiments of the first aspect, please refer to the description of the embodiments of the first aspect of the present application, and the detailed description is omitted herein.

For a detailed description of the other portions of the dielectric layer 35 that are the same as the embodiments of the first aspect, please refer to the description of the embodiments of the first aspect of the present application, and the detailed description is omitted herein.

The second aspect of the present application is the same as the embodiments of the first aspect, please refer to the description of the corresponding portions of the embodiments of the first aspect, and the detailed description is omitted herein.

The circuit board integrated inductor 100 of the second aspect of the present application is further described below by way of specific embodiments.

Example 4

The circuit board integrated inductor 100 of the present embodiment includes a circuit board 10 and a magnetic film layer 31, the circuit board 10 includes a substrate 11 and a coil 13, the coil 13 is embedded in the substrate 11, the coil 13 includes two layers of sub-coils 13a electrically connected, and a supporting layer 113 is disposed between the two layers of sub-coils 13 a; the magnetic film layer 31 is carried on the substrate 11, the magnetic film layer 31 includes a first magnetic film sub-layer 311, a second magnetic film sub-layer 313 and a third magnetic film sub-layer 315, the first magnetic film sub-layer 311 and the second magnetic film sub-layer 313 are respectively disposed on opposite sides of the coil 13, the third magnetic film sub-layer 315 is disposed on the substrate 11 in a penetrating manner and is disposed on the periphery of the coil 13, and the third magnetic film sub-layer 315 is respectively connected with the first magnetic film sub-layer 311 and the second magnetic film sub-layer 313; a dielectric layer 35 is further disposed between the coil 13 and the first magnetic film sub-layer 311 and between the coil 13 and the second magnetic film sub-layer 313; the length of the inductance part of the circuit board integrated inductance 100 is 2.0mm, the width is 1.2mm, and the height is 0.25mm; the thickness of the support layer 113 is 50 μm; the coil 13 is a copper coil 13, the line width of the coil 13 is 260 μm, the line thickness is 70 μm, and the line distance is 140 μm; the dielectric layer 35 is a glass fiber/epoxy resin composite board, and the thickness of the dielectric layer 35 is 30 mu m; the first magnetic film sub-layer 311, the second magnetic film sub-layer 313 and the third magnetic film sub-layer 315 are made of FeNi alloy, the relative magnetic permeability is 1000, the electrical conductivity is 40KS/m, and the thicknesses of the first magnetic film sub-layer 311 and the second magnetic film sub-layer 313 are 20 μm.

Comparative example 2

The circuit board integrated inductor 100 of the present embodiment includes a circuit board 10 and a magnetic film layer 31, the circuit board 10 includes a substrate 11 and a coil 13, the coil 13 is embedded in the substrate 11, the coil 13 includes two layers of sub-coils 13a electrically connected, and a supporting layer 113 is disposed between the two layers of sub-coils 13 a; the magnetic film layer 31 is carried on the substrate 11, the magnetic film layer 31 includes a first magnetic film sub-layer 311 and a second magnetic film sub-layer 313, and the first magnetic film sub-layer 311 and the second magnetic film sub-layer 313 are respectively disposed on opposite sides of the coil 13; a dielectric layer 35 is further disposed between the coil 13 and the first magnetic film sub-layer 311 and between the coil 13 and the second magnetic film sub-layer 313; the length of the inductance part of the circuit board integrated inductance 100 is 2.0mm, the width is 1.2mm, and the height is 0.25mm; the thickness of the support layer 113 is 50 μm; the coil 13 is a copper coil 13, the line width of the coil 13 is 260 μm, the line thickness is 70 μm, and the line distance is 140 μm; the dielectric layer 35 is a glass fiber/epoxy resin composite board, and the thickness of the dielectric layer 35 is 30 mu m; the first magnetic film sub-layer 311 and the second magnetic film sub-layer 313 are made of FeNi alloy, have a relative magnetic permeability of 1000, have an electrical conductivity of 40KS/m, and have a thickness of 20 μm.

The inductance values of the integrated circuit board inductors 100 of example 4 and comparative example 2 were tested at an operating frequency of 1MHz by performing simulation calculation according to standard GB/T8554-1998, and the lateral magnetic induction intensity distribution of the corresponding inductance portion of the integrated circuit board inductor 100 was calculated by using the eddy current field simulation of ANSYS Maxwell, and the test results are shown in the following tables 4, 22 and 23.

Table 4 simulation test data of the circuit board integrated inductor 100 of example 4 and comparative example 2

Example	Example 4	Comparative example 2
			Third magnetic film sub-layer 315	Has the following components	Without any means for
Inductance value (nH)	7.1	6.2

As can be seen from table 4, compared with the case where only the first magnetic film sub-layer 311 and the second magnetic film sub-layer 313 are disposed on opposite sides of the coil 13 (comparative example 2), the third magnetic film sub-layer 315 is used to connect the first magnetic film sub-layer 311 and the second magnetic film sub-layer 313 (example 4), and under the same conditions, the inductance value of the inductance in the integrated circuit board inductor 100 can be increased, and in example 4, compared with comparative example 2, the inductance value is increased from 6.2nH to 7.1nH, which is increased by approximately 15%.

Fig. 22 shows the magnetic induction pattern of the side surface of the circuit board integrated inductor 100 of example 4, and fig. 23 shows the magnetic induction pattern of the side surface of the circuit board integrated inductor 100 of comparative example 2. As can be seen from fig. 22 and 23, the side surface of the circuit board integrated inductor 100 of example 4 is substantially free from magnetic leakage, and the side surface of the circuit board integrated inductor 100 of comparative example 2 is free from magnetic leakage.

The size of the inductor part on the integrated inductor of the circuit board is limited, and the position, size, appearance and the like of the coil have great influence on the performance of the inductor. Therefore, the scheme for further improving the inductance with the limited size under the condition that the inductance size is unchanged is provided.

Referring to fig. 24 to 26, a third aspect of the present application provides a circuit board integrated inductor 100, which includes a circuit board 10 and a magnetic layer 30. The circuit board 10 includes a substrate 11 and a coil 13, the coil 13 is embedded in the substrate 11, and the coil 13 includes a main body 131; the magnetic layer 30 is carried on the circuit board 10 and at least partially overlaps the coil 13; the distance w1 between the front projected outline of the main body 131 on the surface of the substrate 11 and the front projected outline of the magnetic layer 30 on the surface of the substrate 11 is in the range of: w1 is less than or equal to 30 mu m and less than or equal to 300 mu m.

In the present embodiment, the surface of the substrate 11 refers to the surface of the substrate 11 on which the relevant components such as the processor 15, the memory 17, and the like are mounted.

Further, a distance w1 between an outer contour of the orthographic projection of the main body 131 on the surface of the substrate 11 and an outer contour of the orthographic projection of the magnetic layer 30 on the surface of the substrate 11 is in a range of: w1 is less than or equal to 50 mu m and less than or equal to 200 mu m. Still further, a distance w1 between an outer contour of the orthographic projection of the main body 131 on the surface of the substrate 11 and an outer contour of the orthographic projection of the magnetic layer 30 on the surface of the substrate 11 is in a range of: w1 is more than or equal to 80 mu m and less than or equal to 160 mu m. Specifically, the distance w1 between the outer contour of the orthographic projection of the main body portion 131 on the surface of the substrate 11 and the outer contour of the orthographic projection of the magnetic layer 30 on the surface of the substrate 11 may be, but is not limited to, 30 μm, 50 μm, 80 μm, 100 μm, 120 μm, 150 μm, 180 μm, 200 μm, 230 μm, 250 μm, 280 μm, 300 μm, etc.

The distance w1 between the outer contour of the front projection of the main body 131 on the surface of the substrate 11 and the outer contour of the front projection of the magnetic layer 30 on the surface of the substrate 11 is too large or too small, which affects the inductance value of the integrated circuit board inductor 100, and when the coil 13 is energized with current, magnetic lines of force in the loop of the main body 131 of the coil 13 and magnetic lines of force outside the loop form a closed loop. The area in the loop of the main body 131 is proportional to the magnetic resistance of the coil 13, and when the inductance size (the size of the magnetic layer 30) is fixed, the larger the coil 13, the larger the area in the loop, the larger the magnetic resistance in the loop, the smaller the area outside the loop and the smaller the magnetic resistance outside the loop; the size of the ring of the main body 131 also affects the length of the ring-shaped outer magnetic circuit, and the larger the ring is, the longer the effective length side of the coil 13 is, and the inductance value of the inductance can be increased, but the longer the center of the ring-shaped outer region is, the longer the distance side from the center of the ring to the center of the ring is, the larger the ring-shaped outer magnetic circuit is, and the ring-shaped outer magnetic resistance is increased, so that the size of the coil 13 needs to be balanced between the ring-shaped inner magnetic resistance and the ring-shaped outer magnetic resistance. When w1 is too small, the inductance value of the integrated circuit board inductor 100 is reduced, and when w1 is too large, the effective length of the coil 13 is shortened, and the inductance value of the integrated circuit board inductor 100 is also reduced. When 80 μm.ltoreq.w1.ltoreq.160 μm may enable the inductance value of the circuit board integrated inductor 100 to have a higher inductance value in the case where the size of the magnetic layer 30 is fixed.

The coil 13 of the circuit board integrated inductor 100 according to the third embodiment of the present application includes a circuit board 10 and a magnetic layer 30, the circuit board 10 includes a substrate 11 and a coil 13, the coil 13 is embedded in the substrate 11, the coil 13 includes a main body portion 131, and a distance w1 between an outer contour of front projection of the main body portion 131 on a surface of the substrate 11 and an outer contour of front projection of the magnetic layer 30 on the surface of the substrate 11 is: w1 is less than or equal to 30 mu m and less than or equal to 300 mu m. The dimensions of the inductive devices are typically limited such that, with the same inductive device area of the circuit board integrated inductor 100 and the same number of layers of the coil 13, the range of w1 is controlled to be: the thickness of w1 is less than or equal to 30 μm and less than or equal to 300 μm, so that the circuit board integrated inductor 100 can obtain a higher inductance value under the condition of the same area of the magnetic layer 30. In addition, the circuit board integrated inductor 100 of the embodiment integrates the inductor on the circuit board 10, so that the electronic equipment can be miniaturized and ultrathin when the inductor is applied to the electronic equipment, and the inductor and the circuit board 10 are prepared together without independent mounting, thereby improving the packaging efficiency. Furthermore, the inductor is integrated in the circuit board 10, so that the position of the circuit board 10 corresponding to the inductor can be saved for mounting other components, the area on the circuit board 10 is saved, and the wiring and piece distribution capabilities of the circuit board 10 are enhanced.

Referring to fig. 27, in some embodiments, the main body 131 includes at least one layer of sub-coils 13a, and when the main body 131 includes at least two layers of sub-coils 13a, the at least two layers of sub-coils 13a are stacked in sequence and electrically connected in sequence, each layer of sub-coils 13a has an opening 1301, the openings 1301 of the at least two layers of sub-coils 13a are staggered, and along the stacking direction of the at least two layers of sub-coils 13a, the at least two layers of sub-coils 13a overlap except for the portion of the opening 1301 corresponding to each layer of sub-coils 13 a. When the main body 131 includes at least two layers of sub-coils 13a, if the at least two layers of sub-coils 13a are arranged in a staggered manner, a part of the magnetic field generated by one layer of sub-coil 13a may be offset by the magnetic field generated by the other layer of sub-coil 13a in the adjacent two layers of sub-coils 13a, so that the magnetic field intensity of the whole coil 13 is weakened, and when the at least two layers of sub-coils 13a are overlapped, the weakening effect between the layers of the adjacent sub-coils 13a is weakened as much as possible, so that the area of the inductor is utilized to the maximum extent, and the synergistic strengthening effect of the adjacent sub-coils 13a is realized to the maximum extent.

In some embodiments, each layer of the sub-coil 13a includes a first end 1303 and a second end 1305, the first end 1303 and the second end 1305 are disposed opposite to each other, and the first end 1303 and the second end 1305 define the opening 1301; the coil 13 further includes a first lead wire 133 and a second lead wire 135, the first lead wire 133 and the second lead wire 135 are electrically connected to both end portions of the main body portion 131, respectively, and the first lead wire 133 and the second lead wire 135 are spaced apart from each other on the same side of the main body portion 131. The first end 1303 and the second end 1305 of each layer of sub-coils 13a are arranged opposite each other, such that no other partial coil 13 is present between any two opposite parts of the sub-coils 13a in the same layer of sub-coils 13 a. In this way, the existence of another part of the coil 13, for example, the coil 13 with an e-shaped structure, between two opposite parts of the sub-coil 13a in the same layer of sub-coil 13a can be better avoided, and the mutual cancellation between magnetic fields generated by different parts of the sub-coil 13a after the coil 13 is electrified can be better avoided, so that the integrated inductor 100 of the circuit board has a higher inductance value.

In some embodiments, the gap w2 between the first end 1303 and the second end 1305 of each layer of the sub-coil 13a ranges from 50 μm to 200 μm. Specifically, the gap w2 between the first end 1303 and the second end 1305 of each layer of the sub-coil 13a may be, but is not limited to, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm, 100 μm, 110 μm, 120 μm, 130 μm, 140 μm, 150 μm, 160 μm, 170 μm, 180 μm, 190 μm, 200 μm, etc. when w2 is too small, the existing etching process is difficult to realize, and when w2 is too large, the effective length of the coil 13 is reduced, so that the inductance value of the integrated circuit board inductor 100 is reduced.

In some embodiments, the at least two layers of sub-coils 13a include adjacent first and second sub-coils 13a1 and 13a2, the first end 1303 of the first sub-coil 13a1 being electrically connected to the second end 1305 of the second sub-coil 13a 2; along the arrangement direction of the first end 1303 and the second end 1305 of the first sub-coil 13a1, the overlapping length w3 of the first end 1303 of the first sub-coil 13a1 and the second end 1305 of the second sub-coil 13a2 is in the range of 100 μm.ltoreq.w3.ltoreq.500 μm. Specifically, w3 may be, but is not limited to, 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, 350 μm, 400m, 450 μm, 500 μm, etc. Too small w3 can reduce the hole size of the via hole in the overlapping area, which is unfavorable for process realization.

In some embodiments, each of the sub-coil 13a, the first lead 133, and the second lead 135 comprises at least two wire layers 1311 connected in parallel. In this way, under the condition that the total thickness or total cross-sectional area of each layer of sub-coil 13a (i.e. the total cross-sectional area of the wires) is the same, the thickness of the single-layer wire layer 1311 can be made thinner, the utilization rate of the cross-sectional area of each layer of wire layer 1311 can be improved, the alternating current resistance of the whole coil 13 can be reduced, the alternating current copper loss caused by the skin effect of the coil 13 at high frequency can be reduced, and the inductance efficiency of the circuit board integrated inductor 100 can be improved.

For a detailed description of other aspects of the conductive line layer 1311, please refer to the corresponding parts of the above embodiments, and the detailed description is omitted here.

Referring to fig. 7 and 8 again, in some embodiments, the substrate 11 includes an insulating layer 111, and the insulating layer 111 is disposed between any two adjacent conductive wire layers 1311; the thickness d2 of each of the insulating layers 111 in the stacking direction of the at least two wiring layers 1311 ranges from: d2 is more than or equal to 50 μm and less than or equal to 500 μm. In other words, the interval between the adjacent two wire layers 1311 of the coil 13 ranges from 50 μm to 500 μm. Further, in the stacking direction of the at least two wire layers 1311, the thickness d2 of each insulating layer 111 ranges from: d2 is less than or equal to 100 mu m and less than or equal to 250 mu m. Specifically, the thickness d2 of each of the insulating layers 111 may be, but is not limited to, 50 μm, 80 μm, 100 μm, 120 μm, 150 μm, 180 μm, 200 μm, 220 μm, 250 μm, 280 μm, 300 μm, 320 μm, 350 μm, 380 μm, 400 μm, 420 μm, 450 μm, 480 μm, 500 μm, etc. Although the coil 13 is formed by using at least two wire layers 1311 connected in parallel, the skin effect of each wire layer 1311 is reduced, the ac impedance may still be large due to the proximity effect between the adjacent two wire layers 1311, and thus the thickness of the insulating layer 111 cannot be too thin. When the thickness of the insulating layer 111 is too thick, the thickness of the inductor in the integrated inductor 100 of the circuit board is increased, the space of the circuit board 10 is occupied, and the difficulty of the via hole (i.e. the difficulty of the opening) of the insulating layer 111 is increased.

Referring to fig. 9 again, the circuit board 10 of the third embodiment further includes a processor 15 and a memory 17, wherein the processor 15 and the memory 17 are both carried on the surface of the substrate 11, and the processor 15 is electrically connected with the memory 17 and the coil 13, respectively. The processor 15 is used for controlling the magnitude and direction of the current flowing through the coil 13. The memory 17 is used to store program code required for the operation of the processor 15.

Referring to fig. 12 to 14 again, in some embodiments, the magnetic layer 30 includes a magnetic film layer 31, the magnetic film layer 31 includes a first magnetic film sub-layer 311, a second magnetic film sub-layer 313, and a third magnetic film sub-layer 315, the first magnetic film sub-layer 311 and the second magnetic film sub-layer 313 are respectively disposed on opposite sides of the coil 13, the third magnetic film sub-layer 315 penetrates through the substrate 11 and is located at the periphery of the coil 13, and the third magnetic film sub-layer 315 is respectively connected with the first magnetic film sub-layer 311 and the second magnetic film sub-layer 313. The first magnetic film sub-layer 311 and the second magnetic film sub-layer 313 are respectively disposed on opposite sides of the circuit board 10, the middle is insulated by the substrate 11, the substrate 11 is insulated, the magnetic permeability is generally 1, the magnetic resistance is relatively large, and the third magnetic film sub-layer 315 is disposed to communicate the first magnetic film sub-layer 311 with the second magnetic film sub-layer 313, so as to form a closed magnetic loop, reduce the magnetic resistance of the magnetic film layer 31, and improve the inductance value (i.e., inductance value) of the integrated circuit board inductor 100. In addition, the third magnetic film sub-layer 315 is disposed on the side of the coil 13, so as to reduce the magnetic leakage phenomenon of the integrated inductor 100 of the circuit board and improve the electromagnetic interference (EMI) performance. In other embodiments of the present application, the magnetic film layer 31 may also include only the first magnetic film sub-layer 311 or the second magnetic film sub-layer 313, or include both the first magnetic film sub-layer 311 and the second magnetic film sub-layer 313. The present application is not particularly limited.

Referring to fig. 14, the third magnetic film sub-layer 315 may alternatively be a continuous magnetic film portion 3151 around the periphery of the coil 13.

In some embodiments, the coil 13 further includes a first lead 133 and a second lead 135, the first lead 133 and the second lead 135 being electrically connected to two ends of the main body 131, respectively, the first lead 133 and the second lead 135 being spaced apart on the same side of the main body 131; the third magnetic film sub-layer 315 is located on the other peripheral side of the main body portion 131 except the peripheral side on which the first lead 133 and the second lead 135 are provided. If the magnetic field strength of the first lead 133 and the second lead 135 of the coil 13 is large, and the third magnetic film sub-layer 315 is disposed too close to the first lead 133 and the second lead 135, magnetic saturation is likely to occur at the position of the third magnetic film sub-layer 315 close to the first lead 133 and the second lead 135, which is not beneficial to the improvement of the inductance value of the integrated circuit board inductor 100.

For a detailed description of other parts of the magnetic glue layer 33 that are the same as the embodiments of the first and second aspects, please refer to the descriptions of the embodiments of the first and second aspects of the present application, and the detailed descriptions thereof are omitted.

Referring again to fig. 21, in some embodiments, the circuit board integrated inductor 100 of the embodiments further includes a dielectric layer 35, where the dielectric layer 35 is located between the coil 13 and the magnetic film layer 31, for insulating the coil 13 from the magnetic film layer 31. While ensuring the insulation performance, the higher the permeability of the dielectric layer 35 is, and the higher the inductance value of the manufactured circuit board integrated inductor 100 is. For a detailed description of the other portions of the dielectric layer 35 that are the same as the embodiments of the first aspect, please refer to the description of the embodiments of the first aspect of the present application, and the detailed description is omitted herein.

For a detailed description of other parts of the dielectric layer 35 that are the same as the embodiments of the first and second aspects, please refer to the descriptions of the embodiments of the first and second aspects of the present application, and the detailed descriptions are omitted herein.

The third aspect of the present application is similar to the embodiments of the first aspect and the second aspect, please refer to the description of the corresponding portions of the embodiments of the first aspect and the second aspect, and the detailed description is omitted herein.

Examples 5 to 11, comparative example 3 and comparative example 4

The circuit board integrated inductor 100 of each embodiment and the comparative example comprises a circuit board 10 and a magnetic layer 30, the circuit board 10 comprises a substrate 11 and a coil 13, the coil 13 is embedded in the substrate 11, a main body portion 131 of the coil 13 comprises two layers of sub-coils 13a which are electrically connected, a supporting layer 113 is arranged between the two adjacent layers of sub-coils 13a, the supporting layer 113 is a polyimide layer, the thickness of the supporting layer 113 is 12.5 μm, the two layers of sub-coils 13a are of a square structure with an opening 1301, the coil 13 is a copper coil 13, the line width of the copper coil 13 is 260 μm, and the line thickness is 70 μm; the magnetic layer 30 is a magnetic adhesive layer 33, the magnetic adhesive layer 33 covers the two opposite surfaces of the circuit board 10 opposite to the coil 13, the length of the magnetic adhesive layer 33 is 2.5mm, the width is 2.0mm, the thickness is 0.3mm, and the relative magnetic permeability of the magnetic adhesive layer 33 is 20. The distance w1 between the outer contour of the front projection of the main body 131 on the surface of the substrate 11 and the outer contour of the front projection of the magnetic layer 30 on the surface of the substrate 11 in each of the examples and the comparative examples is shown in table 5 below.

The circuit board integrated inductors 100 of examples 5 to 11, comparative example 3 and comparative example 4 were tested for inductance value at an operating frequency of 1MHz according to the standard GB/T8554-1998 by performing simulation calculations, and the test results are shown in table 5 below.

Table 5 simulation test data of the circuit board integrated inductors 100 of examples 5 to 11, comparative example 3 and comparative example 4

Example	w1(μm)	Inductance value (nH)
			Comparative example 3	10	44.5
Example 5	30	50.8
			Example 6	50	54.4
Example 7	100	58.3
			Example 8	150	58.2
Example 9	200	56.6
			Example 10	250	53.7
Example 11	300	50.4
			Comparative example 4	350	46.8

As can be seen from table 5, as the distance w1 between the front projected outline of the main body 131 on the surface of the substrate 11 and the front projected outline of the magnetic layer 30 on the surface of the substrate 11 increases gradually, the inductance value of the integrated circuit board inductance 100 increases gradually, and when w1 is 100 μm, the inductance value of the integrated circuit board inductance 100 reaches a peak value, and when w1 increases continuously, the inductance value of the integrated circuit board inductance 100 decreases gradually. Therefore, when the distance w1 between the outer contour of the orthographic projection of the main body portion 131 on the surface of the substrate 11 and the outer contour of the orthographic projection of the magnetic layer 30 on the surface of the substrate 11 satisfies 80 μm+.w1+.160μm, the inductance value of the circuit board integrated inductor 100 can be made to have a higher inductance value with the size of the magnetic layer 30 fixed.

Example 12

The integrated circuit board inductor 100 of the present embodiment includes a circuit board 10 and a magnetic layer 30, the circuit board 10 includes a substrate 11 and a coil 13, the coil 13 is embedded in the substrate 11, a main body portion 131 of the coil 13 includes a layer of sub-coil 13a electrically connected, the sub-coil 13a has a square structure with an opening 1301, the coil 13 is a copper coil 13, a line width of the copper coil 13 is 260 μm, and a line thickness is 70 μm; the magnetic layer 30 is a magnetic adhesive layer 33, the magnetic adhesive layer 33 covers two opposite surfaces of the circuit board 10 opposite to the coil 13, the length of the magnetic adhesive layer 33 is 2.5mm, the width is 2.0mm, the thickness is 0.3mm, the relative permeability of the magnetic adhesive layer 33 is 20, and the structure of the coil 13 in this embodiment is shown in fig. 28.

Comparative example 5 and comparative example 6

The circuit board integrated inductor 100 of this comparative example comprises a circuit board 10 and a magnetic layer 30, the circuit board 10 comprises a substrate 11 and a coil 13, the coil 13 is embedded in the substrate 11, a main body portion 131 of the coil 13 comprises a layer of sub-coil 13a electrically connected, the sub-coil 13a is of an irregular or incomplete square structure with an opening 1301, the coil 13 is a copper coil 13, the line width of the copper coil 13 is 260 μm, and the line thickness is 70 μm; the magnetic layer 30 is a magnetic adhesive layer 33, the magnetic adhesive layer 33 covers the two opposite surfaces of the circuit board 10 opposite to the coil 13, the length of the magnetic adhesive layer 33 is 2.5mm, the width is 2.0mm, the thickness is 0.3mm, the relative permeability of the magnetic adhesive layer 33 is 20, the structure of the coil 13 of the comparative example 5 is shown in fig. 29, and the structure of the coil 13 of the comparative example 6 is shown in fig. 30.

The circuit board integrated inductors 100 of example 12, comparative example 5 and comparative example 6 were tested for inductance value at an operating frequency of 1MHz according to standard GB/T8554-1998 by simulation, and the test results are shown in table 6 below.

Table 6 simulation test data for the circuit board integrated inductor 100 of example 12, comparative example 5, and comparative example 6

Example	Coil 13 structure	Inductance value (nH)
			Example 12	Chinese character kou-shaped	14.9
Comparative example 5	Irregular square shape	14.0
			Comparative example 6	Incomplete Chinese character 'kou' shape	12.4

As can be seen from the results of table 6, the regular notch-shaped structure has a higher inductance value than the irregular notch-shaped structure and the incomplete notch-shaped structure in the case that the size of the inductance portion corresponding to the integrated circuit board inductance 100 is unchanged.

Referring to fig. 31 and 4, a fourth embodiment of the present application further provides an inductor 200, which includes a coil layer 210 and a magnetic layer 30. The coil layer 210 includes a coil 13, the coil 13 including at least two wire layers 1311 connected in parallel; the magnetic layer 30 is disposed at one side of the coil layer 210.

For detailed descriptions of the coil 13 and the magnetic layer 30, please refer to the corresponding parts of the embodiments of the first aspect of the present application, and the detailed descriptions thereof are omitted.

The coil 13 of the inductor 200 according to the fourth embodiment of the present application includes at least two parallel conductive wire layers 1311, so that in the case where the total thickness or total cross-sectional area of the conductive wires forming the coil 13 (i.e., the total cross-sectional area of the conductive wires) is the same, the thickness of the single-layer conductive wire layer 1311 can be made thinner, the utilization rate of the cross-sectional area of each layer of conductive wire layer 1311 can be improved, the ac resistance of the whole coil 13 can be reduced, the ac copper loss due to the skin effect of the coil 13 at high frequency can be reduced, and the efficiency of the inductor 200 can be improved.

In some embodiments, the thickness of each of the wire layers 1311 along the stacking direction of the at least two wire layers 1311 is less than or equal to 2 times the skin depth of the wire layers 1311 at the operating frequency of the inductor 200. Please refer to the corresponding parts of the embodiments of the first aspect of the present application in detail, and are not described herein again.

In some embodiments, the thickness d1 of each of the wire layers 1311 along the stacking direction of the at least two wire layers 1311 ranges from: d1 is less than or equal to 5 mu m and less than or equal to 94 mu m. Please refer to the corresponding parts of the embodiments of the first aspect of the present application in detail, and are not described herein again.

Optionally, the coil 13 comprises at least one layer of sub-coils 13a. As shown in fig. 3, when the coil 13 includes at least two layers of sub-coils 13a, the at least two layers of sub-coils 13a are sequentially stacked and spaced apart, and each of the sub-coils 13a includes at least two wire layers 1311 connected in parallel. Each of the sub-coils 13a includes at least two conductive wire layers 1311 connected in parallel, and it is understood that each of the sub-coils 13a is formed by at least two conductive wire layers 1311 connected in parallel, and any two adjacent sub-coils 13a are electrically connected in sequence. Each sub-coil 13a comprises at least two parallel wire layers 1311, so that the utilization rate of the cross-sectional area of each wire layer 1311 can be better improved, the alternating current resistance of the coil 13 is reduced, the alternating current copper loss caused by the skin effect of the coil 13 at high frequency is reduced, and the efficiency of the inductor 200 is improved.

Referring to fig. 4 and 5 again, in some embodiments, the coil 13 includes a main body 131, a first lead 133 and a second lead 135, the main body 131 includes the at least one layer of sub-coils 13a, and when the main body 131 includes at least two layers of sub-coils 13a, the at least two layers of sub-coils 13a are sequentially arranged at intervals and are sequentially electrically connected; each of the sub-coils 13a includes the at least two wire layers 1311 connected in parallel; the first lead wire 133 and the second lead wire 135 are electrically connected to both end portions of the main body 131, respectively, and the first lead wire 133 and the second lead wire 135 are spaced apart from each other on the same side of the main body 131; the third magnetic film sub-layer 315 is located on the other peripheral side of the main body portion 131 except the peripheral side on which the first lead 133 and the second lead 135 are provided. Please refer to the corresponding parts of the embodiments of the first aspect to the third aspect of the present application in detail, and the detailed description is omitted herein.

Referring again to fig. 7, in some embodiments, the distance w1 between the front projected outer contour of the main body 131 on the surface of the substrate 11 and the front projected outer contour of the magnetic layer 30 on the surface of the substrate 11 is in the range of: w1 is less than or equal to 30 mu m and less than or equal to 300 mu m. Please refer to the corresponding parts of the embodiments of the first aspect to the third aspect of the present application in detail, and the detailed description is omitted herein.

For a detailed description of other aspects of the coil 13, please refer to the description of the corresponding parts of the embodiments of the first aspect of the present application, which is not respected here.

In some embodiments, the coil layer 210 further includes an insulating layer 111, the insulating layer 111 being disposed between any adjacent two wire layers 1311; the thickness d2 of each of the insulating layers 111 in the stacking direction of the at least two wiring layers 1311 ranges from: d2 is more than or equal to 50 μm and less than or equal to 500 μm. In other words, the distance d2 between the parallel at least two conductive wire layers 1311 is in the range of: d2 is more than or equal to 50 μm and less than or equal to 500 μm. Please refer to the corresponding parts of the embodiments of the first aspect of the present application in detail, and are not described herein again.

In some embodiments, the coil layer 210 further includes a support layer 113, where the support layer 113 is insulating, and the support layer 113 is used to support the coil 13, and when the coil 13 includes at least two layers of sub-coils 13a, the support layer 113 is disposed between any two adjacent layers of sub-coils 13 a. Alternatively, the two sub-coils 13a on opposite sides of the support layer 113 are electrically connected by punching vias in the support layer 113, depositing a conductive metal (e.g., copper).

Referring to fig. 32, in some embodiments, the magnetic layer 30 includes a magnetic film layer 31, the magnetic film layer 31 includes a first magnetic film sub-layer 311 and a second magnetic film sub-layer 313, and the first magnetic film sub-layer 311 and the second magnetic film sub-layer 313 are respectively disposed on opposite sides of the coil layer 210. Please refer to the corresponding parts of the embodiments of the first aspect to the third aspect of the present application in detail, and the detailed description is omitted herein.

Referring to fig. 33, in some embodiments, the magnetic film layer 31 further includes a third magnetic film sub-layer 315, and the third magnetic film sub-layer 315 is disposed on the periphery of the coil 13 and is connected to the first magnetic film sub-layer 311 and the second magnetic film sub-layer 313, respectively. Please refer to the corresponding parts of the embodiments of the first aspect to the third aspect of the present application in detail, and the detailed description is omitted herein.

For a detailed description of other parts of the magnetic film layer 31 that are the same as those of the first embodiment, please refer to the description of the first embodiment of the present application, and the detailed description is omitted herein.

In some embodiments, the magnetic layer 30 further includes a magnetic glue layer 33, the magnetic glue layer 33 being disposed between the coil 13 and the magnetic film layer 31. The magnetic glue layer 33 is disposed between the coil 13 and the magnetic film layer 31, so that the magnetic permeability and the inductance of the inductor 200 can be improved, and the coil 13 and the magnetic film layer 31 can be insulated.

Referring to fig. 34, in some embodiments, the inductor 200 of the present application further includes a dielectric layer 35, where the dielectric layer 35 is located between the coil 13 and the magnetic film 31, and is used to insulate the coil 13 from the magnetic film 31. While ensuring the insulation performance, the higher the permeability of the dielectric layer 35 is, and the higher the inductance value of the inductor 200 is.

The fourth aspect of the present application is the same as the embodiments of the first aspect, please refer to the description of the corresponding portions of the embodiments of the first aspect, and the detailed description is omitted herein.

Referring to fig. 35 and 36, an embodiment of the fifth aspect of the present application further provides an electronic device 300, where the electronic device 300 includes a display screen 310 and the circuit board integrated inductor 100 according to any of the first aspect to the third aspect of the present application. The processor 15 of the integrated circuit board inductor 100 is electrically connected to the coil 13 and the display screen 310, respectively, and the processor 15 is used for controlling the display of the display screen 310 and controlling the magnitude and direction of the current flowing through the coil 13.

The electronic device 300 of the embodiment of the present application may be, but is not limited to, a portable electronic device 300 such as a mobile phone, a tablet computer, a notebook computer, a desktop computer, a smart band, a smart watch, an electronic reader, a game console, and the like. In the embodiment of the present application, the electronic device 300 is illustrated by using a mobile phone as an example, and should not be construed as limiting the protection scope of the present application.

For a detailed description of the integrated circuit board inductor 100, please refer to the corresponding parts of the above embodiments, and the detailed description is omitted here.

Alternatively, the display 310 may be, but is not limited to, one or more of a liquid crystal display, a light emitting diode display (LED display), a Micro light emitting diode display (Micro LED display), a sub-millimeter light emitting diode display (Mini LED display), an organic light emitting diode display (OLED display), etc.

The sixth aspect of the present application further provides an electronic device 300, the electronic device 300 including: the electronic device 300 comprises a display 310, a processor 15 and an inductor 200 according to the fourth aspect of the present application. The processor 15 is electrically connected to the display screen 310 and the coil 13 of the inductor 200, respectively, and the processor 15 is used for controlling the display of the display screen 310 and controlling the magnitude and direction of the current flowing through the coil 13.

For detailed descriptions of the display 310, the inductor 200 and the processor 15, please refer to the corresponding parts of the above embodiments, and the detailed descriptions are omitted herein.

It should be understood that the electronic device 300 in this embodiment is only one form of the electronic device 300 to which the circuit board integrated inductor 100 or the inductor 200 is applied, and should not be construed as a limitation of the electronic device 300 provided in the present application, nor should it be construed as a limitation of the circuit board integrated inductor 100 or the inductor 200 provided in the various embodiments of the present application.

Reference in the present application to "an embodiment," "implementation" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly understand that the embodiments described herein may be combined with other embodiments. Furthermore, it should be understood that the features, structures, or characteristics described in the embodiments of the present application may be combined arbitrarily without contradiction to each other to form yet another embodiment without departing from the spirit and scope of the technical solutions of the present application.

Finally, it should be noted that the above embodiments are merely for illustrating the technical solution of the present application and not for limiting, and although the present application has been described in detail with reference to the above preferred embodiments, it should be understood by those skilled in the art that the technical solution of the present application may be modified or equivalent replaced without departing from the spirit and scope of the technical solution of the present application.

Claims

1. A circuit board integrated inductor, comprising:

2. The circuit board integrated inductor of claim 1, wherein a thickness of each of the wire layers is less than or equal to 2 times a skin depth of the wire layers at an operating frequency of the circuit board integrated inductor in a lamination direction of the at least two wire layers.

3. The circuit board integrated inductor as claimed in claim 2, wherein a thickness d1 of each of the wire layers in a lamination direction of the at least two wire layers is in a range of: d1 is less than or equal to 5 mu m and less than or equal to 94 mu m.

4. The circuit board integrated inductor of claim 1, wherein the substrate comprises an insulating layer disposed between any two adjacent wire layers; the thickness d2 of each insulating layer along the stacking direction of the at least two conducting wire layers is in the range of: d2 is more than or equal to 50 μm and less than or equal to 500 μm.

5. The integrated circuit board inductor of claim 1, wherein the magnetic layer comprises a magnetic film layer comprising a first magnetic film sub-layer, a second magnetic film sub-layer, and a third magnetic film sub-layer, the first magnetic film sub-layer and the second magnetic film sub-layer being disposed on opposite sides of the coil, respectively; the third magnetic film sub-layer penetrates through the substrate and is located on the periphery of the coil, and the third magnetic film sub-layer is connected with the first magnetic film sub-layer and the second magnetic film sub-layer respectively.

6. The circuit board integrated inductor of claim 5, wherein the third magnetic film sub-layer is continuously disposed around the periphery of the coil; alternatively, the third magnetic film sub-layer includes a plurality of magnetic film portions disposed at intervals around the outer circumference of the coil.

7. The circuit board integrated inductor of claim 5, wherein the ratio of the length L1 of the third magnetic film sub-layer to the peripheral length L2 of the magnetic film layer ranges from: L1/L2 is less than or equal to 1/20 and less than or equal to 3/4.

8. The circuit board integrated inductor of claim 1, wherein the coil comprises a body portion; the distance w1 between the front projection outline of the main body part on the surface of the substrate and the front projection outline of the magnetic layer on the surface of the substrate is as follows: w1 is less than or equal to 30 mu m and less than or equal to 300 mu m.

9. The circuit board integrated inductor of claim 8, wherein the coil further comprises a first lead and a second lead, the first lead and the second lead being electrically connected to two ends of the main body portion, respectively, the first lead and the second lead being spaced apart on a same side of the main body portion; the main body part includes at least one deck sub-coil, when main body part includes at least two-layer sub-coil, at least two-layer sub-coil interval sets up in proper order and electric connection in proper order, every layer the sub-coil includes parallelly connected at least two-layer wire layer.

10. A circuit board integrated inductor, comprising:

11. The circuit board integrated inductor of claim 10, wherein a ratio of a length L1 of the third magnetic film sub-layer to a peripheral length L2 of the magnetic film layer ranges from: L1/L2 is less than or equal to 1/20 and less than or equal to 3/4.

12. The circuit board integrated inductor according to claim 10 or 11, wherein the coil includes a main body portion, a first lead and a second lead, the first lead and the second lead being electrically connected to both end portions of the main body portion, respectively, the first lead and the second lead being spaced apart on the same side of the main body portion; the third magnetic film sub-layer is located on the other peripheral side of the main body portion except the peripheral side on which the first lead and the second lead are provided.

13. The circuit board integrated inductor of claim 12, wherein a shortest distance s1 between the first lead and the third magnetic film sub-layer is greater than or equal to 0.5mm and a shortest distance s2 between the second lead and the third magnetic film sub-layer is greater than or equal to 0.5mm.

14. The integrated circuit board inductor of claim 12, wherein the main body portion includes at least one layer of sub-coils, and when the main body portion includes at least two layers of sub-coils, the at least two layers of sub-coils are sequentially spaced apart and sequentially electrically connected; each layer of the sub-coil comprises at least two layers of conducting wire layers which are connected in parallel.

15. The circuit board integrated inductor of claim 14, wherein a thickness of each of the wire layers is less than or equal to 2 times a skin depth of the wire layers at an operating frequency of the circuit board integrated inductor in a lamination direction of the at least two wire layers.

16. The circuit board integrated inductor of claim 15, wherein the substrate comprises an insulating layer disposed between any two adjacent wire layers; the thickness d2 of each insulating layer along the stacking direction of the at least two conducting wire layers is in the range of: d2 is more than or equal to 50 μm and less than or equal to 500 μm.

17. The circuit board integrated inductor of claim 12, wherein a distance w1 between an outer contour of the orthographic projection of the main body portion on the surface of the substrate and an outer contour of the orthographic projection of the magnetic film layer on the surface of the substrate ranges from: w1 is less than or equal to 30 mu m and less than or equal to 300 mu m.

18. An inductor, comprising:

and the magnetic layer is arranged on one side of the coil layer.

19. The inductor of claim 18, wherein each of the wire layers has a thickness of less than or equal to 2 times a skin depth of the wire layer at an operating frequency along a lamination direction of the at least two wire layers; the range of the distance d2 between the at least two parallel conducting wire layers is as follows: d2 is more than or equal to 50 μm and less than or equal to 500 μm.

20. An electronic device comprising the circuit board integrated inductor of any one of claims 1-17; alternatively, an inductance as claimed in claim 18 or claim 19.