CN117524286A

CN117524286A - Method and equipment for testing service life of fuse circuit

Info

Publication number: CN117524286A
Application number: CN202210901694.0A
Authority: CN
Inventors: 宋标; 牛罗伟; 孔令枫
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-07-28
Filing date: 2022-07-28
Publication date: 2024-02-06

Abstract

The embodiment of the disclosure provides a method and equipment for testing the service life of a fuse circuit, which relate to the technical field of semiconductors and comprise the following steps: reading a first blowing state of each fuse cell in the fuse array by using a fuse reading circuit; applying NBTI stress to the fuse reading circuit according to the time periods of applying the plurality of NBTI stresses; after the application time period of each NBTI stress is over, re-reading the second blowing state of each fuse unit in the fuse array by using a fuse reading circuit; and determining the service life of the fuse circuit according to the first fusing state, the application duration of each NBTI stress and the second fusing state read again by the fuse reading circuit after the application duration of each NBTI stress is over. The embodiment of the disclosure can accurately evaluate the service life of the fuse circuit based on the NBTI effect of the semiconductor device.

Description

Method and equipment for testing service life of fuse circuit

Technical Field

The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a method and equipment for testing the service life of a fuse circuit.

Background

Currently, one-time programmable memories (eFuses) have been widely used in semiconductor memory devices.

In modern integrated circuit manufacturing processes, with the continued shrinking of semiconductor integrated device feature sizes and the use of new materials and structures, the critical dimensions of semiconductor memory devices, such as dynamic random access memory (Dynamic Random Access Memory, DRAM for short), are becoming smaller, thereby limiting the number of times the fuse circuits in efuses can be read.

In order to ensure the reliability of the fuse circuit, the effective service life of the fuse circuit needs to be accurately evaluated. However, how to evaluate the effective service life of the fuse circuit is a technical problem that needs to be solved at present.

Disclosure of Invention

The embodiment of the disclosure provides a method and equipment for testing the service life of a fuse circuit, which can accurately evaluate the effective service life of the fuse circuit.

In a first aspect, embodiments of the present disclosure provide a method for testing a service life of a fuse circuit, the fuse circuit including a fuse reading circuit and a fuse array formed by fuse cells; the method comprises the following steps:

reading a first blowing state of each fuse cell in the fuse array with the fuse reading circuit;

applying a negative bias temperature instability (Negative Bias Temperature Instability, NBTI) stress to the fuse read circuit for a plurality of NBTI stress applying durations, respectively;

Re-reading a second blown state of each fuse cell in the fuse array with the fuse reading circuit after each of the NBTI stress applying periods is completed;

and determining the service life of the fuse circuit according to the first fusing state, the NBTI stress applying time periods and the second fusing state read again by the fuse reading circuit after each NBTI stress applying time period is finished.

In some embodiments, the reading, with the fuse read circuit, the first blown state of each fuse cell in the fuse array includes:

inputting a blowing instruction to a corresponding fuse unit in the fuse array according to preset topology data;

the first blown state of each fuse cell in the fuse array is read with the fuse read circuit.

In some embodiments, before the applying the NBTI stress to the fuse read circuit, the method further includes:

determining the NBTI stress applying time periods based on a preset functional relation between the NBTI stress applying time period and the estimated service life time period; wherein each NBTI stress application period corresponds to a different estimated life period.

In some embodiments, the NBTI stress application period t is a function of the estimated lifetime period Y:

t＝(Vstress/Vop)^a*Y

where vstres represents the input voltage of the fuse read circuit when the NBTI stress is applied, vop represents the original input voltage of the fuse read circuit, and a represents the voltage degradation coefficient.

In some embodiments, the determining the service life of the fuse circuit according to the first fusing state, the respective NBTI stress applying periods, and the second fusing state re-read by the fuse reading circuit after each of the NBTI stress applying periods is completed includes:

comparing the first fusing state with the second fusing state read again by the fuse reading circuit after the application time of the NBTI stress is finished;

determining a maximum value of NBTI stress applying time period corresponding to the fuse reading circuit under the condition that the first fusing state is consistent with the second fusing state re-read by the fuse reading circuit;

determining the estimated life time corresponding to the maximum value according to the functional relation between the NBTI stress applying time and the estimated life time;

And determining the estimated life time corresponding to the maximum value as the service life of the fuse circuit.

In some embodiments, the fuse reading circuit includes an inverter, where the inverter includes an NMOS tube and a PMOS tube, an input end of the inverter is a gate commonly connected to the NMOS tube and the PMOS tube, and an output end of the inverter is a drain commonly connected to the NMOS tube and the PMOS tube.

In a second aspect, embodiments of the present disclosure provide a testing apparatus for a service life of a fuse circuit, the fuse circuit including a fuse reading circuit and a fuse array composed of fuse cells; the device comprises:

a first reading module for reading a first blowing state of each fuse cell in the fuse array using the fuse reading circuit;

the processing module is used for respectively applying NBTI stress to the fuse reading circuit according to the time periods of applying the NBTI stress of the negative bias voltage temperature instability;

the second reading module is used for re-reading a second fusing state of each fuse unit in the fuse array by using the fuse reading circuit after the application duration of each NBTI stress is over;

and the evaluation module is used for determining the service life of the fuse circuit according to the first fusing state, the NBTI stress applying time periods and the second fusing state read again by the fuse reading circuit after each NBTI stress applying time period is finished.

In some embodiments, the first reading module is to:

In some embodiments, the processing module is further to:

t＝(Vstress/Vop)^a*Y

In some embodiments, the evaluation module is to:

In a third aspect, an embodiment of the present disclosure provides an electronic device, including: at least one processor and memory;

the memory stores computer-executable instructions;

the at least one processor executes computer-executable instructions stored by the memory, causing the at least one processor to perform a method of testing the life of a fuse circuit as provided in the first aspect.

In a fourth aspect, embodiments of the present disclosure provide a computer-readable storage medium having stored therein computer-executable instructions that, when executed by a processor, implement a method of testing the lifetime of a fuse circuit as provided in the first aspect.

In a fifth aspect, embodiments of the present disclosure provide a computer program product comprising a computer program which, when executed by a processor, implements a method of testing the lifetime of a fuse circuit as provided in the first aspect.

According to the testing method and the testing equipment for the service life of the fuse circuit, based on the NBTI effect of the semiconductor device, NBTI stresses with different durations are applied to the fuse reading circuit, ageing of the fuse reading circuit is accelerated, then the change of specific parameters of the fuse circuit is measured, and the change rule of the parameter degradation quantity along with the NBTI stress time can be obtained, so that the service life of the fuse circuit can be accurately estimated.

Drawings

Fig. 1 is a schematic layout diagram of a memory chip according to an embodiment of the disclosure;

fig. 2 is a schematic structural diagram of a memory cell of a memory chip according to an embodiment of the disclosure;

FIG. 3 is a schematic diagram of an inverter according to an embodiment of the disclosure;

FIG. 4 is a flowchart illustrating a method for testing the service life of a fuse circuit according to an embodiment of the present disclosure;

FIGS. 5 and 6 are schematic diagrams of two topology data structures provided in embodiments of the present disclosure, respectively;

FIG. 7 is a schematic diagram of a program module of a testing apparatus for testing the service life of a fuse circuit according to an embodiment of the disclosure;

fig. 8 is a schematic hardware structure of an electronic device according to an embodiment of the disclosure.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are some embodiments of the present disclosure, but not all embodiments. Based on the embodiments in this disclosure, all other embodiments that a person of ordinary skill in the art would obtain without making any inventive effort are within the scope of protection of this disclosure. Furthermore, while the disclosure has been presented by way of example only, it should be appreciated that various aspects of the disclosure may be separately implemented in a complete embodiment.

It should be noted that the brief description of the terms in the present disclosure is only for convenience in understanding the embodiments described below, and is not intended to limit the embodiments of the present disclosure. Unless otherwise indicated, these terms should be construed in their ordinary and customary meaning.

The terms first, second and the like in the description and in the claims and in the above-described figures are used for distinguishing between similar or similar objects or entities and not necessarily for describing a particular sequential or chronological order, unless otherwise indicated. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the disclosure are, for example, capable of operation in sequences other than those illustrated or otherwise described herein.

Furthermore, the terms "comprise" and "have," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a product or apparatus that comprises a list of elements is not necessarily limited to those elements expressly listed, but may include other elements not expressly listed or inherent to such product or apparatus.

The term "module" as used in the embodiments of the present disclosure refers to any known or later developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware or/and software code that is capable of performing the function associated with that element.

Embodiments of the present disclosure relate to the field of semiconductors, and more particularly to the field of dynamic random access memory (Dynamic Random Access Memory, abbreviated DRAM) testing. Among them, DRAM has been widely used as a common memory chip in various electronic devices.

The memory chip generally includes a plurality of Bit Lines (BL), a plurality of Word Lines (WL), and a plurality of memory cells, wherein each memory cell is connected to a corresponding one of the Word lines WL and the Bit Line BL.

For a better understanding of the embodiments of the present disclosure, referring to fig. 1, fig. 1 is a schematic layout diagram of a memory chip according to an embodiment of the present disclosure.

In some embodiments, taking one Bank in a DRAM memory as an example, a plurality of bit lines may be divided into 128 bit line groups, each having 8 bit lines therein, and the bit lines in each bit line group are denoted as BL0, BL1, BL2 … … BL7 for convenience of description below. The plurality of word lines may be divided into 8192 word line groups, each having 8 word lines therein, and the bit lines in each of the bit line groups are denoted as WL0, WL1, WL2 … … WL7 for convenience of description hereinafter.

The plurality of memory cells P11-P88 are distributed in a matrix, wherein the memory cells in the first column are all connected with a word line WL0, the memory cells in the second column are all connected with a word line WL1, and the memory cells in the eighth column are all connected with a word line WL7 by analogy; the memory cells of the first row are all connected to bit line BL0, the memory cells of the second row are all connected to bit line BL1, and so on, the memory cells of the eighth row are all connected to bit line BL7, such that each memory cell is connected to one word line WL and one bit line BL.

Each memory cell generally includes a capacitor structure and a transistor having a gate connected to a Word Line (WL), a drain connected to a Bit Line (BL), and a source connected to the capacitor structure; the voltage signal on WL can control the on or off of the transistor, and further read the data signal stored in the capacitor structure through BL, or write the data signal into the capacitor structure through BL for storage.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a memory cell of a memory chip according to an embodiment of the disclosure.

In some embodiments, each memory cell 10 includes a transistor 12 and a capacitor 11, where the gate of the transistor 12 is connected to the word line WL, the source of the transistor 12 is connected to the bit line BL, the drain of the transistor 12 is connected to the capacitor 11, and it should be noted that the source of the transistor 12 may also be connected to the capacitor 11, and accordingly, the drain of the transistor 12 is connected to the bit line BL.

In some embodiments, the data line BL may write a high signal "1" to the storage capacitor C when the signal on the word line WL turns on the switching transistor 12, and the charge on the storage capacitor C slowly leaks over time after the signal on the word line WL turns off the switching transistor 12. The time between the leakage of the storage capacitor C from the high level signal '1' to the low level signal '0' is the data storage time of the storage capacitor C. The data storage time of the storage capacitor C needs to be longer than a preset time to realize the dynamic storage function of the dynamic random access memory.

In modern integrated circuit manufacturing processes, one-time programmable memories (eFuses) have been widely used in DRAMs, such as recording chip IDs, production information, repair row and column information, and the like.

With the continued shrinking of semiconductor integrated device feature sizes and the use of new materials and structures, the critical dimensions of semiconductor memory devices are becoming smaller, thereby limiting the number of readable times for fuse circuits. In order to ensure reliability of eFuse data reading, accurate assessment of the effective life of the fuse circuit is required.

In view of the above technical problems, the embodiments of the present disclosure provide a method for testing the service life of a fuse circuit, based on the NBTI effect of a semiconductor device, by applying NBTI stresses of different durations to a fuse reading circuit, accelerating the burn-in of the fuse reading circuit, and then measuring the change of specific parameters of the fuse circuit, the change rule of the parameter degradation along with the time of the NBTI stress can be obtained, so that the service life of the fuse circuit can be accurately estimated. The following description will be made with reference to the detailed examples.

In some embodiments, the fuse circuit includes a fuse reading circuit and a fuse array formed by fuse units, for example, the fuse array may be formed by n×n fuse units.

In some embodiments, the fuse array may be arranged in the same manner as the memory cell array shown in fig. 1.

Alternatively, each fuse unit may include a fuse.

The fuse reading circuit is used for reading the fusing state of each fuse unit in the fuse array.

Illustratively, if the fuse of a certain fuse cell is blown (blow), the fuse read circuit outputs a 1; if the fuse of a certain fuse cell is not blown, the fuse read circuit outputs 0.

In some embodiments, the fuse read circuit includes a Latch (Latch) circuit that may include an inverter or the like.

Optionally, the inverter includes an NMOS tube and a PMOS tube, the input end of the inverter is a gate commonly connected to the NMOS tube and the PMOS tube, and the output end is a drain commonly connected to the NMOS tube and the PMOS tube.

For a better understanding of the embodiments of the present disclosure, referring to fig. 3, fig. 3 is a schematic structural diagram of an inverter provided in the embodiments of the present disclosure.

In fig. 3, the inverter includes a P-channel enhancement MOS (pMOS) and an N-channel enhancement MOS (NMOS).

Wherein when input v _IN When the voltage is low, the pMOS is turned on, the NMOS is turned off, and the output v _OUT Is a high voltage; when v _IN When the voltage is high, the NMOS is turned on, the pMOS is turned off, and the output v _OUT Is low.

The main failure mechanism of the inverter is NBTI effect, which refers to degradation of a series of electrical parameters caused by applying negative grid voltage to the PMOSFET at high temperature (the common stress condition is grid oxide electric field at constant temperature of 125 ℃, and the source electrode, the drain electrode and the substrate are grounded).

Among them, as the size of semiconductor devices is reduced and new materials and structures are used, the NBTI effect of the semiconductor devices is more and more remarkable, and the performance of the semiconductor devices is more affected, for the following reasons:

1) The physical dimensions of semiconductor devices continue to decrease, and the operating voltage does not decrease as the physical dimensions shrink, resulting in increased electric field stress on the device. In addition, the threshold voltage of the device is not reduced in equal proportion with the working voltage, and the leakage current is degraded in a larger proportion under the same voltage.

2) With the increase of circuit integration, the increase of chip power consumption causes the increase of device operating temperature to make NBTI more serious.

3) The introduction of new materials in the MOS structure causes the generation of dielectric layer traps under NBTI stress, so that NBTI is more remarkable.

The explanation model that NBTI uses is a reactive diffusion model, and when the grid electrode of a semiconductor device is under negative bias, a large number of Si-H bonds are formed at the Si/SiO2 interface of the semiconductor device after hydrogen passivation. Under the action of a vertical electric field, the generated holes react with Si-H to separate hydrogen atoms and form H, H + or H2. The reacted silicon dangling bonds attract a charge, becoming a positively charged interface trap charge. The unstable state thus formed is called an interface state, which is a reversible electrochemical reaction. The voltage-bearing terminal and the recovery stage can be divided according to the difference of the gate voltage and the source voltage.

When the transistor starts to operate, the gate voltage and the source voltage of the PMOS transistor are in a negative bias state, and this stage may be referred to as a voltage-receiving stage. When subjected to high temperatures and a compressive state for a period of time, the Si-H bonds with weak forces at the Si-SiO2 interface break, leaving interface traps and hydrogen atoms in the channel. While the instability of the hydrogen atoms may make it easier to combine into hydrogen gas and spill over the gate of the device. As the duration of the stressed state increases, the density of interface traps increases linearly, resulting in an increasing threshold voltage of the PMOS transistor.

This phase may be a recovery phase when the gate voltage, source voltage of the PMOS transistor is in a positive bias state. At this time, part of the hydrogen gas previously bound by the hydrogen atoms is re-broken under the energy and re-bound with the interface traps (si+) under the action of the reverse electric field to form new si—h bonds. This reduces the density of interface traps within the channel, allowing the threshold voltage of the transistor to be restored.

Although the threshold voltage of the PMOS transistor can be recovered under the NBTI effect, the NBTI effect has only a partial recovery characteristic. When the PMOS transistor is in a pressed stage, a large number of Si-H bonds are broken, so that the threshold voltage of the transistor rises rapidly, when the transistor is switched from the pressed stage to a recovery stage, the threshold voltage of the transistor gradually drops, the state before the voltage is not pressed can not be recovered all the time, and a section of unrecoverable aging value is left after each pressed stage. When the NBTI effect is in the recovery stage, the number of regenerated Si-H bonds is only a small part, and the number of Si-H bonds cannot always be recovered to the state before the compression stage, so the NBTI effect only has partial recovery characteristics. The threshold voltage of the PMOS transistor will therefore rise continuously during the process of experiencing the NBTI effect, thereby increasing the propagation delay of the logic gate, eventually leading to gradual degradation or even failure of the device performance.

According to experimental study of NBTI effect, NBTI degradation factors of a MOS device are mainly influenced by gate voltage Vg and temperature T, different structural sizes (gate width W and gate length L) of the device and some process factors in device manufacturing.

When determining the NBTI of a PMOS device, normally, NBTI stress is applied to the device to be tested for a certain time, and then the change of specific parameters of the device is measured to obtain the change rule of the parameter degradation quantity along with the stress time, so that the service life of the device is estimated.

Based on the failure mechanism described above, in some embodiments of the present disclosure, accelerated burn-in testing is performed on the fuse read circuit to evaluate the reliability of the fuse circuit after simulating 1 year/5 years/10 years or more of normal use of the fuse circuit.

Referring to fig. 4, fig. 4 is a flowchart illustrating steps of a method for testing a service life of a fuse circuit according to an embodiment of the disclosure. In one possible implementation manner, the method for testing the service life of the fuse circuit includes:

s401, reading a first fusing state of each fuse unit in the fuse array by using a fuse reading circuit.

In the embodiment of the disclosure, the first fusing state of each fuse cell in the fuse array may be read in advance by using the fuse reading circuit and then saved.

In some embodiments, a plurality of fuse circuits of the same type may also be prepared in advance, and in the same manner, the first blowing states of the respective fuse cells in the fuse array of each fuse circuit are read and then saved separately.

S402, applying NBTI stress to the fuse reading circuit according to the time periods of applying the NBTI stresses.

In some embodiments, the plurality of NBTI stress application durations may be determined based on a functional relationship between a pre-set NBTI stress application duration and an estimated lifetime duration; wherein, each NBTI stress application duration corresponds to a different estimated life duration.

For example, based on a preset functional relationship between the NBTI stress applying duration and the estimated lifetime duration, it is determined that the NBTI stress applying duration corresponding to the estimated lifetime of 1 year is t1, the NBTI stress applying duration corresponding to the estimated lifetime of 2 years is t2, and the NBTI stress applying duration corresponding to the estimated lifetime of 3 years is t3, … …

After determining the plurality of NBTI stress applying durations, applying NBTI stress to the fuse read circuit according to the respective NBTI stress applying durations.

Optionally, applying the NBTI stress to the fuse read circuit includes applying a high voltage Vstress to the fuse read circuit.

In some embodiments, NBTI stress may be applied to the PMOS tubes in the fuse read circuit according to a plurality of NBTI stress application durations, respectively.

S403, after the application time of each NBTI stress is over, the second fusing state of each fuse unit in the fuse array is read again by using a fuse reading circuit.

In some embodiments, the example, assuming the determined NBTI stress application duration includes: step S403 may include:

1) When the time period of applying NBTI stress to the fuse reading circuit in the first fuse circuit reaches t1, the NBTI stress applied to the fuse reading circuit is canceled, and then the second fusing state of each fuse unit in the fuse array of the first fuse circuit is read again by using the fuse reading circuit.

2) When the time period of applying NBTI stress to the fuse reading circuit in the second fuse circuit reaches t2, the NBTI stress applied to the fuse reading circuit is canceled, and then the second fusing state of each fuse unit in the fuse array of the second fuse circuit is read again by using the fuse reading circuit.

3) When the duration of applying NBTI stress to the fuse reading circuit in the third fuse circuit reaches t3, the NBTI stress applied to the fuse reading circuit is canceled, and then the second fusing state of each fuse unit in the fuse array of the third fuse circuit is read again by using the fuse reading circuit.

In other embodiments, the step S403 may also include:

1) When the time period of applying NBTI stress to the fuse reading circuit in the fuse circuit reaches t1, the NBTI stress applied to the fuse reading circuit is canceled, and then the second blowing state of each fuse unit in the fuse array of the fuse circuit is read again by using the fuse reading circuit.

2) And continuing to apply NBTI stress to the fuse reading circuit in the fuse circuit, canceling the NBTI stress applied to the fuse reading circuit when the accumulated applying time of the NBTI stress reaches t2, and then re-reading the second blowing state of each fuse unit in the fuse array of the fuse circuit by using the fuse reading circuit.

2) And continuing to apply NBTI stress to the fuse reading circuit in the fuse circuit, canceling the NBTI stress applied to the fuse reading circuit when the accumulated applying time of the NBTI stress reaches t3, and then re-reading the second blowing state of each fuse unit in the fuse array of the fuse circuit by using the fuse reading circuit.

S404, determining the service life of the fuse circuit according to the first fusing state, the application time of each NBTI stress, and the second fusing state read again by the fuse reading circuit after each NBTI stress application time is over.

In some embodiments, by way of example, assuming still that the determined duration of applying the NBTI stress includes t1, t2, and t3, and assuming that the duration of applying the NBTI stress to the fuse reading circuit in the first fuse circuit reaches t1, the second blowing state of each fuse cell in the fuse array of the first fuse circuit, which is re-read by using the fuse reading circuit, is consistent with the first blowing state of each fuse cell in the fuse array of the first fuse circuit, which is read by using the fuse reading circuit, it may be estimated that the read information of the fuse circuit is valid after 1 year of use of the first fuse circuit.

When the duration of applying the NBTI stress to the fuse reading circuit in the second fuse circuit reaches t2, the second blowing state of each fuse cell in the fuse array of the second fuse circuit, which is re-read by the fuse reading circuit, is consistent with the first blowing state of each fuse cell in the fuse array of the second fuse circuit, which is read by the fuse reading circuit, it can be estimated that the reading information of the fuse circuit is valid after 2 years of use of the second fuse circuit.

When the duration of applying the NBTI stress to the fuse reading circuit in the third fuse circuit reaches t3, the second blowing state of each fuse cell in the fuse array of the third fuse circuit, which is re-read by the fuse reading circuit, is inconsistent with the first blowing state of each fuse cell in the fuse array of the third fuse circuit, which is read by the fuse reading circuit, it can be estimated that the third fuse circuit will have an error in reading after 3 years of use.

By the above comparison, it can be determined that the service life of the fuse circuit is 2 years.

According to the testing method for the service life of the fuse circuit, provided by the embodiment of the disclosure, based on the NBTI effect of the semiconductor device, NBTI stresses with different durations are applied to the fuse reading circuit, ageing of the fuse reading circuit is accelerated, then the change of specific parameters of the fuse circuit is measured, and the change rule of the parameter degradation amount along with the NBTI stress time can be obtained, so that the service life of the fuse circuit can be accurately estimated.

Based on what is described in the above embodiments, in some embodiments of the present disclosure, the initial blowing states of the respective fuse cells in the above fuse array may be read in advance; and then inputting a blowing instruction to a corresponding fuse unit in the fuse array according to the preset topology data.

For example, referring to fig. 5 and 6, fig. 5 and 6 are schematic diagrams of two topology data structures provided in the embodiments of the present disclosure, respectively.

In fig. 5 and 6, "1" means fused and "0" means not fused.

After a blowing instruction is input to a corresponding fuse unit in the fuse array according to the preset topology data, a first blowing state of each fuse unit in the fuse array is read by using a fuse reading circuit.

In some embodiments, the theoretical blowing state of each fuse unit in the fuse array may be determined based on the pre-read initial blowing state of each fuse unit in the fuse array and the pre-set topology data, and then it is determined whether the first blowing state of each fuse unit in the fuse array read by the fuse reading circuit is consistent with the theoretical blowing state, if so, it indicates that the fuse circuit works normally, and a subsequent testing step may be performed; if the fuse circuits are inconsistent, the fuse circuits are abnormal in operation, and the fuse circuits need to be repaired before subsequent testing steps can be performed.

In some embodiments of the present disclosure, a functional relationship between the NBTI stress application duration t and the estimated lifetime duration Y may be set as:

t＝(Vstress/Vop)^a*Y

Alternatively, the estimated life duration Y may be in days, months, or years, which is not limited in the embodiments of the present disclosure.

In some embodiments, a is ≡ 1.

In some embodiments of the present disclosure, in assessing the life of a fuse circuit, the following steps may be included:

1. and comparing the first fusing state with the second fusing state read again by the fuse reading circuit after the application time period of each NBTI stress is over.

2. And determining the maximum value of NBTI stress applying time duration corresponding to the fuse reading circuit under the condition that the first fusing state is consistent with the second fusing state re-read by the fuse reading circuit.

3. And determining the estimated life time corresponding to the maximum value according to the functional relation between the NBTI stress applying time and the estimated life time.

4. And determining the estimated life time corresponding to the maximum value as the service life of the fuse circuit.

According to the testing method for the service life of the fuse circuit, the first fusing state of each fuse unit in the fuse array is firstly read by the fuse reading circuit, then NBTI stress is respectively applied to the fuse reading circuit according to a plurality of preset NBTI stress applying time periods, and then the second fusing state of each fuse unit in the fuse array is read again by the fuse reading circuit after each NBTI stress applying time period is finished; and according to the first fusing state, the NBTI stress applying time periods and the second fusing state read again by the fuse reading circuit after each NBTI stress applying time period is finished, the service life of the fuse circuit can be estimated. That is, in the embodiment of the present disclosure, the aging of the fuse reading circuit may be accelerated by using the NBTI effect of the semiconductor device, and the service life of the fuse circuit may be estimated according to the correspondence between the accelerated aging time and the service life of the fuse reading circuit.

Based on what is described in the above embodiments, a testing apparatus for a service life of a fuse circuit is also provided in the embodiments of the disclosure. The fuse circuit comprises a fuse reading circuit and a fuse array formed by fuse units.

Referring to fig. 7, fig. 7 is a schematic program module of a testing apparatus for service life of a fuse circuit according to an embodiment of the disclosure, where the testing apparatus 70 for service life of a fuse circuit includes:

a first reading module 701 is configured to read a first blowing state of each fuse cell in the fuse array by using the fuse reading circuit.

The processing module 702 is configured to apply NBTI stresses to the fuse reading circuit according to a plurality of NBTI stress applying durations, respectively.

And a second reading module 703, configured to re-read, by using the fuse reading circuit, the second blowing state of each fuse cell in the fuse array after each of the NBTI stress applying periods is completed.

And an evaluation module 704, configured to determine a service life of the fuse circuit according to the first blowing state, the NBTI stress applying periods, and the second blowing state re-read by the fuse reading circuit after each of the NBTI stress applying periods is completed.

According to the testing device for the service life of the fuse circuit, based on the NBTI effect of the semiconductor device, NBTI stresses with different durations are applied to the fuse reading circuit, ageing of the fuse reading circuit is accelerated, then the change of specific parameters of the fuse circuit is measured, and the change rule of the parameter degradation quantity along with the NBTI stress time can be obtained, so that the service life of the fuse circuit can be accurately estimated.

In some embodiments, the first read module 701 is to:

In some embodiments, the processing module 702 is further to:

determining a plurality of NBTI stress applying durations based on a preset functional relation between the NBTI stress applying durations and the estimated service life durations; wherein each NBTI stress application period corresponds to a different estimated life period.

t＝(Vstress/Vop)^a*Y

In some embodiments, the evaluation module 704 is to:

In some embodiments, the inverter includes an NMOS tube and a PMOS tube, an input terminal of the inverter is a gate commonly connected to the NMOS tube and the PMOS tube, and an output terminal of the inverter is a drain commonly connected to the NMOS tube and the PMOS tube.

It should be noted that, in the embodiment of the disclosure, details of the specific execution of the first reading module 701, the processing module 702, the second reading module 703 and the evaluation module 704 may refer to relevant details in the embodiment shown in fig. 1 to 6, and details are not repeated here.

Further, based on what is described in the foregoing embodiments, there is also provided in an embodiment of the disclosure an electronic device including at least one processor and a memory; wherein the memory stores computer-executable instructions; the at least one processor executes computer-executable instructions stored in the memory to implement each step in the method for testing the service life of the fuse circuit as described in the above embodiment, which is not described herein.

For a better understanding of the embodiments of the present disclosure, referring to fig. 8, fig. 8 is a schematic diagram of a hardware structure of an electronic device according to an embodiment of the present disclosure.

As shown in fig. 8, the electronic apparatus 80 of the present embodiment includes: a processor 801 and a memory 802; wherein:

a memory 802 for storing computer-executable instructions;

the processor 801 is configured to execute the computer-executable instructions stored in the memory to implement the steps of the method for testing the service life of the fuse circuit described in the foregoing embodiments, and may be specifically referred to as related description in the foregoing method embodiments.

Alternatively, the memory 802 may be separate or integrated with the processor 801.

When the memory 802 is provided separately, the device further comprises a bus 803 for connecting said memory 802 and the processor 801.

Further, based on the description in the foregoing embodiments, a computer readable storage medium is further provided in the embodiments of the present disclosure, where computer executable instructions are stored in the computer readable storage medium, and when the processor executes the computer executable instructions, the steps of the method for testing the service life of the fuse circuit described in the foregoing embodiments are implemented, which is not described herein again.

Further, based on the descriptions in the foregoing embodiments, a computer program product is also provided in the embodiments of the present disclosure, where the computer program product includes a computer program that, when executed by a processor, implements each step of the method for testing the service life of a fuse circuit as described in the foregoing embodiments, and this embodiment is not repeated herein.

It should be understood that in several embodiments provided by the present disclosure, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the division of the modules is merely a logical function division, and there may be additional divisions when actually implemented, for example, multiple modules may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or modules, which may be in electrical, mechanical, or other forms.

The modules described as separate components may or may not be physically separate, and components shown as modules may or may not be physical units, may be located in one place, or may be distributed over multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional module in the embodiments of the present disclosure may be integrated in one processing unit, or each module may exist alone physically, or two or more modules may be integrated in one unit. The units formed by the modules can be realized in a form of hardware or a form of hardware and software functional units.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present disclosure, and not for limiting the same; although the present disclosure has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A testing method of the service life of a fuse circuit is characterized in that the fuse circuit comprises a fuse reading circuit and a fuse array formed by fuse units; the method comprises the following steps:

applying NBTI stress to the fuse reading circuit according to a plurality of negative bias temperature instability NBTI stress applying periods;

2. The method of claim 1, wherein the reading, with the fuse read circuit, the first blown state of each fuse cell in the fuse array comprises:

3. The method of claim 1, wherein before applying the NBTI stress to the fuse read circuit in accordance with the respective plurality of NBTI stress application durations, further comprising:

4. The method of claim 3, wherein the NBTI stress application period t is as a function of the estimated lifetime period Y:

t＝(Vstress/Vop)^a*Y

5. The method of claim 3 or 4, wherein said determining the service life of the fuse circuit based on the first blowing state, the respective NBTI stress application durations, and the second blowing state re-read by the fuse reading circuit after each of the NBTI stress application durations has ended comprises:

6. The method of claim 1, wherein the fuse reading circuit comprises an inverter, the inverter comprises an NMOS tube and a PMOS tube, an input end of the inverter is a gate commonly connected to the NMOS tube and the PMOS tube, and an output end of the inverter is a drain commonly connected to the NMOS tube and the PMOS tube.

7. The device for testing the service life of the fuse circuit is characterized by comprising a fuse reading circuit and a fuse array formed by fuse units; the device comprises:

8. The apparatus of claim 7, wherein the first reading module is to:

9. The apparatus of claim 7, wherein the processing module is further configured to:

10. The apparatus of claim 9, wherein the NBTI stress application period t is a functional relationship with the estimated lifetime period Y:

t＝(Vstress/Vop)^a*Y

11. The apparatus of claim 9 or 10, wherein the evaluation module is configured to:

12. The apparatus of claim 7, wherein the fuse read circuit comprises an inverter comprising an NMOS transistor and a PMOS transistor, wherein an input terminal of the inverter is a gate commonly connected to the NMOS transistor and the PMOS transistor, and an output terminal of the inverter is a drain commonly connected to the NMOS transistor and the PMOS transistor.

13. An electronic device, comprising: at least one processor and memory;

the memory stores computer-executable instructions;

the at least one processor executing computer-executable instructions stored in the memory causes the at least one processor to perform the method of testing the life of a fuse circuit as claimed in any one of claims 1 to 6.

14. A computer readable storage medium having stored therein computer executable instructions which, when executed by a processor, implement a method of testing the lifetime of a fuse circuit as claimed in any one of claims 1 to 6.

15. A computer program product comprising a computer program which, when executed by a processor, implements a method of testing the lifetime of a fuse circuit as claimed in any one of claims 1 to 6.