CN117524121A - Display driving circuit and display device - Google Patents
Display driving circuit and display device Download PDFInfo
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- CN117524121A CN117524121A CN202210914399.9A CN202210914399A CN117524121A CN 117524121 A CN117524121 A CN 117524121A CN 202210914399 A CN202210914399 A CN 202210914399A CN 117524121 A CN117524121 A CN 117524121A
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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Abstract
The application discloses display drive circuit and display device, this display drive circuit includes: a plurality of address input circuits each generating and outputting an address signal based on a clock signal and an encoding signal; the input end of each decoder receives an address signal output by an address input circuit, decodes each address signal in the received address signals one by one, and sequentially outputs trigger signals through a plurality of output ends of the decoder; and a plurality of signal latch circuits, an input terminal of each of the signal latch circuits receiving a trigger signal output from one of a plurality of output terminals of the decoder, the signal latch circuits latching the received trigger signal based on the clock signal and continuously outputting the trigger signal. Based on the mode, the display driving efficiency can be effectively improved.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a display driving circuit and a display device.
Background
In the prior art, when refreshing pixels corresponding to each row or each column in a pixel array in a display device, it is generally required to send a corresponding trigger signal to each row or each column of pixel circuits in the pixel array one by one, so as to realize the row-by-row or column-by-column refreshing of a picture corresponding to the display device.
The disadvantage of the prior art is that, when the decoder sends the corresponding trigger signal to one row or one column of pixel circuits in the pixel array to trigger the refresh of the pixel circuits, the decoder needs to go through the decoding process of an address signal and continuously send the trigger signal obtained by the decoding process to the corresponding pixel circuit until the refresh is completed, that is, the refresh process duration corresponding to the one row or one column of pixel circuits needs to include the refresh process duration and the trigger signal receiving duration, which makes the refresh duration of each row or each column of pixel circuits in the pixel array longer, and further makes the display driving efficiency lower.
Disclosure of Invention
The technical problem that this application mainly solves is how to improve display driving efficiency.
In order to solve the technical problem, a first technical scheme adopted in the application is as follows: a display driving circuit, comprising: a plurality of address input circuits, a first input terminal of each address input circuit receiving a clock signal, a second input terminal of each address input circuit receiving a code signal, each address input circuit generating and outputting an address signal based on the clock signal and the code signal; the decoder comprises a plurality of input ends, the input end of each decoder respectively receives an address signal output by an address input circuit, and the decoder performs decoding processing on each address signal in the received address signals one by one and sequentially outputs a trigger signal through a plurality of output ends of the decoder; a plurality of signal latch circuits, an input terminal of each of which receives a trigger signal output from one of a plurality of output terminals of the decoder, the signal latch circuits latching the received trigger signal based on the clock signal and continuously outputting the trigger signal; the decoder is used for decoding the next address signal in the address signals after the current trigger signal is received by the corresponding signal latch circuit, wherein the current trigger signal is a trigger signal output by decoding based on one address signal in the address signals.
The display driving circuit further comprises a pixel array module, wherein the pixel array module comprises a plurality of pixel unit groups, each pixel unit group comprises a plurality of pixel units, and the input end of each pixel unit group is connected with the output end of the corresponding signal latch circuit; the pixel unit group is used for controlling the corresponding pixel units to respectively acquire the pixel display data when receiving the trigger signal, and the pixel units respectively update the display based on the pixel display data when receiving the trigger signal.
The display driving circuit further comprises a data storage module, and the data storage module is respectively connected with the plurality of pixel unit groups; the pixel unit group is specifically used for controlling the corresponding pixel units to respectively acquire the pixel display data from the data storage module when the trigger signal is received.
Each signal latch circuit comprises a switch module and a latch module; the first input end of the switch module receives the clock signal, the second input end of the switch module receives the trigger signal output by the corresponding output end of the decoder, and the output end of the switch module is connected with the input end of the latch module; the switch module is used for conducting the second input end and the output end of the switch module and outputting a trigger signal to the latch module when based on the clock signal; the latch module is used for latching the trigger signal after receiving the trigger signal and continuously outputting the trigger signal when latching the trigger signal.
The switch module is a transmission gate module, the transmission gate module comprises an NMOS tube and a PMOS tube, the first end of the NMOS tube is connected with the first end of the PMOS tube, the second end of the NMOS tube is connected with the second end of the PMOS tube, the first end of the NMOS tube is an input end of the switch module, and the second end of the NMOS tube is an output end of the switch module; the driving end of the NMOS tube receives the clock signal, and the driving end of the PMOS tube receives the complementary signal of the clock signal.
The latch module comprises a first NOT gate, a second NOT gate and a trigger signal output circuit, wherein the output end of the first NOT gate is connected with the input end of the second NOT gate, and the output end of the second NOT gate is connected with the input end of the first NOT gate; the input end of the first NOT gate is the input end of the latch module, the output end of the first NOT gate is connected with the input end of the trigger signal output circuit, the output end of the trigger signal output circuit is the output end of the latch module, and the trigger signal output circuit is used for outputting a trigger signal based on the signal output by the first NOT gate.
The first input end of the trigger signal output circuit receives the time control signal, the second input end of the trigger signal output circuit receives the signal output by the first NOT gate, and the trigger signal output circuit is used for outputting the trigger signal in preset output time based on the time control signal and the signal output by the first NOT gate.
The trigger signal output circuit comprises a NOR gate; the first input end of the NOR gate receives the time control signal, the second input end of the NOR gate receives the signal output by the first NOR gate, and the output end of the NOR gate outputs the trigger signal in the preset output time corresponding to the low level interval of the time control signal.
The switch module is an NMOS tube, the first end of the NMOS tube is an input end of the switch module, the second end of the NMOS tube is an output end of the switch module, the driving end of the NMOS tube receives a clock signal, or the switch module is a PMOS tube, the first end of the PMOS tube is an input end of the switch module, the second end of the PMOS tube is an output end of the switch module, and the driving end of the PMOS tube receives a complementary signal of the clock signal.
In order to solve the technical problem, a second technical scheme adopted by the application is as follows: a display device includes the display driving circuit.
The beneficial effects of the application are that: compared with the prior art, the display driving circuit in the technical scheme of the application can latch and continuously output the trigger signal output by the decoder through the plurality of signal latch circuits, so that the decoder can start decoding processing of the next address signal after transmitting the trigger signal to the corresponding signal latch circuit without maintaining transmission of the trigger signal.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram showing the structure of a first embodiment of a driving circuit of the present application;
FIG. 2 is a timing diagram of one embodiment of a clock signal according to the present application;
FIG. 3 is a schematic diagram of a second embodiment of the driving circuit of the present application;
FIG. 4 is a schematic diagram of a third embodiment of a driving circuit according to the present application;
fig. 5 is a schematic diagram showing the structure of a fourth embodiment of the driving circuit of the present application;
fig. 6 is a schematic structural view showing a fifth embodiment of the driving circuit of the present application;
fig. 7 is a schematic diagram showing the structure of a sixth embodiment of the driving circuit of the present application;
fig. 8 is a schematic structural view of an embodiment of the display device of the present application.
Detailed Description
The present application is described in further detail below with reference to the drawings and examples. It is specifically noted that the following examples are only for illustration of the present application, but do not limit the scope of the present application. Likewise, the following embodiments are only some, but not all, of the embodiments of the present application, and all other embodiments obtained by one of ordinary skill in the art without inventive effort are within the scope of the present application.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
In the description of the present application, it is to be understood that the terms "mounted," "configured," "connected," and "connected" are to be interpreted broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected, unless explicitly stated and defined otherwise; the connection can be mechanical connection or electric connection; may be directly connected or may be connected via an intermediate medium. It will be apparent to those skilled in the art that the foregoing is in the specific sense of this application.
The present application first proposes a display driving circuit, referring to fig. 1, fig. 1 is a schematic structural diagram of a first embodiment of the display driving circuit of the present application, and as shown in fig. 1, the display driving circuit includes a plurality of address input circuits 11, a decoder 12, and a plurality of signal latch circuits 13.
The first input of each address input circuit 11 is arranged to receive a clock signal (CLK) provided by a clock circuit, the second input of each address input circuit 11 is arranged to receive a corresponding encoded signal, and the address input circuits 11 are arranged to process the received encoded signals to generate and output corresponding address signals.
The decoder 12 includes a plurality of input terminals, wherein each input terminal of the decoder 12 is respectively connected to an output terminal of a corresponding one of the address input circuits 11, so that the decoder can respectively receive the address signal inputted by each of the address input circuits 11 through each input terminal, and the decoder 12 can be used to simultaneously receive a plurality of address signals, or receive the address signals one by one, which is not limited herein. The decoder 12 may perform decoding processing on the received address signals one by one in a preset order and output trigger signals obtained by the decoding processing.
An input terminal of each signal latch circuit 13 is connected to one of a plurality of output terminals of the decoder 12, respectively, to receive the corresponding output first trigger signal. The input terminal of each signal locking circuit 13 also receives a clock signal, and after the output terminal of the corresponding decoder 12 transmits a first trigger signal, the corresponding connected signal latch circuit 13 is capable of receiving the first trigger signal based on the clock signal, latching the received trigger signal, and outputting a display driving signal based on the latched trigger signal. The display driving signal can be used for controlling a display device using the display driving circuit to refresh display data.
Wherein the decoder 12 is specifically configured to: after the current trigger signal is received by the corresponding signal latch circuit, decoding processing is performed on the next address signal in the plurality of address signals.
The current trigger signal may be a trigger signal output by the decoder 12 in a first time based on decoding processing performed on one address signal of the plurality of address signals, and the next address signal corresponds to an address signal to be decoded by the decoder 12 in a second time, wherein the second time is a time nearest to the first time after the first time. The first time and the second time are two clock cycles which are adjacent in sequence.
It should be noted that, each trigger signal may be used to trigger refresh display on a plurality of pixel units in a row or a column in the pixel array, and after receiving the trigger signal, the corresponding pixel unit may perform refresh display based on corresponding pixel display data.
In an application scenario, referring to fig. 2, fig. 2 is a timing diagram of an embodiment of the clock signal of the present application, and as shown in fig. 2, the clock signal appears in three clock cycles over time: based on the display driving circuit, the first clock period a, the second clock period B and the third clock period C take the first address signal and the second address signal of two adjacent decoding processes as examples, and the flow of the decoding process and the display driving is as follows:
in the first clock cycle a, the decoder 12 may perform decoding processing on the first address signal to obtain a corresponding first trigger signal.
In the second clock period B, the corresponding signal latch circuit 13 may receive the first trigger signal corresponding to the first address signal, latch the first trigger signal, and continuously output the first display driving signal to the outside based on the latched first trigger signal, and at the same time, the decoder 12 may stop outputting the first trigger signal, and start decoding the second address signal to obtain another corresponding first trigger signal.
In the third clock period C, the corresponding signal latch circuit 13 may receive the first trigger signal corresponding to the second address signal, latch the first trigger signal, and continuously output the second display driving signal to the outside based on the latched first trigger signal.
In practice, based on the display driving circuit, the decoding processing flow corresponding to any one address signal and the trigger signal output flow are separated into two clock periods in the clock signal for processing, so that the decoding processing of one address signal and the latching and outputting of the trigger signal corresponding to the other address signal can be simultaneously performed in the same clock period, the output interval time of a plurality of trigger signals is reduced, the total duration of refreshing display of each row/each column of pixel units row by row based on a plurality of trigger signals is reduced, and the efficiency of display driving is improved.
Compared with the prior art, the display driving circuit in the technical scheme of the application can latch and continuously output the trigger signal output by the decoder through the plurality of signal latch circuits, so that the decoder can start decoding processing of the next address signal after transmitting the trigger signal to the corresponding signal latch circuit without maintaining transmission of the trigger signal.
In an embodiment, referring to fig. 3, fig. 3 is a schematic structural diagram of a second embodiment of the display driving circuit of the present application, as shown in fig. 3, the display driving circuit further includes a pixel array module 14, the pixel array module 14 includes a plurality of pixel unit groups 141, each pixel unit group 141 includes a plurality of pixel units, and an input end of each pixel unit group 141 is connected to an output end of a corresponding signal latch circuit 13 to receive a corresponding trigger signal.
Each pixel unit group 141 is configured to control, when a trigger signal is received, a plurality of pixel units included in the pixel unit group to respectively acquire pixel display data, and each pixel unit is configured to display, when the trigger signal is received, based on the acquired pixel display data.
Specifically, the pixel array module 14 may include a pixel array formed by a plurality of pixel units, and each pixel unit group 141 may be a plurality of pixel units corresponding to one row or one column in the pixel array. After a plurality of pixel units in a certain row or a certain column receive corresponding trigger signals, the pixel units in the row or the column can respectively acquire pixel display data required to be displayed in corresponding positions from a designated data storage module, so that each pixel unit can perform refreshing display of pixel points based on the acquired pixel display data, and further the pixel units in each row or each column are sequentially refreshed and displayed, and finally the integral refreshing display of a display picture corresponding to a pixel array is completed.
Optionally, as shown in fig. 3, the display driving circuit further includes a data storage module 15, where the data storage module 15 is respectively connected to the plurality of pixel unit groups 141, and the pixel unit group 141 is specifically configured to control, when receiving the trigger signal, the plurality of pixel units included in the pixel unit group to respectively obtain the pixel display data from the data storage module 15.
Specifically, the data storage module 15 may be one or more, and each pixel unit group 141 is connected to the data storage module 15 storing the pixel display data required by the corresponding pixel unit group.
In an embodiment, referring to fig. 4, fig. 4 is a schematic structural diagram of a third embodiment of the display driving circuit of the present application, and as shown in fig. 4, each signal latch circuit 13 includes a switch module 131 and a latch module 132.
A first input terminal of the switch module 131 receives the clock signal, a second input terminal of the switch module 131 receives the first trigger signal output by the corresponding output terminal of the decoder, and an output terminal of the switch module 131 is connected to an input terminal of the latch module 132.
The switch module 131 is configured to turn on the second input terminal and the output terminal of the switch module 131 when based on the clock signal, and output a first trigger signal to the latch module 132. The latch module 132 is configured to latch the trigger signal after receiving the first trigger signal, and continuously output a display driving signal based on the latched first trigger signal.
Specifically, in an example, as shown in fig. 5, the switch module 131 includes a transmission gate module, where the transmission gate module includes an NMOS tube 1311 and a PMOS tube 1312, a first end of the NMOS tube 1311 is connected to a first end of the PMOS tube 1312, a second end of the NMOS tube 1311 is connected to a second end of the PMOS tube 1312, the first end of the NMOS tube 1311 is an input end of the switch module, the second end of the NMOS tube 1311 is an output end of the switch module, a driving end of the NMOS tube 1311 receives a clock signal, and a driving end of the PMOS tube 1312 receives the clock signal. In one embodiment of the present application, the clock signals received by the NMOS tube 1311 and the PMOS tube 1312 are complementary signals.
In another example, the switch module 131 may also be a single NMOS transistor, where the first end of the NMOS transistor is an input end of the switch module, the second end of the NMOS transistor is an output end of the switch module, and the driving end of the NMOS transistor receives the clock signal, or the switch module may be a single PMOS transistor, where the first end of the PMOS transistor is an input end of the switch module, the second end of the PMOS transistor is an output end of the switch module, and the driving end of the PMOS transistor receives a complementary signal of the clock signal.
Compared with a common switch, such as a single NMOS tube or a single PMOS tube, the transmission gate module has lower on resistance, higher off resistance and higher data transmission rate.
Optionally, as shown in fig. 6, the latch module 132 includes a first not gate 1321, a second not gate 1322, and a trigger signal output circuit 1323, where an output terminal of the first not gate 1321 is connected to an input terminal of the second not gate 1322, and an output terminal of the second not gate 1322 is connected to an input terminal of the first not gate 1321.
The input end of the first not gate 1321 is the input end of the latch module 132, the output end of the first not gate 1321 is connected to the input end of the trigger signal output circuit 1323, the output end of the trigger signal output circuit 1323 is the output end of the latch module, and the trigger signal output circuit 1323 is used for outputting a display driving signal based on the signal output by the first not gate 1321.
Specifically, the latch formed by the first not gate 1321 and the second not gate 1322 latches the first trigger signal received through the switch module 131, and continuously outputs the first trigger signal to the trigger signal output circuit 1323, and further outputs the display driving signal through the trigger signal output circuit 1323. Since the signal output through the first not gate 1321 is a second trigger signal complementary to the first trigger signal, the trigger signal output circuit 1323 converts the second complementary signal based on the time control signal to obtain the original first trigger signal, and then outputs the first trigger signal. That is, the display driving signal is the first trigger signal.
Further, as shown in fig. 6, the first input terminal of the trigger signal output circuit 1323 receives the time control signal (tc), the second input terminal of the trigger signal output circuit 1323 receives the signal output by the first not gate, and the trigger signal output circuit 1323 is configured to output the trigger signal within a preset output time based on the time control signal and the signal output by the first not gate.
Specifically, the trigger signal output circuit 1323 may determine a preset output time by the time control signal and output the corresponding trigger signal only within the preset output time.
It should be noted that, through the effect of the trigger signal output circuit 1323, the total duration of the trigger signal output can be regulated and controlled, so as to reserve the relevant processing duration of the corresponding row/column pixel units after receiving the trigger signal, ensure the normal operation of the refresh display of the corresponding display device, and improve the reliability of the display driving circuit.
Further, as shown in fig. 7, the trigger signal output circuit 1323 includes a nor gate.
The first input terminal of the nor gate receives the time control signal (tc), the second input terminal of the nor gate receives the signal output from the first nor gate 1321, and the output terminal of the nor gate outputs the trigger signal within a preset output time corresponding to a low level interval of the time control signal.
Specifically, as shown in fig. 7, it is assumed that the input terminal of the first not gate 1321 receives the trigger signal, and the trigger signal is a high level signal, and the latch output is a low level signal through the effect of the first not gate 1321, that is, the second input terminal of the nor gate receives the low level signal. At this time, if the first input end of the nor gate receives the low-level signal, the output end of the nor gate will output the same high-level signal as the trigger signal, if the first input end of the nor gate receives the high-level signal, the output end of the nor gate will output the low-level signal complementary to the trigger signal, and the length of the high-low level interval in the time control signal can be adjusted based on the characteristics, so as to adjust the preset output time, so that the nor gate only outputs the trigger signal in the preset output time, ensuring normal operation of refresh display of the corresponding display device, and improving the reliability of the display driving circuit.
The present application also discloses a display device, referring to fig. 8, fig. 8 is a schematic structural diagram of an embodiment of the display device of the present application, and as shown in fig. 8, the display device 20 includes a display driving circuit 21, where the display driving circuit 21 may be a display driving circuit in any one of the foregoing embodiments, and is not limited herein.
The display device may be any of a television, a tablet computer, a desktop display screen, a mobile phone and other types of display devices, and is specifically determined according to practical requirements, and is not limited herein. The screen of the display device may be a liquid crystal display screen, or may be other types of display screens, which may be specifically determined according to practical requirements, and is not limited herein.
Compared with the prior art, the display driving circuit in the technical scheme of the application can latch and continuously output the trigger signal output by the decoder through the plurality of signal latch circuits, so that the decoder can start decoding processing of the next address signal after transmitting the trigger signal to the corresponding signal latch circuit without maintaining transmission of the trigger signal.
In the description of the present application, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" is at least two, such as two, three, etc., unless explicitly defined otherwise.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and further implementations are included within the scope of the preferred embodiment of the present application in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the embodiments of the present application.
Logic and/or steps represented in the flowcharts or otherwise described herein, e.g., may be considered as a ordered listing of executable instructions for implementing logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device (which can be a personal computer, server, network device, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions). For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). In addition, the computer readable medium may even be paper or other suitable medium on which the program is printed, as the program may be electronically captured, via, for instance, optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory.
The foregoing description is only of embodiments of the present application, and is not intended to limit the scope of the patent application, and all equivalent structures or equivalent processes using the descriptions and the contents of the present application or other related technical fields are included in the scope of the patent application.
Claims (10)
1. A display driving circuit, comprising:
a plurality of address input circuits, each of which has a first input terminal receiving a clock signal and a second input terminal receiving a code signal, each of which generates and outputs an address signal based on the clock signal and the code signal;
the decoder comprises a plurality of input ends, the input end of each decoder respectively receives the address signals output by the address input circuit, and the decoder performs decoding processing on each address signal in the received address signals one by one and sequentially outputs trigger signals through a plurality of output ends of the decoder;
a plurality of signal latch circuits each having an input terminal receiving the trigger signal and a clock signal output from one output terminal of the decoder, the signal latch circuits latching the received trigger signal based on the clock signal and continuously outputting the trigger signal;
the decoder is configured to decode a next one of the plurality of address signals after a current trigger signal is received by the corresponding signal latch circuit, where the current trigger signal is the trigger signal output by decoding based on one of the plurality of address signals.
2. The display drive circuit according to claim 1, further comprising a pixel array module including a plurality of pixel cell groups, each of the pixel cell groups including a plurality of pixel cells, an input of each of the pixel cell groups being connected to an output of a corresponding one of the signal latch circuits;
the pixel unit group is used for controlling a plurality of corresponding pixel units to respectively acquire pixel display data when the trigger signal is received, and the pixel units respectively update the display based on the pixel display data when the trigger signal is received.
3. The display drive circuit according to claim 2, further comprising a data storage module connected to the plurality of pixel cell groups, respectively;
the pixel unit group is specifically configured to control a corresponding plurality of pixel units to respectively obtain the pixel display data from the data storage module when the trigger signal is received.
4. A display driver circuit according to any one of claims 1 to 3, wherein each of the signal latch circuits comprises a switch module and a latch module;
the first input end of the switch module receives the clock signal, the second input end of the switch module receives the trigger signal output by the corresponding output end of the decoder, and the output end of the switch module is connected with the input end of the latch module;
the switch module is used for conducting the second input end and the output end of the switch module based on the clock signal and outputting the trigger signal to the latch module;
the latch module is used for latching the trigger signal after receiving the trigger signal and continuously outputting the trigger signal when latching the trigger signal.
5. The display driving circuit according to claim 4, wherein the switch module is a transmission gate module, the transmission gate module includes an NMOS tube and a PMOS tube, a first end of the NMOS tube is connected to a first end of the PMOS tube, a second end of the NMOS tube is connected to a second end of the PMOS tube, the first end of the NMOS tube is an input end of the switch module, and the second end of the NMOS tube is an output end of the switch module;
the driving end of the NMOS tube receives the clock signal, and the driving end of the PMOS tube receives the complementary signal of the clock signal.
6. The display driver circuit of claim 4, wherein the latch module comprises a first not gate, a second not gate, and a trigger signal output circuit, the output of the first not gate being connected to the input of the second not gate, the output of the second not gate being connected to the input of the first not gate;
the input end of the first NOT gate is the input end of the latch module, the output end of the first NOT gate is connected with the input end of the trigger signal output circuit, the output end of the trigger signal output circuit is the output end of the latch module, and the trigger signal output circuit is used for outputting the trigger signal based on the signal output by the first NOT gate.
7. The display driver circuit of claim 6, wherein the first input of the trigger signal output circuit receives a time control signal, the second input of the trigger signal output circuit receives the signal output by the first not gate, and the trigger signal output circuit is configured to output the trigger signal within a preset output time based on the time control signal and the signal output by the first not gate.
8. The display drive circuit according to claim 7, wherein the trigger signal output circuit includes a nor gate;
the first input end of the nor gate receives a time control signal, the second input end of the nor gate receives a signal output by the first nor gate, and the output end of the nor gate outputs the trigger signal in a preset output time corresponding to a low level interval of the time control signal.
9. The display driving circuit according to claim 4, wherein the switch module is an NMOS transistor, a first end of the NMOS transistor is an input end of the switch module, a second end of the NMOS transistor is an output end of the switch module, and a driving end of the NMOS transistor receives the clock signal, or
The switch module is a PMOS tube, the first end of the PMOS tube is the input end of the switch module, the second end of the PMOS tube is the output end of the switch module, and the driving end of the PMOS tube receives the complementary signals of the clock signals.
10. A display device comprising the display driving circuit according to any one of claims 1 to 9.
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| CN202210914399.9A CN117524121A (en) | 2022-07-28 | 2022-07-28 | Display driving circuit and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210914399.9A CN117524121A (en) | 2022-07-28 | 2022-07-28 | Display driving circuit and display device |
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