CN117521595A - Signal processing method, system, electronic device and storage medium - Google Patents

Abstract

The embodiment of the invention provides a signal processing method, a system, electronic equipment and a storage medium, wherein the method is applied to a hardware acceleration simulation platform and comprises the following steps: acquiring a starting signal for controlling the design power-on of a chip; based on the starting signal, collecting bus data of a chip design formed by signal data of the key driving signal to obtain target bus data, wherein the target bus data comprises all or part of bus data; the key driving signal is related to the power-on time sequence of the chip design and is part of signals used in the power-on process; measuring the clock frequency of a clock signal of which the signal data validity is determined in the key driving signal to obtain the measurement data of the clock signal; and transmitting the target bus data and the measurement data. According to the technical scheme provided by the embodiment of the invention, only the data and the measurement data of part of key driving signals are collected, so that the data quantity in the power-on analysis of the chip design is reduced, and a data basis is provided for improving the analysis efficiency of the power-on failure reasons.

Description

Signal processing method, system, electronic device and storage medium

Technical Field

The embodiment of the application relates to the technical field of chip design, in particular to a signal processing method, a system, electronic equipment and a storage medium.

Background

Chip design and verification are one of links in the chip manufacturing process, and power-on success of chip design is a precondition for carrying out subsequent verification of chip design. In the initial stage of the project start of the chip, the stability of the design code of the chip is low, and the problems exist when the design code of the chip, namely the chip design, is transplanted to a hardware acceleration simulation platform for verification. Therefore, chip design power failure is a relatively common problem in hardware-accelerated simulation verification, and therefore, analysis of chip design power failure is very important. Under the background, how to provide a technical scheme, reduce the collection of data volume during the power failure analysis of the chip design, so as to provide a basis for improving the analysis efficiency of the power failure cause, and become a technical problem to be solved by those skilled in the art.

Disclosure of Invention

In view of this, embodiments of the present invention provide a signal processing method, system, electronic device, and storage medium, which reduce the data size collection during the power failure analysis of the chip design, so as to provide a basis for improving the analysis efficiency of the power failure cause.

In order to achieve the above purpose, the embodiment of the present invention provides the following technical solutions.

In a first aspect, an embodiment of the present invention provides a signal processing method, which is applied to a hardware acceleration simulation platform, including:

acquiring a starting signal, wherein the starting signal is used for controlling the power-on operation of chip design;

based on the starting signal, collecting the bus data designed by the chip to obtain target bus data, wherein the target bus data comprises all bus data or part of bus data; the bus data of the chip design is formed by signal data of key driving signals, the key driving signals are related to power-on time sequences of the chip design, and the key driving signals are part of signals in signals used when the chip design is powered on;

measuring the clock frequency of the clock signal in the key driving signal to obtain measurement data of the clock signal, wherein the clock frequency of the clock signal is used for determining the validity of signal data of the key driving signal in target bus data;

and transmitting the target bus data and the measurement data.

In a second aspect, an embodiment of the present invention provides a signal processing method, applied to a server, including:

Acquiring target bus data and measurement data of a chip design, wherein the target bus data and the measurement data of the chip design are generated by the signal processing method in the first aspect;

generating a time sequence waveform diagram based on the acquired target bus data; and obtaining a clock frequency based on the acquired measurement data; the timing waveform diagram includes an operational waveform of a critical drive signal, and a clock frequency of the clock signal is used to determine validity of signal data of the critical drive signal in the target bus data.

In a third aspect, an embodiment of the present invention provides a signal processing system, including:

a hardware-accelerated simulation platform configured to perform the signal processing method of the first aspect;

and a server for acquiring and storing target bus data and measurement data from the hardware acceleration simulation platform, the server being configured to perform the signal processing method according to the second aspect.

In a fourth aspect, an embodiment of the present invention provides an electronic device, including a memory storing a program and a processor calling the program stored in the memory, to perform the signal processing method according to the first aspect, or to perform the signal processing method according to the second aspect.

In a fifth aspect, an embodiment of the present invention provides a storage medium storing a program that when executed implements the signal processing method according to the first aspect, or implements the signal processing method according to the second aspect.

The signal processing method provided by the embodiment of the invention is applied to a hardware acceleration simulation platform, and after a starting signal for powering on a chip design is obtained, bus data of the chip design are acquired to obtain target bus data; the target bus data comprises all bus data or part of bus data; because the bus data of the chip design is formed by signal data of key driving signals, the key driving signals are related to the power-on time sequence of the chip design, and the key driving signals are part of signals in the signals used by the chip design when the chip is powered on; therefore, the data volume of the collected target bus data is smaller than the data volume obtained by collecting all signals used when the chip is powered on; meanwhile, the power-on failure analysis of the chip design is aimed at the analysis of key driving signals related to the power-on time sequence of the chip design, and the validity of signal data of the key driving signals influences the working characteristics of the chip design so as to influence the power-on time sequence of the chip design, so that the measurement of the clock frequency of the clock signals can be aimed at determining the validity of the signal data of the key driving signals in the target bus data, thereby being convenient for meeting analysis requirements when the power-on failure analysis of the chip design is carried out subsequently; therefore, the signal processing method provided by the embodiment of the invention can reduce the collection of the data volume during the power-on failure analysis of the chip design, and can provide a basis for improving the analysis efficiency of the power-on failure reason while meeting the power-on failure analysis of the subsequent chip design.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic flow chart of chip manufacture;

FIG. 2 is a flow chart of a signal processing method according to an embodiment of the invention;

FIG. 3 is a schematic diagram of another flow chart of a signal processing method according to an embodiment of the present invention;

FIG. 4 is a schematic flow chart of a signal processing method according to an embodiment of the invention;

FIG. 5 is a schematic flow chart of a signal processing method according to an embodiment of the present invention;

FIG. 6a is a schematic diagram showing the result of an implementation of a data processing method according to an embodiment of the present invention;

FIG. 6b is a schematic diagram showing the result of another implementation of the data processing method according to the embodiment of the present invention;

FIG. 7 is a schematic diagram showing the result of another implementation of the signal processing method according to the embodiment of the present invention;

FIG. 8 is a schematic diagram of a frame structure of a signal processing system according to an embodiment of the present invention;

fig. 9 is another schematic structural diagram of a signal processing system according to an embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

With the advancement of integrated circuit technology, the scale of chips has increased, for example, the entire system can be integrated into a single chip design, referred to as a system on chip (SoC). Among them, a typical SoC system may integrate CPU processor cores, memory controllers, various high-speed interface controllers, such as universal serial bus (USB, universal Serial Bus) interfaces, ethernet interfaces, high-speed serial computer expansion bus (PCIE, peripheral component interconnect express) interfaces, etc., data-on-chip networks, data bridges, power management systems, etc.

With the dramatic increase in the design scale of chip systems, there are correspondingly increasing challenges in the design of chip systems. In order to complete the design and manufacture of the chip system as soon as possible, the design and verification of the chip system is very important; and detecting whether the operation and data transmission requirements of the chip system are met or not through the design and verification of the chip system.

To facilitate understanding of the overall design and manufacturing process of the chip, please refer to fig. 1, fig. 1 is a schematic flow chart of the chip manufacturing process.

As shown in fig. 1, the overall flow of the chip manufacturing includes: system level requirements definition phase 001, architecture/system level design phase 002, chip design and chip design verification phase 003, physical design and physical verification phase 004, layout and post-release flow phase 005, chip fabrication phase 006, chip packaging and testing phase 007.

The chip design and the verification stage 003 of the chip design are two links in the chip manufacturing process. After the chip design is completed, the chip design can be obtained, and the chip design and verification stage 003 of the chip design is at the front end design of the chip. The chip design and verification stage 003 of the chip design comprises an IP level chip design 0031, an SoC level chip design 0033, an IP level chip design verification 0032 and an SoC level chip design verification 0034, which are respectively developed and ensured from the two angles of chip design and chip design verification to realize the requirement of system level definition, and the two requirements complement each other to reduce the defects of the chip in the design process. The earlier in the chip manufacturing process, the lower the time and cost it takes to find a problem, and therefore, chip design and verification of the chip design are critical to the quality of the chip manufacturing, the time costs spent, and the material costs.

The power-on monitoring is an important link in the verification of the chip design after the chip design is completed, and can be used for ensuring that the chip design can be correctly initialized and operated when the chip is powered on. In the initial stage of verification and starting of chip design, the stability of the design code of the chip design is low, and the problems existing when the design code is transplanted to a hardware acceleration simulation platform for verification are more. Chip design power-on failure is a common problem in the process of chip design verification by a hardware acceleration simulation platform, and is usually caused by errors generated by power-on time sequences of the chip design, so that analysis of the power-on failure reasons of the chip design is analysis of the power-on time sequences of the chip design, and signals related to the power-on time sequences of the chip design mainly comprise reset signals; the power supply signal, the indication signal of the power supply state, and the clock signal of the system are key driving signals, namely the reset signal, the power supply signal, the indication signal of the power supply state, and the clock signal of the system are main signals causing the power-on time sequence of the chip design to generate errors. In the verification process of the chip design, the chip design is electrified to cause a problem, and when the reason of the failure of the chip design in electrifying is analyzed, the signal waveforms of all the signals used in the chip design in electrifying can be captured, and the analysis can be performed according to the captured signal waveforms. However, since the time for acquiring the signal waveforms is relatively long and the acquired signal waveforms are relatively large, the signal waveforms need to be analyzed one by one when the signal waveforms are analyzed, so that the debugging (debug) for the power-on failure of the chip design is relatively high in complexity.

Therefore, in order to solve the above-mentioned problems, the embodiment of the present invention provides a signal processing method, which only collects signal data of a key driving signal affecting a power failure of a chip design, and avoids a capturing process of a signal waveform, so that analysis efficiency of a cause of the power failure of a subsequent chip design can be improved.

Referring to fig. 2, fig. 2 is a flow chart of a signal processing method according to an embodiment of the invention.

As shown in fig. 2, the process may include the steps of:

step S100, a starting signal is obtained, wherein the starting signal is used for controlling the power-on operation of chip design.

After the chip design is completed, the design code of the chip design can be verified (i.e. the chip design is verified) so as to verify whether the function of the chip design meets the design requirement of the chip design, and in the verification process of the chip design, the primary task is that the chip design is successfully powered on, so that a starting signal is required to be acquired, and the power-on operation of the chip design is controlled; after the chip design is powered on successfully, the design code of the chip design can be run smoothly, and verification of the chip design is performed.

The starting signal can control the power-on operation of starting the chip design so as to facilitate the subsequent chip design verification after the power-on is successful. Meanwhile, when power-on failure occurs in the power-on process of the chip design, the reason of the power-on failure of the chip design can be analyzed, so that the reason of the power-on failure of the chip design is analyzed and solved; the chip design can be ensured to be started normally. The reason analysis of the power failure of the chip design can rapidly and accurately locate the problem signal, and corresponding solving measures are adopted for the located problem signal. The analysis of the power failure reasons of the chip design has very important significance for ensuring the normal work of the chip design, improving the product quality and shortening the development period of the chip design.

Step S101, based on the starting signal, collecting the bus data of the chip design to obtain target bus data; and measuring the clock frequency of the clock signal in the key driving signal to obtain the measurement data of the clock signal.

Wherein the target bus data includes all or part of bus data; the bus data of the chip design is formed by signal data of key driving signals, the key driving signals are related to power-on time sequences of the chip design, and the key driving signals are part of signals in signals used when the chip design is powered on; the clock frequency of the clock signal is used for determining the validity of signal data of the key driving signal in the target bus data.

To facilitate computer processing of signals, an input analog signal is typically converted to a digital signal, whereby the digital signal is used to represent the state of an analog signal, i.e., a signal represented by a string of binary digits, to facilitate computer identification. In one time, the signal data of each signal is a binary number of single bits, so in the embodiment of the invention, bus data is formed according to the signal data of the key driving signals to be collected, so that the signal data of each key driving signal is transmitted by using a data bus. Because the data bus has high-speed transmission capability, the data transmission efficiency can be accelerated by using the data bus to transmit bus data.

Since the critical driving signal is part of the signals used by the chip design at power-up, in one embodiment, the bus data of the chip design is formed from the signal data of the critical driving signal, which may include:

the bus data of the chip design is formed by signal data of one key driving signal or by signal data of all key driving signals which are spliced.

When the bus data is formed by signal data of one critical driving signal, that is, each critical driving signal is independently transmitted by using the data bus, since the signal data of each critical driving signal is single-bit, the bus data is single-bit data at this time, and the target bus data includes all bus data or part of bus data, which may mean that the target bus data includes all signal data of one critical driving signal or part of signal data of one critical driving signal. Of course, in the subsequent analysis, the target bus data formed based on each key driving signal transmitted independently is processed independently, and then integrated and analyzed.

The signal data of each key driving signal is independently transmitted, so that the follow-up targeted checking of a certain key driving signal can be facilitated.

When the bus data is formed by splicing signal data of all the key driving signals, the data bus is used for uniformly transmitting each key driving signal.

In one embodiment, the signal data of all the key driving signals are spliced to form bus data, and the signal data of single bit of each key driving signal can be spliced to form multi-bit bus data, and the data bus at the moment can adopt a multi-bit data bus to transmit the collected target bus data. At this time, the data bus for transmitting the target bus data may be selected to have a bit width greater than or equal to the bit width of the bus data according to the bit width of the spliced bus data. The data bus can carry a plurality of data bits, and has the capability of high-speed transmission, so that the requirement of processing and transmitting a large amount of data can be met.

The data bus is used for transmission after the signal data of each key driving signal are spliced, so that the frequency of data transmission can be reduced, the transmission of the signal data of each key driving signal is facilitated, and in addition, when the reason of power-on failure of the subsequent chip design is analyzed, the signal data of each key driving signal can be conveniently comprehensively processed and analyzed, and the analysis of an analyst is facilitated.

The chip design can verify the function of the subsequent chip design after the power-on success, so that when the power-on failure occurs in the power-on process of the chip design, it is very necessary to analyze the reason of the power-on failure of the chip design. The reason of the power failure of the chip design is analyzed, so that the chip design can be started normally, and the function of the chip design is verified.

In the process of verifying the chip design by using the hardware acceleration platform, signal waveforms of all signals used when the chip design is powered on are captured at the same time, and then the signal waveforms are analyzed to locate reasons of failure of powering on the chip design, for example, on one hand, the captured signal waveforms are waveforms of all signals used when the chip design is powered on, so that the time for capturing the signal waveforms is long, and the resource time for occupying the hardware acceleration simulation platform is long; on the other hand, the number of captured signal waveforms is large and the variety of signals is complicated, which increases the difficulty of analysis in the subsequent analysis of the signal waveforms. Meanwhile, in the analysis of the power-on failure of the chip design, the working period of the clock signal indicates that the chip design is in a working state, so that the capturing of the waveforms of the signals needs to be captured in the working period of the clock signal, and the working period of the clock signal is effectively used for analyzing the reason of the power-on failure of the chip design, and the working period of the clock signal is determined by the clock frequency of the clock signal, so that whether the signal waveforms of the captured signals are in the working period of the clock signal or not is determined by the clock frequency of the clock signal, and meanwhile, whether the clock frequency of the clock signal is accurate or not is also determined, thereby ensuring that the working waveforms of the captured signals are effective, and being beneficial to the analysis of the reason of the power-on failure of the chip design; therefore, based on the manner in which the signal waveform is captured, there is also a problem in that it is impossible to determine whether the captured signal waveform is necessarily within the duty cycle of the clock signal; if the captured signal waveforms are not in the working period of the clock signal, it is indicated that the working waveforms of the signals are ineffective for the analysis of the power-on failure of the chip design, and the time of the clock signal generation or the corresponding trigger condition is further precisely positioned to capture the signal waveforms of the signals in the working period of the clock signal for analysis, so that the complexity of the power-on failure analysis of the chip design is further increased.

Therefore, in the embodiment of the invention, a mode of directly capturing the signal waveform on a hardware acceleration simulation platform and analyzing the reason of power failure through the captured signal waveform is not adopted; the method is characterized in that the method is carried out on a hardware acceleration simulation platform, when the chip design is powered on, signal data corresponding to part of signals in the used signals, namely key driving signals, are collected (bus data of the chip design are collected), and then the collected target bus data are transmitted in a data bus transmission mode, so that the target bus data are used as a data basis for subsequent power-on failure analysis of the chip design; therefore, all signal waveforms do not need to be captured and displayed on the hardware acceleration simulation platform, and long-time occupation of resources of the hardware acceleration simulation platform is avoided; meanwhile, the clock frequency of the clock signal is measured, so that when the reason of the power failure is analyzed later, the validity of the signal data of the key driving signal in the collected target bus data can be determined based on the clock frequency, and the reliability and the accuracy of the analysis of the reason of the power failure of the chip design are ensured; in the embodiment of the invention, the signal data of part of key driving signals are collected, so that the data volume in the subsequent power failure analysis of chip design can be reduced, and the aim of improving the efficiency of the power failure analysis while not affecting the power failure analysis can be fulfilled.

The key driving signals are part of signals in signals used when the chip design is powered on, and are main analysis objects related to the power-on time sequence of the chip design when the power-on of the chip design fails. Therefore, when the signal data for carrying out the power failure analysis is collected, the signal data of the key driving signal is selected to be collected, so that the reliability and the accuracy of the subsequent analysis of the power failure of the chip design can be ensured, and the data volume of the subsequent analysis can be reduced.

In one embodiment, the critical drive signals include a reset signal, a power signal, an indication of a power state, and a clock signal of a chip design.

The power ok up (changed to 1) signal indicates that the chip design power-up fails, so the power ok up (changed to 1) signal indicates that the chip design power-up process is performed, the initial state of the power ok is 0, and the power ok becomes 1 after the chip design power-up is successful. The chip design power-on means that when the power supply management circuit detects that the power supply voltage is stable and can safely supply power to the chip design, the signal pin 'powerOK' indicating the power supply state is pulled up by the indication signal of the power supply state, and the chip design can work normally; therefore, the acquisition of signal data of the indication signal of the power state is important for the power failure analysis of the chip design.

In the simulation process of chip design verification, the basic function of the reset signal is to force the circuit to a certain state, so that the analysis of the reset signal is also important when the power-on failure of the chip design occurs.

The power supply signal provides a power supply voltage required by power supply for the chip design, and affects the power supply operation of the chip design, so that the power supply signal is an important signal to be analyzed when analyzing the reason of power supply failure of the chip design.

The clock signal is a key driving signal for ensuring that the internal devices of the chip design can work normally after the chip design is completed in the design process, so that the clock signal is also an important signal to be analyzed when the reason of the power-on failure of the chip design is analyzed.

The embodiment of the invention can acquire the signal data of the key driving signals affecting the power failure of the chip design in a targeted manner, so that a reliable data basis can be provided when the power failure analysis is performed on the basis of the acquired data.

Step S102, transmitting the target bus data and the measurement data.

And sending the collected target bus data and measurement data (namely the measurement data of the clock signal) to serve as a data basis for subsequent analysis of the power failure of the chip design, so that the analysis and the use of the power failure of the chip design are facilitated.

It can be seen that, the signal processing method provided by the embodiment of the invention is applied to a hardware acceleration simulation platform, and after a starting signal for powering on a chip design is obtained, bus data of the chip design is collected to obtain target bus data; the target bus data comprises all bus data or part of bus data; because the bus data of the chip design is formed by signal data of key driving signals, the key driving signals are related to the power-on time sequence of the chip design, and the key driving signals are part of signals in the signals used by the chip design when the chip is powered on; therefore, the data volume of the collected target bus data is smaller than the data volume obtained by collecting all signals used when the chip is powered on; meanwhile, the power-on failure analysis of the chip design is aimed at the analysis of key driving signals related to the power-on time sequence of the chip design, and the validity of signal data of the key driving signals influences the working characteristics of the chip design so as to influence the power-on time sequence of the chip design, so that the measurement of the clock frequency of the clock signals can be aimed at determining the validity of the signal data of the key driving signals in the target bus data, thereby being convenient for meeting analysis requirements when the power-on failure analysis of the chip design is carried out subsequently; therefore, the signal processing method provided by the embodiment of the invention can reduce the collection of the data volume during the power-on failure analysis of the chip design, and can provide a basis for improving the analysis efficiency of the power-on failure reason while meeting the power-on failure analysis of the subsequent chip design.

In order to further reduce the data size of the collected target bus data and improve the efficiency of the subsequent power failure analysis on the basis of ensuring the reliability of the power failure analysis of the subsequent chip design, in one embodiment, the bus data of the key driving signals can be further optimized and then collected to obtain the target bus data. Referring to fig. 3, fig. 3 is another flow chart of the signal processing method according to the embodiment of the invention.

As shown in fig. 3, the process may include the steps of:

step S200, acquiring a starting signal, wherein the starting signal is used for controlling the power-on operation of chip design.

Step S201, detecting the bus data of the chip design based on the start signal.

And detecting the bus data, and filtering the data with little influence in the subsequent power-on failure analysis process in the bus data, so as to acquire the key bus data to obtain the target bus data.

When the bus data is formed by the signal data of one key driving signal, detecting the signal data of the one key driving signal, namely, single bit data; when the bus data is formed by splicing all signal data of the key driving signals, the spliced signal data, namely multi-bit data, is detected. The manner of detection does not change, but the number of data detected (i.e. the number of bits) in one instant is different.

Step S202, detecting whether the bus data meets a first trigger condition, if yes, executing step S203, and if not, executing step S201.

The first trigger condition can be used for screening out interested data related to power-on failure analysis of the chip design in the bus data, and when the bus data meets the first trigger condition, the bus data can be collected so as to reduce the data volume of the collected target bus data.

Step 203, collecting the bus data of the chip design to obtain target bus data.

When the bus data of the chip design meets the first trigger condition, the bus data is collected to obtain effective data, namely target bus data, so that the data volume of subsequent analysis, for example, the data volume generated in the actual power-on process occupies the storage space 10G, and after optimization processing, the obtained effective data volume of the target bus data occupies the storage space 36M.

And if the bus data does not meet the first trigger condition, continuing to detect the bus data of the chip design, namely executing step S201.

The method comprises the steps of controlling the acquisition process of bus data through a first trigger condition, screening out target bus data effective for power-on analysis from the bus data, wherein the transmitted target bus data are part of the bus data, and directly acquiring and transmitting the bus data when the first trigger condition is not used for screening the bus data, wherein the transmitted target bus data are all the bus data.

The bus data is screened by using the first triggering condition, so that the data quantity required to be acquired and processed subsequently can be further reduced on the basis of ensuring the reliability of the subsequent power-on failure analysis, and the efficiency of the power-on failure analysis of the chip design is improved.

In order to accurately detect the bus data to determine the target bus data, in one embodiment, the first trigger condition is that the bus data of the chip design changes in data state, and step S201 may include:

detecting the data state of the bus data designed by the chip based on the starting signal;

step S202 may include:

detecting whether the data state of the bus data is changed, if so, acquiring the bus data of the chip design to obtain target bus data, and if not, continuously detecting the data state of the bus data of the chip design based on the starting signal.

Since the bus data is formed by the signal data of the key driving signals, the signal data of each key driving signal is single-bit data, when the bus data is formed by the signal data of one key driving signal, the data state of single-bit binary data can be detected, and if the bus data is formed by splicing all the signal data of the key driving signals, the multi-bit binary data can be uniformly detected.

For ease of understanding, the signal data splice formation using bus data as all of the critical drive signals is described as an example. For example, the total number of the key driving signals is 4, and the bus data formed by splicing the signal data of the 4 key driving signals is 4-bit data. When the data state of the bus data of the chip design is detected, the bus data is detected to be 0010 at the previous time t-1, and the bus data is detected to be 0011 at the next time t, and it can be seen that the number of the fourth bit in the bus data is changed, so that the data state of the bus data of the chip design is changed. The bus data may be considered to satisfy the first trigger condition at this time.

In order to facilitate detecting whether the data state of the bus data changes, in one embodiment, the detecting the data state of the bus data of the chip design based on the start signal includes:

detecting the data value of the bus data designed by the chip based on the starting signal;

when detecting that the data state of the bus data changes, the first trigger condition is satisfied, and the bus data designed by the chip is collected to obtain target bus data, including:

And when the data value of the same bit in the bus data is detected, and when the data value is overturned at the adjacent moment, the first trigger condition is met, and the bus data designed by the chip is acquired to obtain target bus data.

The data value of one bit in the detected bus data is flipped at an adjacent time, which may be described in the foregoing embodiment, for bus data formed by signal data of all 4 key driving signals, where the detected bus data is 0010 at the previous time t-1, and the detected bus data is 0011 at the next time t, then the fourth bit of the bus data is flipped from 0 to 1, which indicates that the bus data is flipped, and then the first trigger condition is satisfied.

Of course, when the bus data is formed by signal data of one key driving signal, it is possible to detect whether or not the data value of the adjacent time is inverted for the bus data of a single bit. For example, when the bus data detected at the previous time t-1 is "0", and the bus data detected at the next time t is "1", the data value of the bus data on the single bit is flipped, and the first trigger condition is satisfied.

At this time, when the data state of the bus data indicated by the first trigger condition is changed, the data value corresponding to one bit in the bus data is flipped at an adjacent time.

In order to enable the target bus data to have continuity, so that the state of the key driving signal can be better and more accurately displayed when the collected target bus data is analyzed later, in one embodiment, the bus data can be partially collected in advance before the first trigger condition is not met, so that after the bus data meets the first trigger condition, the pre-collected partial bus data can be combined to obtain the finally collected target bus data, the target bus data can embody the data state of the partial bus data before the data state change, and when the working waveform of the key driving signal is restored based on the target bus data later, the restored signal waveform has continuity, the change trend of the key driving signal can be better displayed, and the analysis of subsequent power-on failure is facilitated.

Referring to fig. 4, fig. 4 is a schematic flow chart of a signal processing method according to an embodiment of the invention.

As shown in fig. 4, the process may include the steps of:

step S300, a starting signal is obtained, wherein the starting signal is used for controlling the power-on operation of chip design.

Step S301, detecting the bus data of the chip design based on the start signal.

Step S302, data acquisition is carried out on bus data of the chip design before the first trigger condition is not met according to the pre-trigger acquired data quantity, and first acquired data are obtained.

Wherein, the pre-trigger data collection amount can be 1024 bytes of data amount; the pre-trigger acquisition data volume can be determined by the data of the actual data covered by the signal waveform, and the continuity of the target bus data can be ensured. The data of the pre-trigger acquisition data amount (for example, 1024 bytes of data) is acquired in advance before the first trigger condition is satisfied, so that the state change of the key driving signal is observed for the target bus data later. In one embodiment, the first collected data of the pre-trigger collected data amount can be collected through a shift register, and the bus data designed by the chip is continuously updated through the cyclic shift of the shift register before the bus data does not meet the first trigger condition, so that the continuity of the collected first collected data is ensured, and further the continuity of the target bus data is ensured.

Step S303, detecting whether the bus data meets a first trigger condition, if yes, executing step S304, and if not, executing step S301.

Step S304, collecting the bus data of the chip design after the first trigger condition is met, and obtaining second collected data.

When the bus data is detected to meet the first trigger condition, the analysis of the reason of the power-on failure of the chip design is facilitated for facilitating the subsequent visual observation of the state transition of the key driving signal, and the acquisition of partial data quantity can be performed aiming at the bus data before the first trigger condition is not met, so that the finally obtained target bus data can have continuity; that is, the acquired target bus data includes, as the data of interest, bus data of a pre-trigger acquisition data amount (for example, pre-trigger acquisition depth) before a reference time at which the bus data is detected to satisfy the first trigger condition, that is, the first acquisition data, while bus data satisfying the first trigger condition after the reference time is acquired as the second acquisition data.

Step S305, obtaining target bus data based on the first collected data and the second collected data.

In one embodiment, to facilitate the transmission and processing of subsequent data, the final collected target bus data may be written to a status register.

For facilitating the subsequent processing of the target bus data, the target bus data may include data information representing the signal state, i.e. binary digits; the target bus data may further include a timestamp corresponding to the time of obtaining the target bus data and an address corresponding to the data information, so as to facilitate subsequent processing and analysis of the target bus data.

The timestamp may refer to signal data of each target bus, i.e. signal data of the key driving signal, and corresponding time information, so as to facilitate analysis of a state change time point of the key driving signal.

The address corresponding to the data information may be used to indicate a register address of the critical driving signal corresponding to the data information (the register address corresponds to an ID of one chip design), so that the meaning represented by the critical driving signal may be determined by the address, for example, the ID information of the chip design corresponding to the critical driving signal may be determined.

And when the bus data is detected to not meet the first trigger condition, continuing to detect the bus data, and executing step S301.

In order to enable the obtained measurement data of the clock signal to have higher reliability and accuracy, in an embodiment, in step S101, the measuring the clock frequency of the chip design to obtain the measurement data of the clock signal may include:

acquiring a clock signal to be tested of the chip design;

setting actual gate time based on a clock edge of the clock signal to be tested, wherein the actual gate time is an integer multiple of a clock period of the clock signal to be tested;

counting the clock period of the clock signal to be measured in the actual gate time, and counting the clock period of the standard clock signal under the actual gate time;

and when the actual gate time reaches the second trigger condition, recording the count value of the clock period of the clock signal to be tested and the count value of the clock period of the standard clock signal to obtain the measurement data of the clock signal.

The clock signal to be tested can be a main clock signal such as a main system clock signal, a PLL clock signal, an external clock signal, a subsystem clock signal and the like in the power-on process of chip design.

The measured clock frequency is a measurement of the clock frequency for the primary clock signal.

In order to reduce measurement errors when measuring clock frequency, the embodiment of the invention selects to use an equal-precision frequency measurement method to measure the clock frequency. Meanwhile, in order to further improve the accuracy of clock frequency measurement and reduce measurement errors, the embodiment of the invention improves the equivalent precision frequency measurement.

In the embodiment of the invention, when the clock frequency is measured based on the equal-precision frequency measurement method, the actual gate control time, namely the actual gate time, is not a fixed value in the equal-precision frequency measurement method, and the actual gate time is related to the clock signal to be measured and is an integral multiple of the clock period of the clock signal to be measured; therefore, the embodiment of the invention sets the actual gate time to be the integral multiple of the clock period of the clock signal to be measured, and simultaneously sets the actual gate time of the measurement frequency according to the clock edge of the clock signal to be measured, thereby ensuring that the frequency can be measured as long as the clock period of the clock signal exists and reducing the measurement error.

After the setting of the actual gate time is completed, counting the clock periods of the standard clock signal and the clock signal to be detected in the actual gate time, and calculating the clock frequency of the clock signal to be detected through a formula. The actual gate time is an integral multiple of the clock period of the clock signal to be tested, and the embodiment of the invention selects to set the actual gate time according to the clock edge of the clock signal to be tested, so that the error of +/-1 clock period generated by the clock signal to be tested can be eliminated.

Wherein the standard clock signal is set at the time of measurement, is a known quantity, i.e. the clock frequency of the standard clock signal is known; the actual gate time is actually a segment of a digital signal, which can be represented by 010, for example, wherein the duration of the number 1 represents the effective time for counting the clock cycles of the clock signal to be measured and the clock cycles of the standard clock signal.

In other embodiments, measurement errors may be further reduced by increasing the actual gate time.

In order to facilitate understanding of the implementation of the measurement of the clock frequency, the embodiment of the present invention is described by taking the actual gate time as T and the clock frequency of the standard clock signal as fc as an example.

Firstly, generating an actual gate time T through a clock edge of a clock signal to be detected;

and then, respectively counting the clock period of the clock signal to be tested and the clock period of the standard clock signal under the actual gate time.

Setting the count value of the clock period of the clock signal to be measured as X in the actual gate time, taking the clock period of the clock signal to be measured as Tft as an example, the calculation of the clock frequency of the clock signal to be measured can be expressed as:

ft=1/Tft, whereby equation 1 can be obtained:

X tft=x/ft=t, where the measurement is error free.

In the actual gate time, the clock cycle count value of the standard clock signal is Y (the measurement error at this time is 1), and taking the clock cycle of the standard clock signal as Tfc as an example, the clock frequency of the standard clock signal can be expressed as:

fc=1/Tfc, whereby equation 2 can be obtained:

y=tfc=y/fc=t, and at this time, since there is an error in the count value of the clock cycle of the standard clock signal, the maximum error is 1 standard clock cycle.

Combining equation 1 and equation 2 above yields equation 3 containing only the count value and clock frequency of the respective clock cycles:

X/fc＝Y/fc＝T；

transforming equation 3 to obtain a calculation formula 1 of the clock frequency ft of the clock signal to be measured:

ft＝X*fc/Y。

the clock frequency ft of the clock signal to be measured can be obtained by bringing a known quantity, that is, the clock frequency fc of the standard clock signal, the count value X of the clock period of the measured clock signal, and the count value Y of the clock period of the standard clock signal into the calculation formula 1.

Therefore, the embodiment of the invention adopts an improved equal-precision frequency measurement method to measure and obtain the count value of the clock period of the clock signal to be measured and the count value of the clock period of the standard clock signal, acquires the count value recorded at the moment when the second trigger condition is met, and sends the measured data of the clock signal as the measured data of the clock signal so as to facilitate the subsequent calculation of the clock frequency ft of the clock signal to be measured based on the measured count value and the clock frequency fc of the standard clock signal and facilitate the observation of the clock signal based on the calculated clock frequency ft of the clock signal to be measured.

To ensure that the clock frequency of the clock signal to be measured can be measured, in one embodiment, the second trigger condition may be a clock falling edge of the actual gate time.

Since the actual gate time is an integer multiple of the clock period of the clock signal to be measured, the maximum error generated is + -1 clock period of the standard clock signal. Setting the falling edge of the actual gate time as a second trigger condition, and when the falling edge of the actual gate time is detected, indicating that the counting of the frequency counter is completed, namely, completing the counting of the clock cycles of the clock signal to be detected and the counting of the clock cycles of the standard clock signal; the clock frequency is ensured to be measured as long as the clock period of the clock signal to be measured exists.

The embodiment of the invention also provides a signal processing method which is applied to the server to process the data (the target bus data and the measurement data of the clock signal) acquired by the hardware acceleration simulator in the previous embodiment, thereby facilitating the analysis of the reasons of the power-on failure of the chip design.

Referring to fig. 5, fig. 5 is a schematic flow chart of a signal processing method according to an embodiment of the invention.

As shown in fig. 5, the process may include the steps of:

Step S400, obtaining target bus data and measurement data of chip design.

The target bus data and the measurement data of the chip design are generated by the signal processing method described in the foregoing embodiment. The target bus data can be obtained by collecting bus data formed by signal data of key driving signals related to a chip design power-on time sequence; the measurement data may be a count value of a clock cycle of the clock signal to be measured and a count value of a clock cycle of the standard clock signal, which are measured based on the improved equal-precision frequency measurement method.

Step S401, generating a time sequence waveform diagram based on the acquired target bus data; and obtaining a clock frequency based on the acquired measurement data.

The timing waveform diagram includes an operational waveform of a critical drive signal. When the data acquisition basis corresponding to the target bus data, namely the bus data, is formed by the signal data of one key driving signal, the analysis of the power-on failure reason of the chip design is the analysis of the power-on time sequence of the chip design, namely the analysis of all key driving signals related to the power-on time sequence of the chip design, so that the restoration of the working waveforms of the corresponding key driving signals can be respectively carried out based on the bus data corresponding to the acquired target bus data formed by each key driving signal, the number of the key driving signals is taken as 4 as an example for explanation, thereby obtaining the working waveforms of 4 independent key driving signals, and further uniformly combining the working waveforms of the 4 independent key driving signals, thereby forming a time sequence waveform diagram, and being convenient for an analyst to carry out time sequence analysis on the working waveforms of all the key driving signals.

When the bus data corresponding to the target bus data is formed by the signal data of all the key driving signals, the working waveforms of all the key driving signals can be directly restored at one time based on the target bus data at the moment, so that a time sequence waveform chart which is convenient for analysis and use by an analysis staff is formed.

Since the target bus data is obtained based on the bus data formed by the critical driving signals, information capable of reflecting the state and waveform trend of the critical driving signals may be included in the target bus data, so that a timing waveform chart including the operation waveform of the critical driving signals may be generated based on the analysis processing of the target bus data.

The timing waveform diagram is generated by combining signal data of key driving signals such as clock signals, reset signals, power supply signals and indication signals of power states, so that waveforms of main signals related to power-on failure analysis of chip design, namely power-on time sequence of chip design, can be contained in the timing waveform diagram, and reliability of analysis results obtained based on the analysis of the timing waveform diagram is ensured.

In the time sequence waveform diagram, the state of the data information in the corresponding working waveform in the acquired time can be displayed for each key driving signal aimed at in the embodiment of the invention, so that the method can be used for assisting an analyst in determining the reason of the power failure of the chip design when the reason of the power failure of the chip design is analyzed later.

In the hardware acceleration simulation platform, the count value of the clock period of the clock signal to be tested and the count value of the clock period of the standard clock signal which meet the second trigger condition are obtained by utilizing the improved equal-precision frequency measurement method; therefore, when the server receives the measurement data of the clock signal, the clock frequency of the clock signal can be obtained according to the count value (the count value of the clock period of the clock signal to be measured and the count value of the clock period of the standard clock signal) by using the calculation formula 1 of the clock frequency ft of the clock signal to be measured.

When an analyst analyzes the cause of the power failure, based on the calculated clock frequency, it can be determined whether the clock frequency exists at the corresponding moment, and whether the clock frequency is correct for the clock signal with the clock frequency, so as to determine whether each key driving signal is effective in the corresponding clock frequency, that is, whether the target bus data is collected in the effective working state of the chip design.

It can be seen that, the signal processing method provided by the embodiment of the invention is applied to a server, and the target bus data and the measurement data from the hardware acceleration simulation platform are obtained by the server, wherein the target bus data comprises all bus data or part of bus data; because the bus data of the chip design is formed by signal data of key driving signals, the key driving signals are related to the power-on time sequence of the chip design, and the key driving signals are part of signals in the signals used by the chip design when the chip is powered on; therefore, the data size of the target bus data processed by the server is smaller than the data size obtained by all the acquisition of the corresponding signals when the chip is powered on; meanwhile, the power-on failure analysis of the chip design is aimed at the analysis of key driving signals related to the power-on time sequence of the chip design, and the validity of signal data of the key driving signals influences the working characteristics of the chip design so as to influence the power-on time sequence of the chip design, so that the measurement of the clock frequency of the clock signals can be used for determining the validity of the signal data of the key driving signals in target bus data, and the analysis requirement can be met conveniently when the power-on failure analysis of the chip design is carried out subsequently; therefore, the signal processing method provided by the embodiment of the invention avoids the analysis of the reason of the power-on failure processed on the hardware acceleration platform, but transmits the data obtained by the hardware acceleration simulation platform to the server, and the server is utilized to analyze and process the uploaded data, so that the occupation time of resources of the hardware acceleration simulation platform can be reduced; meanwhile, the server can conduct subsequent power-on failure analysis of the chip design based on the data volume of the lower chip design during power-on failure analysis, and can provide a basis for improving the analysis efficiency of power-on failure reasons.

To facilitate the observation and analysis of the timing waveform diagram, please continue to refer to fig. 5, as shown in fig. 5, the method may further include:

step S402, the generated timing waveform diagram is shown.

To facilitate the observation and analysis of the timing waveform diagram, the timing waveform diagram generated based on the target bus data may be presented, that is, the server may provide an interactive interface to present the timing waveform diagram to the analyst in the interactive interface based on the analyst's operation. And the observation and analysis of the time sequence waveform diagram are convenient.

For ease of understanding, please refer to fig. 6a and fig. 6b, fig. 6a is a schematic diagram of an implementation result of a data processing method according to an embodiment of the present invention, and fig. 6b is a schematic diagram of another implementation result of a data processing method according to an embodiment of the present invention.

The abscissa in fig. 6a and 6b each represents data information obtained by processing and analyzing based on the target bus data (bus data corresponding to the target bus data at this time, formed by concatenating signal data of all the key driving signals); the ordinate represents signals related to the power-on timing of the chip design, such as key driving signals such as a power supply signal, a reset signal, an indication signal of a power state, and a clock signal related to the power-on timing of the chip design.

Fig. 6a is a schematic diagram of an analysis result corresponding to the collected target bus data after the bus data is detected and optimized, and fig. 6b is a schematic diagram of an analysis result corresponding to the target bus data directly collected without the bus data being detected and optimized, it can be seen that after the bus data is screened and optimized, the displayed time sequence waveform diagram is clearer, and the subsequent analysis personnel can conveniently check and observe.

In another embodiment, to facilitate analysis of the trend of the critical driving signal, the method may further include:

processing the acquired target bus data to obtain state information of key driving signals, wherein the state information is used for representing state changes of all the key driving signals; and storing the state information to obtain a state log so as to inquire the state change of each key driving signal based on the state log.

The target bus data obtained by the hardware acceleration simulator is obtained based on bus data formed by signal data of the key driving signals, so that the target bus data can comprise data information, address and other information representing the key driving signals, and after the server obtains the target bus data, the target bus data can be processed based on the target bus data to obtain state information of the key driving signals, and further, according to state changes of the key driving signals represented by the state information, reasons for causing power-on failure of the chip design are analyzed to locate the key driving signals causing the power-on failure of the chip design.

The state information may be stored in a log manner, for example, the server may store the state information into a state log after generating the state information of the key driving signal based on the target bus data; when a subsequent analyst needs to analyze the power-on failure of the chip design or check the working state of the key driving signals, the state log can be directly checked, so that the change condition of the key driving signals is known, the key driving signals with problems are more accurately positioned, and the determined key driving signals with problems are subjected to relevant analysis and processing.

The time information in the target bus data, that is, the time stamp described in the foregoing embodiment, is not shown in the time-series waveform diagram, but is recorded in the state log storing the state information, and is shown to the analyst in the form of data; when an analyst observes the time sequence waveform diagram to find that the signal waveform of one key driving signal possibly causes the power-on failure of the chip design, the time information correspondingly recorded in the state log can be combined to further determine whether the key driving signal is the cause of the power-on failure of the chip, analysis can be assisted by the analyst, and reliability of analysis results is ensured.

In one embodiment, the processing the acquired target bus data to obtain the state information of the critical driving signal may include:

and generating state information of the key driving signals based on the data information in the acquired target bus data, the acquisition time corresponding to the data information and the address corresponding to the data information.

The data information may be binary digits in the collected bus data, and the signal name corresponding to the collected bus data represents the signal name of the key driving signal, and the acquisition time corresponding to the data information may be the collection time of the target bus data, for example, in the working process of the key driving signal, when the bus data meets the first trigger condition, the working time corresponding to the collected target bus data is the working time corresponding to the collected target bus data. The address may be a register address of a specific critical driving signal corresponding to the data information.

For example, the target bus data is formed by signal data (indication signal of power state) of one key driving signal, in the acquired target bus data, the data information may be 000001, the data information represents the signal name of the key driving signal, the signal name of the key driving signal which the data information may represent is set to be the indication signal of the power state, and the address represents a register address addr corresponding to the indication signal of the key driving signal being the power state; the acquisition time corresponding to the data information may be an acquisition time after the first trigger condition is satisfied. Because the data information indicates the indication signal of the power state, the state information of the indication signal of the corresponding power state at this time is that when the data of the last bit is changed from 0 to 1 at the previous time, the time t corresponding to the last bit indicates that the chip design is successfully powered on; the state information of the obtained key driving signal after processing based on the target bus data at this time may be expressed as that the power-on start is successful at the time t when the indication signal of the power state becomes "1" in the chip design where the register address is addr and the ID information is a, for example.

In order to smoothly generate the clock frequency of the clock signal to be measured, in one embodiment, the obtaining the clock frequency based on the obtained measurement data includes:

obtaining clock frequency of the clock signal to be measured based on the count value of the clock period of the clock signal to be measured in the obtained measurement data and the count value of the clock period of the standard clock signal, and obtaining the clock frequency;

the method further comprises the steps of:

and storing the clock frequency to obtain a clock frequency log so as to query the clock frequency based on the clock frequency log and determine the validity of the signal data of each key driving signal.

Based on the foregoing embodiments, it may be known that the measurement data of the clock signal is measured according to the improved equal-precision frequency measurement method, and therefore, after obtaining the measurement data of the clock signal, the server may calculate, according to calculation formula 1 in the improved equal-precision frequency measurement method, based on the obtained count value X of the clock period of the clock signal to be measured, the count value Y of the clock period of the standard clock signal, and the clock frequency fc of the standard clock signal in the measurement data of the clock signal, to obtain the clock frequency ft=x×fc/Y of the clock to be measured.

The clock frequency may be stored in a log manner for later analysts to view based on the clock analysis log. The clock frequency, i.e. the clock frequency generated based on the measurement data of the clock signal, may be recorded in a clock analysis log.

Referring to fig. 7, fig. 7 is a schematic diagram illustrating a result of another implementation of the signal processing method according to the embodiment of the invention.

As shown in fig. 7, in the clock analysis log, the calculated clock frequency may be recorded, so that whether the clock frequency exists or not and whether the existing clock frequency is accurate or not can be checked based on the clock analysis log, so as to ensure whether the signal data of the key driving signal is valid or not, that is, whether the analysis of the power-on failure cause of the chip design is beneficial or not.

The embodiment of the invention also provides a signal processing system. Referring to fig. 8, fig. 8 is a schematic diagram of a frame structure of a signal processing system according to an embodiment of the invention.

As shown in fig. 8, the system may include:

a hardware acceleration simulation platform 1, the hardware acceleration simulation platform 1 being configured to perform the aforementioned signal processing method applied to the hardware acceleration simulation platform;

and a server 2 for acquiring and storing the target bus data and the measurement data from the hardware acceleration simulation platform 1, wherein the server 2 is configured to execute the signal processing method applied to the server.

The server 2 can analyze and process the target bus data and the measurement data of the hardware acceleration simulation platform 1 to obtain a processing result, so that an analyst can analyze state changes of a key driving signal and a clock signal according to the processing result and can acquire important information related to time sequence analysis. Important information such as the high level, low level, rising edge and falling edge moments of the critical drive signals and clock signals, and the duration of the clock signals and critical drive signals, for example, may be included.

It can be seen that the signal processing system provided by the embodiment of the invention comprises the hardware acceleration simulation platform 1 and the server 2, wherein the target bus data and the measurement data from the hardware acceleration simulation platform 1 are obtained by the server 2, and the target bus data comprise all bus data or part of bus data; because the bus data of the chip design is formed by signal data of key driving signals, the key driving signals are related to the power-on time sequence of the chip design, and the key driving signals are part of signals in the signals used by the chip design when the chip is powered on; therefore, the data size of the target bus data processed by the server 2 is smaller than the data size obtained by all the acquisition of the corresponding signals when the chip is powered on; meanwhile, the power-on failure analysis of the chip design aims at the analysis of key driving signals related to the power-on time sequence of the chip design, and the validity of signal data of the key driving signals influences the working characteristics of the chip design, so that the power-on time sequence of the chip design is influenced; therefore, the server 2 can obtain the clock frequency based on the obtained measurement data of the clock signal, so as to determine the validity of the signal data of the key driving signal in the target bus data based on the clock frequency, thereby meeting the analysis requirement; therefore, the signal processing system provided by the embodiment of the invention avoids the analysis of the reason of the power-on failure processed on the hardware acceleration platform 1, but transmits the data obtained by the hardware acceleration simulation platform 1 to the server 2, and utilizes the server 2 to analyze and process the uploaded data, so that the occupation time of resources of the hardware acceleration simulation platform 1 can be reduced; meanwhile, the server 2 can perform subsequent power-on failure analysis of chip design based on the data volume of the lower chip design during power-on failure analysis, and can provide a basis for improving the analysis efficiency of power-on failure reasons.

In order to be able to establish a data transfer relationship between the hardware acceleration simulation platform 1 and the server 2, in one embodiment, a transfer tool may also be used to complete the transfer of the target bus data and the measurement data of the clock signal.

With continued reference to fig. 8, as shown in fig. 8, the system may further include:

and the data transmission module 3 is used for transmitting the target bus data and the measurement data acquired by the hardware acceleration simulation platform 1 to the server 2.

The data transmission module 3 may receive the target bus data and the measurement data of the hardware acceleration simulation platform 1, for example, the data transmission module 3 may transmit the target bus data and the measurement data received in the status register. Then uploading the target bus data and the measurement data stored in the status register to the server 2; to enable data interaction between the hardware acceleration simulation platform 1 and the server 2.

For data interaction based on meeting the requirements of the use of the hardware acceleration simulation platform 1 and the server 2, in one embodiment, the data transmission module 3 may comprise a direct storage interface.

In the embodiment of the invention, a direct storage interface (Direct Programming Interface for C, DPI-C) is adopted to realize data interaction between the hardware acceleration simulation platform 1 and the server 2.

Because in the hardware acceleration simulation platform 1, the design code of the running chip design is written based on the language of the hardware simulation accelerator based on the SystemVerilog; the script file for performing data processing in the server 2 is written based on the C language, so that in order to enable the data collected by the hardware acceleration platform 1 (the target bus data and the measurement data of the clock signal) to be directly applied to the server 2 for performing subsequent analysis processing, the embodiment of the invention adopts a direct storage interface; a direct storage interface, such as SCEMI-2.0, is employed between the hardware acceleration simulation platform 1 and the server 2 to enable data interaction of the hardware acceleration simulation platform 1 and the server 2.

In the embodiment of the invention, a use mode based on a SystemVerilog direct programming interface C (DPI-C) function is adopted, the C function on the side of a server 2 (HVL, hardware Verification Language) is called on the side of a hardware accelerator simulation platform 1 (HDL, hardware Description Language), and data is uploaded to the server 2. By using DPI-C direct memory interface, the data interaction of cross-language platform can be realized, and the accurate record of the target bus data and the measurement data of key driving signals is ensured. When the hardware acceleration simulation platform 1 collects target bus data and measurement data, the data are transmitted to corresponding C functions for processing. The C-function will upload the data to the server 2 while storing the target bus data and the measurement data in the files of the server 2. For example in a text file, a log file of the server 2, facilitating the analysis and processing of the subsequent data. The data transmission module 3 realizes the uploading and storage functions of data, and the direct storage interface is used as the data transmission module 3, so that the target bus data and the measurement data acquired by the hardware acceleration simulation platform 1 can be accurately recorded and stored in the file of the server 2, a foundation is provided for subsequent data anomaly analysis and processing, and a user can conveniently access and analyze the data, thereby accelerating the speed of problem positioning and solving.

Referring to fig. 9, fig. 9 is a schematic diagram of another structure of a signal processing system according to an embodiment of the invention.

As shown in fig. 9, the hardware acceleration simulation platform 1 of the system may include:

the starting signal acquisition module 11 is used for acquiring a starting signal, wherein the starting signal is used for controlling the power-on operation of chip design;

the bus data acquisition module 12 is configured to acquire, based on the start signal, bus data of the chip design, to obtain target bus data, where the target bus data includes all or part of bus data; the bus data of the chip design is formed by signal data of key driving signals, the key driving signals are related to power-on time sequences of the chip design, and the key driving signals are part of signals in signals used when the chip design is powered on;

the clock frequency measurement module 13 is configured to measure a clock frequency of a clock signal in the critical driving signal to obtain measurement data of the clock signal, where the clock frequency of the clock signal is used to determine validity of signal data of the critical driving signal in the target bus data;

A data transmitting module 14 for transmitting the target bus data and the measurement data.

The bus data collection module 12 may collect key driving signals, for example, a power state indication signal pwr, a reset signal reset, and key driving signals (including a power supply signal and a clock signal).

The clock frequency measurement module 13 may count clock cycles of the clock signal to obtain measurement data of the clock signal.

The target bus data collected by the bus data collection module 12 and the measurement data of the clock signal obtained by the clock frequency measurement module 13 need to be uploaded according to the detection condition of the signal, so the bus data collection module 12 and the clock frequency measurement module 13 are located in the detector monitor.

For example, the target bus data collected by the bus data collection module 12 needs to be uploaded when the bus data is detected to meet the first trigger condition (for example, the data of the bus data is flipped); the measured data of the clock signal obtained by the clock frequency measuring module 13 needs to be uploaded when the actual gate time satisfies the second trigger condition (e.g., the falling edge of the actual gate time).

When the bus data acquisition module 12 and the clock frequency measurement module 13 need to upload data to the server 2, the data transmission module 3 (represented by SCEMI-2.0 in fig. 9) may be used to upload data to the server 2.

The design under test (DUT, design Under Test) shown in fig. 9 is the chip design being powered up, i.e., the chip design being verified.

With continued reference to fig. 9, as shown in fig. 9, the server 2 may include:

a chip design power-on data acquisition module 21, configured to acquire target bus data and measurement data of a chip design, where the target bus data and the measurement data of the chip design are generated by the hardware acceleration simulation platform 1;

a timing waveform diagram generating module 22, configured to generate a timing waveform diagram based on the acquired target bus data; the time sequence waveform diagram comprises working waveforms of key driving signals;

a clock frequency generating module 23, configured to obtain a clock frequency based on the obtained measurement data, where the clock frequency of the clock signal is used to determine validity of signal data of the key driving signal in the target bus data;

an interactive interface 24, configured to display the time-series waveform diagram generated by the time-series waveform diagram generating module 22;

a state log generating module 25, configured to process the obtained target bus data to obtain state information of the key driving signals, where the state information is used to represent a state change of each key driving signal; and storing the state information to obtain a state log so as to inquire the state change of each key driving signal based on the state log.

The chip design power-on data acquisition module 21 is utilized to receive the target bus data and the measurement data sent by the data transmission module 3, so that subsequent processing can be facilitated.

The timing waveform diagram generating module 22 generates a timing waveform diagram according to the target bus data received by the chip design power-on data obtaining module 21, and visually displays a change process of the key driving signal, for example, the timing waveform diagram may include important information such as power-on time of the chip design, state of the key driving signal, and the like, so as to analyze reasons of power-on failure based on the timing waveform diagram.

The clock frequency generating module 23 obtains the clock frequency according to the obtained measurement data, so as to conveniently confirm whether the clock frequency exists and whether the existing clock frequency is accurate, and facilitate the use of analysts.

The state log generating module 25 may generate state information of the key driving signal according to the target bus data to represent a conversion state of the key driving signal, and store the state information as a state log, so as to facilitate use by an analyst.

In another embodiment, the clock frequency generating module 23 is configured to obtain the clock frequency based on the obtained measurement data, which may include:

And generating the clock frequency of the clock signal to be measured based on the count value of the clock period of the clock signal to be measured and the count value of the clock period of the standard clock signal in the acquired measurement data of the clock signal.

The generated clock frequency may be recorded in a clock analysis log so that subsequent analysts may determine from the clock analysis log whether a clock frequency is present and whether the clock frequency present is accurate.

An embodiment of the present invention provides an electronic device, including a memory and a processor, where the memory stores a program, and the processor invokes the program stored in the memory to perform a signal processing method applied to a hardware acceleration simulation platform according to any one of the previous embodiments, or to perform a signal processing method applied to a server according to any one of the previous embodiments.

An embodiment of the present invention provides a storage medium storing a program that when executed implements a signal processing method applied to a hardware acceleration simulation platform as set forth in any one of the foregoing embodiments, or implements a signal processing method applied to a server as set forth in any one of the foregoing embodiments.

The foregoing describes several embodiments of the present invention, and the various alternatives presented by the various embodiments may be combined, cross-referenced, with each other without conflict, extending beyond what is possible embodiments, all of which are considered to be embodiments of the present invention disclosed and disclosed.

Although the embodiments of the present invention are disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (20)

1. The signal processing method is characterized by being applied to a hardware acceleration simulation platform and comprising the following steps of:

acquiring a starting signal, wherein the starting signal is used for controlling the power-on operation of chip design;

based on the starting signal, collecting the bus data designed by the chip to obtain target bus data, wherein the target bus data comprises all bus data or part of bus data; the bus data of the chip design is formed by signal data of key driving signals, the key driving signals are related to power-on time sequences of the chip design, and the key driving signals are part of signals in signals used when the chip design is powered on;

Measuring the clock frequency of the clock signal in the key driving signal to obtain measurement data of the clock signal, wherein the clock frequency of the clock signal is used for determining the validity of signal data of the key driving signal in target bus data;

and transmitting the target bus data and the measurement data.

2. The signal processing method of claim 1, wherein the bus data of the chip design is formed of signal data of a critical driving signal, comprising:

the bus data of the chip design is formed by signal data of one key driving signal or by signal data of all key driving signals which are spliced.

3. The signal processing method according to claim 2, wherein the acquiring the bus data of the chip design based on the start signal to obtain the target bus data includes:

based on the starting signal, detecting bus data designed by the chip;

and when the bus data is detected to meet the first trigger condition, acquiring the bus data designed by the chip to obtain target bus data.

4. A signal processing method according to claim 3, further comprising:

According to the pre-trigger data acquisition amount, carrying out data acquisition on bus data designed by a chip before the first trigger condition is not met to obtain first acquisition data;

when the bus data is detected to meet the first trigger condition, the bus data of the chip design is acquired to obtain target bus data, which comprises the following steps:

when the bus data is detected to meet the first trigger condition, acquiring the bus data designed by the chip after meeting the first trigger condition to obtain second acquired data;

and obtaining target bus data based on the first acquired data and the second acquired data.

5. The signal processing method of claim 3, wherein the first trigger condition is a data state change of bus data of the chip design, and the detecting the bus data of the chip design based on the start signal comprises:

detecting the data state of the bus data designed by the chip based on the starting signal;

when the bus data is detected to meet the first trigger condition, the bus data of the chip design is acquired to obtain target bus data, which comprises the following steps:

When the data state of the bus data is detected to be changed, the first trigger condition is met, and the bus data designed by the chip is acquired to obtain target bus data.

6. The signal processing method of claim 5, wherein detecting the data state of the bus data of the chip design based on the enable signal comprises:

detecting the data value of the bus data designed by the chip based on the starting signal;

when detecting that the data state of the bus data changes, the first trigger condition is satisfied, and the bus data designed by the chip is collected to obtain target bus data, including:

and when the data value on one bit in the bus data is detected, and when the adjacent moment turns over, the first trigger condition is met, and the bus data designed by the chip is acquired to obtain target bus data.

7. The signal processing method according to claim 2, wherein the measuring the clock frequency of the clock signal in the critical driving signal to obtain the measurement data of the clock signal includes:

Acquiring a clock signal to be tested of the chip design;

setting actual gate time based on a clock edge of the clock signal to be tested, wherein the actual gate time is an integer multiple of a clock period of the clock signal to be tested;

counting the clock cycles of the clock signal to be measured and counting the clock cycles of the standard clock signal in the actual gate time;

and when the actual gate time reaches the second trigger condition, recording the count value of the clock period of the clock signal to be tested and the count value of the clock period of the standard clock signal to obtain the measurement data of the clock signal.

8. The signal processing method of claim 7, wherein the second trigger condition is a clock falling edge of the actual gate time.

9. The signal processing method according to any one of claims 1 to 8, wherein the key driving signals include a reset signal, a power supply signal, an indication signal of a power supply state, and a clock signal of a chip design.

10. A signal processing method, applied to a server, comprising:

acquiring target bus data and measurement data of a chip design, the target bus data and the measurement data of the chip design being generated by the signal processing method according to any one of claims 1 to 9;

Generating a time sequence waveform diagram based on the acquired target bus data; and obtaining a clock frequency based on the acquired measurement data; the timing waveform diagram includes an operational waveform of a critical drive signal, and a clock frequency of the clock signal is used to determine validity of signal data of the critical drive signal in the target bus data.

11. The signal processing method of claim 10, further comprising:

processing the acquired target bus data to obtain state information of key driving signals, wherein the state information is used for representing state changes of all the key driving signals; and storing the state information to obtain a state log so as to inquire the state change of each key driving signal based on the state log.

12. The signal processing method as claimed in claim 11, wherein said processing the acquired target bus data to obtain state information of the critical driving signal comprises:

and generating state information of the key driving signals based on the data information in the acquired target bus data, the acquisition time corresponding to the data information and the address corresponding to the data information.

13. The signal processing method of claim 12, wherein the deriving the clock frequency based on the acquired measurement data comprises:

generating the clock frequency of the clock signal to be measured based on the count value of the clock period of the clock signal to be measured in the acquired measurement data and the count value of the clock period of the standard clock signal to obtain the clock frequency;

the method further comprises the steps of:

and storing the clock frequency to obtain a clock frequency log so as to query the clock frequency based on the clock frequency log and determine the validity of the signal data of each key driving signal.

14. A signal processing system, comprising:

a hardware-accelerated simulation platform configured to perform the signal processing method of any of claims 1-9;

a server to obtain and store target bus data and measurement data from the hardware acceleration simulation platform, the server being configured to perform the signal processing method of any of claims 10-13.

15. The signal processing system of claim 14, further comprising:

and the data transmission module is used for transmitting the target bus data and the measurement data acquired by the hardware acceleration simulation platform to the server.

16. The signal processing system of claim 15, wherein the data transmission module comprises a direct memory interface.

17. The signal processing system of claim 16, wherein the hardware-accelerated simulation platform comprises:

the starting signal acquisition module is used for acquiring a starting signal, and the starting signal is used for controlling the power-on operation of chip design;

the bus data acquisition module is used for acquiring the bus data designed by the chip based on the starting signal to obtain target bus data, wherein the target bus data comprises all or part of bus data; the bus data of the chip design is formed by signal data of key driving signals, the key driving signals are related to power-on time sequences of the chip design, and the key driving signals are part of signals in signals used when the chip design is powered on;

the clock frequency measuring module is used for measuring the clock frequency of the clock signal in the key driving signal to obtain measurement data of the clock signal, and the clock frequency of the clock signal is used for determining the validity of the signal data of the key driving signal in the target bus data;

And the data transmission module is used for transmitting the target bus data and the measurement data.

18. The signal processing system of claim 17, wherein the server comprises:

the chip design power-on data acquisition module is used for acquiring target bus data and measurement data of the chip design, wherein the target bus data and the measurement data of the chip design are generated by the hardware acceleration simulation platform;

the time sequence waveform diagram generation module is used for generating a time sequence waveform diagram based on the acquired target bus data; the time sequence waveform diagram comprises working waveforms of key driving signals;

the clock frequency generation module is used for obtaining clock frequency based on the acquired measurement data, and the clock frequency of the clock signal is used for determining the validity of signal data of the key driving signal in the target bus data;

the interactive interface is used for displaying the time sequence waveform diagram generated by the time sequence waveform diagram generating module;

the state log generation module is used for processing the acquired target bus data to obtain state information of the key driving signals, wherein the state information is used for representing state changes of the key driving signals; and storing the state information to obtain a state log so as to inquire the state change of each key driving signal based on the state log.

19. An electronic device comprising a memory in which a program is stored and a processor that invokes the program stored in the memory to perform the signal processing method according to any one of claims 1 to 9 or to perform the signal processing method according to any one of claims 10 to 13.

20. A storage medium storing a program which, when executed, implements the signal processing method according to any one of claims 1 to 9 or implements the signal processing method according to any one of claims 10 to 13.