CN117521575A - Groove type SIC-MOSFET preparation method - Google Patents
Groove type SIC-MOSFET preparation method Download PDFInfo
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Abstract
The invention provides a preparation method of a trench SIC-MOSFET, which belongs to the technical field of semiconductors and comprises the following steps: s1, establishing a simulation model, and establishing a two-dimensional model of the SIC-DTMOSFET by using a TCAD simulation tool; s2, in the process of carrying out two-dimensional structure simulation, qualitatively analyzing the single event effect of the device, adding a basic model in the simulation, adding a heavy ion incidence model and a thermodynamic model, carrying out gate oxide damage simulation and single event burnout simulation S3, and carrying out life prediction on the simulation model based on a BP neural network; and S4, optimizing a preparation method of the trench SIC-MOSFET according to simulation data conditions of a simulation model, and then performing actual preparation, thereby solving the problems that the gate oxide quality at the bottom of the trench is poor, electric field concentration is easy to occur at the corner of the trench, and the breakdown characteristic of the device is deteriorated because the oxidation rate at the bottom of the trench is far lower than that of the side wall of the trench.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a preparation method of a trench SIC-MOSFET.
Background
The development of power electronics systems has placed higher demands on the performance of semiconductor devices, in particular in the areas of high temperature, high frequency, radiation resistance, high voltage, etc. The traditional silicon material device manufacturing process is mature, but the performance of the material itself limits the application of the silicon device in extreme working environments. Compared with silicon (Si) materials, the silicon carbide (SIC) materials have larger forbidden band width, higher electron saturation drift velocity, stronger irradiation resistance, higher breakdown electric field and thermal conductivity, so that the silicon carbide (SIC) materials have wide application prospects in the fields of power electronic equipment, aerospace systems, high-speed rail traction equipment, military electronic communication systems and the like.
Compared with a planar gate SIC MOSFET device, the trench SIC MOSFET device has the advantages that the channel mobility is improved, the JFET effect is eliminated, the on-resistance of the device is obviously reduced, the dimension of a primary cell is reduced, and the power density is increased by forming a channel on the side wall of the trench.
In the conventional gate oxide preparation process of the SIC trench MOSFET, the oxidation rate of the trench bottom is far lower than that of the trench side wall, so that the quality of the gate oxide at the trench bottom is poor, electric field concentration is easy to occur at the trench corner, and the breakdown characteristic of the device is deteriorated.
Disclosure of Invention
The embodiment of the invention provides a preparation method of a trench SIC-MOSFET, which solves the problems that the gate oxide quality at the bottom of a trench is poor, electric field concentration is easy to occur at the corner of the trench, and the breakdown characteristic of a device is deteriorated because the oxidation rate of the bottom of the trench is far lower than that of the side wall of the trench.
In view of the above problems, the technical scheme provided by the invention is as follows:
the invention provides a preparation method of a trench SIC-MOSFET, which comprises the following steps:
s1, establishing a simulation model, and establishing a two-dimensional model of the SIC-DTMOSFET by using a TCAD simulation tool;
s2, in the process of carrying out two-dimensional structure simulation, qualitatively analyzing the single event effect of the device, adding a basic model in the simulation, and additionally adding a heavy ion incidence model and a thermodynamic model to carry out gate oxide damage simulation and single event burnout simulation;
s3, life prediction is carried out on the simulation model based on the BP neural network;
and S4, optimizing the preparation method of the trench SIC-MOSFET according to the simulation data condition of the simulation model, and then performing actual preparation.
As a preferred embodiment of the present invention, in the step S2, the basic model includes an SRH composite model, an auger composite model, a mobility model, and an incomplete ionization model, which are related to doping and temperature.
In the step S2, the simulation of the damage of the gate oxide layer is a time evolution process of the electric field intensity of the gate oxide layer of the device, and as the incident position is far away from the center of the gate, the electric field intensity in the gate oxide layer gradually becomes smaller, and a larger electric field intensity exists at the corner of the gate oxide layer, so that the gate oxide layer of the device is potentially damaged by the larger electric field intensity, thereby forming a leakage current channel.
As a preferred technical solution of the present invention, the generation rate of electron hole pairs generated by the heavy ion incident device can be calculated by the following formula:
G(l，w，t)＝G LET (l)R(w，l)T(t)
wherein R (w, l) and T (T) are spatiotemporal distribution functions describing electron hole pair production rate, G LET (l) LET generation density is related to the incident particle LET, w and l being the radius and length of the trajectory of the incident particle.
In the step S2, the single particle burn-out simulation is that the source-drain bias voltage applied when the internal lattice temperature of the device exceeds 3000K in the simulation is defined as the threshold voltage of the device SEB, a significant high temperature point is generated at the epitaxial layer and the substrate after the heavy ions are incident on the device, the lattice temperature of the point increases with time, when t=1ns, the point reaches the maximum value, electron hole pairs are generated after the heavy ions are incident on the device, the electrons move towards the drain under the action of an electric field, the electric field intensity at the point further increases, significant impact ionization is caused, the electrons continue to be accelerated to move under the action of the electric field, and a large current density is generated locally, so that the instantaneous off-state current is greatly increased, and the calculation is performed by the thermal power formula p=ui.
In the step S3, as a preferred technical solution of the present invention, life prediction of the simulation model is specifically as follows:
modeling the conduction voltage drop and drain current data of the device, and modeling the mathematical model T j ＝f(V DS ，I D ) Fitting the simulation data, establishing a junction temperature prediction scheme, and fitting the data by using a mathematical fitting tool in a MATLAB tool box, wherein the obtained junction temperature prediction mathematical model expression is as follows:
wherein V is DS Is the conduction voltage drop, T j Junction temperature, I D Is drain current, a 0 -a 6 Fitting coefficients for junction temperature.
As a preferable technical scheme of the invention, the life prediction of the simulation model adopts MATLAB to compare the prediction effects of two algorithms, the two algorithms give the same input parameters, the life of the same module is predicted, and the obtained life times prediction error percentage is obtained.
As a preferred technical scheme of the invention, in order to verify the feasibility of the service life prediction method for SIC-MOSFET by BP neural network in the step S3, a hardware circuit and a transplanting program are designed, a control circuit, a driving circuit and a display circuit are integrated on a PCB board and matched with an ADC acquisition module, the SIC-MOSFET is driven to be conducted, meanwhile, conduction voltage drop and drain current are acquired, and after the operation of a junction temperature prediction model and a service life prediction model transplanted in an FPGA, the obtained predicted junction temperature and service life times are displayed on a display screen for observation.
As a preferable technical scheme of the invention, the actual preparation method of the trench SIC-MOSFET in the step S4 is as follows:
ion implantation and annealing, implanting ions into the base region and the source region in a high-temperature environment to form a P type region and an N type region, and recovering the crystal structure of the material through annealing to reduce the defect density;
etching the groove and removing the oxide layer, depositing Si on SIC, and then oxidizing at low temperature to obtain high-quality SiO 2 The dielectric layer is etched and the oxide layer is removed, and the oxide layer on the side wall of the groove is required to be removed so as to reduce the density of the surface state;
depositing single-layer Si on SIC by ALD process, oxidizing, and circulating for several times to obtain high-quality SiO 2 A dielectric layer.
Compared with the prior art, the invention has the beneficial effects that:
according to the invention, through a model experiment on a structure, in the actual working process, the module is subjected to the dual effects of electric stress and thermal stress to cause fatigue damage and ageing failure, so that the service life of the SIC-MOSFET is predicted, the problems of a preparation method and the structure are conveniently and timely found, a reliable basis is provided for the requirement of system maintenance, the TCAD simulation is combined, the SIC-MOSFET is subjected to the gate oxide damage simulation and the single particle burn-out simulation, the problems of the SIC-MOSFET preparation method and the structure are more comprehensively known, an optimized scheme is obtained, and the service life of the SIC-MOSFET is prolonged.
The foregoing description is only an overview of the present invention, and is intended to be implemented in accordance with the teachings of the present invention in order that the same may be more clearly understood and to make the same and other objects, features and advantages of the present invention more readily apparent.
Drawings
FIG. 1 is a schematic flow chart of a method for fabricating a trench SIC-MOSFET according to the present invention;
fig. 2 is a schematic diagram of a practical preparation flow of a trench SIC-MOSFET preparation method disclosed in the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, based on the embodiments of the invention, which are apparent to those of ordinary skill in the art without inventive faculty, are intended to be within the scope of the invention.
Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, based on the embodiments of the invention, which are apparent to those of ordinary skill in the art without inventive faculty, are intended to be within the scope of the invention.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the apparatus or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
Example 1
Referring to fig. 1-2, the invention provides a technical scheme that: a preparation method of a trench SIC-MOSFET comprises the following steps:
s1, establishing a simulation model, and establishing a two-dimensional model of the SIC-DTMOSFET by using a TCAD simulation tool;
s2, in the process of carrying out two-dimensional structure simulation, qualitatively analyzing the single event effect of the device, adding a basic model in the simulation, and additionally adding a heavy ion incidence model and a thermodynamic model to carry out gate oxide damage simulation and single event burnout simulation;
s3, life prediction is carried out on the simulation model based on the BP neural network;
s4, optimizing a preparation method of the trench SIC-MOSFET according to simulation data conditions of a simulation model, and then performing actual preparation, wherein the specific preparation process is as follows:
ion implantation and annealing, implanting ions into the base region and the source region in a high-temperature environment to form a P type region and an N type region, and recovering the crystal structure of the material through annealing to reduce the defect density;
etching the groove and removing the oxide layer, depositing Si on SIC, and then oxidizing at low temperature to obtain high-quality SiO 2 The dielectric layer is etched and the oxide layer is removed, and the oxide layer on the side wall of the groove is required to be removed, so that the density of surface states is reduced, and the performance of the device is improved;
atomic layer regulation and control are carried out by adopting an ALD (atomic layer deposition) process, the mode has high control precision and good uniformity, the mode is suitable for a groove type device, monolayer Si is deposited on SIC (silicon carbide) by adopting the ALD process, then oxidation is carried out, and multiple times of circulation are carried out, so that high-quality SiO (silicon oxide) is obtained 2 A dielectric layer.
In addition, the ALD process prepared SiO 2 If the interface of the SIC insulating layer is not processed, high interface states can be caused due to lattice mismatch and the like, and at present, different SiO2/SIC interface processing methods and subsequent insulating layer growth modes are mainly studied.
The embodiment of the invention is also realized by the following technical scheme.
In an embodiment of the invention, in step S2, the basic model comprises a doping, temperature dependent SRH composite model, auger composite model, mobility model and incomplete ionization model.
In the embodiment of the invention, in step S2, the simulation of the damage of the gate oxide layer is that the electric field intensity of the gate oxide layer of the device is injected from the same position in the evolution process along with time, as the incidence position is far away from the center of the gate, the electric field intensity in the gate oxide layer is gradually reduced, the maximum position of the electric field intensity of the gate oxide layer is caused by the fact that ions are injected into the device to generate electron hole pairs, the holes generate serious accumulation effect on the gate oxide layer, the larger electric field intensity causes the gate oxide layer of the device to form potential damage, a leakage current channel is formed, and a seed damage mechanism explains that the gate leakage current of the irradiated device is increased in the gate characteristic test.
In an embodiment of the present invention, the generation rate of electron hole pairs generated by the heavy ion incidence device can be calculated by the following formula:
G(l，w，t)＝G LET (l)R(w，l)T(t)
wherein R (w, l) and T (T) are spatiotemporal distribution functions describing electron hole pair production rate, G LET (l) LET generation density is related to the incident particle LET, w and l being the radius and length of the trajectory of the incident particle.
In the embodiment of the invention, in step S2, the single particle burnout simulation is to define the source-drain bias voltage applied when the internal lattice temperature of the device exceeds 3000K in the simulation as the threshold voltage of the device SEB, generate a distinct high-temperature point at the epitaxial layer and the substrate after heavy ions are incident on the device, the lattice temperature of the point increases with time, reaches the maximum value when t=1 ns, generates electron hole pairs after the heavy ions are incident on the device, and the electrons move towards the drain under the action of an electric field, so that the electric field intensity is further increased, significant impact ionization is caused, the electrons continue to be accelerated and move under the action of the electric field, and generate a large current density in a local area, so that the instantaneous off-state current is greatly increased, calculated by a thermal power formula p=ui, and the lattice temperature of the local large current density exceeds the melting point of the SIC material, so that the single particle burnout event occurs.
In the embodiment of the present invention, in step S3, life prediction of the simulation model is specifically as follows:
modeling the conduction voltage drop and drain current data of the device, and modeling the mathematical model T j ＝f(V DS ，I D ) Fitting the simulation data, establishing a junction temperature prediction scheme, and fitting the data by using a mathematical fitting tool in a MATLAB tool box, wherein the obtained junction temperature prediction mathematical model expression is as follows:
wherein V is DS Is the conduction voltage drop, T j Junction temperature, I D Is drain current, a 0 -a 6 Fitting coefficients for junction temperature.
In the embodiment of the invention, the life prediction of the simulation model is carried out by comparing the prediction effects of two algorithms by adopting MATLAB, the two algorithms give the same input parameters, the life of the same module is predicted, and the obtained life times prediction error percentage is obtained.
In the embodiment of the invention, in order to verify the feasibility of the service life prediction method of the SIC-MOSFET by using the BP neural network in the step S3, a hardware circuit and a transplanting program are designed, a control circuit, a driving circuit and a display circuit are integrated on a PCB and matched with an ADC acquisition module, the conduction voltage drop and the drain current are acquired while the SIC-MOSFET is driven to be conducted, and the obtained predicted junction temperature and the obtained service life times are displayed on a display screen for observation after the operation of a junction temperature prediction model and a service life prediction model transplanted in the FPGA.
In addition, based on the simulation of BP neural network, actual experimental simulation is carried out, primary life prediction is carried out on SIC-MOSFET modules with power circulation of 3000 times, in the experimental process, a heating table is adopted to heat the modules in an acrylic glass cover, a temperature measuring instrument is used for continuously measuring the temperature of the modules, when the temperature of the modules is consistent with the set temperature of the heating table, the temperature in the acrylic glass cover reaches heat balance, and the junction temperature is the temperature of the heating table;
after the heating platform reaches a thermal steady state, a key is pressed to send double pulses, drain current and conduction voltage drop data are collected after waiting 40 mu s, the collected conduction voltage drop and drain current are calculated through a model transplanted in an FPGA, experimental data of the model are compared with experimental data of simulation operation, and data difference is calculated;
junction temperature prediction of the SIC-MOSFET model with 3000 times of power circulation under different gradient junction temperatures and different gradient drain currents can be performed, the junction temperature prediction of the SIC-MOSFET model in the early aging stage can be performed, the accuracy of the junction temperature prediction is high, and reliable input parameters are provided for a neural network for life prediction;
the LCD display is used for visually displaying the data of the model and the simulation operation, so that the data comparison is convenient.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, and various modifications and variations may be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
It should be understood that the specific order or hierarchy of steps in the processes disclosed are examples of exemplary approaches. Based on design preferences, it is understood that the specific order or hierarchy of steps in the processes may be rearranged without departing from the scope of the present disclosure. The accompanying method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented.
In the foregoing detailed description, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments of the subject matter require more features than are expressly recited in each claim. Rather, as the following claims reflect, invention lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate preferred embodiment of this invention.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. The processor and the storage medium may reside as discrete components in a user terminal.
For a software implementation, the techniques described herein may be implemented with modules (e.g., procedures, functions, and so on) that perform the functions described herein. These software codes may be stored in memory units and executed by processors. The memory unit may be implemented within the processor or external to the processor, in which case it can be communicatively coupled to the processor via various means as is known in the art.
The foregoing description includes examples of one or more embodiments. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the aforementioned embodiments, but one of ordinary skill in the art may recognize that many further combinations and permutations of various embodiments are possible. Accordingly, the embodiments described herein are intended to embrace all such alterations, modifications and variations that fall within the scope of the appended claims. Furthermore, as used in the specification or claims, the term "comprising" is intended to be inclusive in a manner similar to the term "comprising," as interpreted when employed as a transitional word in a claim. Furthermore, any use of the term "or" in the specification of the claims is intended to mean "non-exclusive or".
Claims (9)
1. The preparation method of the trench SIC-MOSFET is characterized by comprising the following steps of:
s1, establishing a simulation model, and establishing a two-dimensional model of the SIC-DTMOSFET by using a TCAD simulation tool;
s2, in the process of carrying out two-dimensional structure simulation, qualitatively analyzing the single event effect of the device, adding a basic model in the simulation, and additionally adding a heavy ion incidence model and a thermodynamic model to carry out gate oxide damage simulation and single event burnout simulation;
s3, life prediction is carried out on the simulation model based on the BP neural network;
and S4, optimizing the preparation method of the trench SIC-MOSFET according to the simulation data condition of the simulation model, and then performing actual preparation.
2. The method according to claim 1, wherein in the step S2, the basic model includes an SRH composite model, an auger composite model, a mobility model, and an incomplete ionization model, which are related to doping and temperature.
3. The method for fabricating a trench SIC-MOSFET according to claim 1, wherein in step S2, the simulation of the damage of the gate oxide layer is a time-dependent evolution of the electric field strength of the gate oxide layer of the device from the same location, and the electric field strength in the gate oxide layer becomes smaller gradually as the incident location is away from the center of the gate, and a larger electric field strength exists at the corner of the gate oxide layer, and the larger electric field strength causes the gate oxide layer of the device to form a potential damage, thereby forming a leakage current channel.
4. The method for fabricating a trench SIC-MOSFET according to claim 1, wherein the rate of generation of electron-hole pairs by the heavy ion incident device is calculated by the following formula:
G(l，w，t)＝G LET (l)R(w，l)T(t)
wherein R (w, l) and T (T) are spatiotemporal distribution functions describing electron hole pair production rate, G LET (l) LET generation density is related to the incident particle LET, w and l being the radius and length of the trajectory of the incident particle.
5. The method for preparing the trench SIC-MOSFET according to claim 1, wherein in the step S2, the single particle burn-out simulation is that the source-drain bias voltage applied when the internal lattice temperature of the device exceeds 3000K in the simulation is defined as the threshold voltage of the device SEB, a significant high temperature point is generated at the epitaxial layer and the substrate after the heavy ions are incident on the device, the lattice temperature of the point increases with time, when t=1ns, the maximum value is reached, the electron hole pair is generated after the heavy ions are incident on the device, the electrons move towards the drain under the action of the electric field, so that the electric field intensity is further increased, significant impact ionization is caused, the electrons continue to be accelerated under the action of the electric field, a large current density is locally generated, so that the instantaneous off-state current is greatly increased, and the calculation is performed by the thermal power formula p=ui.
6. The method for preparing the trench SIC-MOSFET according to claim 1, wherein in the step S3, life prediction is performed on the simulation model specifically as follows:
data simulating conduction voltage drop and drain current of device, and number of pairsLearning model T j ＝f(V DS ，I D ) Fitting the simulation data, establishing a junction temperature prediction scheme, and fitting the data by using a mathematical fitting tool in a MATLAB tool box, wherein the obtained junction temperature prediction mathematical model expression is as follows:
wherein V is DS Is the conduction voltage drop, T j Junction temperature, I D Is drain current, a 0 -a 6 Fitting coefficients for junction temperature.
7. The method for preparing the trench SIC-MOSFET according to claim 6, wherein the simulation model performs life prediction by comparing prediction effects of two algorithms by MATLAB, and the two algorithms give the same input parameters, predict the life of the same module, and obtain the life time prediction error percentage.
8. The method for preparing the trench type SIC-MOSFET according to claim 1, wherein in order to verify the feasibility of the life prediction method for the SIC-MOSFET by using the BP neural network in the step S3, a hardware circuit and a transplanting program are designed, a control circuit, a driving circuit and a display circuit are integrated on a PCB board and matched with an ADC acquisition module, the SIC-MOSFET is driven to be conducted, meanwhile, conduction voltage drop and drain current are acquired, and the obtained predicted junction temperature and life times are displayed on a display screen for observation after the operation of a junction temperature prediction model and a life prediction model transplanted in an FPGA.
9. The method for manufacturing a trench SIC-MOSFET according to claim 1, wherein the actual manufacturing method of the trench SIC-MOSFET in step S4 is as follows:
ion implantation and annealing, implanting ions into the base region and the source region in a high-temperature environment to form a P type region and an N type region, and recovering the crystal structure of the material through annealing to reduce the defect density;
etching the groove and removing the oxide layer, depositing Si on SIC, and then oxidizing at low temperature to obtain high-quality SiO 2 The dielectric layer is etched and the oxide layer is removed, and the oxide layer on the side wall of the groove is required to be removed so as to reduce the density of the surface state;
depositing single-layer Si on SIC by ALD process, oxidizing, and circulating for several times to obtain high-quality SiO 2 A dielectric layer.
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