CN117520213A

CN117520213A - Data processing method, device, computer equipment and readable storage medium

Info

Publication number: CN117520213A
Application number: CN202311388894.1A
Authority: CN
Inventors: 瞿浩
Original assignee: Shenzhen Demingli Electronics Co Ltd
Current assignee: Shenzhen Demingli Electronics Co Ltd
Priority date: 2023-10-24
Filing date: 2023-10-24
Publication date: 2024-02-06

Abstract

The invention discloses a data processing method, a data processing device, computer equipment and a readable storage medium. The method comprises the following steps: applying for a first fixed address memory area as a mode table at a host end, wherein the mode table comprises a plurality of logic block addresses, and each logic block address corresponds to a target mode; maintaining a mode table, and applying a second fixed address memory area at a host end as a data buffer, wherein the data buffer comprises write-in data and read-out data; generating characteristic data according to the logical block addresses and the mode table, generating residual data according to the target modes corresponding to the logical block addresses, and storing the characteristic data and the residual data into a data buffer; and checking the characteristic data and the residual data, and determining the problem type according to the mode table and the logic block address when data checking is inconsistent. The method and the device save the memory use of the host end and reduce a large amount of problem positioning analysis time.

Description

Data processing method, device, computer equipment and readable storage medium

Technical Field

The present invention relates to the field of data processing technologies, and in particular, to a data processing method, a data processing device, a computer device, and a readable storage medium.

Background

When a host interacts with a device, a read/write command specified by the protocol involves interaction of data between the host and the device, where the data written by the host is expected to be consistent with the data read from the device. The prior scheme is mainly used for verifying the capability of the device firmware to store and read correct data, firstly, adopting a temporary variable to record pattern when generating writing data, taking an application heap in a script as a data buffer, setting the whole data buffer as the pattern, and finally, issuing a writing command and reading verification, and ending the script.

However, the above method has several disadvantages: (1) When the script is finished, all variables are recovered by the system, and when a problem occurs, the system cannot trace back, and whether the problem is that unexpected data written caused by a host problem cannot be delimited or unexpected data returned caused by a device problem can occur; (2) The written data is single, and when a problem occurs, whether the lba (logic block address, logical block address) is overwritten or not and whether the latest data is read or not are not clear; (3) If different data are to be written in the lba, the difficulty of maintaining the pattern by applying for temporary variables is high, and the writing operation and the reading verification are required to be completed in one script.

Disclosure of Invention

In view of the above, the present invention aims to overcome the deficiencies in the prior art and provide a data processing method, apparatus, computer device and readable storage medium.

The invention provides the following technical scheme:

in a first aspect, an embodiment of the present disclosure provides a data processing method, where the method includes:

applying for a first fixed address memory area as a mode table at a host end, wherein the mode table comprises a plurality of logic block addresses, and each logic block address corresponds to a target mode;

maintaining the mode table, and applying for a second fixed address memory area to be used as a data buffer at the host end;

generating characteristic data according to the logical block addresses and the mode table, generating residual data according to target modes corresponding to the logical block addresses, and storing the characteristic data and the residual data into the data buffer;

and checking the characteristic data and the residual data, and determining the problem type according to the mode table and the logic block address when data checking is inconsistent.

Further, the method further comprises:

when the memory of the host is insufficient to store the mode table, segmenting the logical block address to obtain a plurality of mode sub-tables, wherein the mode sub-tables comprise a dirty state and a clean state;

storing the mode table into a preset flash memory, and storing each mode sub-table into the memory of the host side.

Further, the maintaining the mode table includes:

judging whether a mode sub-table where the logical block address is located exists in the memory of the host side;

when the mode sub-table exists in the memory of the host side, acquiring a target mode corresponding to the logical block address, and recording the target mode into the mode table;

and when the mode sub-table does not exist in the memory of the host, acquiring a target mode corresponding to the logical block address according to the state of the mode sub-table, and recording the target mode into the mode table.

Further, the data buffer includes write data and read data, the generating feature data according to the logical block address and the pattern table includes:

writing the logical block address in a first interval byte of the writing data, and writing the mode table in a second interval byte of the writing data;

and merging the data contained in the first interval byte and the second interval byte into the characteristic data.

Further, the determining the problem type according to the mode table and the logical block address includes:

when the logical block addresses in the characteristic data are inconsistent in data verification, determining that the logical block addresses are equipment-side table entry problems;

and when the target mode in the characteristic data is inconsistent in data verification, analyzing whether the characteristic data is historical data according to the mode table, and determining the characteristic data as the equipment-side table item problem or the equipment-side garbage collection problem when the characteristic data is the historical data.

Further, the method further comprises:

modifying the logical block address of the unfinished write command in the mode table into virtual data;

and restoring the current mode of the logical block address of the incomplete write command in the mode table to a history mode.

Further, the method further comprises:

applying for a third fixed address memory area as a cache table at the host, wherein the cache table comprises a plurality of slots, and each write command corresponds to one slot number;

updating the data in the mode table into the cache table according to the slot number of each write command, and judging whether the write command is successfully executed or not;

when the write command is successfully executed, synchronizing the current mode of the corresponding slot number to the mode sub-table;

and when the write command fails to be executed, clearing the cache table where the corresponding slot number is located.

In a second aspect, in an embodiment of the present disclosure, there is provided a data processing apparatus, the apparatus including:

the first application module is used for applying a first fixed address memory area at a host end as a mode table, wherein the mode table comprises a plurality of logic block addresses, and each logic block address corresponds to a target mode;

the second application module is used for maintaining the mode table and applying for a second fixed address memory area as a data buffer at the host end;

the data generation module is used for generating characteristic data according to the logical block addresses and the mode table, generating residual data according to target modes corresponding to the logical block addresses, and storing the characteristic data and the residual data into the data buffer;

and the data verification module is used for verifying the characteristic data and the residual data, and determining the problem type according to the mode table and the logical block address when data verification is inconsistent.

In a third aspect, in an embodiment of the present disclosure, there is provided a computer device, including a memory storing a computer program and a processor implementing the steps of the data processing method described in the first aspect when the computer program is executed by the processor.

In a fourth aspect, in an embodiment of the present disclosure, there is provided a computer readable storage medium storing a computer program which, when executed by a processor, implements the steps of the data processing method described in the first aspect.

The beneficial effects of this application:

the data processing method provided by the embodiment of the application comprises the following steps: applying for a first fixed address memory area as a mode table at a host end, wherein the mode table comprises a plurality of logic block addresses, and each logic block address corresponds to a target mode; maintaining the mode table, and applying for a second fixed address memory area to be used as a data buffer at the host end; generating characteristic data according to the logical block addresses and the mode table, generating residual data according to target modes corresponding to the logical block addresses, and storing the characteristic data and the residual data into the data buffer; and checking the characteristic data and the residual data, and determining the problem type according to the mode table and the logic block address when data checking is inconsistent. The method and the device save the memory use of the host end and reduce a large amount of problem positioning analysis time.

In order to make the above objects, features and advantages of the present invention more comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. Like elements are numbered alike in the various figures.

FIG. 1 shows a flow chart of a data processing method provided in an embodiment of the present application;

FIG. 2 is a schematic diagram of a mode table according to an embodiment of the present application;

FIG. 3 is a schematic diagram illustrating a data generation manner according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a data processing apparatus according to an embodiment of the present application;

fig. 5 shows a schematic structural diagram of a computer device according to an embodiment of the present application.

Detailed Description

Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention.

It will be understood that when an element is referred to as being "fixed to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. The terms "vertical," "horizontal," "left," "right," and the like are used herein for illustrative purposes only.

In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.

Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the templates herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.

Example 1

Referring to fig. 1, a flowchart of a data processing method in an embodiment of the present application is shown, where the data processing method provided in the embodiment of the present application includes the following steps:

step S110, a first fixed address memory area is applied as a mode table at the host end, wherein the mode table comprises a plurality of logic block addresses, and each logic block address corresponds to a target mode.

In this embodiment, a first fixed address memory area is applied as a pattern table, where the pattern table is used to record a target pattern corresponding to each logical block address lba, and the content including the write data also includes a manner of generating data. Each byte in the pattern table corresponds to a logical block address lba, and the structure is shown in FIG. 2.

It should be noted that the disc memory size required here is: capacity of disk x (1 byte/sector size), exemplified by SATA disk of 512G size: 512g× (1 byte/512 byte) =1g.

It can be understood that when the memory at the host side is insufficient to store the pattern table, the logical block address lba needs to be segmented, and each segment of logical block address lba corresponds to one pattern table, so as to obtain multiple pattern tables, where each pattern table includes a dirty state and a clean state, when the pattern table is written into data, the pattern table is changed from the clean state to the dirty state, and when the pattern table is brushed down to the pattern table, the pattern table is changed from the dirty state to the clean state. Storing the mode table into a preset flash memory nand (such as emmc), and storing each mode sub-table into the memory of the host side.

The method introduces the mode table and the mode sub-table, and can well solve the problem that the memory of a host end of a large-capacity disc is insufficient to store the complete mode table. And each target mode pattern occupies only 1byte in the memory, so that the memory use is saved to a certain extent, and the pattern table can be acquired at any time during the power-on period of the host terminal.

Step S120, maintaining the mode table, and applying for the second fixed address memory area as a data buffer at the host side.

Before writing data, the pattern table needs to be maintained, and the data characteristic pattern corresponding to the logical block address lba needs to be recorded in the pattern table.

Specifically, for reading data, the maintenance flow is as follows: firstly judging whether a mode sub-table where a logical block address lba is located exists in a memory of a host end, if so, directly acquiring a target mode pattern corresponding to the logical block address lba, and recording the target mode pattern into a mode table; if the logical block address lba is not in the dirty state, judging whether the current mode sub-table is in the dirty state, if the current mode sub-table is not in the dirty state, loading the mode sub-table in which the logical block address lba is located in a mode table into a designated position of a host side memory, if the current mode sub-table is in the dirty state, brushing the mode sub-table down into the mode table, clearing the mode sub-table to be in the clean state, loading the mode sub-table in which the logical block address lba is located in the mode table into the designated position of the host side memory, finally moving the designated position into the next mode sub-table in the memory, further obtaining a target mode pattern corresponding to the logical block address lba, and recording the target mode pattern into the mode table.

Further, for writing data, the maintenance flow is as follows: firstly judging whether a mode sub-table where a logical block address lba is located exists in a memory of a host side, if so, directly shifting a target mode pattern corresponding to the logical block address lba on a corresponding offset of the corresponding mode sub-table, recording the target mode pattern into a mode table, and giving a dirty state to the mode sub-table; if the mode sub-table is not in the dirty state, judging whether the current mode sub-table is in the dirty state, if the current mode sub-table is not in the dirty state, loading the mode sub-table in which the logical block address lba is located in a mode table to a designated position of a host side memory, if the current mode sub-table is in the dirty state, brushing the mode sub-table down to the mode table, clearing the mode sub-table to be in the clean state, loading the mode sub-table in which the logical block address lba is located in the mode table to the designated position of the host side memory, finally moving the designated position to the next mode sub-table in the memory, further, recording the target mode pattern corresponding to the logical block address lba on the corresponding offset of the corresponding mode sub-table to the mode pattern table, and giving the dirty state to the mode sub-table.

And applying a second fixed address memory area at the host end as a data buffer, wherein the data buffer is used for storing write data to be written into the disc and read data read from the disc. The data buffer will be evenly distributed according to the cmd queue depth of the storage medium protocol, and each slot will correspond to a fixed area.

The size of the second fixed address memory area depends on the cmd queue depth of the storage medium protocol and the maximum IO size of the single command, i.e. data buffer size=cmd queue depth×max IO, exemplified by SATA disk: 32×32m=1g.

According to the embodiment, through applying for the data buffer, the actual data written and read is recorded in the area, the area can be used as very practical debug information and evidence, and when data inconsistency occurs, the problem of fast delimitation can be attributed to a host end or a device equipment end.

And step S130, generating characteristic data according to the logical block addresses and the mode table, generating residual data according to target modes corresponding to the logical block addresses, and storing the characteristic data and the residual data into the data buffer.

In this embodiment, in order to facilitate positioning of an entry problem, the logical block address lba data is written in a first interval byte (8 bytes) of the write data, and in order to facilitate garbage collection and positioning of an entry problem, the pattern table data is written in a second interval byte (8 bytes) of the write data. The data (first 16 bytes of data) included in the first interval byte and the second interval byte are referred to as feature data.

The bytes of the remaining space are filled with data generated according to each target pattern, and in order to save the time of data verification, this embodiment provides 3 ways of generating data when generating data, and the view is shown in fig. 3. Mode 1: feature data + all data for the remaining space; mode 2: feature data + second 16 bytes of data; mode 3: and finally, storing the characteristic data and the residual data into a data buffer.

The method adopts the mode of adding the residual data to the characteristic data, so that the problem positioning time can be shortened. Compared with the traditional byte-by-byte full verification, the method for generating various data can greatly save the execution time of the host script by properly applying head-to-tail verification.

And step S140, checking the characteristic data and the residual data, and determining the problem type according to the mode table and the logical block address when data checking is inconsistent.

The data verification is divided into two parts, and the feature data and the residual data are verified, and when the residual data are performed, the verification is performed according to the three modes when the data are generated in step S130.

Firstly, checking the characteristic data, if the characteristic data fails to check, checking the residual data if the characteristic data passes the check, and ending the checking flow if the residual data passes the check, and if the residual data does not pass the check, the data is not consistently reported to be wrong.

When data verification inconsistency occurs at a logical block address lba in the feature data, the device side list item is quickly and preliminarily determined to be in error (the problem that the device side list item refers to old data and covers new data); when the target modes in the characteristic data are inconsistent in data verification, whether the characteristic data are historical data is analyzed according to a mode table recorded by a host side, and when the characteristic data are the historical data, the high probability can be determined to be that the table items of the equipment side are in error or the garbage collection and the error of the equipment side are in error, so that a large amount of problem positioning analysis time is shortened.

It should be noted that, in order to facilitate data verification of the spot scene, each recorded target pattern includes a current mode of current writing and a history mode of last writing, when the spot scene appears, the current mode is preferentially used for verification, and when the data is inconsistent for the first time, the history mode is used for verification.

In an alternative embodiment, since the present application maintains the pattern table in advance for write commands, it is expected that all write commands can be expected to complete. Then when an exception occurs in the write command, a maintenance error will occur in the pattern table, affecting some test item results that follow. The present application also provides three schemes for exception handling:

(1) All logical block addresses lba corresponding to incomplete write commands in the mode table are changed into virtual data in the mode table pattern table, namely the host end can consider that the logical block addresses lba are not written or the data of the logical block addresses lba are not credible, and when a virtual target mode is acquired, the host end can not check the data.

(2) Because the pattern table records the history pattern written by each logical block address lba, the current pattern in the pattern table can be recovered to the history pattern by the logical block addresses lba corresponding to the incomplete write command, for example: dummy pattern=0, the current mode obtained is 0x35, and then the mode is restored to 0x03.

(3) Applying for a third fixed address memory area as a cache table cache pattern table at the host end, where the cache table includes a plurality of slot slots, each write command corresponds to a slot number, each slot shares a single area, and the total size of the area is: data buffer size/sector size, exemplified by sata: 1G/512 byte=2m. Updating the data in the pattern table to the cache table cache pattern table according to the slot number of each write command, and judging whether the write command is successfully executed or not; and when the write command is successfully executed, synchronizing the current mode of the corresponding slot number to the mode sub-table, and when the write command is failed to be executed, clearing the cache table cache pattern table where the corresponding slot number is located.

According to the data processing method provided by the embodiment of the application, a first fixed address memory area is applied to a host side as a mode table, wherein the mode table comprises a plurality of logic block addresses, and each logic block address corresponds to a target mode; maintaining the mode table, and applying for a second fixed address memory area to be used as a data buffer at the host end; generating characteristic data according to the logical block addresses and the mode table, generating residual data according to target modes corresponding to the logical block addresses, and storing the characteristic data and the residual data into the data buffer; and checking the characteristic data and the residual data, and determining the problem type according to the mode table and the logic block address when data checking is inconsistent. The method and the device save the memory use of the host end and reduce a large amount of problem positioning analysis time.

Example 2

As shown in fig. 4, a schematic structural diagram of a data processing apparatus 400 according to an embodiment of the present application includes:

a first application module 410, configured to apply for a first fixed address memory area as a mode table at a host side, where the mode table includes a plurality of logical block addresses, and each logical block address corresponds to a target mode;

a second application module 420, configured to maintain the mode table, and apply for a second fixed address memory area as a data buffer at the host side;

the data generating module 430 is configured to generate feature data according to the logical block addresses and the pattern table, generate remaining data according to a target pattern corresponding to each logical block address, and store the feature data and the remaining data in the data buffer;

and a data verification module 440, configured to verify the feature data with the remaining data, and determine a problem type according to the pattern table and the logical block address when data verification disagreement occurs.

Optionally, the data processing apparatus 400 further includes:

the segmentation module is used for segmenting the logical block address to obtain a plurality of mode sub-tables when the memory of the host side is insufficient to store the mode table, wherein the mode sub-tables comprise a dirty state and a clean state;

the storage module is used for storing the mode table into a preset flash memory and storing each mode sub-table into the memory of the host side.

Optionally, the data processing apparatus 400 further includes:

the judging module is used for judging whether a mode sub-table where the logical block address is located exists in the memory of the host side;

the first recording module is used for acquiring a target mode corresponding to the logical block address when the mode sub-table exists in the memory of the host side, and recording the target mode into the mode table;

and the second recording module is used for acquiring a target mode corresponding to the logical block address according to the state of the mode sub-table when the mode sub-table does not exist in the memory of the host side, and recording the target mode into the mode table.

Optionally, the data processing apparatus 400 further includes:

a writing module, configured to write the logical block address in a first interval byte of the write data, and write the pattern table in a second interval byte of the write data;

and the merging module is used for merging the data contained in the first interval byte and the second interval byte into the characteristic data.

Optionally, the data processing apparatus 400 further includes:

the first determining module is used for determining the problem of the table item at the equipment end when the data verification inconsistency occurs at the logical block addresses in the characteristic data;

and the second determining module is used for analyzing whether the characteristic data is historical data according to the mode table when the target modes in the characteristic data are inconsistent in data verification, and determining the characteristic data as the equipment-side table item problem or the equipment-side garbage collection problem when the characteristic data are the historical data.

Optionally, the data processing apparatus 400 further includes:

the modifying module is used for modifying the logical block address of the unfinished write command in the mode table into virtual data;

and the recovery module is used for recovering the current mode of the logical block address of the incomplete write command in the mode table to be a history mode.

Optionally, the data processing apparatus 400 further includes:

the third application module is used for applying a third fixed address memory area as a cache table at the host end, wherein the cache table comprises a plurality of slots, and each write command corresponds to one slot number;

the updating module is used for updating the data in the mode table into the cache table according to the slot number of each write command and judging whether the write command is successfully executed or not;

the synchronization module is used for synchronizing the current mode of the corresponding slot number to the mode sub-table when the write command is successfully executed;

and the clearing module is used for clearing the cache table where the corresponding slot number is located when the write command fails to be executed.

The data processing device provided by the embodiment of the application saves the memory use of the host end and reduces a large amount of problem positioning analysis time.

Example 3

The embodiment of the application also provides computer equipment. Referring specifically to fig. 5, fig. 5 is a basic structural block diagram of a computer device according to the present embodiment.

The computer device 5 comprises a memory 51, a processor 52, a network interface 53 which are communicatively connected to each other via a system bus. It should be noted that only the computer device 5 with components 51-53 is shown in the figures, but it should be understood that not all of the illustrated components are required to be implemented and that more or fewer components may be implemented instead. It will be appreciated by those skilled in the art that the computer device herein is a device capable of automatically performing numerical calculations and/or information processing in accordance with predetermined or stored instructions, the hardware of which includes, but is not limited to, microprocessors, application specific integrated circuits (Application Specific Integrated Circuit, ASICs), programmable gate arrays (fields-Programmable Gate Array, FPGAs), digital processors (Digital Signal Processor, DSPs), embedded devices, etc.

The computer equipment can be a desktop computer, a notebook computer, a palm computer, a cloud server and other computing equipment. The computer equipment can perform man-machine interaction with a user through a keyboard, a mouse, a remote controller, a touch pad or voice control equipment and the like.

The memory 51 includes at least one type of readable storage medium including flash memory, hard disk, multimedia card, card memory (e.g., SD or D slot compatibility test memory, etc.), random Access Memory (RAM), static Random Access Memory (SRAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), programmable Read Only Memory (PROM), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the storage 51 may be an internal storage unit of the computer device 5, such as a hard disk or a memory of the computer device 5. In other embodiments, the memory 51 may also be an external storage device of the computer device 5, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash Card (Flash Card) or the like, which are provided on the computer device 5. Of course, the memory 51 may also comprise both an internal memory unit of the computer device 5 and an external memory device. In this embodiment, the memory 51 is typically used to store an operating system and various application software installed on the computer device 5, such as computer readable instructions of a socket compatibility test method. Further, the memory 51 may be used to temporarily store various types of data that have been output or are to be output.

The processor 52 may be a central processing unit (Central Processing Unit, CPU), controller, microcontroller, microprocessor, or other data processing chip in some embodiments. The processor 52 is typically used to control the overall operation of the computer device 5. In this embodiment, the processor 52 is configured to execute computer readable instructions stored in the memory 51 or process data, such as computer readable instructions for executing the socket compatibility test method.

The network interface 53 may comprise a wireless network interface or a wired network interface, which network interface 53 is typically used to establish communication connections between the computer device 5 and other electronic devices.

The computer device provided in this embodiment may execute the data processing method, and this embodiment is not described herein. The data processing method here may be the data processing method of each of the above embodiments.

Example 4

The present embodiment also provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor implements the steps of the data processing method in the embodiment, and the embodiment is not described herein again.

In this embodiment, the computer-readable storage medium includes a flash memory, a hard disk, a multimedia card, a card memory (e.g., SD or DX memory, etc.), a Random Access Memory (RAM), a Static Random Access Memory (SRAM), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), a programmable read-only memory (PROM), a magnetic memory, a magnetic disk, an optical disk, and the like. In some embodiments, the computer readable storage medium may be an internal storage unit of a computer device, such as a hard disk or a memory of the computer device. In other embodiments, the computer readable storage medium may also be an external storage device of a computer device, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash Card (Flash Card), etc. that are provided on the computer device. Of course, the computer-readable storage medium may also include both internal storage units of a computer device and external storage devices. In this embodiment, the computer-readable storage medium is typically used to store an operating system and various types of application software installed on a computer device. Furthermore, the computer-readable storage medium may also be used to temporarily store various types of data that have been output or are to be output.

In the several embodiments provided in this application, it should be understood that the disclosed apparatus and method may be implemented in other manners as well. The apparatus embodiments described above are merely illustrative, for example, of the flow diagrams and block diagrams in the figures, which illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In addition, functional modules or units in various embodiments of the invention may be integrated together to form a single part, or the modules may exist alone, or two or more modules may be integrated to form a single part.

The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a smart phone, a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. The storage medium may be a nonvolatile storage medium or a volatile storage medium, and for example, the storage medium may be: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention.

Claims

1. A method of data processing, the method comprising:

2. The data processing method of claim 1, wherein the method further comprises:

3. The data processing method according to claim 2, wherein the maintaining the pattern table includes:

4. The data processing method according to claim 1, wherein the data buffer contains write data and read data, the generating feature data from the logical block address and the pattern table, comprising:

5. The data processing method according to claim 1, wherein said determining a problem type from said pattern table and said logical block address comprises:

6. A data processing method according to claim 3, characterized in that the method further comprises:

7. The data processing method of claim 6, wherein the method further comprises:

8. A data processing apparatus, the apparatus comprising:

9. A computer device comprising a memory and a processor, the memory storing a computer program, the processor implementing the steps of the data processing method of any of claims 1-7 when the computer program is executed.

10. A computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program which, when executed by a processor, implements the steps of the data processing method of any of claims 1-7.