CN117519792A - Register release method, processor, chip and electronic equipment - Google Patents
Register release method, processor, chip and electronic equipment Download PDFInfo
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
- G06F9/5022—Mechanisms to release resources
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Abstract
The embodiment of the invention provides a register release method, a processor, a chip and electronic equipment, wherein the method comprises the following steps: determining an instruction result identifier corresponding to a target logic register in a current instruction; when the instruction result identifier indicates that the value of the target logic register is a preset value, mapping the target logic register to a preset physical register; wherein the value of the preset physical register is the preset value; releasing an initial mapping register and a target mapping register corresponding to the target logic register, wherein the initial mapping register is a physical register mapped by the target logic register before the current instruction is executed, and the target mapping register is a physical register mapped by the target logic register after the current instruction is executed. The scheme of the embodiment of the invention can more effectively utilize the physical register resource and improve the resource utilization efficiency of the physical register.
Description
Technical Field
The embodiment of the invention relates to the technical field of processors, in particular to a register release method, a processor, a chip and electronic equipment.
Background
Physical registers in a processor require register mapping when in use. Specifically, based on the architectural design of the instruction set of a processor, the processor, during the execution of the instruction phase, needs to assign physical registers to logical registers specified on the instruction set architecture, a process known as register mapping. However, in a processor in which multithreading Cheng Luan is executed, the resource utilization efficiency of the physical registers is to be improved when multithreading is executed simultaneously.
Disclosure of Invention
In view of this, embodiments of the present invention provide a method, a processor, a chip, and an electronic device for releasing a register, so as to improve the resource utilization efficiency of a physical register.
In order to achieve the above purpose, the embodiment of the present invention provides the following technical solutions.
In a first aspect, an embodiment of the present invention provides a method for releasing a register, including:
determining an instruction result identifier corresponding to a target logic register in a current instruction, wherein the target logic register is used for storing an instruction result of the current instruction;
when the instruction result identification indicates that the value of the target logical register is a preset value,
mapping the target logic register to a preset physical register; wherein the value of the preset physical register is the preset value;
releasing an initial mapping register and a target mapping register corresponding to the target logic register, wherein the initial mapping register is a physical register mapped by the target logic register before the current instruction is executed, and the target mapping register is a physical register mapped by the target logic register after the current instruction is executed.
Preferably, the determining the instruction result identifier corresponding to the target logic register in the current instruction includes:
reading the value of the bit corresponding to the current instruction in the identification register;
or,
and reading the value of the instruction result identification bit of the item corresponding to the current instruction in the submission queue.
Preferably, the mapping the target logical register to a preset physical register, specifically, in the target register mapping table, the mapping relationship of the target logical register is modified to be mapped to the preset physical register.
Preferably, the target register mapping table includes a commit register mapping table, where the commit register mapping table is a mapping table of a physical register and a logical register used for a commit flow after the instruction is executed.
Preferably, the target register mapping table further includes a prediction register mapping table, where the prediction register mapping table is a mapping table of physical registers and logical registers after the instruction is launched and renamed in the instruction execution flow.
Preferably, before determining the instruction result identifier corresponding to the target logic register in the current instruction, the method further includes:
obtaining an instruction result of a current instruction;
and when the instruction result is a preset value, configuring an instruction result identifier so that the instruction result identifier indicates that the value of the target logic register is the preset value.
Preferably, when the instruction result is a preset value, the instruction result identifier is configured, specifically, the instruction result identifier is configured to be a first value;
and when the instruction result is not a preset value, configuring the instruction result identification as a second value.
Preferably, when the instruction result is a preset value, the configuring the instruction result identifier to be a first value includes:
configuring a bit in an identification register corresponding to the current instruction as a first value;
or,
and configuring an instruction result identification bit of an item corresponding to the current instruction in the submission queue to be a first value.
Preferably, after the instruction result of the current instruction is obtained, the method further includes:
and writing the instruction result into a target mapping register corresponding to the target logic register.
Preferably, when the instruction result identifier indicates that the value of the target logical register is a preset value, the method further includes:
and modifying a source physical register of the instruction which depends on the target logical register in the scheduling queue into a preset physical register.
Preferably, when the instruction result identifier indicates that the value of the target logical register is a preset value, the method further includes:
when there is a dependency on the target logical register for an issued instruction that is already in the issue stage, processing is based on the data in the target map register.
Preferably, the method further comprises: if the current instruction is cancelled, initializing an instruction result identifier corresponding to the current instruction.
Preferably, the initializing an instruction result identifier corresponding to the current instruction includes:
when the instruction result identification is stored in the identification register, resetting a bit corresponding to the current instruction in the identification register;
or,
and when the instruction result identification stores the item corresponding to the current instruction in the commit queue, resetting the instruction result identification bit of the item corresponding to the current instruction in the commit queue.
In a second aspect, an embodiment of the present invention provides a processor, including:
the submitting unit is used for determining an instruction result identifier corresponding to a target logic register in the current instruction, wherein the target logic register is used for storing the instruction result of the current instruction; when the instruction result identifier indicates that the value of the target logic register is a preset value, mapping the target logic register to a preset physical register; wherein the value of the preset physical register is the preset value; releasing an initial mapping register and a target mapping register corresponding to the target logic register, wherein the initial mapping register is a physical register mapped by the target logic register before the current instruction is executed, and the target mapping register is a physical register mapped by the target logic register after the current instruction is executed;
and the physical register file is used for providing physical registers as an initial mapping register, a target mapping register and a preset physical register.
Preferably, the processor further includes a renaming unit, configured to modify, when the target register mapping table includes a prediction register mapping table, a mapping relationship of the target logical register to be mapped to a preset physical register in the prediction register mapping table based on an instruction of the commit unit.
Preferably, the submitting unit is further configured to obtain an instruction result of the current instruction; and when the instruction result is a preset value, configuring an instruction result identifier so that the instruction result identifier indicates that the value of the target logic register is the preset value.
Preferably, the processor further includes a scheduling unit, configured to modify a source physical register of an instruction that depends on the target logical register in the scheduling queue into a preset physical register when the instruction result identifier indicates that the value of the target logical register is a preset value.
In a third aspect, an embodiment of the present invention provides a chip including a processor as described in the second aspect.
In a fourth aspect, an embodiment of the present invention provides an electronic device, including a chip as described in the third aspect.
The embodiment of the invention provides a register release method, a processor, a chip and electronic equipment, wherein the method comprises the following steps: determining an instruction result identifier corresponding to a target logic register in a current instruction; when the instruction result identifier indicates that the value of the target logic register is a preset value, mapping the target logic register to a preset physical register; wherein the value of the preset physical register is the preset value; releasing an initial mapping register and a target mapping register corresponding to the target logic register, wherein the initial mapping register is a physical register mapped by the target logic register before the current instruction is executed, and the target mapping register is a physical register mapped by the target logic register after the current instruction is executed.
It can be seen that, in the embodiment of the present invention, when the value of the target logical register is a preset value, the target logical register is mapped to a preset physical register whose value is the preset value, so that the initial mapping register and the target mapping register corresponding to the target logical register can be released at the same time, and further more register resources are provided for other threads. Obviously, the scheme of the embodiment of the invention can more effectively utilize the physical register resource and improve the resource utilization efficiency of the physical register.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an instruction processing flow;
FIG. 2 is an alternative example diagram of a logical register map physical register;
FIG. 3 is a diagram of an alternative flow example of a register release flow;
FIG. 4 is a schematic diagram of a processor according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of an alternative flow chart of a register release method according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of an alternative configuration of an identification register according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of an alternative structure of a commit queue according to an embodiment of the present invention;
FIG. 8 is a diagram illustrating an alternative embodiment of a register release procedure according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of an alternative method for releasing registers according to an embodiment of the present invention;
fig. 10 is a schematic diagram of a processor according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the processor, in order to execute the computing task, the task may be decomposed into a plurality of instructions, and the plurality of instructions are processed simultaneously by a multithreading mechanism to obtain a corresponding computing result. For an instruction, referring to an instruction processing flow diagram shown in fig. 1, an instruction processing procedure may include an instruction fetching flow, a decoding flow, an execution flow, a commit flow, and the like.
The instruction fetching flow refers to fetching instructions according to instruction fetching instructions predicted by a branch prediction unit at the front end of the processor, and the instructions are extracted from an instruction cache; the decoding flow is used for decoding and analyzing the acquired instruction to obtain operation information which can be executed by the machine; an execution flow for executing an operation based on the decoded instruction to generate an execution result; and submitting a flow for writing the execution result into the memory or the external equipment.
In the decoding flow, an operation code (OpCode) of the instruction, an operand, a control field, a logic register in which a source operand and a destination operand are stored in the instruction, and other required information can be obtained by analysis; in the execution flow, the number of the physical register corresponding to the logical register can be obtained by combining the table entries in the register mapping table according to the logical register stored by the source operand and the destination operand; and according to the number of the physical register, acquiring data corresponding to the source operand from the physical register file, obtaining a real-time storage result, and writing the real-time storage result back to the physical register corresponding to the destination operand.
The register map may record a mapping relationship between the physical registers actually allocated and the architectural registers. During processing of instructions, a logical register may be mapped to different physical registers based on different instruction processing stages. For example, referring to an alternative example diagram of a logical register map physical register shown in fig. 2, in one thread 0, logical register lrn1 has a register number prn of 30 (labeled prn_30 in the figure) corresponding to the physical register (the physical register may be referred to as an initial map register), and when there is a new instruction write lrn1, a new physical register (the physical register may be referred to as a target map register) may be allocated for lrn1, and the corresponding register number prn is 40 (labeled prn_40 in the figure), and at this time, the target map register for lrn1 is updated to prn as 40 in the register map table.
However, under a multithreaded parallel processing mechanism, multiple threads process multiple instructions simultaneously and share a set of physical registers. Based on the limited physical register resources, how to effectively utilize the physical register resources has an important effect on the instruction processing efficiency.
In an alternative example, consider that the target mapped register mapped by the logical register is subject to instruction commit, and thus the physical registers mapped by the logical register in different stages may be recorded and the initial mapped register released during instruction commit flow.
Referring to an alternative flow example diagram of a register release flow shown in fig. 3, still taking the register number prn of the initial mapping register of lrn as 30 and the register number prn of the target mapping register as 40 as an example, in the instruction commit queue (request queue), the target mapping register under the instruction may be recorded as 40 (new prn=40), and the initial mapping register as 30 (old prn=30). If the result lrn1 =0 is calculated in the "result stage", 0 is written into the target map register in the "write-back stage", and at the same time, the initial map register is released in the "commit stage".
The inventors further studied that, in some specific scenarios, for example, when a video coding algorithm calculates YUV (a color coding method representing a color image, where Y is luminance, U is blue chromaticity, and V is red chromaticity) residual data, intra-frame or inter-frame information is often relatively close, and the calculated residual data is often all zeros. Thus, given that some specific results often appear, improvements in schemes can be made for those specific results.
Specifically, the inventor considers that when calculating an instruction with a specific result, mapping a logic register recording the result to a physical register with a value of the specific result, and then releasing an initial mapping register and a target mapping register in an instruction transmitting flow at the same time, thereby effectively utilizing physical register resources and improving instruction processing efficiency.
In view of this, an embodiment of the present invention provides a method for releasing a register, a processor, a chip, and an electronic device, where the method includes: determining an instruction result identifier corresponding to a target logic register in a current instruction; when the instruction result identifier indicates that the value of the target logic register is a preset value, mapping the target logic register to a preset physical register; wherein the value of the preset physical register is the preset value; releasing an initial mapping register and a target mapping register corresponding to the target logic register, wherein the initial mapping register is a physical register mapped by the target logic register before the current instruction is executed, and the target mapping register is a physical register mapped by the target logic register after the current instruction is executed.
It can be seen that, in the embodiment of the present invention, when the value of the target logical register is a preset value, the target logical register is mapped to a preset physical register whose value is the preset value, so that the initial mapping register and the target mapping register corresponding to the target logical register can be released at the same time, and further more register resources are provided for other threads. Obviously, the scheme of the embodiment of the invention can more effectively utilize the physical register resource and improve the resource utilization efficiency of the physical register.
The following describes the register release scheme in the embodiment of the present invention in detail.
The embodiment of the invention provides a processor, which can be understood as being used for executing the register release method described in the above embodiment. Specifically, fig. 4 shows an architecture schematic diagram of a processor according to an embodiment of the present invention. As shown in fig. 1, the processor may include: instruction fetch unit 101, decode unit 102, execution unit 103, commit unit 104, register map 105, and physical register file 106.
The instruction fetch unit 101 may fetch instructions from the instruction cache according to instruction fetch instructions, for example, according to instruction fetch instructions predicted by a branch prediction unit at the front end of the processor.
The decode unit 102 may decode and parse the instruction obtained by the instruction fetch unit 101 to obtain operation information executable by a machine, for example, an operation code (OpCode) of the parsed instruction, an operand, and a control field to form a machine executable uop (micro instruction), and obtain a logical register in which a source operand and a destination operand of the instruction are stored, and other required information.
The execution unit 103 may perform operations based on the decoded instructions to generate execution results. The execution unit 103 combines the table entries in the register mapping table 105 to obtain the numbers of the physical registers corresponding to the logical registers according to the logical registers stored by the source operands and the destination operands decoded by the decoding unit 102; according to the number of the physical register, acquiring data corresponding to a source operand from the physical register file 106 to obtain a real-time storage result; and writing the real-time storage result back to a physical register corresponding to the destination operand.
A Commit Unit (Commit Unit) 104, configured to Commit an instruction result of the instruction execution to the write memory or the external device. When a processor executes instructions, it performs operations and operations on the data and stores the results in an internal register or cache, which are only committed to memory or external devices for use by other programs or processors. The commit unit writes the instruction results of the instruction execution from the target logical register into the memory or external device.
It should be noted that, the register mapping table 105 may record a mapping relationship between the physical registers and the architectural registers that are actually allocated. Reestablishing or modifying the mapping between physical and logical registers in the physical register file 106 may be accomplished by modifying the mapping in the register map 105. It should be noted that, the logical registers are registers defined on the instruction set architecture, and are also registers used by a programmer when using assembly language, and the physical registers are hardware resources actually existing in the processor.
It should be further noted that the instruction fetch unit 101, the decode unit 102, the execution unit 103, the commit unit 104, and the physical register file 106 shown in fig. 4 may be logic circuit units in a processor. In addition, it is to be understood that fig. 4 illustrates only a part of an alternative structure of a processor, and the processor may include other devices that are possible, for example, the processor may also include other circuit devices that are not necessary for understanding the disclosure of the embodiments of the present invention, and the embodiments of the present invention will not be further described in view of the fact that the other circuit devices are not necessary for understanding the disclosure of the embodiments of the present invention.
On the basis of the optional architecture of the processor, the embodiment of the invention provides a register release method, and referring to an optional flow diagram of the register release method provided by the embodiment of the invention shown in fig. 5, the register release method comprises the following steps:
step S10: determining an instruction result identifier corresponding to a target logic register in a current instruction;
the current instruction may be understood as an instruction being executed by the current thread. The target logic register is a logic register defined by a current instruction and used for storing an instruction result, wherein before the current instruction is executed, a physical register mapped by the target logic register is an initial mapping register, and after the current instruction is executed, a physical register mapped by the target logic register is a target mapping register.
The instruction result identifier is used for marking whether the value of the target logic register is a preset value (i.e. whether the instruction result is a preset value), wherein when the target logic register is the preset value, the instruction result identifier can be configured to be a first value, for example, 1, so as to mark the target logic register as the preset value (i.e. the instruction result is the preset value); when the target logical register is not a preset value, the instruction result identifier may be configured to be a second value, e.g., "0", to mark that the target logical register is not a preset value (i.e., the instruction result is not a preset value). In an alternative example, the preset value may be "0", and in other examples, the preset value may also be other values, which are not limited herein.
The instruction result identifier may be stored in a preset identifier register, or may be stored in an entry (entry) corresponding to the current instruction in a commit queue (request).
Wherein, in the example configured with the identification register, the identification register may include multiple bits, wherein one bit of the identification register corresponds to a current instruction, the number of bits of the identification register is greater than or equal to the maximum number of instructions executed in parallel in the processor, in a specific example, the number of bits of the identification register may be the same as the number of items of the commit queue, and the bits (bits) of the identification register correspond to the items (entries) of the commit queue one to one. Referring to fig. 6, an optional structure schematic diagram of an identification register provided by an embodiment of the present invention is shown, taking the number of entries of a commit queue as 100 as an example, where the identification register may be 100 bits, and may be named as request_queue_invalid_prn [99:0]. In a specific example, the initial value of each bit in the identifier register may be "0", and when the value of the corresponding target logic register is a preset value, the identifier register may be configured
The value of the corresponding bit of the memory is "1".
Correspondingly, when the instruction result identifier corresponding to the target logic register in the current instruction needs to be determined, the value of the bit corresponding to the current instruction in the identifier register can be read to determine the instruction result identifier of the current instruction.
With continued reference to fig. 6, taking the current instruction rid=15 and the target logical register lrn1 as an example, the bit request_queue_invalid_prn [15] corresponding to the instruction rid=15 in the identification register may be read to determine whether the value of the target logical register lrn1 is a preset value.
In an example where the instruction result identifier is stored in an entry (request queue) corresponding to a current instruction, an instruction result identifier bit may be configured in the entry corresponding to the current instruction in the commit queue, and the instruction result identifier bit may store a value of the instruction result identifier corresponding to the current instruction. For example, referring to fig. 7, an optional structure diagram of a commit queue according to an embodiment of the present invention may be shown, where when the number of entries in the commit queue is 100, the instruction result identifier bit may be named as request_queue_invalid_prn [99:0], for example, when the current instruction rid=15, the instruction result identifier bit of the entry corresponding to the current instruction is request_queue_invalid_prn [15]. Correspondingly, when the instruction result identification corresponding to the target logic register in the current instruction needs to be determined, the value of the instruction result identification bit of the item corresponding to the current instruction in the submission queue can be read, and then the instruction result identification of the current instruction is determined.
It will be appreciated that this step may be performed based on the commit flow of the current instruction by the commit unit.
When the instruction result identifier indicates that the value of the target logical register is a preset value, with continued reference to fig. 5, the following steps may be performed:
step S11: mapping the target logic register to a preset physical register;
it may be appreciated that after determining the corresponding instruction result identifier, whether the value of the target logical register is a preset value may be determined based on the instruction result identifier, so that different flows may be executed based on the instruction result identifier. In a specific implementation, when the instruction result identifier indicates that the value of the target logic register is a preset value, the step is executed, and when the instruction result identifier indicates that the value of the target logic register is not the preset value, the normal processing flow of the instruction can be executed.
In combination with the foregoing example regarding the instruction result identifier, when the instruction result identifier indicates that the first value indicates that the target logical register is a preset value, it may be determined whether the instruction result identifier is the first value, if so, the instruction result identifier indicates that the value of the target logical register is the preset value, and then the target logical register may be mapped to a preset physical register whose value is the preset value.
The preset physical register may be a physical register configured in advance and storing the preset value, that is, the value of the preset physical register is the preset value. In the preset scheme, the value of the preset physical register may be fixed until other requirements exist, and a preset value corresponding to the requirements may be configured. Based on the preset physical register fixed to a preset value, the target logical registers with the preset value in different threads/different instructions can be mapped to the preset physical register, so that one preset physical register can simultaneously correspond to a plurality of target logical registers, and more physical register resources are reserved for allocation. In a specific example, referring to an alternative flowchart illustration of a register release flowchart provided in the embodiment of the present invention shown in fig. 8, the preset value may be "0", the preset physical register may be zero prn, and accordingly, taking the target logical register as lm1 as an example, lm1 may be mapped to zero prn (labeled prn_0 in the figure).
When the instruction result identifier indicates that the value of the target logic register is a preset value, the mapping relation of the target logic register can be modified to be mapped to a preset physical register by modifying a mapping table of the target logic register.
In an alternative example, the target register map may include at least a COMMIT (COMMIT) register map, which is a map of physical and logical registers used to COMMIT a flow after an instruction has been executed.
Accordingly, by modifying the commit register mapping table, the reading of the data of the target logical register may be performed based on the record of the commit register mapping table in the commit flow of the instruction. It will be appreciated that modifications based on the commit register map may be performed based on the commit flow of the current instruction at the commit unit.
In a further example, when a prediction (speculum) register map is present, the target register map may also include the prediction register map. The prediction register mapping table is a mapping table of a physical register and a logical register of an instruction after being transmitted and renamed in the instruction execution flow. It will be appreciated that by modifying the prediction register mapping table, when a subsequent instruction of the current thread requires reading the data of the target logical register (i.e. dependent on the target logical register), the reading of the data of the target logical register may be performed based on the record of the prediction register.
It should be further noted that the modification based on the prediction register mapping table may be performed on the current instruction commit flow based on the renaming unit. In an alternative example, the processor may include the renaming unit, where the renaming is configured to modify a mapping relationship between a logical register and a physical register in the prediction register mapping table, and specifically may be based on an instruction of the commit unit, where the mapping relationship between the target logical register is modified to be mapped to a preset physical register in the prediction register mapping table.
With continued reference to fig. 5, step S12 is performed: releasing an initial mapping register and a target mapping register corresponding to the target logic register;
the initial mapping register is a physical register mapped by the target logic register before the current instruction is executed, and the target mapping register is a physical register mapped by the target logic register after the current instruction is executed;
with continued reference to fig. 8, taking the register number prn of the initial mapping register of lrn1 as 30 and the register number prn of the target mapping register as 40 as an example, when the instruction result identifier indicates that the value of the target logical register is a preset value, the initial mapping register prn_30 and the target mapping register prn_40 corresponding to the target logical register may be released.
It should be noted that, the step S11 and the step S12 may be performed sequentially or simultaneously, or the step S12 may be performed first and then the step S11 may be performed, which is not limited herein.
In a specific implementation, steps S10 to S12 may be performed in the instruction submission flow. In an alternative example, the commit flow of the instruction may include 3 stages (stages), where stage 1 (i.e., stage 1) may be used to determine whether the commit signal is valid, and if so, stage 2 (i.e., stage 2) is performed, the target logical register is mapped to the target mapped register, and step S10 is performed. Taking the foregoing instruction rid=15, where the register number prn of the initial mapping register of the target logic register lrn1 is 30, and the register number prn of the target mapping register is 40 as an example, stage 2 may write prn 40 in the COMMIT register mapping table entry corresponding to lrn1, and read out the instruction result identifier request_index_prn [15] corresponding to the instruction. After that, stage 3 (i.e. stage 3) is executed, when the instruction result identifier indicates that the value of the target logical register is a preset value, step S11 and step S12 are executed, and the initial mapping register prn 30 and the target mapping register prn 40 of lrn1 are released to a free list (freelist), and at the same time, the prn corresponding to lrn of the prediction (spec) register mapping table and the COMMIT (COMMIT) register mapping table is written into a preset physical register, for example, a zero number prn.
In a further embodiment of the present invention, the source physical register (source prn) of the instruction that depends on the target logical register in the dispatch queue is also modified to a preset physical register to avoid instruction execution errors. Wherein the modification based on the dispatch queue may be performed based on the dispatch unit's commit flow of the current instruction. In an alternative example, the processor may include the scheduling unit for scheduling and arranging instructions to be executed according to a predetermined scheduling algorithm and rule for the purpose of improving processor efficiency and performance.
It should be noted that, when the instruction already in the issue stage is an issued instruction and there is a dependency on the target logic register, the target mapping register is in a state of not being covered by new data based on a time difference between the released and reassigned target mapping registers, so that the issued instruction can be processed based on the data in the target mapping register without instruction processing errors.
In a further example, if the current instruction is cancelled (flush), the instruction result identifier corresponding to the current instruction is initialized, and specifically, the initialization may be zero clearing. Correspondingly, when the instruction result identifier is stored in the identifier register, a bit corresponding to the current instruction in the identifier register can be cleared; or when the instruction result identification stores the item corresponding to the current instruction in the commit queue, the instruction result identification bit of the item corresponding to the current instruction in the commit queue may be cleared.
It can be seen that, in the embodiment of the present invention, when the value of the target logical register is a preset value, the target logical register is mapped to a preset physical register whose value is the preset value, so that the initial mapping register and the target mapping register corresponding to the target logical register can be released at the same time, and further more register resources are provided for other threads. Obviously, the scheme of the embodiment of the invention can more effectively utilize the physical register resource, improve the resource utilization efficiency of the physical register and improve the instruction processing efficiency.
The register release method provided in the embodiment of the present invention may further include a configuration process for identifying an instruction result, and referring to an optional flowchart of another register release method provided in the embodiment of the present invention shown in fig. 9, the configuration process is performed before step S10, and in a specific implementation, the configuration process may be performed in an instruction execution flow, and may include:
step S20: obtaining an instruction result of a current instruction;
specifically, in the instruction execution flow, in the stage of writing back the instruction result after the instruction execution is completed, the instruction result of the current instruction may be obtained.
In an alternative example, in the stage of writing back the instruction result, the instruction result is further written into a target mapping register corresponding to a target logic register.
Step S21: and when the instruction result is a preset value, configuring an instruction result identifier so that the instruction result identifier indicates that the value of the target logic register is the preset value.
When the instruction result is a preset value, based on the target logic register being used for storing the instruction result, the instruction result being the preset value can be understood as that the value stored in the target logic register is the preset value.
In a specific example, when the instruction result is stored in the identification register, a bit corresponding to the current instruction in the identification register may be configured to be a corresponding value, for example, the instruction result may be configured to be identified as a first value, so as to mark the target logic register as a preset value. Taking the current instruction rid=15 as an example, the bit request_queue_invalid_prn [15] corresponding to the instruction in the configuration identification register, specifically, the bit may be configured to be a first value, such as "1".
In an example where the instruction result identification is stored in the commit queue for an item corresponding to a current instruction, then the instruction result identification bit of the item in the commit queue corresponding to the current instruction may be configured to a corresponding value, e.g., the instruction result identification may be configured to be a first value to mark the target logical register as a preset value. Taking the current instruction rid=15 as an example, the instruction result identification bit request_queue_invalid_prn [15] of the entry corresponding to the current instruction in the commit queue is configured, and specifically, the bit may be configured to be a first value, such as "1".
In a further example, when the instruction result is not a preset value, the instruction result identification may be configured to be a second value, e.g., the second value may be "0".
It will be appreciated that this step may be performed based on the execution flow of the current instruction by the execution unit.
The execution unit is used for executing the processes from the step S20 to the step S21, so that the configuration of the instruction result identification is realized.
The embodiment of the present invention further provides a processor, the structure of which can refer to the architecture schematic diagram of the processor provided in the embodiment of the present invention shown in fig. 10, where the processor at least includes:
the submitting unit is used for determining an instruction result identifier corresponding to a target logic register in the current instruction, wherein the target logic register is used for storing the instruction result of the current instruction; when the instruction result identifier indicates that the value of the target logic register is a preset value, mapping the target logic register to a preset physical register; wherein the value of the preset physical register is the preset value; releasing an initial mapping register and a target mapping register corresponding to the target logic register, wherein the initial mapping register is a physical register mapped by the target logic register before the current instruction is executed, and the target mapping register is a physical register mapped by the target logic register after the current instruction is executed;
and the physical register file is used for providing physical registers as an initial mapping register, a target mapping register and a preset physical register.
In an alternative example, the preset physical register may be a register with a preset position selected from physical registers, or may be a specific register provided in another unit or module, which is not specifically limited herein.
In some embodiments, the processor further comprises a renaming unit configured to modify, in the prediction register mapping table, the mapping relationship of the target logical register to map to a preset physical register based on the indication of the commit unit when the target register mapping table includes the prediction register mapping table.
In some embodiments, the commit unit is further configured to obtain an instruction result of the current instruction; and when the instruction result is a preset value, configuring an instruction result identifier so that the instruction result identifier indicates that the value of the target logic register is the preset value.
In some embodiments, the processor further comprises a scheduling unit for modifying a source physical register of an instruction in the scheduling queue that depends on the target logical register to a preset physical register when the instruction result identification indicates that the value of the target logical register is a preset value.
The embodiment of the invention also provides a chip which can comprise the processor. The function of the hardware devices in the processor may be as described in the corresponding parts above.
The embodiment of the invention also provides electronic equipment which can comprise the chip; the electronic device may be a terminal device or a cloud server device.
The foregoing describes several embodiments of the present invention, and the various alternatives presented by the various embodiments may be combined, cross-referenced, with each other without conflict, extending beyond what is possible embodiments, all of which are considered to be embodiments of the present invention disclosed and disclosed.
Although the embodiments of the present invention are disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (19)
1. A register release method, comprising:
determining an instruction result identifier corresponding to a target logic register in a current instruction, wherein the target logic register is used for storing an instruction result of the current instruction;
when the instruction result identification indicates that the value of the target logical register is a preset value,
mapping the target logic register to a preset physical register; wherein the value of the preset physical register is the preset value;
releasing an initial mapping register and a target mapping register corresponding to the target logic register, wherein the initial mapping register is a physical register mapped by the target logic register before the current instruction is executed, and the target mapping register is a physical register mapped by the target logic register after the current instruction is executed.
2. The method for releasing a register according to claim 1, wherein determining an instruction result identifier corresponding to a target logical register in a current instruction includes:
reading the value of the bit corresponding to the current instruction in the identification register;
or,
and reading the value of the instruction result identification bit of the item corresponding to the current instruction in the submission queue.
3. The method according to claim 1, wherein the mapping of the target logical register to a predetermined physical register is performed by modifying a mapping relation of the target logical register to a predetermined physical register in a target register mapping table.
4. A method of releasing registers as claimed in claim 3, wherein the target register map comprises a commit register map, the commit register map being a map of physical and logical registers used for a commit flow after execution of the instruction.
5. The method of claim 4, wherein the target register map further comprises a prediction register map, the prediction register map being a map of physical and logical registers of the instruction after the instruction has been launched and renamed in the instruction execution flow.
6. The method for releasing a register according to claim 1, wherein before determining the instruction result identifier corresponding to the target logical register in the current instruction, the method further comprises:
obtaining an instruction result of a current instruction;
and when the instruction result is a preset value, configuring an instruction result identifier so that the instruction result identifier indicates that the value of the target logic register is the preset value.
7. The method according to claim 6, wherein when the instruction result is a preset value, the instruction result identifier is configured, specifically, the instruction result identifier is configured to be a first value;
and when the instruction result is not a preset value, configuring the instruction result identification as a second value.
8. The method of claim 7, wherein configuring the instruction result identification to be a first value when the instruction result is a preset value, comprises:
configuring a bit in an identification register corresponding to the current instruction as a first value;
or,
and configuring an instruction result identification bit of an item corresponding to the current instruction in the submission queue to be a first value.
9. The method according to claim 6, wherein after the instruction result of the current instruction is obtained, further comprising:
and writing the instruction result into a target mapping register corresponding to the target logic register.
10. The register release method according to claim 1, wherein when the instruction result identification indicates that the value of the target logical register is a preset value, further comprising:
and modifying a source physical register of the instruction which depends on the target logical register in the scheduling queue into a preset physical register.
11. The register release method according to claim 1, wherein when the instruction result identification indicates that the value of the target logical register is a preset value, further comprising:
when there is a dependency on the target logical register for an issued instruction that is already in the issue stage, processing is based on the data in the target map register.
12. The register release method according to claim 1, further comprising: if the current instruction is cancelled, initializing an instruction result identifier corresponding to the current instruction.
13. The register release method according to claim 12, wherein initializing an instruction result identification corresponding to the current instruction comprises:
when the instruction result identification is stored in the identification register, resetting a bit corresponding to the current instruction in the identification register;
or,
and when the instruction result identification stores the item corresponding to the current instruction in the commit queue, resetting the instruction result identification bit of the item corresponding to the current instruction in the commit queue.
14. A processor, comprising:
the submitting unit is used for determining an instruction result identifier corresponding to a target logic register in the current instruction, wherein the target logic register is used for storing the instruction result of the current instruction; when the instruction result identifier indicates that the value of the target logic register is a preset value, mapping the target logic register to a preset physical register; wherein the value of the preset physical register is the preset value; releasing an initial mapping register and a target mapping register corresponding to the target logic register, wherein the initial mapping register is a physical register mapped by the target logic register before the current instruction is executed, and the target mapping register is a physical register mapped by the target logic register after the current instruction is executed;
and the physical register file is used for providing physical registers as an initial mapping register, a target mapping register and a preset physical register.
15. The processor of claim 14, further comprising a renaming unit to modify a mapping relationship of the target logical register to map to the preset physical register in a prediction register map based on an indication of a commit unit when the target register map includes the prediction register map.
16. The processor of claim 15, wherein the commit unit is further configured to obtain an instruction result of a current instruction; and when the instruction result is a preset value, configuring an instruction result identifier so that the instruction result identifier indicates that the value of the target logic register is the preset value.
17. The processor of claim 14, further comprising a dispatch unit to modify a source physical register of an instruction in a dispatch queue that depends on a target logical register to a preset physical register when the instruction result identification indicates that the value of the target logical register is a preset value.
18. A chip comprising a processor as claimed in any one of claims 14 to 17.
19. An electronic device comprising the chip of claim 18.
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