CN117517932A - Inter-chip TSV test circuit and test method - Google Patents
Inter-chip TSV test circuit and test method Download PDFInfo
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Abstract
The invention belongs to the field of design testability of very large scale integrated circuits, and discloses a TSV test circuit and a test method between core particles, wherein a test path, a test instruction and a read-write data register are configured through a core particle test configuration circuit; receiving test vectors and capturing test responses through the read-write data register set; the method comprises the steps of controlling the initializing, testing and capturing operations of TSV testing through a TSV array testing control circuit; selecting a row to be tested in the TSV array through an address decoding circuit; generating a test vector required for testing the TSV through a test vector generating circuit; judging whether the test TSV has faults or not through a comparison circuit; and controlling the transmission of the test vector on the TSVs and the reception of the test response through the TSV receiving array and the TSV transmitting array. The test circuit provided by the invention meets the test requirement of TSV among the core particles, reduces the occupation of hardware area, is highly automated in the test process, and reduces the core particle test cost.
Description
Technical Field
The invention belongs to the field of design for testability of very large scale integrated circuits, and particularly relates to a TSV test circuit and a test method between core particles.
Background
The chip (chip) technology integrates a plurality of chips into one package through an interconnection technology such as an internal TSV, etc., forming a dedicated functional chip. The application of the core particle technology avoids the problem of overlong connecting wires, realizes high-performance on-chip interconnection, reduces power consumption and has better performance.
In 3D chip, the stacked cores are connected by through silicon vias (Through Silicon Via, TSV). In the manufacturing and bonding stage of the TSVs, various types of failures may be caused by the improper or insufficient filling of the TSVs, micro voids on the TSVs and large voids at the bottom, misaligned bumps, etc. While some failures may be identified at the pre-bond stage, not all TSV failures may be detected by the pre-bond test. Furthermore, new defects are introduced during the core stacking process, so that the post-bond TSV test must be performed. However, the conventional DFT test method cannot test for delay faults at the post-binding stage because the interval between data capture and data update states in the standard test access controller exceeds one test clock period and the test clock rate is low, so that the boundary scan test technique based on the IEEE 1149 series is insufficient for detecting faults such as small delays of high-speed interconnection lines between core particles, and the conventional test method is insufficient for meeting the requirements of rapidity, accuracy and automation. Furthermore, the method of providing each TSV with a packing register or BIST occupies a large area, and the production cost is increased drastically.
There are also studies in the prior art on this, but the ideal effect is still not achieved; as in patent application TW201101316a, a method for testing TSVs based on BIST circuit is proposed, which can realize test access to the TSVs after 3D stacking, but because a test circuit needs to be added to each TSV to be tested, the area is too large; secondly, because the scheme tests all TSVs in a layer at the same time, if the test response of each TSV is not shifted out, fault location cannot be realized, but shifting out all responses causes time cost to increase; finally, this solution only provides a way to BIST the circuit of the TSVs, and how the BIST circuit is implemented in particular is not described.
Disclosure of Invention
In order to solve the technical problems, the invention provides the inter-core TSV test circuit and the test method, which can detect connectivity, delay and the like, and have the advantages of more efficient test process, shorter test time and higher test coverage rate; the embedded TSV array test control circuit has the advantages that the test process is highly automated, the dependence on a test machine is greatly reduced, and the core particle test cost is reduced.
The invention discloses a TSV test circuit among core particles, which comprises a core particle test configuration circuit, a read-write data register set, a TSV array test control circuit, an address decoding circuit, a test vector generation circuit, a comparison circuit, a TSV receiving array and a TSV transmitting array;
the core particle test configuration circuit is connected with the test ports of the adjacent core particles and is used for configuring a test path, a test instruction and a read-write data register;
the read-write data register set is used for receiving a test vector and a capture test response from an external port and activating the TSV array test control circuit;
the TSV array test control circuit controls the address decoding circuit to select TSVs to be tested row by row under the action of the functional clock func_clk, and controls the initializing, testing and capturing operation of the TSV test;
the test vector generation circuit is used for automatically generating a test vector required by TSV test;
the TSV receiving array and the TSV transmitting array are used for controlling the transmission and the reception of the test vector on the TSVs;
the comparison circuit is used for judging the test result, capturing the test response by the read-write data register set and transmitting the test response out for observation.
Further, the read-write data register set consists of n-bit test data register sets with shifting, capturing and updating functions;
the test data input end tdi of the lowest-order test data register set is connected with an external test data input port, the functional input end pi is connected with the output port tsv_fail of the comparison circuit, the test data input ends and the functional input ends of the rest-order test data register set are connected with the adjacent low-order test data output end tdi_ rwr, and the highest-order test data output port tdo_ rwr is used as the output port of the read-write data register set;
the output ports of the register Ureg responsible for updating function in the test data register set are respectively used as the output ports from low order to high order of the read-write data register set, from the 0-n-1; when seed [ n-1:0] =n' b1, output port rwr _en=1;
the clock input end of a register SCreg of the n-bit test data register group, which is responsible for shifting and capturing functions, is connected with the output end of mux4, the data selection input end of mux4 is an input port cnt_active, the 0 input end is an input port tck, the 1 input end is the output end of AND gate and1, the input end of AND gate and1 is an input port test_end, and the other input end is an input port func_clk; the clock input ends of Ureg are connected with the output end of a NOT1, and the input end of NOT1 is a t input port tck.
The SCreg of the read-write data register group moves into the test vector or moves out of the test response when the shift enabling signal is valid (rwr _se=1), the lowest bit captures the 1-bit test response from the comparison circuit when the capture enabling signal is valid (rwr _ce=1), the rest bits capture the test response stored by the adjacent low bits, and the Urreg stores the test vector when the update enabling signal is valid (rwr _ue=1), so that the test vector is ensured not to change during the capturing stage. When the output signal cnt_active=0 of the TSV array data control circuit, the clock end of the SCreg is controlled by the external test signal tck, and when cnt_active=1, the clock input end of the SCreg is the functional clock func_clk and the output signal test_end phase of the TSV array data control circuit, that is, when the TSV array data control circuit is in an active state, a clock pulse is driven into the SCreg at the last clock of the row TSV test for capturing the test response. The output end of Ureg is the initial test vector seed [ n-1:0] of the test vector generating circuit, which is used for activating the test vector generating circuit, the valid test data n' b1 is updated to the Ureg register set, and the output enable signal rwr _ready=1.
Further, the TSV array test control circuit includes three input ports func_clk, rwr_ready, and tlr, five output ports com_rstn, test_begin, test_active, test_end, cnt_active, and a length of 2 n A counter of +1 bits; the reset end of the counter is an input port tlr, the clock input ends are func_clk and rwr _ready phase, namely when rwr _ready=1, the counter starts counting under the action of the functional clock func_clk, and the output cnt [ n: 0]]For the count value, the output port cnt_active is set to (2 after the start of the count n +1) x n-1 clocks are 1, otherwise are 0.
The TSV array test control circuit divides TSV testing into three stages, wherein the first stage is a test initialization stage, and in a first counting period, namely a cnt=6' b0 stage, an output port comrst_n=0, a reset end of the comparison circuit is effective at the moment, and a value of the comparison circuit is cleared; the output port test_begin=1, and at this time, the test vector generation circuit selects the seed value of the read-write register set to be input in parallel for initializing the test vector generation circuit. When cnt is in the second to last counting period, the output port active_test=1 is the TSV test stage, and the TSV receiving array and the TSV transmitting array are in a test mode. When cnt is in the last count period, for the test capture phase, output port test_end=1, write register set captures test response and address decode circuit selects the next row of TSVs for the next timeAnd (5) testing. Since the TSV array is an n×n matrix, when cnt is performed n times 2 n The counting is ended after the timing of +1 bits and the last capture is done by the core test configuration circuit, so only work is required (2 n +1) ×n-1 cycles, cnt_active=1 is used to flag the counter operating state.
Further, the address decoding circuit is formed by an n-bit shift counter, a clock input port of the shift counter is connected with an output end of the AND gate and2, one input end of the shift counter is connected with an input port test_end, the other input end of the shift counter is connected with an input port func_clk, namely, a clock pulse is driven in a test capturing period of the TSV array test control circuit, and an effective value 1 is shifted one bit to be higher so as to start the next test; the input end of the NOT2 is an input port cnt_active, and the output port is connected with the input end of the AND gate 3; the other input end of the AND gate and3 is an input port rwr _en, and the output end is connected to the end 1 at the lowest position of the shift counter; one input end of the OR gate 1 is connected to the output end of the AND gate 3, the other input end of the OR gate is connected to the output end of the NOT gate 3, and the output end of the OR gate is connected to the clear 0 end of a register of the high n-1 bits of the shift counter; the input end of the NOT3 is an input port rwr _en, and the output end is connected to the clear 0 end of the lowest bit of the shift counter; the output port is addr [ n-1:0]; the valid address output value is one and only one bit is 1, and when addr [ t ] =1, the t-th row TSV open test is selected.
The address decoding circuit can be divided into three working states, namely, a TSV test mode is not selected, namely rwr _en=0, at the moment, n register clear 0 ends of the shift counter are all valid, the address decoding circuit outputs all 0, and the TSV is in a normal working state; secondly, a TSV test mode is selected but TSV test is not performed, namely rwr _en=1 and cnt_active=0, the seed value is not transmitted to the read-write register set, the TSV array control circuit does not start to work, at the moment, the 1 end of the lowest position is effective, the zero clearing ends of the rest bits are effective, the output of the address decoding circuit is n' b1, and the address bit selects the first row of TSVs to be ready to enter a test state; thirdly, in the TSV test stage, namely rwr _en=1 and cnt_active=1, the set ends of n registers of the shift counter are invalid, the shift counter starts to work, after one row of TSVs are tested, one pulse is driven into the clock end of the register in the test capturing period, the effective value 1 moves right, and the TSVs in the next row are selected to be ready to enter a test state.
Further, the TSV receiving array is composed of n×n receiving TSVs, and comprises n (n+1) AND gates and n OR gates, and the input ports are addr [ n-1:0] from the address decoding circuit]Testpattern [ n-1:0] of test vector generation circuit]TSV array test control circuit test_active and input value TSV [ n ] from other core grains 2 -1:0]The output port is sendTSV [ n-1:0]]And a reveiveTSV [ n-1:0]]；
In the TSV receiving array, each receiving TSV decodes a bit addrn phase with an address corresponding to the ith row, 0< i <6 rows, and is used for shielding the value received by the TSVs of the non-test row, and the output value phase of the AND gate of each row is used as the output port receiver TSV [ j ] of the jth row, 0< j <6 rows, so that the output port receiver TSV [ n-1:0] represents the value received by the TSVs of the tested row; the input value of testpattern [ n-1:0] is respectively expressed in test_active phase and serves as output port sendTSV [ n-1:0] to represent the test data value of each column; the values of the receiver TSV [ n-1:0] and the testpattern [ n-1:0] are transmitted into a comparison circuit to judge whether faults exist.
Further, the TSV transmission array is composed of n×n transmission TSVs, and includes n 2 Two data selectors and n AND gates, the input port is addr [ n-1:0] from the address decoding circuit]Testpattern [ n-1:0] of test vector generation circuit]And a TSV array test control circuit test_active, wherein an output port is an output value TSV0[ n ] transmitted to other core grains 2 -1:0]；
In the TSV transmitting array, each function output value connected with other core grains is connected to the 0 input end of the alternative data selector, the 1 input end is connected with the AND value of the testpattern and the test_active corresponding to the column where the TSV is located, the selection input end is connected with the address decoding bit of the row where the TSV is located, and the output end is used as the output port TSV [ n ] 2 -1:]The method comprises the steps of carrying out a first treatment on the surface of the Therefore, in the normal working mode, the value of the input TSV is the output of the original functional circuit, and in the test mode, the test vector value is output from the row to be tested to the TSV to start the test.
Further, the comparison circuit comprises n-level comparison units and n-1 OR gates; the comparison unit comprises an exclusive or gate xor1, an exclusive or gate or2 and a D trigger reg1, wherein input ports are sendTSV, receiveTSV, func _clk and com_rstn, and output ports are TSV_fail; the input end of the exclusive or gate xor1 is an input port sendTSV and a receiver tsv, and the output end is connected to the input end of the exclusive or gate xor 2; the other input end of the OR gate 2 is connected with the output end of the D trigger reg1, and the output end is connected with the D input end of the D trigger reg 1; the clock input end of the D trigger reg1 is an input port func_clk, the zero clearing end is an input port com_rstn, and the output end is an output port TSV_fail;
the sendTSV ports and the receiver TSV ports of the n-level comparison unit are respectively connected with sendTSV [ n-1:0] and receiver TSV [ n-1:0] from the TSV output array from low order to high order, and the func_clk and the com_rstn are respectively connected with the input ports func_clk and the com_rstn; the high-order output ports of the comparison unit are connected with the OR values of all low-order output ends of the comparison unit through n-1 OR gates, and the OR values are used as the output ports TSV_fail of the comparison circuit;
the comparison circuit is responsible for judging whether a fault exists in the currently tested row TSVs, if so, the output end TSV_fail=1, otherwise, the TSV_fail=0. Under the output port com_rstn of the array control circuit, clearing 0 all D triggers in the TSV test initialization stage; in the TSV test stage, the sending value and the receiving value of each TSV in the test row are transmitted into a corresponding comparison unit, the value sendTS V before transmission and the value receiveTSV after the TSV transmission are compared through an exclusive OR gate and stored into a D trigger, if the value sendTS V is different from the value of the receiveTSV, the TSV is indicated to have faults, otherwise, the value does not exist, and finally, the output value is the value of each comparison unit, and the value indicates whether the row has faults or not.
The inter-chip TSV testing method based on the test circuit comprises the following steps:
step 1, resetting a test circuit;
step 2, configuring a test path, and opening the test paths of two core particles connected with the TSV to be tested;
step 3, configuring a test instruction and selecting a TSV test mode;
step 4, configuring a read-write register, and transmitting the required seed into the read-write register group through a tdi port and keeping the read-write register unchanged;
step 5, initializing TSV test, comparing the 0 of the circuit, and driving an initial value into a test vector generating circuit;
step 6, TSV test, wherein a test vector generation circuit generates a pseudo-random sequence to enter a TSV array test, and a comparison circuit judges whether the test is passed or not;
step 7, judging whether the current test line is an nth line, if not, entering step 8, and if yes, entering step 9;
step 8, capturing test response under the TSV array test control circuit, updating the test decoding circuit, and returning to the step 5;
step 9, capturing test response under the control of a core particle test configuration circuit;
and step 10, shifting out the test response and observing.
The beneficial effects of the invention are as follows: the inter-core TSV test circuit can test TSV connectivity, delay and the like under a functional clock, solves the problem that delay faults are caused by the fact that a low-speed test clock cannot cover tiny defects, is more efficient in test process, shorter in test time and higher in test coverage rate, and improves test efficiency and production efficiency; because the TSV array method is adopted for testing, each TSV does not need to be inserted into a test vector generation unit and a test comparison unit, different rows of TSVs multiplex the same group of test circuits, the test circuits are more compact in design and high in integration, the integration reduces the occupation of circuit areas, the cost is reduced, and meanwhile, the requirements of a core particle system and a high-performance computing system which are integrated on a large scale are met better; the outermost part of the test circuit is controlled by only 5 JTAG ports, a new test port is not required to be added, a standardized test scheme is provided, and the problem that core grains from different manufacturers are difficult to test, control and access is solved; because the TSV array test control circuit is embedded, the test process is highly automated, and because the test is carried out independent of external test vectors, the dependence on a test machine is greatly reduced, and the core particle test cost is reduced.
Drawings
FIG. 1 is a schematic diagram of a TSV test circuit between die according to the present invention;
FIG. 2 is a schematic diagram showing the detailed structure of the read-write data register according to the present invention;
fig. 3 is a schematic diagram of a TSV array test control circuit according to the present invention;
FIG. 4 is a timing diagram of the output signals of the TSV array test control circuit according to the present invention;
FIG. 5 is a schematic diagram showing a detailed structure of an address decoding circuit according to the present invention;
FIG. 6 is a schematic diagram showing the detailed structure of the test vector generation circuit according to the present invention;
fig. 7 is a schematic diagram of a detailed structure of a TSV transmission array according to the present invention;
fig. 8 is a schematic diagram of a detailed structure of a TSV receiving array according to the present invention;
FIG. 9 is a detailed schematic diagram of the comparison circuit according to the present invention;
FIG. 10 is a schematic diagram of an inter-die TSV test circuit according to an embodiment of the present invention;
FIG. 11 is a test flow diagram of an embodiment of an inter-die TSV test circuit according to the present invention;
fig. 12 is a simulation waveform diagram of an embodiment of a TSV test circuit between die according to the present invention.
Detailed Description
In order that the invention may be more readily understood, a more particular description of the invention will be rendered by reference to specific embodiments that are illustrated in the appended drawings.
The overall structure of the inter-chip TSV test circuit is shown in figure 1, and the inter-chip TSV test circuit is composed of a chip test configuration circuit, a read-write data register set, a TSV array test control circuit, an address decoding circuit, a test vector generation circuit, a comparison circuit, a TSV receiving array and a TSV transmitting array. The core particle test configuration circuit is connected with the test ports of the adjacent core particles and is used for configuring a test path, a test instruction and a configuration data register, when TSV test is carried out, the test paths of the two core particles connected by the TSV are required to be opened firstly, then the configuration instruction register is in a TSV test mode, at the moment, rwr _en=1, and the read-write data register is placed between tdi and tdo of the core particle universal controller so as to realize selective access to the read-write data register, so that the TSV test is started.
The read-write data register is shown in fig. 2, the update register Ureg is cleared 0 first under the action of the reset signal tlr of the core test configuration circuit, and rwr _se, rwr_ce and rwr _ue will be set to 1 when the data register is shifted, captured and updated respectively after the TSV test mode is selected. Under the action of rwr _se, the shift/capture register SCreg shifts in external test data from the tdi port on the rising edge of tck; then under the action of rwr _ue, the test data in the SCreg is updated to Ureg at the falling edge of tck, the output port seed [4:0] of the Ureg is used as an initial value for activating the test vector generation circuit, and rwr _ready=1 is used for marking that the initial value of the read-write data register is ready after the correct initial value 00001 is updated; when the TSV array test control circuit is effective (cnt_active=1), when the TSV array test control circuit is in a test capturing stage (test_end=1), SCreg0 captures a test response from a pi port at the rising edge of a functional clock func_clk, in actual circuit connection, the pi terminal is connected with an output port tsv_fail of a comparison circuit, SCreg1/2/3/4 captures the value of the previous bit, and after capturing four times, SCreg0/1/2/3 is the test result of the 4/3/2/1 row respectively; when the TSV testing stage is finished, under the action of rwr _ce, performing primary test response capture, wherein SCreg0/1/2/3/4 is the test result of 5/4/3/2/1 rows respectively; finally, under the action of rwr _se, the five-bit output result is passed from the tdo_ rwr port to the core test configuration circuit and the observations are output.
As shown in fig. 3, the TSV array test control circuit first clears the counter to 0 under the action of the reset signal tlr of the core test configuration circuit, and prepares to start counting. When the initial value for activating the test vector generation circuit is already input into the read-write data register set, the output value rwr _ready=1 of the read-write data register, the modulo 33 counter of the TSV array test control circuit starts counting under the effect of the falling edge of the functional clock func_clk, which divides the TSV test into three phases, the 1 st counting period is a test initialization phase, the 2 nd to 32 nd counting periods are TSV test phases, and the 33 rd counting period is a test capture phase.
The output signal state of the TSV array test control circuit is shown in fig. 4, the com_n is connected with the clear 0 end of the comparison circuit, the test_begin is connected with the test vector generation circuit, the active_test is connected with the TSV sending array and the TSV output array, and the test_end and the cnt_active are connected with the read-write data register set and the address decoding circuit. In the test initialization stage, the value of the output port com_n=0 controls the comparison circuit to be cleared, and the output port test_begin=1 controls the test vector generation circuit to select the seed [4:0] value of the read-write register group to be input in parallel so as to activate the linear feedback shift register; in the TSV test stage, an output port active_test=1, a TSV sending array transmits a test vector generated by a test generating circuit into TSVs, and a TSV receiving array receives values of test rows and transmits the values into a comparison circuit; in the test capture phase, the output port test_end=1, the write register set captures the test response and the address decoding circuit selects the next row of TSVs for the next test. Since the core test configuration circuit must enter the capture state before entering the shift state, the fifth test capture is performed under the action of the core test configuration circuit, cnt_active holds 5×33-1 high levels for controlling the read-write data register set to perform only 4 capture operations under func_clk.
The address decoding circuit is shown in fig. 5, and is composed of a 5-stage linear feedback shift register, the clear 0 end and the set 1 end are respectively composed of an output port rwr _en of the core particle test configuration circuit and output ports cnt_active and test_end of the TSV test array control circuit, and an output port addr [4:0] is transmitted into the TSV transmitting array and the TSV receiving array to select test rows. When the TSV test mode is not selected (rwr _en=0), the zero clearing end of the five-stage register is effective, addr [4:0] =00000, and the TSV is in a normal working state; when the TSV test mode has been selected but the TSV test has not been performed (rwr _en=1 and cnt_active=0), addr [4:0] =00001, selecting the first row of TSVs to be ready to enter the test state; when the TSVs are tested (rwr _en=1 and cnt_active=1), in the test capturing stage of the TSV array test control circuit, the five-stage register clock terminal is driven with a pulse, the effective value 1 is shifted to the right, and the next row of TSVs is selected to be ready to enter the test state.
The test vector generation circuit is shown in fig. 6, in the test initialization stage of the TSV array test control circuit, the output value seed [4:0] of the read-write data register is parallel transferred into the register in the test vector generation circuit, then under the action of func_clk, the test vector testpattern [4:0] with 31 different bits is output, the incoming TSV transmission array is used for being transmitted to the adjacent core particle, and the TSV receiving array is used as the receiver TSV [4:0] to be transferred into the comparison circuit to judge whether a fault exists.
The TSV transmission array is shown in FIG. 7, and when TSVs are not tested, the output ports TSVs [24:0] are output as functional circuit values; when the TSV is tested, in the TSV test stage of the TSV array test control circuit, the port, connected with the test row TSV selected by the address decoding circuit, outputs the test vector generated by the test vector generating circuit.
The TSV receiving array is shown in fig. 8, and during TSV test, a test response is output to the comparison circuit from the output port receiveTSV [4:0], and the values received by the row TSVs selected by the address decoding circuit and transmitted by the TSV transmitting array of adjacent core grains are transmitted to the comparison circuit from the output port sendTSV [4:0 ].
The comparison circuit, as shown in fig. 9, clears 0 under the action of com_rstn in the test initialization stage of the TSV array test control circuit, clears the result of the previous test, and then compares the values of each bit of the receiveTSV [4:0] and sendTSV [4:0] from the TSV receiving array under the action of func_clk, if each bit is the same, the output port tsv_fail=0 indicates that the row of TSVs has no fault, and if one or more bits are different, the output port tsv_fail=1 indicates that the modified row of TSVs has fault.
Fig. 10 is a schematic diagram of an embodiment of an inter-core TSV test circuit according to the present invention, where the chip system includes core 0, core 1, and core 2, all three cores are inserted into the test circuit, and the test circuit transmits test data with neighboring cores through 5 JTAG ports, and the TSV transmitting array is connected with the TSV receiving array of the neighboring cores through TSVs.
Testing of TSV after binding of core 0 and core 1 according to the test flow diagram shown in FIG. 11:
step 1, resetting a test circuit, wherein trst=0;
step 2, configuring a test path, namely a test path from the core particle 0 to the core particle 1;
step 3, configuring a test instruction and selecting a TSV test mode;
step 4, configuring a read-write register, and transmitting 10000 into the read-write register group through a tdi port and updating the 10000 to Ureg;
step 5, initializing TSV test, clearing 0 by a comparison circuit, and driving seed [4:0] of the read-write data register set into a test vector generation circuit;
step 6, TSV test, wherein a test vector generation circuit generates a pseudo-random sequence to enter a TSV array test, and a comparison circuit judges whether the test is passed or not;
step 7, judging whether the current test line is 5, if not, entering step 8, and if yes, entering step 9;
step 8, capturing test response under the TSV array test control circuit, updating a test decoding circuit, and jumping to the step 5;
step 9, capturing test response under the control of a core particle test configuration circuit;
and step 10, shifting out the test response and observing.
FIG. 12 is a simulated waveform diagram of the TSV test between core 0 and core 1 of FIG. 11, with box (1) being step 1, the test circuit being reset; the frame (2) configures a test path for the step (2), and opens a test interface from the core particle 0 to the core particle 1; the frame (3) is used for configuring a test instruction, and the core particle 0 and the core particle 1 are in a TSV test mode; the frame (4) is used for configuring a read-write data register set, and shifting 5' b00001 into the core grain 0 and the core grain 1; the box (5) is a TSV test under the TSV array test control circuit, and the addr can be observed to be 5' b00001, 5' b00010, 5' b00100, 5' b01000, and 5' b10000 in sequence, different rows are tested in sequence, the last capturing operation of each row of TSV test except the last row is performed, and one sa0 fault exists in the second row test; block (6) is performing a capture operation under the die test configuration circuit; block (7) shifts the test response out of view, finding the test response to be 000001000, and locating the faulty row.
The foregoing is merely a preferred embodiment of the present invention, and is not intended to limit the present invention, and all equivalent variations using the description and drawings of the present invention are within the scope of the present invention. .
Claims (8)
1. The inter-chip TSV test circuit is characterized by comprising a core test configuration circuit, a read-write data register set, a TSV array test control circuit, an address decoding circuit, a test vector generation circuit, a comparison circuit, a TSV receiving array and a TSV transmitting array;
the core particle test configuration circuit is responsible for configuration of a core particle test channel and selection of a test mode;
the read-write data register set is used for receiving a test vector from an external port, activating a TSV array test control circuit, capturing a test response and outputting observation;
the TSV array test control circuit controls the address decoding circuit to select TSVs row by row for testing under the action of the functional clock func_clk, and controls the test initialization, test and capture operation of the TSVs;
the test vector generation circuit is used for automatically generating a test vector required by TSV test;
the TSV transmitting array and the TSV receiving array are respectively used for controlling the transmission of the test vector from the TSV transmitting end and the receiving of the test response at the TSV receiving end;
the comparison circuit is used for judging the test result.
2. The inter-die TSV test circuit according to claim 1 wherein said read-write data register set is composed of n-bit test data register sets having shift, capture, update functions;
the test data input end tdi of the lowest-order test data register set is connected with an external test data input port, the functional input end pi is connected with the output port tsv_fail of the comparison circuit, the test data input ends and the functional input ends of the rest-order test data register set are connected with the adjacent low-order test data output end tdi_ rwr, and the highest-order test data output port tdo_ rwr is used as the test data output port of the read-write data register set;
the output ports of the register Ureg responsible for updating function in the test data register set are respectively used as the output ports from low order to high order of the read-write data register set, from the 0-n-1; when seed [ n-1:0] =n 'b'1, output port rwr _en=1;
the clock input end of a register SCreg of the n-bit test data register group responsible for shifting and capturing functions is connected with the output end of mux4, the data selection input end of mux4 is an input port cnt_active, the 0 input end is an input port tck, the 1 input end is the output end of AND gate and1, the input end of AND gate and1 is an input port test_end, and the other input end is an input port func_clk; the clock inputs of Ureg are all connected to the output of NAND gate not1, the input of not1 being input port tck.
3. The inter-die TSV test circuit according to claim 1, wherein the TSV array test control circuit includes three input ports func_clk, rwr_ready, tlr, five output ports com_rstn, test_begin, test_active, test_end, cnt_active, and length 2 n A counter of +1 bits; the reset end of the counter is an input port tlr, the clock input ends are func_clk and rwr _ready phase, namely when rwr _ready=1, the counter starts counting under the function of the functional clock func_clk, and then the cnt [ n: 0] is output]For the count value, the output port cnt_active is set to (2 after the start of the count n +1) 1 for n-1 clocks, otherwise 0.
4. The inter-die TSV test circuit according to claim 1 wherein the address decode circuit is composed of an n-bit shift counter with a clock input port connected to the output of the and gate and2 and with an input port of and2 connected to the input port test_end and the other to the input port func_clk; the input end of the NOT2 is an input port cnt_active, and the output port is connected with the input end of the AND gate 3; the other input end of the AND gate and3 is an input port rwr _en, and the output end is connected to the end 1 at the lowest position of the shift counter; one input end of the OR gate 1 is connected to the output end of the AND gate 3, the other input end of the OR gate is connected to the output end of the NOT gate 3, and the output end of the OR gate is connected to the clear 0 end of a register of the high n-1 bits of the shift counter; the input end of the NOT3 is an input port rwr _en, and the output end is connected to the clear 0 end of the lowest bit of the shift counter; the output port is addr [ n-1:0]; when addr [ i ] =1, then the ith row TSV open test is selected.
5. The inter-die TSV test circuit according to claim 1 wherein the TSV receiving array is composed of n×n receiving TSVs including n (n+1) and n or gates with input ports addr [ n-1:0] from the address decoding circuit]Testpattern [ n-1:0] of test vector generation circuit]TSV array test control circuit test_active and input value TSV [ n ] from other core grains 2 -1:0]The output port is sendTSV [ n-1:0]]And a reveiveTSV [ n-1:0]]；
In the TSV receiving array, each receiving TSV decodes a bit addrn phase with an address corresponding to the ith row, 0< i <6 rows, and is used for shielding the value received by the TSVs of the non-test row, and the output value phase of the AND gate of each row is used as the output port receiver TSV [ j ] of the jth row, 0< j <6 rows, so that the output port receiver TSV [ n-1:0] represents the value received by the TSVs of the tested row; the input value of testpattern [ n-1:0] is respectively expressed in test_active phase and serves as output port sendTSV [ n-1:0] to represent the test data value of each column; the values of the receiver TSV [ n-1:0] and the testpattern [ n-1:0] are transmitted into a comparison circuit to judge whether faults exist.
6. The inter-die TSV test circuit according to claim 1 wherein said TSV transmit array is composed of n×n transmit TSVs, including n 2 Two data selectors and n AND gates, the input port is addr [ n-1:0] from the address decoding circuit]Testpattern [ n-1:0] of test vector generation circuit]And a TSV array test control circuit test_active, wherein an output port is an output value TSV [ n ] transmitted to other core grains 2 -1:0]；
In the TSV transmitting array, each function output value connected with other core grains is connected with the 0 input end of a data selector, the 1 input end is connected with the AND value of the testpattern and the test_active corresponding to the column where the TSV is located, and the selection input end is connected with the address solution of the row where the TSV is locatedCode bit, output end as output port TSV [ n ] 2 -1:0]The method comprises the steps of carrying out a first treatment on the surface of the Therefore, in the normal working mode, the value of the input TSV is the output of the original functional circuit, and in the test mode, the test vector value is output from the row to be tested to the TSV to start the test.
7. The inter-die TSV test circuit according to claim 1 wherein said comparison circuit includes n-level comparison units and n-1 or gates; the comparison unit comprises an exclusive or gate xor1, an exclusive or gate or2 and a D trigger reg1, wherein input ports are sendTSV, receiveTSV, func _clk and com_rstn, and output ports are TSV_fail; the input end of the exclusive or gate xor1 is an input port sendTSV and a receiver tsv, and the output end is connected to the input end of the exclusive or gate xor 2; the other input end of the OR gate 2 is connected with the output end of the D trigger reg1, and the output end is connected with the D input end of the D trigger reg 1; the clock input end of the D trigger reg1 is an input port func_clk, the zero clearing end is an input port com_rstn, and the output end is an output port TSV_fail;
the sendTSV ports and the receiver TSV ports of the n-level comparison unit are respectively connected with sendTSV [ n-1:0] and receiver TSV [ n-1:0] from the TSV output array from low order to high order, and the func_clk and the com_rstn are respectively connected with the input ports func_clk and the com_rstn; the high-order output ports of the comparison unit are connected with the OR values of all low-order output ends of the comparison unit through n-1 OR gates, and the OR values are used as the output ports TSV_fail of the comparison circuit; a fault is indicated when the output tsv_fail=1, and no fault is indicated when tsv_fail=0.
8. A method of inter-die TSV testing, characterized in that it is based on a test circuit implementation according to any of claims 1-7, comprising the steps of:
step 1, resetting a test circuit;
step 2, configuring a test path, and opening the test paths of two core particles connected with the TSV to be tested;
step 3, configuring a test instruction and selecting a TSV test mode;
step 4, configuring a read-write register, and transmitting the required seed into the read-write register group through a tdi port and keeping the read-write register unchanged;
step 5, initializing TSV test, comparing the 0 of the circuit, and driving an initial value into a test vector generating circuit;
step 6, TSV test, wherein a test vector generation circuit generates a pseudo-random sequence to enter a TSV array test, and a comparison circuit judges whether the test is passed or not;
step 7, judging whether the current test line is an nth line, if not, entering step 8, and if yes, entering step 9;
step 8, capturing test response under the TSV array test control circuit, updating the test decoding circuit, and returning to the step 5;
step 9, capturing test response under the control of a core particle test configuration circuit;
and step 10, shifting out the test response and observing.
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