CN117517911A

CN117517911A - Method and apparatus for determining output charge of wide bandgap device without hardware modification

Info

Publication number: CN117517911A
Application number: CN202310973578.4A
Authority: CN
Inventors: V·希瓦拉姆; N·R·赫格德; K·N·H·斯里; A·奈克; S·布; Y·M·派; V·美利那马内
Original assignee: Tektronix Inc
Current assignee: Tektronix Inc
Priority date: 2022-08-03
Filing date: 2023-08-03
Publication date: 2024-02-06

Abstract

Methods and apparatus for determining the output charge of a wide bandgap device without hardware modification are disclosed. A test and measurement instrument comprising: a user interface; one or more probes connected to a Device Under Test (DUT); and one or more processors to take measurements during application of the double pulse test to the DUT to create measurement data, identify a measurement start point, find a measurement stop point, determine an output charge qos of the DUT using the measurement data between the measurement start point and the measurement stop point, and display the output charge to a user. A method of determining an output charge of a Device Under Test (DUT) includes: taking measurements during application of the double pulse test to create measurement data; identifying a measurement start point; finding a measurement stopping point; determining an output charge qos of the DUT using measurement data between the measurement start point and the measurement stop point; and displaying the output charge.

Description

Method and apparatus for determining output charge of wide bandgap device without hardware modification

Cross Reference to Related Applications

According to U.S. c. ≡119, the present disclosure claims priority from indian provisional patent application No.202221044476 entitled "METHOD FOR DETERMINING OUTPUT CHARGE (QOSS) OF WBG DEVICES WITHOUT HARDWARE MODIFICATION," filed on 3 at month 8 of 2022, the disclosure of which is incorporated herein by reference in its entirety.

Technical Field

The present disclosure relates generally to test and measurement instruments and methods, and more particularly to testing wide bandgap semiconductors.

Background

Semiconductor materials used in power electronics are being converted from silicon to Wide Band Gap (WBG) semiconductors such as silicon carbide (SiC) and gallium nitride (GaN). WBG semiconductors have excellent performance at higher power levels in automotive and industrial applications. The testing process for MOSFETs (metal oxide semiconductor field effect transistors) or IGBTs (insulated gate bipolar transistors) typically involves the use of a Double Pulse Test (DPT) method. DPT testing typically turns on and off power switches Devices Under Test (DUTs) at different current levels to control and measure the devices throughout a range of operating conditions.

To measure WBG power loss, it is necessary to characterize the device on-resistance, capacitance, and gate charge parameters. The characteristics section of the semiconductor data table typically lists the dynamic characteristics of the device. The output charge, known as Qoss, is an important parameter for devices with body diodes.

Accurate measurement of output charge is of primary importance because it directly affects the switching speed of WBG devices and the capacitance characteristics of SiC MOSFET body diodes during turn-on. Reverse recovery charge (Qrr) is a characteristic of the power device and consists of stored bipolar charge that is cleared during the shutdown process and capacitive contributions that limit charging of the output capacitance Coss to the DC link voltage.

Currently, engineers find output charge (qos) and reverse recovery charge (Qrr) indistinguishable for WBG devices. Since WBG solutions are used for varying temperature conditions, there is a need to measure the increase in qos at different junction temperatures. The reverse current pulse is superimposed with bipolar charge oscillations, which result in a large settling time at the recovery zone. Figure 2 shows a graphical representation of the regions of the pulse that may cause these errors.

Conventional solutions involve the placement of a gate resistor (R _g ) To reduce capacitive overshoot. To determine simple characteristic parameters, the DUT may have additional, unnecessary circuit elements that result in hardware errors, such as improper soldering of the joints.

Other proposals include determining the qos on the second pulse of reverse recovery current. However, qoss should be separated from Qrr based on slope, as shown in fig. 2. This approach will provide an incorrect qos for WBG devices.

Drawings

Fig. 1 shows a reverse current curve with varying pulse regions.

Fig. 2 shows a graphical representation of the zones used in the current qos computation.

Fig. 3 shows a circuit diagram of parasitic elements in a DPT power circuit.

Fig. 4 shows an embodiment of a calculated qos on a first drain current reverse pulse.

Fig. 5 shows a qos determined on the drain current reverse pulse using an alternative test setup.

FIG. 6 shows a determined Qos on a first drain current reverse pulse, where V _ds-th Is V _dspeak Is set to a threshold level of (1).

FIG. 7 shows the voltage for V at 600V _ds Use I _d For varying junction temperature and peak reverse current I _RR So-called Qoss plots.

FIG. 8 shows the voltage for V at 800V _ds Use I _d For varying junction temperature and peak reverse current I _RR Qos mapping in terms of

FIG. 9 shows for V _ds Or 600V using V _ds And I _d For varying junction temperature and peak reverse current I _RR So-called qos plots.

FIG. 10 shows the voltage for V at 800V _ds Using V _ds And I _d For varying junction temperature and peak reverse current I _RR So-called qos plots.

Fig. 11 shows an embodiment of a user interface for a qos configuration page in a WBG DPT solution in an oscilloscope.

Fig. 12 shows an embodiment of a test and measurement instrument.

Detailed Description

Embodiments herein apply a double pulse test to a wide bandgap semiconductor device, capture the resulting waveform and perform an analysis on the waveform to determine the output charge of the device. Unlike current methods, embodiments herein perform the analysis non-invasively and much more accurately.

In a double pulse test, the test and measurement instrument applies an on pulse to the device, which can be adjusted as needed to achieve the desired drain current. The instrument then turns off the first pulse for a short period of time so as not to affect the load current. The instrument then applies a second pulse to the device, which is typically long enough only for the measurement to be taken, and then turns off the second pulse.

Test and measurement devices connected to a Device Under Test (DUT) capture measurements of device characteristics during testing. The device may be subjected to the test multiple times at different temperatures to allow for the most accurate measurement.

Embodiments generally relate to using measurement data to identify a first point in the measurement data (i.e., a measurement start point) and a second point in the measurement data (i.e., a measurement stop point). The determination of the second point varies from embodiment to embodiment, but the first point results from finding the first valley in the measurement data. In one embodiment, the measurement data is drain current I _d . In another embodiment, the measurement data includes drain current and low side drain-source voltage V _ds Both of which.

The embodiments herein use measurements found at the first pulse of a two-pulse test. When the gate voltage rises, current I _d Falling and forming a valley, in some embodiments of the test setup, the magnitude of the first valley in the current is dependent on the junction temperature. Any oscillations due to stored bipolar charge depend on resistance, blocking capacitor and parasitics.

Fig. 1 shows an example of a reverse current curve with varying pulse regions. The reverse current curves result from drain current measurements taken from the DUT during the double pulse test, each of curves 10, 12, 14 and 16 representing a separate test performed on the DUT. The curves each have a zero crossing 20, the zero crossing 20 defining the temporal start of the pulse region of interest. Line 22 shows the second zero crossing for curve 10, line 24 represents the second zero crossing for curve 14, and line 26 represents the second zero crossing for curve 16.

Fig. 3 illustrates a typical test setup for performing a Double Pulse Test (DPT) on a DUT. There are two switching devices, a "high side" device and a "low side" device, in a half-bridge configuration. One switching device, typically a low-side device, is the Device Under Test (DUT), and the second device is typically the same type of device as the DUT. Note the inductive load on the "high" side device. The inductor is used to replicate circuit conditions that may exist in normal device operation. The power supply or SMU may supply voltage V _DD And Any Function Generator (AFG) or other signal generator may output a trigger DUTA pulse of gate to turn it on to begin conduction of current. An oscilloscope, along with appropriate current and voltage probes, may be used to measure the resulting waveforms from the DUT.

The process for applying the double pulse test and capturing the measurement data may include the following. First, all the remaining charge in the active elements of the circuit must be discharged. One embodiment measures gate voltage V using a high Common Mode Rejection Ratio (CMRR) probe such as TIVP _gs . One embodiment measures drain-source voltage V using calibrated differential probes _ds And measuring drain current I using a current sense resistor _d 。

In one embodiment, the double pulse test uses a gate voltage with the correct source connection to turn on the DUT so that ringing does not occur due to the voltage propagation path. The pulse width of the gate drive is to be controlled by the test to create a double pulse and capture the measurement.

After capture, oscilloscope software may automatically detect the first pulse region of the double pulse test using the gate waveform. A first embodiment of a method to determine the qos algorithm uses drain current. The method uses the current measurement as a source and uses an edge detection algorithm to find the first valley. In this embodiment, the method uses equation 1 to determine the absolute area under the curve of the data.

In equation 1, t1 represents the time of the first zero crossing time of the current, the time of the falling zero crossing, and t2 represents the time of the second zero crossing time of the current, the rising zero crossing time. The qos value determined in this embodiment will have minimal variation for a plurality of current magnitudes and junction temperatures. The test and instrumentation methods discussed in more detail below have a user interface to allow selection to enable or disable computation with absolute operations on each current sample.

Fig. 4 shows a graph 30 representing drain current measurement data taken from a DUT. The falling zero crossing defines the beginning of the pulse zone. The method herein identifies this point using an edge detection process that identifies the onset of a valley in the drain current. In the above embodiment, the second point is the second zero crossing and the output charge is generated by integrating the drain current over time between these two points. Fig. 5 shows the drain current for two different curves 32 and 34. Both curves have zero crossings at 36, with curve 32 having a second zero crossing at 38 and curve 34 having a second zero crossing at 39.

In a second embodiment, the test and measurement instrument will detect a first pulse zone starting with a first zero crossing, the falling zero crossing. This embodiment uses a low side V _ds And I _d Both of which. The method sets the first point to the time at which the first zero crossing time of the current occurs. The method sets the second point to V at _ds Has reached a threshold amplitude V _ds-th Is a time of (a) to be used. These points become the first and second points in time over which the curve of the data is integrated, as shown in equation 2.

As mentioned above, tId is the time of the first zero crossing of the current and tdds is the low side V at which _ds Reaching the threshold V _ds-th Is a time of (a) to be used. V for determining Qos _ds The threshold value of (2) may be V from left in the first pulse region _ds Is the first occurrence of stabilization of (c). Alternatively, it may be V in the first pulse zone _ds A specific percentage of the peak value of (a). FIG. 6 shows I _d Curves 42 and V _ds Curve 40, zero crossing 44 of the drain current, and point 46 where the drain-source voltage is at 80% of its peak. The user may configure the two points to specify a first point and a second point, thereby specifying a region of interest. Test and measurement instruments allow configuration V _ds-th To accommodate testing of fast and slow switches and WBG reference designs. The method of the embodiment allows for a pair V from the left or right side of the first pulse zone _ds-th Level detectionThe configuration is measured and it may allow the percentage of peak value to be set as the threshold value if peak percentage is used. The user can configure the use of V _ds Such as first, last, etc. The user will make an input through the user interface. Alternatively, the system may have default settings, such as use first occurrence.

The above embodiment relies on two points in time. A first point in time (measurement start point) and a second point in time (measurement stop point) define a burst area for determining qos. The embodiment uses the zero crossing time as the first point in time. Typically this will involve a falling zero crossing, but may be reversed. In one embodiment, the second point includes a rising zero crossing. In another embodiment, the second point comprises V _ds The time to settle or the time at which a threshold percentage of the peak value is reached. Other variations of the definition of these points fall within the scope of the claims. The measurement start time and the measurement stop time may occur in time sequence or may be reversed.

As illustrated in fig. 7 and 8, V is stabilized for different _ds Using only current I _d The embodiments of the method to find qos provide qos values within a small standard deviation for varying current and junction temperature. As seen in fig. 7 and 8, qos is expected to be for higher stable V due to high initial charge ingestion _ds Increased and confirmed by device physics. In fig. 7 to 10, each temperature has the same reference numeral. Reference numeral 50 designates 25 ℃ (not shown in fig. 7), 52 designates 50 ℃,54 designates 75 ℃,56 designates 100 ℃,58 designates 125 ℃,60 designates 150 ℃, and 62 designates 175 ℃.

Alternative embodiments use V _ds And I _d To calculate qos. V (V) _ds-th The level parameter may be set at V _ds Is the first occurrence of stabilization of (c). In the first pulse zone V _ds-th The first occurrence of a level may also provide a stopping point for integration, as seen in equation 2. As shown in fig. 9 and 10, the calculated qos amplitude has a value attached to the average valueNear low variation.

Embodiments of testing and measuring allow the user to configure which source they want to use for the second point, or drain current, or drain-source voltage, and set the percentage of peak value if desired. Fig. 11 shows an embodiment of a user interface. The user interface may provide the user with the ability to influence code that one or more processors in the instrument may execute to perform the methods of the embodiments. Fig. 12 shows an embodiment of a test and measurement instrument.

FIG. 12 shows a block diagram of an example test and measurement instrument 60 for implementing the method of the embodiments. The test and measurement instrument 60 includes one or more input ports 62 and one or more output ports 64, the one or more input ports 62 may receive signals from the DUT 68 via probes or connections 69, and the one or more output ports 64 may be any electrical signaling medium. The ports 62, 64 may include receivers, transmitters, and/or transceivers. Input port 62 is used to receive signals from an attached device such as a DUT, MOSFET, power MOSFET, WBG device, or other object under test. The output port 64 is used to carry the generated signal out of the instrument 60 for application to a device or DUT. Examples of output signals include waveforms and constant currents and voltages, and may be applied to one or more devices under test. Each input port 62 may include a channel of a test and measurement instrument 60. Input port 62 is coupled to one or more processors 66 to process signals and/or waveforms received at port 62 from one or more devices under test. The output port 64 may be coupled to a processor 66 or other component within the instrument 60 that generates an appropriate output signal. Although fig. 8 shows only one processor 66 for ease of illustration, multiple processors 66 of different types may be used in combination, rather than a single processor 66, as will be appreciated by those skilled in the art.

The input port 62 may also be connected to a measurement unit within the test instrument 60, which is not depicted here for ease of illustration. Such a measurement unit may include any component capable of measuring aspects of a signal (such as voltage, amperage, amplitude, etc.) received via the input port 62. Output port 64 may also be connected to various components of instrument 60, such as a voltage source, a current source, or a waveform generator, which are not depicted for ease of illustration. The test and measurement instrument 60 may include additional hardware and/or processors, such as conditioning circuitry, analog-to-digital converters, and/or other circuitry to convert the received signals into waveforms for further analysis. The resulting waveforms may then be stored in memory 70 and displayed on display 72.

The one or more processors 66 may be configured to execute instructions from the memory 70 and may perform any methods and/or associated steps indicated by such instructions, such as displaying measured values to coupled devices in accordance with embodiments of the present disclosure. Memory 70 may be implemented as processor cache, random Access Memory (RAM), read Only Memory (ROM), solid state memory, hard disk drive(s), or any other memory type. Memory 70 serves as a medium for storing data, computer program products, and other instructions.

User input received from a user interface is coupled to the processor 66. The user interface 72 may include a keyboard, mouse, trackball, touch screen, and/or any other control employable by a user to utilize the user interface on the display 72 (which may also include a user interface). Although the components of the test instrument 60 are depicted as being integrated within the test and measurement instrument 60, one of ordinary skill in the art will appreciate that any of these components may be external to the test instrument 60 and may be coupled to the test instrument 60 in any conventional manner.

In this way, the test and measurement instrument can accurately and precisely determine the output charge qos of the device under test (such as MOSFET, WBG MOSFET, etc.).

Aspects of the disclosure may operate on specially created hardware, on firmware, on a digital signal processor, or on a specially programmed general-purpose computer including a processor operating according to programmed instructions. The term controller or processor as used herein is intended to include microprocessors, microcomputers, application Specific Integrated Circuits (ASICs), and special purpose hardware controllers. One or more aspects of the present disclosure may be embodied in computer-usable data and computer-executable instructions executed by one or more computers (including monitoring modules) or other devices, such as in one or more program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types when executed by a processor in a computer or other device. The computer-executable instructions may be stored on a non-transitory computer-readable medium such as a hard disk, an optical disk, a removable storage medium, a solid state memory, random Access Memory (RAM), and the like. As will be appreciated by those skilled in the art, the functionality of the program modules may be combined or distributed as desired in various aspects. Furthermore, the functionality may be embodied in whole or in part in firmware or hardware equivalents such as integrated circuits, FPGAs, and the like. One or more aspects of the present disclosure may be more efficiently implemented using specific data structures, and it is contemplated that such data structures are within the scope of the computer-executable instructions and computer-usable data described herein.

In some cases, the disclosed aspects may be implemented in hardware, firmware, software, or any combination thereof. The disclosed aspects may also be implemented as instructions carried by or stored on one or more non-transitory computer-readable media, which may be read and executed by one or more processors. Such instructions may be referred to as a computer program product. As discussed herein, computer-readable media means any medium that can be accessed by a computing device. By way of example, and not limitation, computer readable media may comprise computer storage media and communication media.

Computer storage media means any medium that can be used to store computer readable information. By way of example, and not limitation, computer storage media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital Video Disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, and any other volatile or nonvolatile, removable or non-removable media implemented in any technology. Computer storage media excludes signals themselves and signal transmissions in transitory form.

Communication media means any medium that can be used for communication of computer readable information. By way of example, and not limitation, communication media may include coaxial cables, fiber-optic cables, air, or any other medium suitable for communication of electrical, optical, radio Frequency (RF), infrared, acoustic, or other types of signals.

Example

Illustrative examples of the disclosed technology are provided below. Embodiments of the technology may include one or more of the examples described below, as well as any combination.

Embodiment 1 is a test and measurement instrument comprising: a user interface; one or more probes configured to connect to a Device Under Test (DUT); and one or more processors configured to execute code that causes the one or more processors to: retrieving measurements from the DUT during application of the double pulse test to the DUT to create measurement data; identifying a measurement start point in the measurement data; finding a measurement stopping point in the measurement data; determining an output charge qos of the DUT using measurement data between the measurement start point and the measurement stop point; and displaying the output charge to a user on a user interface.

Example 2 is the test and measurement instrument of example 1, wherein the code that causes the one or more processors to take measurements from the DUT further comprises code that causes the one or more processors to take at least one of a drain current measurement and a low side drain-source voltage measurement.

Example 3 is the test and measurement instrument of example 2, wherein the code that causes the one or more processors to identify a measurement start point in the measurement data includes code that causes the one or more processors to identify a first valley in the drain current and set the measurement start point to a time of a first zero crossing in the drain current.

Example 4 is the test and measurement instrument of example 3, wherein the code that causes the one or more processors to find a measurement stop point in the measurement data comprises code that causes the one or more processors to find a second zero crossing in the drain current and to set a time of the second zero crossing as the measurement stop point.

Example 5 is the test and measurement instrument of example 3, wherein the code that causes the one or more processors to find a measurement stopping point in the measurement data comprises code that causes the one or more processors to find a point at which the low side drain-source voltage reaches a threshold value and to set a time at which the low side drain-source voltage reaches the threshold value as the measurement stopping point.

Example 6 is the test and measurement instrument of example 5, wherein the code that causes the one or more processors to find a point at which the low side drain-source voltage reaches the threshold comprises code that causes the one or more processors to find a stable occurrence of the drain-source voltage.

Example 7 is the test and measurement instrument of example 6, wherein the code that causes the one or more processors to find a stable occurrence of the drain-source voltage comprises code that causes the one or more processors to receive an input from the user interface identifying which stable occurrence is to be used or using a first occurrence of the stability.

Example 8 is the test and measurement instrument of example 6, wherein the code that causes the one or more processors to find a point at which the low side drain-source voltage reaches the threshold comprises code that causes the one or more processors to find a point at which the low side drain-source voltage has reached a predetermined percentage of the peak drain-source voltage.

Example 9 is the test and measurement instrument of example 8, wherein the one or more processors are further configured to execute the code to: which causes the one or more processors to receive an input through the user interface selecting a measurement stop point and setting a predetermined percentage if the predetermined percentage is used.

Example 10 is the test and measurement instrument of any one of examples 1 to 9, wherein the code that causes the one or more processors to use measurement data between the first measurement start point and the second measurement stop point includes code that causes the one or more processors to integrate drain current over time to find a qos.

Example 11 is the test and measurement instrument of any of examples 1 to 10, wherein the one or more processors are further configured to execute code that causes the one or more processors to allow a user to annotate the region of interest on the display.

Example 12 is a method of determining output charge of a Device Under Test (DUT), comprising: retrieving measurements from the DUT during application of the double pulse test to the DUT to create measurement data; identifying a measurement start point in the measurement data; finding a measurement stopping point in the measurement data; determining an output charge qos of the DUT using measurement data between the measurement start point and the measurement stop point; and displaying the output charge to a user on a user interface.

Example 13 is the method of example 12, wherein taking measurements includes taking at least one of a drain current measurement and a low side drain-source voltage measurement.

Example 14 is the method of example 13, wherein identifying a measurement start point in the measurement data includes identifying a first valley in the drain current and setting the measurement start point to a time of a first zero crossing in the drain current.

Example 15 is the method of example 14, wherein finding a measurement stopping point in the measurement data includes finding a second zero crossing in the drain current and setting a time of the second zero crossing as the measurement stopping point.

Example 16 is the method of example 13, wherein finding a measurement stopping point in the measurement data includes finding a point at which the low-side drain-source voltage reaches a threshold and setting a time at which the low-side drain-source voltage reaches the threshold as the measurement stopping point.

Example 17 is the method of example 16, wherein finding a point at which the low-side drain-source voltage reaches the threshold comprises finding a stable occurrence of the drain-source voltage or using a user-specified stable occurrence of the drain-source voltage.

Example 18 is the method of example 16, wherein finding a point at which the low-side drain-source voltage reaches the threshold includes finding a point at which the low-side drain-source voltage has reached a predetermined percentage of the peak drain-source voltage.

Example 19 is the method of example 18, further comprising receiving input through the user interface to configure at least a selection of a measurement stop point, allowing a user to annotate the region of interest on the display, and setting the predetermined percentage if the predetermined percentage is used.

Example 20 is the method of any one of examples 11 to 19, wherein using measurement data between the measurement start point and the measurement stop point includes integrating drain current over time between the measurement start point and the measurement stop point to find qos.

The previously described versions of the disclosed subject matter have many advantages, either described or apparent to one of ordinary skill. Even so, such advantages or features are not required in all versions of the disclosed apparatus, systems or methods.

Additionally, this written description references specific features. It is to be understood that the disclosure in this specification includes all possible combinations of these particular features. Where a particular feature is disclosed in the context of a particular aspect or example, that feature may also be used, to the extent possible, in the context of other aspects and examples.

In addition, when a method having two or more defined steps or operations is referred to in this application, the defined steps or operations may be performed in any order or simultaneously unless the context excludes those possibilities.

All of the features disclosed in the specification, including the claims, abstract and drawings, and all of the steps in any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive. Each feature disclosed in the specification, including the claims, abstract and drawings, may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

Although specific examples of the invention have been illustrated and described for purposes of description, it will be appreciated that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, the invention is not to be restricted except in light of the attached claims.

Claims

1. A test and measurement instrument comprising:

a user interface;

one or more probes configured to connect to a device under test DUT; and

one or more processors configured to execute code that causes the one or more processors to:

retrieving measurements from the DUT during application of the double pulse test to the DUT to create measurement data;

identifying a measurement start point in the measurement data;

finding a measurement stopping point in the measurement data;

determining an output charge qos of the DUT using measurement data between the measurement start point and the measurement stop point; and

the output charge is displayed to the user on a user interface.

2. The test and measurement instrument of claim 1, wherein the code that causes the one or more processors to take measurements from the DUT further comprises code that causes the one or more processors to take at least one of a drain current measurement and a low side drain-source voltage measurement.

3. The test and measurement instrument of claim 2, wherein the code that causes the one or more processors to identify a measurement start point in the measurement data includes code that causes the one or more processors to identify a first valley in the drain current and set the measurement start point to a time of a first zero crossing in the drain current.

4. A test and measurement instrument as claimed in claim 3, wherein the code that causes the one or more processors to find a measurement stop point in the measurement data comprises code that causes the one or more processors to find a second zero crossing in the drain current and to set the time of the second zero crossing as the measurement stop point.

5. The test and measurement instrument of claim 3, wherein the code that causes the one or more processors to find a measurement stop point in the measurement data includes code that causes the one or more processors to find a point at which the low side drain-source voltage reaches a threshold value and to set a time at which the low side drain-source voltage reaches the threshold value as the measurement stop point.

6. The test and measurement instrument of claim 5, wherein the code that causes the one or more processors to find a point at which the low side drain-source voltage reaches a threshold value includes code that causes the one or more processors to find a stable occurrence of the drain-source voltage.

7. The test and measurement instrument of claim 6, wherein the code that causes the one or more processors to find a stable occurrence of the drain-source voltage includes code that causes the one or more processors to receive an input from a user interface identifying which stable occurrence is to be used or which stable first occurrence is to be used.

8. The test and measurement instrument of claim 5, wherein the code that causes the one or more processors to find a point at which the low side drain-source voltage reaches a threshold value includes code that causes the one or more processors to find a point at which the low side drain-source voltage has reached a predetermined percentage of the peak drain-source voltage.

9. The test and measurement instrument of claim 8, wherein the one or more processors are further configured to execute code to: which causes the one or more processors to receive an input through the user interface selecting a measurement stop point and setting a predetermined percentage if the predetermined percentage is used.

10. The test and measurement instrument of claim 1, wherein the code that causes the one or more processors to use measurement data between a measurement start point and a measurement stop point comprises code that causes the one or more processors to integrate drain current over time to find qos.

11. The test and measurement instrument of claim 1, wherein the one or more processors are further configured to execute code that causes the one or more processors to allow a user to annotate a region of interest on a display.

12. A method of determining an output charge of a device under test DUT, comprising:

identifying a measurement start point in the measurement data;

finding a measurement stopping point in the measurement data;

the output charge is displayed to the user on a user interface.

13. The method of claim 12, wherein taking measurements comprises taking at least one of drain current measurements and low side drain-source voltage measurements.

14. The method of claim 13, wherein identifying a measurement start point in the measurement data comprises identifying a first valley in the drain current and setting the measurement start point to a time of a first zero crossing in the drain current.

15. The method of claim 14, wherein finding a measurement stop point in the measurement data comprises finding a second zero crossing in the drain current and setting a time of the second zero crossing as the measurement stop point.

16. The method of claim 13, wherein finding a measurement stop point in the measurement data comprises finding a point at which the low side drain-source voltage reaches a threshold value and finding a time at which the low side drain-source voltage reaches the threshold value as the measurement stop point.

17. The method of claim 16, wherein finding a point at which the low-side drain-source voltage reaches a threshold comprises finding a stable occurrence of the drain-source voltage or using a user-specified stable occurrence of the drain-source voltage.

18. The method of claim 16, wherein finding a point at which the low-side drain-source voltage reaches a threshold comprises finding a point at which the low-side drain-source voltage has reached a predetermined percentage of the peak drain-source voltage.

19. The method of claim 18, further comprising receiving input through a user interface to at least configure selection of a measurement stop point, allowing a user to annotate a region of interest on the display, and setting the predetermined percentage if the predetermined percentage is used.

20. The method of claim 11, wherein using measurement data between a measurement start point and a measurement stop point comprises integrating drain current over time between the measurement start point and the measurement stop point to find qos.