CN117501438A

CN117501438A - Multi-wafer stacking structure and manufacturing method thereof

Info

Publication number: CN117501438A
Application number: CN202180099452.8A
Authority: CN
Inventors: 朱继锋; 雷电; 朱靖华; 张宏英
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-06-15
Filing date: 2021-06-15
Publication date: 2024-02-02
Also published as: WO2022261811A1

Abstract

The application provides a multi-wafer stacking structure and a manufacturing method thereof. The polycrystalline wafer stacking structure that this application obtained stacks the setting through the mode of fusion bonding with a plurality of wafers to make the setting is piled up in the thickness direction of bare chip to the components and parts in the bare chip that the cutting wafer obtained, thereby increase the density of the components and parts in the bare chip, promote the performance of chip under the circumstances that the occupation area of the chip that the realization encapsulation bare chip obtained does not increase. And a plurality of wafers are stacked by fusion bonding, avoiding the introduction of organic matters, thereby avoiding the generation of organic pollution and having simple realization process.

Description

Multi-wafer stacking structure and manufacturing method thereof

Technical Field

The present disclosure relates to the field of electronic technologies, and in particular, to a multi-wafer stacking structure and a method for manufacturing the multi-wafer stacking structure.

Background

With the improvement of chip performance requirements, the number of components such as transistors integrated in a chip is increasing. In order to avoid excessively increasing the size of the chip, the density of the components in the chip needs to be increased as much as possible. Generally, the density of the components in the chip is improved by reducing the channel size of the transistor, but the method for improving the performance of the chip in this way can meet the challenges of huge physical limits, such as mobility reduction, short channel effect, and the like. Apart from the method of overcoming physical limits and continuing to shrink transistor size to achieve chip performance improvement, integrating chips with different functions becomes an important way of improving the performance of system-in-the-system chips in the future.

In the prior art, a plurality of wafers are generally fixed together by an adhesive, so that stacking of the plurality of wafers is realized. However, the gluing method introduces organic impurities into the multi-wafer stack structure, resulting in organic contamination.

Disclosure of Invention

The application provides a multi-wafer stacking structure and a manufacturing method thereof, which aim to improve the density of components in a chip and the performance of the chip in a three-dimensional stacking mode.

In a first aspect, the present application provides a method for manufacturing a multi-wafer stack structure, including the steps of:

sequentially forming a first inorganic dielectric layer, a first connecting layer and a second inorganic dielectric layer on the surface of a first wafer, wherein the first connecting layer is electrically connected with the first wafer; forming a third inorganic dielectric layer on the surface of the second wafer; bonding and fixing one surface of the second wafer, which is away from the third inorganic dielectric layer, with one surface of the second inorganic dielectric layer, which is away from the first wafer, through a fusion bonding process; and forming a second connecting layer on one surface of the third inorganic dielectric layer, which is away from the second wafer, and forming a conductive via penetrating through the third inorganic dielectric layer, the second wafer and the second inorganic dielectric layer, wherein one end of the conductive via is connected with the second connecting layer, and the other end of the conductive via is connected with the first connecting layer.

In this embodiment, after the second wafer and the first wafer are fixed by a fusion bonding (fusion bonding) process, the second connection layer and the conductive via are formed, so that stacking of the first wafer and the second wafer is achieved, and electrical connection between the first wafer and the second wafer is achieved. Compared with the mode of fixing the first wafer and the second wafer through the organic adhesive material, organic pollution can be avoided. In addition, organic pollution is not introduced in other steps of the manufacturing method, so that the quality of the obtained multi-wafer stacking structure is ensured, and the quality of a finally obtained chip is ensured. In the application, since the first wafer and the second wafer are fixed first, and then the second connecting layer and the conductive through hole are formed, when the first wafer and the second wafer are fixed, the surface of the second wafer deviating from the third inorganic dielectric layer and the surface of the second inorganic dielectric layer deviating from the first wafer are both inorganic material surfaces, and the surface of the second wafer deviating from the third inorganic dielectric layer and the surface of the second inorganic dielectric layer deviating from the first wafer are not provided with metal material surface areas, so that the fixation of the first wafer and the second wafer can be realized by adopting a fusion bonding mode. Compared with the mode of fixing the first wafer and the second wafer by the hybrid bonding, the fixed phase of the first wafer and the second wafer by the fusion bonding is lower in difficulty in the implementation process of the fusion bonding.

In some embodiments, after forming the third inorganic dielectric layer on the surface of the second wafer and before bonding and fixing the side of the second wafer facing away from the third inorganic dielectric layer and the side of the second inorganic dielectric layer facing away from the first wafer by fusion bonding, the method further includes: fixing the transfer substrate on one side of the third inorganic dielectric layer, which is away from the second wafer; the second wafer is thinned.

In the embodiment of the application, each wafer stacked is thinned, so that the thickness of the stacked multi-wafer stacked structure obtained by stacking is reduced as much as possible, and the occupied volume of the chip is reduced as much as possible. And the second wafer is thinned after being fixed with the transfer substrate, compared with a mode of directly thinning the second wafer, the method has the advantages that better thinning effect can be achieved, uniformity of each position of the thinned second wafer is better, warping of the thinned second wafer can be avoided, and quality of the thinned second wafer is guaranteed.

In some embodiments, bonding and fixing the side of the second wafer facing away from the third inorganic dielectric layer and the side of the second inorganic dielectric layer facing away from the first wafer by fusion bonding further includes: and removing the transfer substrate. In this embodiment, before bonding and fixing the surface of the second wafer facing away from the third inorganic dielectric layer and the surface of the second inorganic dielectric layer facing away from the first wafer, a carrier wafer is fixed on the surface of the third inorganic dielectric layer facing away from the second wafer, so that in order to avoid the carrier wafer from affecting the subsequent steps, the carrier substrate needs to be removed first, and then the subsequent steps (such as forming the second connection layer, forming a conductive via hole penetrating through the third inorganic dielectric layer, the second wafer and the second inorganic dielectric layer, etc.) are performed.

In some embodiments, the second wafer includes a substrate and a device layer, an interconnect layer, sequentially stacked on the substrate, wherein the step of thinning the second wafer includes: the substrate of the second wafer is thinned. In the embodiment of the application, the substrate of the second wafer is thinned, so that the thinning of the second wafer can be realized, and meanwhile, the damage of a device layer and an interconnection layer in the second wafer caused by thinning can be avoided, and the normal function of the second wafer is ensured.

In some embodiments, after the step of thinning the second wafer, the method further comprises: and flattening the thinned surface of the second wafer. In this embodiment of the application, the surface after the second wafer attenuate is flattened, can guarantee that follow-up second wafer deviates from the one side of third inorganic dielectric layer and the one side that second inorganic dielectric layer deviates from first wafer can realize better laminating and fixed effect.

In some embodiments, the process of securing the transfer substrate to the side of the third inorganic dielectric layer facing away from the second wafer is a fusion bonding process. The transfer substrate is fixed on one side of the third inorganic dielectric layer, which is away from the second wafer, through a fusion bonding (fusion bonding) process, so that organic pollution can be avoided from being introduced organically, and the quality of the finally obtained chip is ensured, compared with a mode of fixing through an organic adhesive material. And, the one side of the second wafer, which is away from the third inorganic dielectric layer, and the transfer substrate are both inorganic material layers, so that the wafer can be fixed in a fusion bonding mode, and compared with the fixation between the wafers realized through a hybrid bonding process, the realization process difficulty is lower because the metal material and the metal material are not bonded.

Wherein fixing the transfer substrate to the side of the third inorganic dielectric layer facing away from the second wafer by a fusion bonding process comprises:

respectively carrying out surface treatment on the surface of the third inorganic dielectric layer facing away from the second wafer and the surface of the transfer substrate facing the third inorganic dielectric layer; attaching the surface of the treated third inorganic dielectric layer facing away from the second wafer and the surface of the transfer substrate facing the second dielectric layer; and carrying out temperature treatment on the third inorganic dielectric layer and the transfer substrate so as to bond and fix the transfer substrate and one surface of the third inorganic dielectric layer, which is away from the second wafer.

In some embodiments, the temperature treatment includes an annealing treatment and the surface treatment process may include a plasma surface treatment, magnetron sputtering, and the like.

In the embodiment of the application, the surface of the third inorganic dielectric layer, which is away from the second wafer, and the surface of the transfer substrate, which is towards the third inorganic dielectric layer, are subjected to surface treatment by a surface treatment process such as plasma activation, so that the surface of the third inorganic dielectric layer, which is away from the second wafer, and the surface of the transfer substrate, which is towards the third inorganic dielectric layer, are activated, and bonding reaction can be performed more easily. The surface of the processed third inorganic dielectric layer, which is away from the second wafer, is attached to the surface of the transfer substrate, which is towards the second dielectric layer, so that the surface of the third inorganic dielectric layer, which is away from the second wafer, is pre-bonded with the surface of the transfer substrate, which is towards the second dielectric layer, and after annealing treatment, chemical bonds are formed between the surface of the third inorganic dielectric layer, which is away from the second wafer, and the surface of the transfer substrate, which is towards the second dielectric layer, so that the fixation of the surface of the third inorganic dielectric layer, which is away from the second wafer, and the surface of the transfer substrate, which is towards the second dielectric layer, is realized.

In the embodiment of the application, the surface of the third inorganic dielectric layer, which is away from the second wafer, and the surface of the transfer substrate, which is towards the third inorganic dielectric layer, are subjected to surface treatment so as to activate the surface of the third inorganic dielectric layer, which is away from the second wafer, and the surface of the transfer substrate, which is towards the third inorganic dielectric layer, so that the temperature required by annealing can be reduced, the process difficulty is reduced, and the manufacturing cost is reduced. In some embodiments, the annealing temperature may be around 200 ℃. It will be appreciated that in some embodiments, it may not be necessary to perform surface treatment on the surface of the third inorganic dielectric layer facing away from the second wafer and the surface of the transfer substrate facing the third inorganic dielectric layer, and the fixation of the surface of the third inorganic dielectric layer facing away from the second wafer and the surface of the transfer substrate facing the second dielectric layer may still be achieved by adopting a high-temperature annealing treatment.

In some embodiments, the first wafer and the second wafer respectively include a substrate, and a device layer and an interconnection layer sequentially stacked on the substrate, the first inorganic dielectric layer is formed on a side of the first wafer away from the substrate of the first wafer, and the third inorganic dielectric layer is formed on a side of the second wafer away from the substrate of the second wafer.

In this embodiment, the substrate side of the wafer is the back side of the wafer, and the interconnect layer side of the wafer is the front side of the wafer (face). The substrate of each wafer is in contact with the interconnect layer of the wafer adjacent thereto, i.e., in this embodiment, the wafers are stacked in a back-to-face (B2F) stack. The back surface of the wafer faces the front surface of the wafer adjacent to the back surface of the wafer, so that the conductive via hole can be formed from the front surface of the wafer like the back surface all the time when the conductive via hole is formed.

In some embodiments, the first connection layer includes a first trace layer, a second trace layer, and an intermediate inorganic dielectric layer between the first trace layer and the second trace layer, and the step of forming the first connection layer on the surface of the first wafer includes:

forming a first wiring layer on the surface of the first inorganic dielectric layer, which is away from the first wafer; forming an intermediate inorganic dielectric layer on the surface of the first inorganic dielectric layer, which is provided with the first wiring layer and is away from the first wafer, wherein the intermediate inorganic dielectric layer covers the first wiring layer; and forming a second wiring layer on the surface of the middle inorganic dielectric layer, which is away from the first wafer. In this embodiment of the application, the wiring layer of first tie layer is two-layer, realizes rewiring through double-deck wiring promptly, and the connection of adjacent wafer is more convenient, and wafer inner structure's design is more free.

In some embodiments, bonding and fixing the side of the second wafer facing away from the third inorganic dielectric layer to the side of the second inorganic dielectric layer facing away from the first wafer by a fusion bonding process includes:

carrying out surface treatment on one surface of the second wafer, which is away from the third inorganic dielectric layer, and one surface of the second inorganic dielectric layer, which is away from the first wafer; bonding one surface of the second wafer, which is away from the third inorganic dielectric layer, with one surface of the second inorganic dielectric layer, which is away from the first wafer; and carrying out temperature treatment on the second inorganic dielectric layer and the second wafer so as to bond and fix one surface of the second wafer, which is away from the third inorganic dielectric layer, with one surface of the second inorganic dielectric layer, which is away from the first wafer.

In the embodiment of the application, the surface treatment is performed on the surface of the second wafer, which is away from the third inorganic dielectric layer, and the surface of the second inorganic dielectric layer, which is away from the first wafer, through the surface treatment process such as plasma activation, so as to activate the surface of the second wafer, which is away from the third inorganic dielectric layer, and the surface of the second inorganic dielectric layer, which is away from the first wafer, so that the bonding reaction can be performed on the surface of the second wafer, which is away from the third inorganic dielectric layer, and the surface of the second inorganic dielectric layer, which is away from the first wafer, more easily. The surface of the processed second wafer deviating from the third inorganic dielectric layer is attached to the surface of the second inorganic dielectric layer deviating from the first wafer, so that the surface of the second wafer deviating from the third inorganic dielectric layer and the surface of the second inorganic dielectric layer deviating from the first wafer form pre-bonding, and after annealing treatment, chemical bonds are formed on the surface of the second wafer deviating from the third inorganic dielectric layer and the surface of the second inorganic dielectric layer deviating from the first wafer, so that the surface of the second wafer deviating from the third inorganic dielectric layer and the surface of the second inorganic dielectric layer deviating from the first wafer are fixed.

In the embodiment of the application, the surface treatment is performed on the surface, deviating from the third inorganic dielectric layer, of the second wafer and the surface, deviating from the first wafer, of the second inorganic dielectric layer, so that the surface, deviating from the third inorganic dielectric layer, of the second wafer and the surface, deviating from the first wafer, of the second inorganic dielectric layer are activated, the temperature required by annealing can be reduced, the process difficulty is reduced, and the manufacturing cost is reduced. In some embodiments, the annealing temperature may be around 200 ℃. It will be appreciated that in some embodiments, it may not be necessary to perform surface treatment on a surface of the second wafer facing away from the third inorganic dielectric layer and a surface of the second inorganic dielectric layer facing away from the first wafer, and fixation of a surface of the second wafer facing away from the third inorganic dielectric layer and a surface of the second inorganic dielectric layer facing away from the first wafer may still be achieved by adopting a high-temperature annealing treatment.

In some embodiments, the first inorganic dielectric layer, the second inorganic dielectric layer, and the third inorganic dielectric layer are all formed by depositing inorganic dielectric materials, and the deposition manner of the first inorganic dielectric layer, the second inorganic dielectric layer, and the third inorganic dielectric layer includes any one of chemical vapor deposition, sputter deposition, ion beam deposition, laser-assisted deposition, physical vapor deposition, atomic layer deposition, and molecular beam epitaxy evaporation.

In some embodiments, after removing the transfer substrate, the method further comprises: and planarizing a surface of the third inorganic dielectric layer facing away from the second wafer. In the embodiment of the application, the surface, deviating from the second wafer, of the third inorganic dielectric layer after the transfer substrate is removed is flattened, so that better attaching and fixing effects can be achieved when the surface, deviating from the second wafer, of the subsequent third inorganic dielectric layer is fixed with other wafers.

In a second aspect, the present application further includes a method for manufacturing a chip, including: the manufacturing method of the multi-wafer stacking structure is used for manufacturing the multi-wafer stacking structure; cutting the multi-wafer stacked structure to obtain a plurality of bare chips.

In the embodiment of the present application, the manufacturing method of the multi-wafer stacking structure is adopted to bond wafers with wafer stacks (W2W bonding) to obtain a multi-wafer stacking structure, then the multi-wafer stacking structure is cut to obtain a bare chip, and then the bare chip is packaged to obtain a required chip. Compared with a mode of cutting a die after a die and die are stacked and bonded (D2D bonding) to obtain a stacked structure, or a mode of cutting a die after a die and wafer are stacked and bonded (D2W bonding) to obtain a stacked structure, the method does not need to perform cutting treatment on a wafer before stacking, and can avoid the influence of impurities generated by cutting on a stacking process. In addition, when stacking, the alignment of a plurality of crystal grains on adjacent wafers can be realized through one-time alignment, and compared with the mode of stacking and bonding the crystal grains and the wafers, the alignment efficiency of the wafer stacking and bonding the crystal grains can be improved, and the alignment process difficulty is reduced. Moreover, the wafer can be subjected to the validity test before the die-to-die stacking bonding process, so that whether the die on each wafer is valid or not can be known. The die-to-die stacking bonding and die-to-wafer stacking bonding methods require testing the effectiveness of each die one by one, so that the process difficulty and the testing efficiency of the die obtained by the method are greatly reduced compared with those of die-to-die stacking bonding and die-to-wafer stacking bonding.

In a third aspect, the present application further provides a multi-wafer stacking structure, where the multi-wafer stacking structure can be manufactured by the manufacturing method of the multi-wafer stacking structure. The multi-crystal wafer stacking structure comprises a plurality of stacked wafers, wherein a dielectric layer is laminated on one surface of each wafer, and each dielectric layer comprises a connecting layer; the dielectric layer comprises a first dielectric layer and a second dielectric layer, two adjacent wafers are separated by the first dielectric layer, and the outermost dielectric layer of the wafer stacking structure is the second dielectric layer; the first dielectric layer comprises a first inorganic dielectric layer, a first connecting layer and a second inorganic dielectric layer which are sequentially stacked; the second dielectric layer comprises a third inorganic dielectric layer and a second connecting layer which are sequentially laminated; conductive through holes are connected between two adjacent dielectric layers, and pass through the wafer between the two adjacent dielectric layers; the first inorganic dielectric layer and the second inorganic dielectric layer are both formed by adopting inorganic dielectric materials.

In the present application, a plurality of wafers are stacked, and the wafers are electrically connected to each other, so that the components can be stacked in the stacking direction of the multi-wafer stacking structure. In the application, a plurality of bare chips are obtained by cutting the multi-wafer stacking structure, and then the bare chips are packaged to obtain the required chips. Because components in the polycrystalline wafer stacking structure are stacked in the stacking direction of the wafers, components in the finally obtained chips can be stacked in the thickness direction, namely, three-dimensional stacking of the components in the chips is realized, so that the density of the components in the chips is improved, the occupied area of the chips is prevented from being increased, the components in the chips can be increased, and the performance of the chips is improved while the occupied area of the chips is prevented from being increased.

In some implementations, each wafer includes a substrate and a device layer, an interconnect layer, and a dielectric layer laminated on a side of the device layer of the wafer facing away from the substrate. In this embodiment, the stacking manner between adjacent wafers is back-to-back stacking.

In some implementations, the first connection layer or the second connection layer includes one or more routing layers; when the wiring layers are multiple layers, an intermediate inorganic dielectric layer is arranged between adjacent wiring layers, a via hole is arranged in the intermediate inorganic dielectric layer, and the via hole is connected with the adjacent wiring layers.

In this embodiment of the present application, the routing layer of the first connection layer or the second connection layer may be one or more layers. When the wiring layer of the first connecting layer or the second connecting layer is a plurality of layers, rewiring is realized through the multi-layer wiring, the connection of adjacent wafers is more convenient, and the design of the internal structure of the wafers can be more free.

Drawings

In order to more clearly illustrate the constructional features and efficacy of the present application, a detailed description thereof will be given below with reference to the accompanying drawings and specific embodiments.

FIG. 1 is a schematic cross-sectional view of a chip according to one embodiment of the present application;

FIG. 2 is a schematic cross-sectional view of a multi-wafer stack structure according to one embodiment of the present disclosure;

FIG. 3 is a schematic cross-sectional view of a multi-wafer stack structure according to another embodiment of the present disclosure;

FIG. 4 is a schematic plan view of any one of the wafers in the multi-wafer stack structure shown in FIG. 2;

FIG. 5 is a schematic cross-sectional view of a multi-wafer stack structure according to another embodiment of the present application;

FIG. 6 is a schematic cross-sectional view of a multi-wafer stack structure according to another embodiment of the present disclosure;

FIG. 7 is a schematic cross-sectional view of a multi-wafer stack structure according to another embodiment of the present disclosure;

FIG. 8 is a flow chart illustrating the fabrication of the multi-wafer stack structure according to the embodiment of FIG. 3;

FIG. 9 is a flowchart showing the specific steps of step 110 in the flowchart of FIG. 8;

fig. 10 to 18 are schematic cross-sectional views of the multi-wafer stack structure of the steps of the flowcharts shown in fig. 8 and 9;

fig. 19 is a flow chart of the chip manufacturing process according to the embodiment shown in fig. 1.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

Referring to fig. 1, a chip is provided. The chip of the application can be various types of chips such as a high-bandwidth memory chip, a pattern sensor chip and the like. The chip comprises a packaging substrate 1, a packaging layer 2 and a bare chip 3, wherein the packaging layer 2 is packaged on the packaging substrate 1, and the bare chip 3 is embedded in the packaging layer 2. The bare chip 3 is connected to the package substrate 1, and the package layer 2 covers the bare chip 3 to protect the bare chip 3. In some embodiments, the bare chip 3 is connected to the package substrate 1 through the solder ball 5, or the bare chip 3 is connected to the package substrate 1 through a bonding wire. An external pin 4 is arranged on one side of the packaging substrate 1, which is away from the packaging layer 2, and the chip is connected with other structures (such as a main board) through the external pin 4, so that the chip is communicated with the other structures outside the chip. In the embodiment of the present application, the bare chip 3 encapsulated in the encapsulation layer 2 may be one or more.

In the application, the bare chip is obtained by cutting the multi-wafer stack structure. Referring to fig. 2, fig. 2 is a schematic cross-sectional view of a multi-wafer stack structure 100 according to some embodiments of the present application, and the die 3 shown in fig. 1 can be obtained by cutting the multi-wafer stack structure 100 obtained according to the present embodiment. The bare chip 3 can be obtained by cutting the multi-wafer stack structure 100. The multi-wafer stack structure 100 includes a plurality of wafers (wafer) 10 stacked. Wherein, a plurality refers to two or more. In this embodiment, the multi-wafer stacking structure 100 includes four wafers 10 stacked in sequence. The four wafers 10 stacked in this order are a first wafer 10A, a second wafer 10B, a third wafer 10C, and a fourth wafer 10D, respectively.

Referring to fig. 4, fig. 4 is a schematic plan view of any one of the wafers 10 in the multi-wafer stack structure 100 shown in fig. 2. In this embodiment, each wafer 10 includes a plurality of dies (die) 11 arranged in an array, and the dies 11 of each wafer 10 overlap in the stacking direction (i.e., the Z direction in fig. 2) of the plurality of wafers 10. In other words, the projections of the dies 11 of each wafer 10 on a reference plane parallel to the plane of the wafer 10 coincide. The multi-wafer stack structure 100 is cut along the gaps between any adjacent dies 11 in the multi-wafer stack structure 100, so that a bare chip can be obtained. The bare chip obtained by cutting the multi-wafer stack structure 100 includes a plurality of dies 11 stacked.

Referring back to fig. 2, a dielectric layer 20 is laminated on one surface of each wafer 10, and two adjacent wafers 10 are separated by the dielectric layer 20. In this embodiment, the dielectric layer 20A is laminated on one surface of the first wafer 10A, the dielectric layer 20B is laminated on one surface of the second wafer 10B, the dielectric layer 20C is laminated on one surface of the third wafer 10C, and the dielectric layer 20D is laminated on one surface of the fourth wafer 10D. The dielectric layer 20A is located between the first wafer 10A and the second wafer 10B, the dielectric layer 20B is located between the second wafer 10B and the third wafer 10C, the dielectric layer 20C is located between the third wafer 10C and the fourth wafer 10D, and the dielectric layer 20D is located at the outermost side of the multi-wafer stack structure 100.

Each wafer 10 includes a substrate, a device layer and an interconnect layer formed on the substrate in sequence. The device layer includes a plurality of components, and the interconnect layer includes interconnect traces through which the different components are electrically connected to obtain a desired integrated circuit. It should be noted that, since each wafer 10 includes a plurality of dies 11, a plurality of components are disposed in the device layer corresponding to each die 11, and the components corresponding to each die 11 are connected through interconnection traces to form an independent integrated circuit. The components in the device layer corresponding to each die 11 in the same wafer 10 are the same, the integrated circuits formed in each die 11 in the same wafer 10 are the same, and the integrated circuits formed in each die 11 are independent of each other. When the multi-wafer stack structure 100 is cut, the same plurality of bare chips can be obtained, and mass production of the bare chips is realized.

In the embodiment of the present application, the substrate side of the wafer 10 is the back side of the wafer 10, and the interconnect layer side of the wafer 10 is the front side of the wafer. The dielectric layer 20 is laminated to the side of the interconnect layers of the wafers 10 remote from the substrate, with the interconnect layer of each wafer 10 in the multi-wafer stack 100 being closer to the substrate of the wafer 10 adjacent thereto than to its substrate. In the embodiment of the present application, the wafers 10 are stacked in a back-to-face (B2F) manner. It will be appreciated that in some embodiments, the dielectric layer 20 may also be laminated on one side of the substrate of the wafer 10, with the substrate of one wafer 10 being disposed adjacent to the substrate of another wafer 10 in an adjacent wafer 10.

Each dielectric layer 20 includes a connection layer 21. A conductive via 22 is connected between two adjacent dielectric layers 20, and the conductive via 22 passes through the wafer 10 between two adjacent dielectric layers 20 and is electrically connected to the connection layer 21 of two adjacent dielectric layers 20 on both sides of the wafer 10. The conductive via 22 is a structure formed by first providing a through hole and filling the through hole with a conductive material. The two adjacent dielectric layers 20 on two opposite sides of the wafer 10 refer to the two adjacent dielectric layers 20 on two opposite sides of the wafer 10 and closest to the wafer 10, and the conductive via 22 connects the two adjacent dielectric layers 20 on two opposite sides of the wafer 10, so that signals can be transmitted between the stacked multi-wafer structures 100, and power can be supplied to components in the wafer 10 through the conductive via 22 in the wafer 10 and the connection layer 21 in the dielectric layer 20, etc. For example, in the embodiment shown in fig. 2, two adjacent dielectric layers 20 on two sides of the wafer 10B are a dielectric layer 20A and a dielectric layer 20B, a conductive via 22 is disposed in the wafer 10B, and the conductive via 22 in the wafer 10B connects the connection layer 21 in the adjacent dielectric layer 20A and the connection layer 21 in the dielectric layer 20B.

In some embodiments of the present application, the conductive via 22 in the wafer 10 is electrically connected to the interconnection layer in the wafer 10 where the conductive via 22 is located, and because the conductive via 22 is electrically connected to the connection layer 21 in the dielectric layer 20 adjacent to the wafer 10 where the conductive via 22 is located, the signal transmitted in the wafer 10 can be transmitted to the connection layer 21 in the dielectric layer 20 through the conductive via 22 thereon, and then transmitted to other adjacent wafers 10, that is, the electrical connection between the adjacent wafers 10 can be realized through the conductive via 22 in the wafer 10 and the connection layer 21 in the dielectric layer 20 between the adjacent two wafers 10, so that the communication between the wafers 10 in the multi-stack wafer structure 100 is realized. For example, in the embodiment shown in fig. 2, the conductive via 22 in the second wafer 10B is disposed through the wafer 10B and is connected to the interconnection layer of the wafer 10B, one end is connected to the connection layer 21 of the dielectric layer 20A, and the other end is connected to the connection layer 21 of the dielectric layer 20B, so that the transmitted signal in the second wafer 10B can be transmitted to the dielectric layer 20A and the first wafer 10A through the conductive via 22 disposed therein, or transmitted to the dielectric layer 20C and the third wafer 10C through the conductive via 22 disposed therein.

In other embodiments of the present application, the conductive vias 22 within the wafer 10 may not be electrically connected to the interconnect layer of the wafer 10 in which they are located. In these embodiments, the interconnect layers of the wafer 10 are electrically connected to the connection layer 21 within the dielectric layer 20 laminated on the wafer 10, and communication between adjacent wafers 10 is achieved through the connection layer 21 and the conductive vias 22 connecting the connection layers 21 within adjacent dielectric layers 20. For example, in the embodiment shown in fig. 2, the interconnect layer portion of the first wafer 10A exposes the surface of the first wafer 10A, and the connection layer 21 in the dielectric layer 20A is connected to the exposed portion of the interconnect layer of the first wafer 10A, that is, the connection layer 21 in the dielectric layer 20A is electrically connected to the interconnect layer of the first wafer 10A. The interconnect layer of the second wafer 10B is connected to the connection layer 21 within the dielectric layer 20B and the conductive vias 22 through the second wafer 10B connect the connection layer 21 within the dielectric layer 20A and the connection layer 21 within the dielectric layer 20B, thereby enabling communication between the first wafer 10A and the wafer 10B. It is understood that the communication between the wafer 10B and the wafer 10C and the electrical connection between the wafer 10C and the wafer 10D may be similar to the electrical connection between the first wafer 10A and the wafer 10B, and will not be described herein.

It should be noted that, in the present application, the number of conductive vias 22 connected between two adjacent dielectric layers 20 is plural, the plurality of conductive vias 22 pass through the wafer 10 between two adjacent dielectric layers 20, and the positions and structures of the conductive vias 22 passing through each die 11 of the wafer 10 and passing through the die 11 are the same. In addition, the positions of the connection layers 21 of the dielectric layer 20 corresponding to each die 11 have the same structure, and the conductive vias 22 arranged in each die 11 are connected with the connection layers 21 arranged at the corresponding positions, so that the multi-wafer stack structure 100 can be cut to obtain a plurality of bare chips with the same structure, and mass production of the bare chips is realized. In addition, the adjacent crystal grains 11 in the cut bare chip can be electrically connected, so that the performance of the bare chip is improved.

In the embodiment of the present application, the dielectric layer 20 between two adjacent wafers 10 is a first dielectric layer, and the outermost dielectric layer 20 of the multi-wafer stack structure 100 is a second dielectric layer. The first dielectric layer includes a first inorganic dielectric layer 23, a first connection layer 21A, and a second inorganic dielectric layer 24 sequentially stacked on the wafer 10. The second dielectric layer includes a third inorganic dielectric layer 25 and a second connection layer 21B sequentially stacked on the wafer 10. The first connection layer 21A is the connection layer 21 of the first dielectric layer. The second connection layer 21B is the connection layer 21 of the second dielectric layer. For example, in the embodiment shown in fig. 2, the dielectric layers 20A, 20B, and 20C are first dielectric layers, and the dielectric layer 20D is a second dielectric layer. The dielectric layers 20A, 20B, and 20C each include a first inorganic dielectric layer 23, a first connection layer 21A, and a second inorganic dielectric layer 24 stacked in this order, and the dielectric layer 20D includes a third inorganic dielectric layer 25 and a second connection layer 21B stacked. Referring to fig. 3, fig. 3 is a schematic cross-sectional view of a multi-wafer stack structure 100 according to another embodiment of the disclosure. In this embodiment, the multi-wafer stacking structure 100 only includes a first wafer 10A and a second wafer 10B stacked together, the dielectric layer 20A between the first wafer 10A and the second wafer 10B is a first dielectric layer, and the dielectric layer 20B on the side of the second wafer 10B away from the first wafer 10A is a second dielectric layer. The dielectric layer 20A includes a first inorganic dielectric layer 23, a first connection layer 21A, and a second inorganic dielectric layer 24, which are stacked in this order, and the dielectric layer 20B includes a third inorganic dielectric layer 25 and a second connection layer 21B, which are stacked.

In the embodiment of the present application, the dielectric layer 20 is a rewiring layer (redistribution layer, RDL), that is, the dielectric layer 20 can be used to transfer the outgoing interface of the wafer 10 to other positions, so as to facilitate connection with the adjacent wafer 10. The adjacent wafers 10 can be connected to different positions of the connection layer 21 in the dielectric layer 20, so that the connection between the two adjacent wafers 10 can be realized without the need of oppositely arranging the connection interfaces (the positions on the wafers 10 for outputting or inputting signals) of the adjacent wafers 10, thereby being convenient for manufacturing and stacking the wafers 10. In this embodiment, the redistribution layer may include one or more redistribution layers, that is, the connection layer 21 includes at least one routing layer 211, and in this embodiment, the first connection layer 21A and the second connection layer 21B each include at least one routing layer 211. When the wiring layers 211 in the connection layer 21 are multiple layers, the connection layer 21 further includes an intermediate inorganic dielectric layer 212 disposed between two adjacent wiring layers 211. The intermediate inorganic dielectric layer 212 is provided with a via 213, and two adjacent wiring layers 211 are communicated through the via 213. In this embodiment, each wiring layer 211 includes metal wires, and the metal wires in adjacent wiring layers 211 are connected through vias 213, so as to realize electrical connection between two adjacent wiring layers 211. The via 213 is a structure formed by providing a hole in the inorganic dielectric layer and filling the hole with a conductive material.

For example, in the embodiment shown in fig. 2, the dielectric layer 20 includes one trace layer 211, i.e., only one trace layer 211 in the first connection layer 21A of the first dielectric layer and the second connection layer 21B of the second dielectric layer. The first wafer 10A and the second wafer 10B are connected to the wiring layer 211 of the first connection layer 21A therebetween, thereby achieving electrical connection between the first wafer 10A and the second wafer 10B. The fourth wafer 10D is connected to the trace layer 211 of the second connection layer 21B, and the signal transmitted in the fourth wafer 10D can be transmitted through the trace layer 211 of the second connection layer 21B. Referring to fig. 5, an embodiment of fig. 5 is a schematic cross-sectional view of a multi-wafer stack structure 100 according to another embodiment of the present application. The difference between this embodiment and the embodiment shown in fig. 2 is that: the first connection layer 21A and the second connection layer 21B are two layers of wiring layers 211, an intermediate inorganic dielectric layer 212 is arranged between two adjacent layers of wiring layers 211, a via hole 213 is arranged on the intermediate inorganic dielectric layer 212, and two ends of the via hole 213 are respectively connected with two adjacent layers of wiring layers 211. It is understood that in some embodiments, the number of the trace layers 211 of the first connection layer 21A and the second connection layer 21B may be three or more. In some embodiments, the number of the trace layers 211 of the first connection layer 21A and the second connection layer 21B may be the same or different. Also, the number of the trace layers 211 of the first connection layer 21A between different wafers 10 may be the same or different.

In some embodiments, the second connection layer 21B of the second dielectric layer further includes a spacer 214. The pad 214 is embedded in the second dielectric layer and electrically connected to the wiring layer of the wafer 10 corresponding to the second dielectric layer. The spacer 214 exposes the second dielectric layer on a side of the wafer 10 facing away from the dielectric layer 20 on which it is disposed. For example, in the embodiment shown in fig. 2, the spacer 214 is embedded within the dielectric layer 20D and is connected to the interconnect layer of the wafer 10D by the via 213. The side of the spacer 214 facing away from the wafer 10D exposes the dielectric layer 20D.

The spacer 214 is used to connect with other structures outside the multi-wafer stack structure 100. After the multi-wafer stack structure 100 is cut to obtain a bare chip, the bare chip can be connected with other external structures through the pad 214, so that communication between the bare chip and other external structures is realized. In some embodiments, the pads 214 have solder balls or bond wires bonded thereto, through which the bare chip is connected to other structures. In some embodiments of the present application, the metal trace of the trace layer 211 in the outermost dielectric layer 20 (i.e., the second dielectric layer) may also at least partially expose the dielectric layer 20 on the side facing away from the wafer 10, and the metal trace of the exposed dielectric layer 20 may be connected with other structures outside the multi-wafer stack structure 100. That is, after the multi-wafer stack structure 100 is cut to obtain a bare chip, the bare chip can be connected with other external structures through the metal wires exposed out of the dielectric layer 20, so that communication between the bare chip and other external structures is realized. For example, in the embodiment shown in fig. 2, solder balls 5 are soldered to both the pads 214 and the metal traces that expose the dielectric layer 20. The bare chip 3 obtained by cutting the multi-wafer stack structure 100 in the embodiment of the present application is connected to the substrate 1 through the solder ball 5, so as to achieve communication between the substrate 1 and the bare chip 3.

In some embodiments of the present application, the materials of the via 213 and the filled conductive material in the conductive via 22 and the metal traces of the trace layer 211 and the pads 214 may be the same, and may be conductive materials such as metal copper or metal aluminum. In some embodiments, the metal traces of the trace layer 211 and the pads 214 can be obtained by the same process.

The first inorganic dielectric layer 23, the second inorganic dielectric layer 24, the third inorganic dielectric layer 25, and the intermediate inorganic dielectric layer 212 are all formed using an inorganic dielectric material. Wherein, dielectric material refers to a material with resistivity exceeding 10 ohm/m. In the embodiment of the application, the inorganic dielectric material is formed by adopting an inorganic material containing Si element. For example, in some embodiments, the inorganic dielectric material may be silicon oxide, silicon nitride, silicon oxycarbide, boron-phosphorus-silicate glass, or the like. In the embodiment of the present application, the inorganic dielectric materials forming the first inorganic dielectric layer 23, the second inorganic dielectric layer 24, the third inorganic dielectric layer 25, and the intermediate inorganic dielectric layer 212 may be the same or different. Also, the inorganic dielectric materials forming the first dielectric layer comprising the first inorganic dielectric layer 23, the second inorganic dielectric layer 24, or the intermediate inorganic dielectric layer 212 between different wafers 10 may be the same or different. In the practice of the present application, the inorganic dielectric materials of the first inorganic dielectric layer 23, the second inorganic dielectric layer 24, or the intermediate inorganic dielectric layer 212 are the same. The first inorganic dielectric layer 23 and the second inorganic dielectric layer 24 are capable of spacing the first connection layer 21A from the wafer 10 to avoid the influence of the wafer 10 on the signal transmission in the first connection layer 21A. Also, the dielectric layer 20 can space the two wafers 10 apart to achieve insulation between the two wafers 10. For example, in the embodiment shown in fig. 2, a first connection layer 21A within a dielectric layer 20A is spaced apart from a first wafer 10A by a first inorganic dielectric layer 23 and is spaced apart from a second wafer 10B by a second inorganic dielectric layer 24. The first wafer 10A is spaced apart from the second wafer 10B by a dielectric layer 20A. In the embodiment of the present application, the third inorganic dielectric layer 25 is capable of isolating the second connection layer 21B from the wafer 10. For example, in the embodiment shown in fig. 2, the second connection layer 21B within the dielectric layer 20D is spaced apart from the fourth wafer 10D by a third inorganic dielectric layer 25.

In the present application, stacking a plurality of wafers 10 and allowing communication between the wafers 10 enables stacking of components in the stacking direction of the multi-wafer stack structure 100. In the present application, a plurality of bare chips are obtained by cutting the multi-wafer stack structure 100, and then the bare chips are packaged to obtain the desired chips. Because the components in the multi-wafer stacking structure 100 are stacked in the stacking direction of the wafer 10, the components in the finally obtained chip can be stacked in the thickness direction, that is, three-dimensional stacking of the components in the chip is realized, so that the density of the components in the chip is improved, the occupied area of the chip is prevented from being increased, the components in the chip can be increased, and the performance of the chip is improved while the occupied area of the chip is prevented from being increased. In some embodiments of the present application, at least a portion of the wafers 10 are thinned during stacking of the wafers 10, so that the thickness of at least a portion of the wafers 10 in the multi-wafer stacking structure 100 is reduced, and the thickness of the chip is reduced as much as possible while the components in the chip are increased, thereby further improving the density of the components in the chip. In some embodiments, the thinned wafer 10 has a thickness less than or equal to 50 μm.

In this application, different chips can be finally obtained by stacking different types and different numbers of wafers 10. The different types of wafers 10 refer to die cut by the wafers 10 and can be used as dies with different functional chips. For example, when the wafer 10 is a logic chip wafer, the die 11 obtained by dicing the logic chip wafer may be used as a bare chip of a logic chip, and the logic chip may perform signal processing on signals transmitted thereto; when the wafer 10 is a memory chip wafer, the crystal grain 11 obtained by cutting the memory chip wafer can be used as a bare chip of the memory chip, and the memory chip can realize the storage of signal data; when the wafer 10 is a photoelectric detection chip wafer, the die 11 obtained by cutting the photoelectric detection chip wafer can be used as a bare chip of the photoelectric detection chip, and the photoelectric detection chip comprises a photoelectric detection circuit, and can detect optical signals and convert the detected optical signals into electrical signals.

For example, referring to fig. 6, fig. 6 is a schematic cross-sectional view of a multi-wafer stack structure 100 according to an embodiment of the disclosure. The die package obtained by dicing the multi-wafer stack structure 100 of the present embodiment is a high bandwidth memory chip. In the multi-wafer stacking structure 100 of the present embodiment, the number of the wafers 10 is five, and the five wafers 10 include one logic chip wafer 12 and four memory chip wafers 13 sequentially stacked on the logic chip wafer 12. The high-bandwidth memory chip obtained in the embodiment can be applied to a high-bandwidth memory, and signals can be processed by the logic chip and then transmitted to the memory chip for storage, or the logic chip extracts the signals stored in the memory chip and transmits the signals after processing. In the embodiment of the application, the memory chip may be a dynamic random access memory (Dynamic Random Access Memory, DRAM) or other memory chip. It will be appreciated that in the multi-wafer stack structure 100 of the embodiment of the present application, the number of the memory chip wafers 13 may be increased again according to the requirement to achieve higher bandwidth.

Referring to fig. 7, fig. 7 is a schematic cross-sectional view of a multi-wafer stack structure 100 according to another embodiment of the disclosure. The bare chip obtained by cutting the multi-wafer stack structure 100 of the present embodiment is packaged, and the chip obtained after packaging the bare chip is a CMOS (Complementary Metal Oxide Semiconductor ) image sensor chip (CMOS Image Sensor, CIS). The number of the wafers 10 of the multi-wafer stack structure 100 of the present embodiment is three, and the three wafers 10 include one photo-detection chip wafer 14, and a logic chip wafer 12 and a memory chip wafer 13 sequentially stacked on the photo-detection chip wafer 14. In this embodiment, the photodetection chip of the CMOS image sensor chip converts the optical signal into an electrical signal and transmits the electrical signal to the logic chip, and the electrical signal is stored in the memory chip after being processed by the logic chip. Alternatively, in some embodiments, the optical signal is converted into an electrical signal by the photodetection chip and then stored in the memory chip, and the logic chip extracts the signal from the memory chip and processes the signal and then transmits the signal.

The present application also provides a method for manufacturing the multi-wafer stack structure 100, which is used for forming the multi-wafer stack structure 100. Referring to fig. 8-18, fig. 8 is a flowchart illustrating the multi-wafer stack structure 100 of fig. 3. Fig. 9 is a flowchart showing the specific steps of step 110 in the flowchart shown in fig. 8. Fig. 10-18 are schematic cross-sectional views of a multi-wafer structure 100 for each step of the flowcharts shown in fig. 8 and 9. Specifically, the method for manufacturing the multi-wafer stack structure 100 includes:

Step 110: referring to fig. 10 to 12, a first inorganic dielectric layer 23, a first connection layer 21A and a second inorganic dielectric layer 24 are sequentially formed on the surface of the first wafer 10A, and the first connection layer 21A is electrically connected to the first wafer 10A.

In this embodiment, the first dielectric layer 20A is laminated on a surface of the first wafer 10A away from the substrate, i.e. the first dielectric layer 20A covers the interconnection layer of the first wafer 10A. It will be appreciated that in some embodiments, the first dielectric layer 20A may also be laminated to a side of the first wafer 10A remote from the interconnect layer.

In the embodiment of the present application, please refer to fig. 9, fig. 9 is a schematic flowchart of step 110 in fig. 8. Step 110 specifically includes:

step 111: referring to fig. 10, a first inorganic dielectric layer 23 is formed on the surface of the first wafer 10A.

In this application, the first inorganic dielectric layer 23 is formed using an inorganic dielectric material. Wherein, dielectric material refers to a material with resistivity exceeding 10 ohm/m. In the embodiment of the application, the inorganic dielectric material is formed by adopting an inorganic material containing Si element. For example, the inorganic dielectric material of the present application may be any of inorganic dielectric materials such as silicon oxide, silicon nitride, silicon oxycarbide, and boron-phosphorus-silicate glass.

In the embodiment of the present application, the first inorganic dielectric layer 23 may be formed on the first wafer 10A by any of deposition methods of inorganic materials such as chemical vapor deposition, sputtering deposition, ion beam deposition, laser assisted deposition, physical vapor deposition, atomic layer deposition, and molecular beam epitaxy deposition.

Step 112: referring to fig. 11, a first connection layer 21A is formed on a surface of the first inorganic dielectric layer 23 facing away from the first wafer 10A, and the first connection layer 21A is electrically connected to the first wafer 10A.

In an embodiment of the present application, the first connection layer 21A includes only one routing layer 211, and the routing layer 211 is connected to the interconnection layer of the first wafer 10A to realize the electrical connection between the first connection layer 21A and the first wafer 22A. In this embodiment, a recess 23a is formed on the first inorganic dielectric layer 23 by a patterning process, and then a through hole 23b is extended from the bottom wall of the recess 23a to the first wafer 10A, where the through hole 23b extends to a position where the surface interconnection layer of the first wafer 10A is exposed. Alternatively, in some embodiments, the interconnect layer of the first wafer 10A does not expose the surface of the first wafer 10A, and then the via 23b extends into the first wafer 10A and connects with the interconnect layer of the first wafer 10A. Then, the through holes 23b and the grooves 23a are filled with conductive material, so that the wiring layer 211 and the via holes 213 are obtained, and the wiring layer 211 is connected with the interconnection layer of the first wafer 10A through the via holes 213. The patterning process specifically comprises the following steps: a photoresist layer is formed on the first inorganic dielectric layer 23, the photoresist layer is patterned by a photomask, the photoresist layer at the corresponding position of the recess 23a is removed, and then the recess 23a is formed by dry etching or wet etching. Referring again to the patterning process described above, a through hole 23b is formed from the bottom wall of the recess 23a into the first wafer 10A. In some embodiments, the grooves 23a and the perforations 23b may also be formed by laser etching or the like. It can be appreciated that, in the embodiment of the present application, since each wafer 10 includes the dies 11 arranged in an array, the metal traces of the trace layer 211 of the first connection layer 21A corresponding to the positions of the dies 11 of each wafer 10 are also identical, that is, the first connection layer 21A includes a plurality of trace areas arranged in an array, and the trace structures in each trace area are identical, so that the structure of the finally cut multi-wafer stack structure 100 to obtain a plurality of bare chips is identical.

In this embodiment, the grooves 23a and the through holes 23b are filled with conductive material by chemical vapor deposition, sputtering deposition, ion beam deposition, laser assisted deposition, physical vapor deposition, atomic layer deposition, molecular beam epitaxy deposition, or the like. It will be appreciated that in some embodiments, the conductive material may be deposited on the walls of the through holes 23b, and then other conductive or insulating materials may be deposited in the through holes 23b, so as to achieve the conductive effect of the through holes 213. The conductive material can be gold, silver, copper, aluminum and other conductive materials with good conductive effect. In this embodiment, the conductive material filled in the through hole 23b is metallic copper.

In this embodiment, the interconnection layer of the first wafer 10A partially exposes the surface of the first wafer 10A, and the via 213 extends to the surface of the first wafer 10A and is connected to the exposed portion of the interconnection layer of the first wafer 10A, i.e. the connection between the first wafer 10A and the routing layer 211 can be achieved. In other embodiments of the present application, the interconnect layer of the first wafer 10A does not expose the surface of the first wafer 10A, and therefore, the via 213 needs to extend into the first wafer 10A and connect with the interconnect layer of the first wafer 10A to electrically connect the trace layer 211 with the first wafer 10A.

When the wiring layer 211 included in the first connection layer 21A is a plurality of layers (as shown in fig. 5), after the wiring layer 211 is formed on the first inorganic dielectric layer 23 and the wiring layer 211 is electrically connected to the first wafer 10A, an intermediate inorganic dielectric layer 212 is further formed on the first inorganic dielectric layer 23 on which the wiring layer 211 is formed. Then, another wiring layer 211 is formed on the intermediate inorganic dielectric layer 212, and the another wiring layer 211 formed on the intermediate inorganic dielectric layer 212 and the wiring layer 211 formed on the first inorganic dielectric layer 23 are electrically connected through the via hole 213. Wherein the intermediate inorganic dielectric layer 212 is also formed by deposition of an inorganic dielectric material. It is understood that the inorganic dielectric material forming the intermediate inorganic dielectric layer 212 may be the same as or different from the material forming the first inorganic dielectric layer 23. In this embodiment, the formation of the intermediate inorganic dielectric layer 212 is the same as that of the first inorganic dielectric layer 23, and will not be described here.

The wiring layer 211 is formed on the intermediate inorganic dielectric layer 212 in the same manner as the wiring layer 211 is formed on the first inorganic dielectric layer 23. Namely, a groove is formed on the formed intermediate inorganic dielectric layer 212 by a patterning process, and a wiring layer 211 perforated to the first inorganic dielectric layer 23 is provided on the bottom wall of the groove. Conductive material is deposited in the grooves and the through holes by various modes such as sputtering deposition, ion beam deposition, laser assisted deposition, physical vapor deposition and the like, the conductive material is deposited in the grooves to form a wiring layer 211 on the intermediate inorganic dielectric layer 212, the through holes are deposited in the through holes to form a via 213, and the via 213 is connected with the wiring layer 211 on the first inorganic dielectric layer 23 and the wiring layer 211 on the intermediate inorganic dielectric layer 212. It is understood that when the trace layer 211 in the first connection layer 21A is more than one layer (i.e., three or more layers), the intermediate inorganic dielectric layer 212 and the trace layer 211 may be stacked continuously with reference to the above-mentioned formation manner of the intermediate inorganic dielectric layer 212 and the trace layer 211 on the intermediate inorganic dielectric layer 212, and the adjacent trace layers 211 may be electrically connected to form the first connection layer 21A including the trace layer 211 of three or more layers.

Step 113: referring to fig. 12, a second inorganic dielectric layer 24 is formed on a surface of the first connection layer 21A facing away from the first wafer 10A.

In the embodiment of the present application, the second inorganic dielectric layer 24 is also formed of an inorganic dielectric material, and the materials of the first inorganic dielectric layer 23 and the intermediate inorganic dielectric layer 212 may be the same or different than those of the first inorganic dielectric layer. In this embodiment, the formation of the second inorganic dielectric layer 24 can refer to the formation of the first inorganic dielectric layer 23, and will not be described herein.

Step 120: referring to fig. 13, a third inorganic dielectric layer 25 is formed on the surface of the second wafer 10B.

The third inorganic dielectric layer 25 is also formed of an inorganic dielectric material, wherein the inorganic dielectric material forming the third inorganic dielectric layer 25 may be the same as or different from the inorganic dielectric material forming the first inorganic dielectric layer 23. In this embodiment, the manner of forming the third inorganic dielectric layer 25 on the surface of the second wafer 10B may refer to the manner of forming the first inorganic dielectric layer 23 on the first wafer 10A, and will not be described herein.

In this embodiment, the third inorganic dielectric layer 25 is formed on the side of the second wafer 10B away from the substrate thereof. It will be appreciated that in some embodiments, the dielectric layer 20B may also be formed on the side of the second wafer 10B remote from its interconnect layer.

It will be appreciated that step 120 may also be provided before step 110.

Step 130: referring to fig. 16, a surface of the second wafer 10B facing away from the third inorganic dielectric layer 25 is bonded and fixed to a surface of the second inorganic dielectric layer 24 facing away from the first wafer 10A through a fusion bonding process.

In this embodiment, the surface of the second wafer 10B facing away from the third inorganic dielectric layer 25 and the surface of the first dielectric layer facing away from the first wafer 10A may be fixed together by a fusion bonding process, so as to fix the first wafer 10A and the second wafer 10B. In this embodiment, the surface of the second wafer 10B facing away from the third inorganic dielectric layer 25 and the surface of the second inorganic dielectric layer 24 facing away from the first wafer 10A are fixed by a fusion bonding process. The specific steps of fixing the second wafer 10B and the second inorganic dielectric layer 24 through the fusion bonding process may include: the surface of the second inorganic dielectric layer 24 facing away from the first wafer 10A and the surface of the second wafer 10B facing away from the third inorganic dielectric layer 25 are subjected to surface treatment by means of plasma or magnetron sputtering or the like, so that the surface of the second inorganic dielectric layer 24 facing away from the first wafer 10A and the surface of the second wafer 10B facing away from the third inorganic dielectric layer 25 are activated, and the bonding reaction can be performed more easily. After the surface treatment is performed on the second inorganic dielectric layer 24 and the second wafer 10B, the second inorganic dielectric layer 24 is contacted with the surface of the second wafer 10B after the surface treatment, the second inorganic dielectric layer 24 and the second wafer 10B are subjected to heat treatment, and bonding is generated between the surface of the second inorganic dielectric layer 24 facing away from the first wafer 10A and the surface of the second wafer 10B facing away from the third inorganic dielectric layer 25 after the heat treatment, that is, the second wafer 10B is fixed with the second inorganic dielectric layer 24. Wherein, the heat treatment can comprise the steps of heating, heat preservation, annealing and the like.

In this embodiment, since the surface of the second inorganic dielectric layer 24 facing away from the first wafer 10A and the surface of the second wafer 10B facing away from the third inorganic dielectric layer 25 are both inorganic material layers, the fixing can be performed by adopting a fusion bonding manner. Compared with the method that the first connection layer 21A is formed on the surface of the first wafer 10A, the second connection layer 21B is formed on the surface of the second wafer 10B, and the conductive through holes 22 for connecting the second connection layer 21B are formed in the second wafer 10B, then the first wafer 10A and the second wafer 10B are bonded together by a hybrid bonding process (i.e. the two sides required to be bonded and fixed include an inorganic material and a metal material, and the two sides required to be bonded and fixed are bonded with the inorganic material and the metal material by the hybrid bonding process), and the conductive through holes 22 in the second wafer 10B are connected with the first connection layer 21A to realize the electrical connection between the first wafer 10A and the second wafer 10B, the realization process is less difficult because the bonding of the metal material and the metal material does not exist. The implementation process difficulty can be lower, the annealing temperature can be lower, and the heat preservation time can be lower.

In addition, in the embodiment of the application, by performing surface treatment on the surface of the second wafer 10B, which is away from the third inorganic dielectric layer 25, and the surface of the second inorganic dielectric layer 24, which is away from the first wafer 10A, so as to activate the surface of the second wafer 10B, which is away from the third inorganic dielectric layer 25, and the surface of the second inorganic dielectric layer 24, which is away from the first wafer 10A, the temperature required for annealing can be reduced, thereby reducing the process difficulty and the manufacturing cost. In some embodiments, the annealing temperature may be around 200 ℃. It will be appreciated that in some embodiments, it is not necessary to perform surface treatment on the side of the second wafer 10B facing away from the third inorganic dielectric layer 25 and the side of the second inorganic dielectric layer 24 facing away from the first wafer 10A, and the fixation of the side of the second wafer 10B facing away from the third inorganic dielectric layer 25 and the side of the second inorganic dielectric layer 24 facing away from the first wafer 10A can still be achieved by adopting a high-temperature annealing treatment. It is understood that the sequence of steps 110, 120 and 130 may be interchanged, so long as the step 130 is ensured to be located after the step 120. In some embodiments, after step 120 and before step 130, it may further include:

step 121: referring to fig. 14, a transfer substrate 30 is fixed on a side of the third inorganic dielectric layer 25 facing away from the second wafer 10B.

In the present embodiment, the transfer substrate 30 may be glass, bulk silicon, sacrificial silicon, or a silicon substrate similar to the substrate of the wafer 10. The transfer substrate 30 may be secured to a side of the third inorganic dielectric layer 25 facing away from the second wafer 10B by a fusion bonding process. The fusion bonding process specifically comprises the following steps: the surface of the third inorganic dielectric layer 25 facing away from the second wafer 10B and the surface of the transfer substrate 30 are subjected to surface treatment by means of plasma or magnetron sputtering or the like, so that the surfaces of the third inorganic dielectric layer 25 and the transfer substrate 30 are activated, and the bonding reaction can be performed more easily. After the surfaces of the third inorganic dielectric layer 25 and the transfer substrate 30 are subjected to surface treatment, the third inorganic dielectric layer 25 is contacted with the surface of the transfer substrate 30 after the surface treatment, the third inorganic dielectric layer 25 and the transfer substrate 30 are subjected to heat treatment, and bonding is generated between the third inorganic dielectric layer 25 and the transfer substrate 30 after the heat treatment, that is, the transfer substrate 30 is fixed with the third inorganic dielectric layer 25, so that the transfer substrate 30 and the second wafer 10B can be connected and fixed through the third inorganic dielectric layer 25. In this embodiment, the third inorganic dielectric layer 25 and the transfer substrate 30 are fixed by the fusion bonding process, so as to realize the fixed connection between the second wafer 10B and the transfer substrate 30, and compared with the mode of fixing the third inorganic dielectric layer 25 and the transfer substrate 30 by using viscose, other intermediate layers do not need to be introduced, so that the introduction of other chemical impurities is avoided, organic pollution is not introduced, and the quality of the finally obtained chip can be improved. In addition, in the embodiment of the present application, the third inorganic dielectric layer 25 and the transfer substrate 30 are both inorganic material layers, and can be fixed by adopting a fusion bonding process, so that the process difficulty is lower compared with the fixing achieved by a hybrid bonding mode.

In this embodiment, by performing surface treatment on the surface of the third inorganic dielectric layer 25 facing away from the second wafer 10B and the surface of the transfer substrate 30 facing the third inorganic dielectric layer 25, so as to activate the surface of the third inorganic dielectric layer 25 facing away from the second wafer 10B and the surface of the transfer substrate facing the third inorganic dielectric layer, the temperature required for annealing can be reduced, thereby reducing the process difficulty and the manufacturing cost. In some embodiments, the annealing temperature may be around 200 ℃. It will be appreciated that in some embodiments, it is also unnecessary to perform surface treatment on the surface of the third inorganic dielectric layer 25 facing away from the second wafer 10B and the surface of the transfer substrate 30 facing the third inorganic dielectric layer 25, and the fixation of the surface of the third inorganic dielectric layer 25 facing away from the second wafer 10B and the surface of the transfer substrate 30 facing the second dielectric layer 24 can still be achieved by adopting a high-temperature annealing treatment.

In the present application, the inorganic dielectric material forming the third inorganic dielectric layer 25 is formed by an inorganic material containing Si element, so that the third inorganic dielectric layer 25 and the transfer substrate 30 can be conveniently and fixedly connected by a fusion bonding process. In this embodiment, the inorganic dielectric materials forming the first inorganic dielectric layer 23, the intermediate inorganic dielectric layer 212, the second inorganic dielectric layer 24 and the third inorganic dielectric layer 25 may also be formed by using an inorganic material containing Si element, so that the sub-inorganic dielectric layer 23, the intermediate inorganic dielectric layer 212, the second inorganic dielectric layer 24 or the third inorganic dielectric layer 25 and other wafers 10 can be conveniently and fixedly connected through a fusion bonding process, other intermediate layers are not required to be introduced, the process implementation difficulty is reduced, the introduction of other chemical impurities is avoided, and the organic pollution is not introduced, thereby improving the quality of the finally obtained chip.

Step 122: referring to fig. 15, the second wafer 10B is thinned.

Specifically, the second wafer 10B is thinned by a thinning process. The thinning process may be a physicochemical polishing, that is, polishing by a polishing disc and chemical solvent etching, to thin the second wafer 10B. In the embodiment of the present application, the substrate of the second wafer 10B is thinned to realize thinning of the second wafer 10B, so that the thickness of the second wafer 10B can be reduced on the basis of ensuring the function of the second wafer 10B, thereby reducing the thickness of the finally obtained multi-wafer stacked structure 100. In addition, in the present application, the second wafer 10B is thinned after the second wafer 10B and the transfer substrate 30 are fixed, so that better thinning uniformity can be achieved when the second wafer 10B is thinned. Compared with the mode of directly thinning the second wafer 10B, the method can avoid warping of the thinned second wafer 10B and ensure the quality of the thinned second wafer 10B.

In some embodiments, the second wafer 10B may be rough machined to a size close to a desired size by physical grinding such as mechanical grinding, and then fine machined to a desired size of the second wafer 10B by chemical solvent etching, etc., to ensure the accuracy of thinning.

In some embodiments, the thinning process further includes a planarization process, that is, after the physicochemical polishing is completed, the thinned substrate of the second wafer 10B is planarized, and the surface of the planarized second wafer 10B is smooth, so that the subsequent operation can be facilitated, and the quality of the obtained multi-wafer stack structure 100 is ensured. In embodiments of the present application, the planarization process may be chemical-mechanical-polishing (CMP), which makes the surface flat and smooth by a combination of chemical reaction and mechanical polishing. It will be appreciated that in some embodiments, the planarization process may also include other processes that resputtered deposited films to planarize the surface or etch the surface with a gas cluster ion beam to planarize the surface, among others.

In some embodiments, step 130 is followed by step 131: referring to fig. 17, the transfer substrate 30 is removed.

In this embodiment, the manner of removing the transfer substrate 30 may be the same as the thinning process of the second wafer 10B, that is, the transfer substrate 30 may be removed by physicochemical polishing. In some embodiments, the transfer substrate 30 may be roughly removed by mechanical rough grinding to a size close to the desired size, and then finely ground by chemical means or the like to completely remove the transfer substrate 30, so as to avoid damaging the third inorganic dielectric layer 25 or the second wafer 10B due to excessive grinding during removal of the transfer substrate 30. In some embodiments, after removing the transfer substrate 30, the planarization treatment is required to be performed on the dielectric layer 20B, so that the planarized surface of the dielectric layer 20B is smooth, which is convenient for the subsequent operation, and ensures the quality of the obtained multi-wafer stack structure 100.

Step 140: referring to fig. 18, a second connection layer 21B is formed on a surface of the third inorganic dielectric layer 25 facing away from the second wafer 10B, and a conductive via 22 passing through the third inorganic dielectric layer 25, the second wafer 10B and the second inorganic dielectric layer is formed, wherein one end of the conductive via 22 is connected to the second connection layer 21B, and the other end is connected to the first connection layer 21A.

In this embodiment, the second connection layer 21B includes a wiring layer 211, and the wiring layer 211 is connected to the conductive via 22 to electrically connect the second connection layer 21B to the conductive via 22. In this embodiment, the manner of forming the conductive via hole 22 and the second connection layer 21B is the same as the manner of forming the via hole 213 and the first connection layer 21A in step 110, and specifically includes: a recess 25a is formed on a surface of the third inorganic dielectric layer 25 facing away from the second wafer 10B through a patterning process, and a through hole 25B is formed from a bottom wall of the recess 25a into the second wafer 10B, such that the through hole 25B extends to the trace layer 211 of the first connection layer 21A. Then, the through holes 25B and the grooves 25a are filled with conductive material, the through holes 25B are filled with conductive material to form conductive via holes 22, the grooves 25a are filled with conductive material to form wiring layers 211 of the second connection layers 21B, one ends of the conductive via holes 22 are connected with the second connection layers 21B, and the other ends are connected with the first connection layers 21A. The patterning process specifically comprises the following steps: a photoresist layer is formed on the third inorganic dielectric layer 25, the photoresist layer is patterned by a photomask, the photoresist layer at the corresponding position of the recess 25a is removed, and then the recess 25a is formed by dry etching or wet etching. Referring again to the patterning process described above, a through hole 25B is formed from the bottom wall of the recess 25a into the second wafer 10B. In some embodiments, the grooves 25a and the perforations 25b may also be formed by laser etching or the like.

In this embodiment, since each wafer 10 includes the dies 11 arranged in an array, the patterns of the metal traces of the second connection layer 21B corresponding to the positions of the dies 11 of each wafer 10 are also the same, that is, the second connection layer 21B includes a plurality of second trace areas arranged in an array, and the trace structures in each second trace area are the same, so that the structures of the multiple bare chips obtained by finally cutting the multi-wafer stacked structure 100 are the same.

In some embodiments of the present application, since there are only two wafers 10 in the multi-wafer stack structure 100, a surface of the trace layer 211 of the second connection layer 21B facing away from the second wafer 10B may partially expose the third inorganic dielectric layer 25. After the multi-wafer stacked structure 100 is cut to obtain a bare chip, the area where the trace layer 211 of the second connection layer 21B of the bare chip exposes the third inorganic dielectric layer 25 can be connected with other structures through solder balls or bonding wires, so as to realize communication between the bare chip and the other structures (such as the substrate 1 in fig. 1).

In the embodiment of the present application, the second connection layer 21B further includes a spacer 214. The spacer 214 is used to connect with other structures outside the multi-wafer stack structure 100. In this embodiment, the pad 214 and the trace layer 211 of the second connection layer 21B can be obtained by the same process. Specifically, when the wiring layer 211 of the second connection layer 21B is formed by patterning, the pad 214 is simultaneously patterned, and the pad 214 is electrically connected to the second wafer 10B. Specifically, a recess 25c is formed on the third inorganic dielectric layer 25 by a patterning process, and a through hole 25d is provided at the bottom of the recess 25c, the through hole 25d extending from the bottom of the recess 25c to the wiring layer of the second wafer 10B and electrically connected to the wiring layer of the second wafer 10B. Then, the through holes 25d and the grooves 25c are filled with a metal material, the metal material filled in the grooves 25c forms the pads 214, the metal material filled in the through holes 25d forms the vias 213, and the vias 213 electrically connect the pads 214 and the second wafer 10B.

In some embodiments, when the multi-wafer stacking structure 100 is obtained by stacking three or more wafers 10 (as shown in fig. 2), the second connection layer 21B formed in the step 140 may not be formed with the spacer 214, and further includes the step 150 after the step 160: a fourth inorganic dielectric layer is formed on the third inorganic dielectric layer 25, and further more wafers 10 are stacked on the second wafer 10B by referring to the steps 120 to 150, so as to obtain the multi-wafer stack structure 100 required in the present application, which is not described herein. It should be noted that, when the multi-wafer stacking structure 10 is obtained by stacking three or more wafers 10, the dielectric layer stacked on the side of the second wafer 10B facing away from the first wafer 10A is a first inorganic dielectric layer, and includes a third inorganic dielectric layer 25, a second connection layer 26, and a fourth inorganic dielectric layer. It should be noted that, when stacking the last wafer 10, referring to steps 120 to 140, the stacking of the last wafer 10 can be completed. For example, when three wafers 10 are stacked in the multi-wafer stacking structure, the required multi-wafer stacking structure can be obtained by repeating the steps 120 to 140 after the step 150. When there are four stacked wafers (as shown in fig. 2), it is necessary to repeat reference to steps 120 to 150 once again after step 150, and repeat reference to steps 120 to 140 once again, so as to obtain the desired multi-wafer stack structure. It should be noted that, when the connection layer 21 of the dielectric layer 20 is formed on the side of the last stacked wafer 10 facing away from the first wafer 10, the pad 214 is formed so as to electrically connect the finally obtained bare chip with other structures through the pad 214.

In this embodiment, the stacking manner of the wafers 10 is developed from the conventional two-dimensional stacking manner to the three-dimensional stacking manner by stacking the plurality of wafers 10 in the vertical direction (i.e., the direction perpendicular to the surface of the wafers 10), so that stacking of the components in the chip in the three-dimensional direction can be realized, and the performance of the chip is improved while the occupation area of the chip is increased. In some embodiments of the present application, when stacking to form the multi-wafer stack structure 100, the substrate of each wafer 10 needs to be thinned to minimize the thickness of the stacked multi-wafer stack structure 100 and minimize the volume occupied by the chips. In addition, the wafer 10 and the transfer substrate 30 are fixed, and then the substrate of the wafer is thinned, so that better thinning uniformity can be realized, and warping of the thinned wafer is avoided. In the method for forming the multi-wafer stack structure 100, no organic matter is applied to obtain the multi-wafer stack structure 100, so that organic pollution is prevented from being introduced in the forming process of the multi-wafer stack structure 100, and the quality of chips is improved.

In the embodiment of the present application, the substrate side of the wafer 10 is the back side thereof, and the interconnect layer side of the wafer is the front side thereof. The substrate of each wafer 10 is in contact with the interconnect layer of the wafer 10 adjacent thereto, i.e., the wafers are stacked in a back-to-face stack in this embodiment. In some embodiments, when several wafers 10 are stacked, the structures of the dies 11 in the wafers 10 can be fabricated using the same mask, and the structures of the dielectric layer 20 connecting the adjacent wafers 10 and the re-wiring layer formed in the dielectric layer 20 can be kept consistent, so that the manufacturing cost can be reduced as compared with other stacking methods (such as back-to-back stacking and face-to-face stacking), the use of different masks for fabricating the die 11 structures and the dielectric layer 20 in the wafers 10 is not required. In addition, in the embodiment of the present application, the back surface of the wafer 10 faces the front surface of the wafer 10 adjacent thereto, and when the conductive via hole is formed, the conductive via hole can be formed from the front surface of the wafer 10 like the back surface direction all the time, and compared with the manner of forming the conductive via hole from the back surface of the wafer 10 to the front surface direction of the wafer 10 in some embodiments, the process of etching to form the conductive via hole can be simpler, and the problem of bursting (blow out) of the wafer 10 is not easy to occur.

In some embodiments of the present application, a chip is provided, and the chip is obtained by packaging the diced bare die 3 of the multi-wafer stack structure 100. Referring to fig. 1, 2 and 19, the chip is formed by:

step 210, manufacturing the multi-wafer stack structure 100 according to the manufacturing method of the multi-wafer stack structure.

In step 220, the multi-wafer stack structure 100 is cut to obtain a plurality of bare chips 3. In the embodiment of the present application, the multi-wafer stack structure 100 is cut along the dicing gaps between the plurality of dies 11 on the wafer 10, thereby obtaining the bare chip 3.

In step 230, the bare chip 3 is electrically connected to at least one surface of the package substrate 1. In other words, the bare chip 3 may be provided on one surface of the package substrate 1, or the bare chip 3 may be provided on both opposite surfaces of the package substrate 1, and the bare chip 3 and the package substrate 1 may be electrically connected. In the embodiment of the present application, the bare chip 3 is electrically connected to the package substrate 1 by means of solder balls or bonding wires.

In step 240, a package layer 2 is formed on a surface of the package substrate 1 facing the bare chip 3, and the package layer 2 covers the bare chip 3, thereby obtaining a desired chip. The encapsulation layer 2 is formed of an encapsulation material such as resin, and the encapsulation layer 2 may be formed by compression molding or the like.

In some embodiments, after step 240, the method further comprises the steps of: and an external pin 4 is formed on one side of the packaging substrate 1, which is away from the packaging layer 2, and the connection and communication of the chip and other structures are realized through the external pin 4.

According to the embodiment of the application, the manufacturing method of the multi-wafer stacking structure is adopted, wafers are bonded (wafer to wafer bonding, W2W bonding) to the wafer stacking structure to obtain the multi-wafer stacking structure, the multi-wafer stacking structure is cut to obtain the bare chip, and the bare chip is packaged to obtain the required chip. Compared with a mode of stacking and bonding (die to die bonding, D2D bonding) the crystal grains to obtain a stacked structure and then cutting to obtain a bare chip, or a mode of stacking and bonding (die to wafer bonding, D2W bonding) the crystal grains to the wafer to obtain a stacked structure and then cutting to obtain the bare chip, the wafer does not need to be subjected to cutting treatment before stacking, and the influence of impurities generated by cutting on the stacking process can be avoided. In addition, when stacking, the alignment of a plurality of crystal grains on adjacent wafers can be realized through one-time alignment, and compared with the mode of stacking and bonding the crystal grains and the wafers, the alignment efficiency of the wafer stacking and bonding the crystal grains can be improved, and the alignment process difficulty is reduced. Moreover, the wafer can be subjected to the validity test before the die-to-die stacking bonding process, so that whether the die on each wafer is valid or not can be known. The die-to-die stacking bonding and die-to-wafer stacking bonding methods require testing the effectiveness of each die one by one, so that the process difficulty and the testing efficiency of the die obtained by the method are greatly reduced compared with those of die-to-die stacking bonding and die-to-wafer stacking bonding.

The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes or substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

The manufacturing method of the multi-wafer stacking structure is characterized by comprising the following steps:

sequentially forming a first inorganic dielectric layer, a first connecting layer and a second inorganic dielectric layer on the surface of a first wafer, wherein the first connecting layer is electrically connected with the first wafer;

forming a third inorganic dielectric layer on the surface of the second wafer;

bonding and fixing one surface of the second wafer, which is away from the third inorganic dielectric layer, and one surface of the second inorganic dielectric layer, which is away from the first wafer, through a fusion bonding process;

and forming a second connecting layer on one surface of the third inorganic dielectric layer, which is away from the second wafer, and forming a conductive via penetrating through the third inorganic dielectric layer, the second wafer and the second inorganic dielectric layer, wherein one end of the conductive via is connected with the second connecting layer, and the other end of the conductive via is connected with the first connecting layer.
The method of claim 1, wherein after forming the third inorganic dielectric layer on the surface of the second wafer and before bonding and fixing, by fusion bonding, a surface of the second wafer facing away from the third inorganic dielectric layer to a surface of the second inorganic dielectric layer facing away from the first wafer, further comprises:

fixing a transfer substrate on one side of the third inorganic dielectric layer away from the second wafer;

thinning the second wafer;

after bonding and fixing the surface of the second wafer, which is away from the third inorganic dielectric layer, and the surface of the second inorganic dielectric layer, which is away from the first wafer, through a fusion bonding mode, the method further comprises:

and removing the transfer substrate.
The method of claim 2, wherein the second wafer comprises a substrate and a device layer and an interconnect layer sequentially stacked on the substrate, and wherein the thinning the second wafer comprises:

and thinning the substrate of the second wafer.
The method of claim 2 or 3, further comprising, after the step of thinning the second wafer:

And flattening the thinned surface of the second wafer.
The method of claim 2, wherein the process of securing the transfer substrate to a side of the third inorganic dielectric layer facing away from the second wafer is a fusion bonding process.
The method of claim 5, wherein the fixing the transfer substrate to the side of the third inorganic dielectric layer facing away from the second wafer by the fusion bonding process comprises:

respectively carrying out surface treatment on the surface of the third inorganic dielectric layer facing away from the second wafer and the surface of the transfer substrate facing towards the third inorganic dielectric layer;

attaching the surface of the treated third inorganic dielectric layer, which is away from the second wafer, to the surface of the transfer substrate, which is towards the second dielectric layer;

and carrying out temperature treatment on the third inorganic dielectric layer and the transfer substrate so as to bond and fix the transfer substrate and one surface of the third inorganic dielectric layer, which is away from the second wafer.
The method of claim 6, wherein the temperature treatment comprises an annealing process.
The method for fabricating a multi-wafer stack structure according to any one of claims 1 to 5, wherein the first wafer and the second wafer each include a substrate, and a device layer and an interconnect layer sequentially stacked on the substrate, the first inorganic dielectric layer is formed on a side of the first wafer away from the substrate of the first wafer, and the third inorganic dielectric layer is formed on a side of the second wafer away from the substrate of the second wafer.
The method of claim 1, wherein the first connection layer comprises a first trace layer, a second trace layer, and an intermediate inorganic dielectric layer between the first trace layer and the second trace layer, and the step of forming the first connection layer on the surface of the first wafer comprises:

forming a first wiring layer on the surface of the first inorganic dielectric layer, which is away from the first wafer;

forming an intermediate inorganic dielectric layer on the surface of the first inorganic dielectric layer, which is provided with the first wiring layer and is away from the first wafer, wherein the intermediate inorganic dielectric layer covers the first wiring layer;

and forming the second wiring layer on the surface of the intermediate inorganic dielectric layer, which is away from the first wafer.
The method of claim 1, wherein bonding and fixing a side of the second wafer facing away from the third inorganic dielectric layer to a side of the second inorganic dielectric layer facing away from the first wafer by a fusion bonding process comprises:

carrying out surface treatment on one surface of the second wafer, which is away from the third inorganic dielectric layer, and one surface of the second inorganic dielectric layer, which is away from the first wafer;

bonding one surface of the second wafer, which is away from the third inorganic dielectric layer, with one surface of the second inorganic dielectric layer, which is away from the first wafer;

and carrying out temperature treatment on the second inorganic dielectric layer and the second wafer so as to bond and fix one surface of the second wafer, which is away from the third inorganic dielectric layer, with one surface of the second inorganic dielectric layer, which is away from the first wafer.
The method of claim 1, wherein the first, second and third inorganic dielectric layers are deposited by using an inorganic dielectric material, and the deposition methods of the first, second and third inorganic dielectric layers include any one of chemical vapor deposition, sputter deposition, ion beam deposition, laser-assisted deposition, physical vapor deposition, atomic layer deposition, and molecular beam epitaxy deposition.
The method of fabricating a multi-wafer stack structure according to claim 2, wherein after removing the transfer substrate, the method further comprises:

and flattening the surface of the third inorganic dielectric layer facing away from the second wafer.
The manufacturing method of the chip is characterized by comprising the following steps:

the multi-wafer stack structure manufactured according to the manufacturing method of the multi-wafer stack structure as claimed in any one of claims 1-12;

and cutting the multi-wafer stacking structure to obtain a plurality of bare chips.
The multi-wafer stacking structure is characterized by comprising a plurality of stacked wafers, wherein a dielectric layer is stacked on one surface of each wafer, and each dielectric layer comprises a connecting layer; the dielectric layer comprises a first dielectric layer and a second dielectric layer, two adjacent wafers pass through the first dielectric layer to be separated, and the outermost dielectric layer of the polycrystalline stacked structure is the second dielectric layer; the first dielectric layer comprises a first inorganic dielectric layer, a first connecting layer and a second inorganic dielectric layer which are sequentially stacked; the second dielectric layer comprises a third inorganic dielectric layer and a second connecting layer which are sequentially laminated; a conductive via is connected between two adjacent dielectric layers, and penetrates through the wafer between the two adjacent dielectric layers; the first inorganic dielectric layer and the second inorganic dielectric layer are both formed by adopting inorganic dielectric materials.
The multi-wafer stack structure of claim 14 wherein each of the wafers includes a substrate and device layers, interconnect layers, stacked in sequence on the substrate, the dielectric layers being stacked on a side of the device layers of the wafers facing away from the substrate.
The multi-wafer stack structure of claim 14 or 15, wherein the first connection layer and the second connection layer comprise one or more routing layers; when the wiring layers are multiple layers, an intermediate inorganic dielectric layer is arranged between every two adjacent wiring layers, a via hole is arranged in the intermediate inorganic dielectric layer, and the via hole is connected with the adjacent wiring layers.