CN117501433A - Electronic carrier power electronic device based on diamond wafer - Google Patents

Abstract

A power device electronics system comprising a thermal management configuration wherein a power electronic chip is attached to a copper substrate and a single crystal diamond substrate is attached to the copper substrate. The copper substrate is sandwiched between the first side of the diamond substrate and the power electronic chip.

Description

Electronic carrier power electronic device based on diamond wafer

Request priority benefit

The present application claims the priority of co-assigned, co-pending U.S. provisional patent application No. 63/243,662 (attorney docket No. DFI-004-pro 2) entitled "diamond wafer based electronic carrier power electronics" and co-pending U.S. provisional patent application No. 63/233,616 (attorney docket No. DFI-004-pro) entitled "diamond wafer based electronic carrier power electronics", the disclosures of which are incorporated herein by reference in their entirety.

Background

Improving energy efficiency of Electric Vehicle (EV) power electronics

Most power inverter architectures include converting direct voltage from a battery into a three-phase ac form compatible with an electric traction motor. The power conversion today ranges from 50 to 250kW (peak 400 kW), depending on the model. In the next few years, MW systems will emerge (truck industry, marine transport, and more importantly, air electric traffic). Each phase requires two power switches mounted in a so-called "half-bridge" topology. During operation, since the three phases are phase shifted by 120 degrees, there are always two switches closed simultaneously (ON) and the other four switches Open (OFF).

To evaluate inverter efficiency, conduction losses are calculated by multiplying the voltage difference at switch closing times the current flowing into the switch, and of course also by 6 (3x2=6 switches). The level of power loss generated is very large and designers are always trying to reduce power loss to increase driving range or reduce battery size. Some other considerations, such as wire bond stress and capacity, gate level power amplifier performance, and overall system size and cost, are also part of the many factors that must be considered when designing an electric traction inverter. Finally, so far, the rule of thumb for reducing power loss is "use of more silicon surface area or use of better heat sinks". Both of these "proposals" have significant drawbacks. The consideration of using more silicon switches does reduce power conduction losses because the "on" state current is shared between a greater number of switches, thus reducing power consumption, but switching losses increase accordingly, especially for IGBTs. Disadvantages are the use of exponential surface attachment, multiplication of weak links in the power path (such as wire bonds), die-to-die differences, physical distance expansion leading to unwanted parasitic inductances, and difficulty in perfectly synchronizing each die with their companion die, ultimately leading to unnecessary complexity and inefficiency of the deployed work. Cost considerations for completion prove that this theory is wrong.

On the other hand, cooling strategies have been of interest in experimental and research and development studies for many years. Designers are not only concerned with silicon improvements, but also recognize that lowering the operating temperature of the die may be a way to improve power efficiency, reduce cost, and improve reliability. While this intuition is certainly true, the materials currently available to ensure satisfactory results have far from been achieved.

Since the electrical and thermal paths for power silicon are identical and both very important, it is very challenging to disconnect them literally to direct the thermal paths to liquid coolant that needs to be electrically isolated for safety reasons and to have as short and elastic an electrical path as possible. This disconnect mechanism ("dielectric") was achieved by the techniques and means shown in fig. 1A-1C, which were not truly significantly developed over the last forty years, but which, although widely adopted, did not perform well.

Fig. 2 depicts a common architecture of a power device. Typically, the device comprises a silicon wafer 1 attached by an attachment 2 to a copper layout (copper layout) 3 thermally coupled to a coolant 6 via a substrate 4 and a dielectric material 5. The current flows mainly laterally in the copper layout 3 but mainly vertically from the die 1 through the attachment 2, the layout 3, the substrate 4 and the dielectric 5. This architecture is characterized by a relatively poor two-dimensional vector heat propagation in the thermal path between the silicon wafer 1 and the coolant 6. For example, if the coolant 6 is at a temperature of about 80 ℃, the die 1 is typically at a temperature of 175 to 200 ℃ due to thermal impedance in the thermal path. The common architecture of fig. 2 can be decomposed by the simplified thermal impedance Rth model shown in fig. 3A and summarized in the table shown in fig. 3B.

Fig. 3 shows that the thermal resistance (Rth) between the die 1 and the coolant 6 is divided into 3 main categories:

1) Dielectric material 5 (Rth 4): by various properties and characteristics, the dielectric material must ensure optimal thermal conductivity in order to achieve the automotive insulation requirements on the order of 1 minute 4kV, which determines the material thickness and thus Rth.

2) Substrate and mechatronic (Rth 2, rth6, rth 8): the substrate provides mechanical robustness and die mountability as well as an exposed surface, ensuring thermal continuity with the coolant through the inverter system (electromechanical integration).

3) Surface bonding is the bonding point of different elements mounted together and can be divided into 3 main groups:

a) Soldering or sintering diffusion (Rth 1), provides optimal thermal conductivity depending on the materials used, interface thickness and thermal conductivity.

b) Ceramic to metal deposited coatings (e.g., al2O3 flame spray), based on porosity and permeability, create an inter-material interface with its own Rth (Rth 3, rth 5);

c) Pressure contact (Rth 7), wherein 2 surfaces are pressed together to form a thermal path (also typically an electrical path). This type of interface is highly dependent on the applied pressure, coplanarity, roughness and geometry of the surface. It is often poor in performance and can degrade over time.

Although not intuitive, liquid-to-solid surface contact (Rth 8) is part of this category, but it is more stable and of better quality/performance depending on the strategy employed. Laminar flow over a flat surface exhibits lower efficiency because only a few molecules in contact with the solid will carry the heat to be extracted on the coolant surface. The rest of the liquid does not actively participate in cooling. Turbulence creates a larger surface contact area and more carrier, but requires implementation of special mechanisms, resulting in more material usage and increased system volume (i.e., thin fins). As indicated above, the total Rth combination of the coolant is more a matter of aggregation of material properties, technology and surface area than of a single dimension. There is a great room for improvement.

Drawings

Fig. 1A-1C depict thermal profiles and side schematic views of different wafer types, showing the general impact of adding diamond to a power electronic device in prior art embodiments.

Fig. 2 depicts a cross-sectional view of a prior art electrical/thermal path in a power device.

Fig. 3A is a view of a thermal resistance Rth model of a prior art electrical/thermal path in a power device.

Fig. 3B is a table containing relevant values for calculating the thermal impedance of an exemplary prior art electrical/thermal path in a power device.

Fig. 4A is a graph showing normalized on-resistance (RdsON) versus temperature for a typical silicon carbide (SiC) power device.

Fig. 4B is a graph depicting the saturation voltage (V) across the collector and emitter of a typical IGBT device _CE(sat) ) A plot of temperature.

FIG. 5 is a table summarizing power conduction losses for a three-phase 250kW inverter system that converts to standard EV car mileage according to current power device standards

Fig. 6 is a cross-sectional view of an improved thermoelectric path power device in accordance with aspects of the present disclosure.

Fig. 7 is a view of a thermal resistance Rth model of an improved electrical/thermal path power device according to aspects of the present disclosure.

Fig. 8 is a table containing calculated correlation values for thermal impedance of an exemplary improved electrical/thermal path power device.

Fig. 9 is a three-quarter side view of a substrate during a method of manufacturing an improved thermoelectric path power device in accordance with aspects of the present disclosure.

Fig. 10 is a three-quarter side view of a transistor attached to a surface of a substrate during a method of manufacturing an improved thermoelectric path power device in accordance with aspects of the present disclosure.

Fig. 11 is a three-quarter side view of a conductive pillar structure coupled to a substrate between transistor devices during fabrication of an improved thermoelectric path power device in accordance with aspects of the present disclosure.

Fig. 12 is a three-quarter side view of a conductive clip and a substrate with conductive posts side-by-side in the fabrication of an improved thermoelectric path power device in accordance with aspects of the present disclosure.

Fig. 13 is a three-quarter side view depicting a conductive clip of a transistor mounted and attached to a substrate during fabrication of an improved thermoelectric/path power device in accordance with aspects of the present disclosure.

Fig. 14 is a three-quarter sectional view illustrating the mounting and attachment of conductors to transistors during the fabrication of an improved thermoelectric path power device in accordance with aspects of the present disclosure.

Fig. 15 is a side view of three-quarters side by side showing a thin flexible Printed Circuit Board (PCB) and substrate clip assembly for gate connection during fabrication of an improved thermoelectric path power device in accordance with aspects of the present disclosure.

Fig. 16 is a three-quarter cross-sectional view depicting the formation of bond wires to a thin flexible (PCB) and pads of a transistor during fabrication of an improved thermoelectric path power device in accordance with aspects of the present disclosure.

Fig. 17 is a three-quarter sectional view illustrating a gate level power amplifier, control and sensing circuitry mounted on a thin flexible PCB coupled to a substrate clip assembly during fabrication of an improved thermoelectric path power device in accordance with aspects of the present disclosure.

Fig. 18 is a circuit diagram depicting an exemplary gate level control circuit layout on a thin flexible PCB in accordance with aspects of the present disclosure.

Fig. 19 is a diagram depicting two improved thermoelectric path power devices aligned in a back-to-back configuration, forming an improved half-bridge device, in accordance with aspects of the present disclosure.

Fig. 20 is a diagram depicting the formation of epoxy compounds in the region of an improved half-bridge device in accordance with aspects of the present disclosure.

Fig. 21 is a diagram depicting three improved half-bridge devices arranged in a parallel configuration in accordance with aspects of the present disclosure.

Fig. 22 is a diagram depicting bus bars rigidly connecting three improved half-bridge devices in a parallel configuration in accordance with an example of the present disclosure.

Fig. 23 is a diagram depicting a cold jet coolant block mounted to three improved half-bridge devices connected via bus bars, in accordance with aspects of the present disclosure.

Fig. 24 is a cross-sectional side view of an improved half-bridge device mounted to a cold jet coolant block in accordance with aspects of the present disclosure.

FIG. 25 is a cross-sectional view of a single cold jet cooling block according to aspects of the present disclosure.

Fig. 26 is a cross-sectional view of a side of a cold jet cooling block facing a half bridge device mount in accordance with aspects of the present disclosure.

Fig. 27 is a cross-sectional side view illustrating a return side of a cold jet cooling block according to aspects of the present disclosure.

Fig. 28 is a diagram illustrating two coolant blocks according to aspects of the present disclosure, wherein the coolant blocks are mounted to both sides of a three-phase power inverter.

Fig. 29 is a diagram depicting a complete three-phase inverter assembly with a motor phase power linkage (motor phase power linkages) installed in accordance with aspects of the present disclosure.

Fig. 30 depicts two coolant blocks mounted to a three-phase inverter having motor phase fasteners coupled to a motor phase power linkage, in accordance with aspects of the present disclosure.

Fig. 31 illustrates an integrated bulk capacitor and other passive circuits that may be coupled to a three-phase inverter on a side opposite a motor phase fastener in accordance with aspects of the present disclosure.

Fig. 32 depicts a top view of a complete three-phase inverter with cooling blocks, in accordance with aspects of the present disclosure.

Fig. 33 illustrates a side view of a complete three-phase inverter with cooling blocks in accordance with aspects of the present disclosure.

Fig. 34 depicts a simplified electric vehicle including an improved three-phase inverter in accordance with aspects of the present disclosure.

Fig. 35 is a layout diagram depicting a simplified direct drive electric vehicle using an improved three-phase inverter in accordance with aspects of the present disclosure.

Fig. 36 is a layout diagram illustrating an alternative embodiment of a direct drive electric vehicle using an improved three-phase inverter in accordance with aspects of the present disclosure.

Detailed Description

Introduction to the invention

The advent of new single crystal Diamond wafers from Diamond foundation and the now proven volume reduction and cost reduction have made significant advances in electric vehicle power electronics to increase driving range by 5.3% and service lives far exceeding 300,000 miles.

SUMMARY

Heat dissipation of Electric Vehicle (EV) power electronics is increasingly limited, and the potential range of electronic architectures has been limited by available materials. Thermal stresses induced into the power semiconductor switches have plagued semiconductor and inverter companies until desperate. Engineers throughout the industry have used materials in electronic device design that do not truly meet the characteristics required for advanced EV power electronic devices, including in particular materials that combine extreme thermal conductivity with extreme voltage insulation.

Single Crystal Diamond (SCD) is the most extreme material-in multiple dimensions, and each dimension is decisive-in particular by a combination of its extreme thermal conductivity and extreme electrical insulation. SCD exhibits excellent dielectric properties including a low dielectric constant of 5.7, a loss tangent of less than 0.0001 at 35Ghz, and a high dielectric strength of 10 MV/cm. This means that a 20um SCD can isolate 20kV while delivering thermal conductivities as high as 3,000W/mK.

The Diamond foundation company located in san francisco, california has realized the production of single crystal Diamond with a wafer size that covers all die sizes required for commercially relevant computer and power electronic chips.

Dilemma of electric traction inverters

The electric traction inverter (PTI) of an EV is a key element of electric travel. PTI has been one of the weakest links in the electric travel implementation due to its complexity, electrical and thermal stresses, and final cost, and the failure rate of the early development of this emerging market is high, with of course the technical hurdle of the Original Equipment Manufacturer (OEM) to adopt admission. Driving conditions and modes often create significant electrical and thermal stresses to the active components of the inverter and its surrounding components and, if mishandled, lead to dramatic life shortening and ultimately system failure.

The advancement of power inverters has been slow and gradual due to the complex design and fabrication exacerbated by the requirements of the routing subsystem, the complex integration of high power electronics, material science, electromechanical integration, and thermal management. The power density is undoubtedly a key performance indicator for modern power inverters to emphasize technology and efficiency. For reference, the most advanced designs are shown as 33kW/L (Tesla Model 3 is 12L, 4.8kg, 400 kW) and 36kW/L (Audi-Tron is 5.5L, 8kg, 200 kW).

The power semiconductor is driven mainly by two factors: thermal conductivity-the path that cools them-and electrical conductivity-the path that carries the high current. While electrical paths have been studied for many years and have been more or less successful, thermal paths have always been a major challenge.

In addition to requiring high thermal and electrical conductivity, power semiconductors also require electrical isolation from other parts of the environment, as they carry high voltages; this is a safety requirement. Unfortunately, voltage isolation barriers (such as DBC substrates) typically exhibit poor thermal conductivity. Common isolation barriers such as high thermal conductivity compounds exhibit 2 to 5W/mK, most advanced oxides such as alumina (ai 2O 3) exhibit 24 to 28W/mK, more modern aluminum nitride (AlN) actually provides 150 to 180W/mK, thus maintaining a significant undesirable thermal difference between the semiconductor junction temperature (Tj) and the cooling mechanism (typically liquid ethylene glycol) at the thickness required to ensure electrical isolation.

Unlike other power consuming devices such as MCUs, logic devices, memories and DSP chips, power semiconductors such as silicon insulated gate bipolar transistors (Si IGBTs) and silicon carbide metal oxide semiconductor field effect transistors (SiC MOSFETs) have the same electrical and thermal paths through their bottom sides. The most common solution today to ensure electrical insulation and high current carrying capability of Si IGBTs and SiC MOSFETs is a Direct Bonded Copper (DBC) substrate. Unfortunately, they do not provide high heat carrying capacity.

Diamond-based power electronics

Diamond and diamond-based solutions have received widespread attention from power semiconductor developers due to their excellent properties. It is known as the "holy cup" for semiconductor applications. This is the only material known in nature to exhibit ultrahigh thermal conductivity and ultrahigh band gap. Unlike conductive graphene (another allotrope of carbon), diamond is a good insulator. The Diamond foundation company now provides a practical and affordable solution to very old problems: how to effectively implement the cooling path of the power semiconductor while ensuring dielectric isolation.

The advantages of diamond have long been known and in fact this is not surprising or novel. Novel and subverted, the Diamond foundation company has now successfully achieved: a. producing high quality single crystal diamond wafers suitable for all chip die sizes; b. reducing the cost to a level required for automotive power electronics; and c.novel power electronics architecture that fully exploits the functionality of the novel diamond wafer.

Previous work by our team and others showed that diamond reduced the peak temperatures of various semiconductors by as much as 20%, which increased power efficiency by 10% during this period.

SCD wafers can be used in a variety of ways near switching semiconductor device junctions: replaced direct bonding copperDBC) Ceramics in the substrate (e.g., alumina (Al ₂ O ₃ ) Aluminum nitride (AlN), silicon nitride (Si) ₃ N ₄ ) A) is provided; replacing the heat spreader in the new discrete package; allowing thinning of the semiconductor wafer. SCD wafers allow for inverter size, weight, and cost reduction based on any and all semiconductor technologies without the need for "betting" on new semiconductors that are commercially attractive.

The importance of maintaining a lower junction temperature

Thermal stresses induced into the power semiconductor switches can lead to failure and loss of energy efficiency. According to the rule of thumb, the life expectancy of the semiconductor is reduced by half for every 10℃increase in temperature, for example, to set the electrical charge of silicon carbideThe temperature of the high temperature spring silicon design of the source switch tends to increase from 175 degrees celsius to 200 degrees celsius. And have almost constant V _ce(Sat) Unlike temperature-coefficient IGBTs, rdsON of MOSFETs (including SiC) is a positive temperature-dependent parameter (TDP), which means that RdsON increases with increasing temperature.

Fig. 4A shows the normalized RdsON of a common SiC device. Since a typical RdsON is designated 1 (e.g., 7 mOhm) at 25 degrees celsius, it increases 45% (10.39 mOhm) at 150 degrees celsius, 64% (11.64 mOhm) at 175 degrees celsius, and 90% (12.87 mOh) at 200 degrees celsius. The increases in RdsON and Tj are divided into a linear region (25 to 150 degrees celsius) and an exponential region (150 to 200 degrees celsius), which means that for the same amount of current (400A), the power conduction loss is 1120W at 25 degrees celsius, 1359W at 100 degrees celsius, 1662W at 150 degrees celsius, 1863W at 175 degrees celsius, and 2060W at 200 degrees celsius.

FIG. 4B shows the V of a typical modern IGBT _ce(sat) . The conduction loss at 400A is 800W at 25 degrees celsius, 920W at 125 degrees celsius, and 1000W at 150 degrees celsius (no further data available). At inverter frequency operation of EV (15 kHz), conduction losses account for about 60% of the cumulative conduction switching losses of the device. This is mainly due to the so-called "tail effect" of the IGBT and it is directly related to the surface area of the silicon chip. The larger the surface, the larger the switching losses. The total cumulative conduction loss and switching loss of the IGBT reaches 1375W at 25 degrees celsius, 1580W at 125 degrees celsius, and 1720W at 150 degrees celsius. Notably, although the efficiency advantage of SiC over IGBTs is very weak, the trend to employ SiC is irreversible, even though the major cost of SiC over IGBTs (about 5 times) underscores the implementation cost, which is beneficial for performance and EV mileage gain.

Since the coolant temperature of the on-vehicle EV is set to 80 degrees celsius as a standard, the challenge here is to make Tj as close as possible to the coolant to eliminate unnecessary conduction loss caused by Tj in the exponential region and the partially linear region of SiC and to allow the die surface area of the IGBT to be reduced. Bipolar structures such as IGBTs are fairly resilient in terms of forward current as long as the temperature-dependent latch condition is not triggered. It is widely accepted that current densities up to 1000A/cm2 set limits and IGBT manufacturers typically remain in 80% to 90% of the limits over the entire temperature range. Controlling the junction temperature of the IGBT under latch conditions enables a significant reduction in the effective area of the die size, thereby correspondingly affecting the switching losses that IGBTs have suffered since birth. Proper application of thermal management solutions, such as the solution of Diamond foundation company, can achieve a balance of modern SiC and antique IGBT technologies for the electric trip frequency switching range (10 to 20 kHz) at a cost of 1/5.

Specific influence on EV mileage

Fig. 5 summarizes the power conduction losses of a three-phase 250kW inverter system that converts to standard EV range according to today's standards. Losses due to 400A current (565A peak) per phase in the range of 80 degrees celsius (coolant) to 200C Tj were investigated.

The "inverter power loss to save" column shows the energy to save for the battery at different Tj, and the range is calculated accordingly from the battery capacity. Assuming that the power switch Tj can be maintained near the coolant temperature (80 degrees celsius), an increase of 5.33% per battery charge or trip of 11.72 miles or mileage can save the total power loss as high as 2812W.

This study is conservative in that it does not take into account renewable energy savings estimated to be 15 to 20% of these figures. This includes power loss temperature dependence in Fast Recovery Diodes (FRDs) associated with IGBTs, thermal dependent losses of SiC MOSFET intrinsic diodes (exhibiting poor performance with respect to temperature), and reduction of associated circuits such as gate level power amplifiers and accessory components. The size reduction of this ratio provides the possibility to integrate the inverter motor directly, eliminating the cable length and the power loss of the terminals, which is a further fraction of the battery capacity.

Overrun temperature: single form factor architecture for implementing EV power electronics

The combination of the extraordinary thermal conductivity, voltage insulation and wafer finish characteristics of single crystal Diamond wafers are now available from Diamond foundation, enabling novel device and system designs and more efficient assembly processes that have not been possible in the industry to pursue GaN, siC and IGBT silicon chips.

Specifically, the SCD wafer of Diamond Foundry enables single form factor power inverters in excess of 1000kW/L (e.g., 400kW for a 0.4L system). This results in greater system efficiency, loss and system cost reduction, which translates into energy savings and electric range expansion.

A novel thermal management configuration in accordance with aspects of the present disclosure is shown in fig. 6. This configuration greatly reduces the thermal impedance element from nine to four elements. In this configuration, the semiconductor die 1 is attached to the copper substrate 3 by a silver attachment 2. The copper substrate 2 is diffusion bonded to the SCD wafer 7. The diffusion process for attachment between the simplified number of elements constituting the thermal path is now reduced to the nanometer level, ensuring free heat propagation from the semiconductor die 1 through the diamond chip 7 to the coolant 6. The use of the SCD wafer 7 allows for more three-dimensional heat propagation, as indicated by the dashed arrow.

One or more pressurized coolant jets 8 deliver coolant 6 to the exposed surface of the diamond wafer 7, providing vertical impingement flow, resulting in better performance than laminar, turbulent, or turbulent "Bao Chipian" solutions. The corresponding thermal impedance model depicted in fig. 7 is in the depicted table, and fig. 8 summarizes these advantages.

Since the total Rth is significantly reduced (0.0155, about 0.11 from the state of the art), the silicon wafer Tj is now closely related to the coolant temperature in the locked position, creating a Tj "clamp" of about 12 degrees celsius above the coolant, thus enabling significant savings in conduction losses compared to the losses described with respect to fig. 5, optimizing the mechanical geometry of the inverter design and reducing the active silicon wafer surface required.

Advanced materials and thermal management techniques of the configuration of fig. 6 can greatly reduce thermal impedance and reduce inverter size, thus paving a road for greatly expanding EV range, reducing cost, and extremely high reliability. Furthermore, the technology is scalable and applicable to similar markets (i.e., power generation, charging stations, grid balancing, etc.) where high power efficiency and reliability are critical tasks.

Exemplary embodiments of the invention

400kW power inverter design introduction:

1) Single switch description

In the example, the single switch configuration begins with a 19.5x0.6 mm silver (Ag) copper top substrate 102 attached to a 20x0.3 mm SCD chip 104. Next, as shown in fig. 10, three transistors (e.g., IGBTs or MOSFETs) are attached to the top substrate using, for example, ag sintering technology.

By way of example and not limitation, MOSFET 106 may be a 130a1200V silicon carbide (SiC) MOSFET device formed on an 8x8 mm silicon chip. Next, as shown in fig. 11, three conductive pillar structures 108 for the high current power path (V L converter) of the MOSFET drain connection are attached to the top substrate. By way of example and not limitation, the post structure may be a 6mm wide silver plated copper post. Next, as shown in fig. 12, a conductive (e.g., copper) clip 110 is mounted on top of the three SiC MOSFETs and sintered to form a high current power path for the MOSFET source connection.

As shown in fig. 13, the clip is mounted and attached to the MOSFET source pad connection, for example using a sintering technique. As shown in fig. 14, electrical connection to MOSFET 106 can be made by sintering top pads 112 on the MOSFET to corresponding bumps 114 on clip 110. As shown in fig. 15, a thin flexible Printed Circuit Board (PCB) 116 is mounted to form a gate router (gate router) for the gate connection 118 of the MOSFET. As shown in fig. 16, conductive extension 120 on PCB 116 is electrically connected to gate level connection 118, for example, by wire bond 122. As shown in fig. 17, a thin flexible PCB gate level power amplifier circuit 124 and a current sensing circuit 126 are added and interconnected with the gate level router 116. An equivalent schematic of the corresponding device is shown in fig. 18.

Subsequently, two identical structures of the type shown in fig. 17 may be aligned back-to-back with the SCD chip 104 facing outward as shown in fig. 19, and then epoxy compounded 127 as shown in fig. 20. The epoxy device shown in fig. 20 may be used for a half-bridge inverter or for unidirectional motor control, so-called half-H-bridge. The sources 110 on each side of the device may be connected anti-parallel. Each side of the device may also be connected in parallel with a diode to shunt the reverse flow of current. The half-bridge device may also be integrated into a switched mode power supply using a synchronous rectifier.

The two half-bridge inverter devices may be arranged together to form a full H-bridge for motor control or as a power converter, such as an ac-to-ac converter, a dc-to-dc converter or a dc-to-ac converter.

The three half-bridge devices may be arranged in parallel as shown in fig. 21 below to form a three-phase inverter apparatus. Each device is aligned with a gate control located between source regions on either side of each half-bridge device. This parallel arrangement allows a short-range rigid connection to be formed between each half-bridge device. Three half-bridge devices of the type shown in fig. 21 may be rigidly connected, such as via bus bars 128, 129, as shown in fig. 22. For a three-phase inverter apparatus, the drains of each side of three half-bridge devices 128 may be connected, and the source on the other side of each half-bridge device 129 may be connected. The spine bus 128 may form a VBUS (+) bus for a three-phase power inverter and the spine bus 129 may form a VBUS (-) bus for a three-phase power inverter. The bus bars provide electrical connection and structural rigidity between the half-bridge devices.

A single crystal diamond die (SCD) 104 allows for efficient cooling of the MOSFETs in each half-bridge device. Cooling blocks 130 may be coupled to each side of the three-phase inverter device, as shown in fig. 22. Each half-bridge device may include cooling fins for radiative cooling or fluid interfaces for liquid or evaporative cooling. The cooling block 130 may be implemented as a cold jet coolant block to provide improved heat transfer between the coolant and the SCD surface. The cold jet coolant block as shown in fig. 24 utilizes the venturi effect to spray the spray coolant onto the SCD surface, thereby creating a high flow rate and a large amount of contact between the coolant and the SCD. As shown, coolant enters the cooling block 130 at a cooling intake port 131. The coolant fills the coolant intake chamber 132 to reach the compression chamber 133. The coolant increases the velocity through the venturi 134 and spreads along the surface of the bell nozzle 135, creating a spray plume of coolant that impinges the SCD 104. The coolant spray plume may be directed to an area of the SCD 104 below the MOSFET 106. The coolant spreads over the SCD 104, thereby removing heat from the MOSFET 106 and SCD 104. The hot coolant circulates upward through the return cavity 136, where it may exit the cooling block 130 and may be cooled before returning to the coolant intake 131. The coolant may be cooled by the radiator and the fin block via expansion and radiant cooling.

The cooling block 130 may include a plurality of bell-shaped nozzles 135, such as, but not limited to, one nozzle per MOSFET 106. As previously discussed, each nozzle 135 may be positioned such that it is directly behind one of the MOSFETs and directs a jet of coolant onto the SCD 104 immediately behind the MOSFET. The coolant O-ring seal 137 may prevent coolant from escaping around the SCD 104.

Fig. 26 is a front view depicting a view of one side of the cooling block mounted facing the three-phase inverter. As shown, the cooling block may include three bell-shaped nozzles 135, each configured to be behind one of the three MOSFETs of the half-bridge device. The return chamber 136 may be located in the space between the bell nozzles 135. FIG. 27 illustrates a cross-sectional view of a return side of a cooling block according to aspects of the present disclosure. As shown, the coolant block includes three nozzle assemblies 139 that are coupled together to cool the three-phase inverter. The coolant block may include any number of nozzle assemblies sufficient to cool the inverter device including the half-bridge device according to aspects of the present disclosure. A return cavity 136 is present on one side of each respective half-bridge device and each return path is connected to allow coolant to flow to a coolant outlet port 138.

Fig. 28 shows a three-phase inverter utilizing two coolant blocks, one coolant block being mounted to each side of the three-phase power inverter and configured to cool one side of each of three half-bridge devices in the three-phase inverter. Fig. 29 depicts a complete three-phase inverter assembly with motor phase power linkage 140 installed. Motor phase power linkage 140 connects the drain and source of each half-bridge device such that current flows only when one side of the half-bridge device is in an on state. Fig. 30 depicts two coolant blocks mounted to a three-phase inverter with motor phase fasteners 141 coupled to motor phase power linkages 140. Fig. 31 shows an integrated bulk capacitor and other passive circuit 142 that may be coupled to a three-phase inverter on a side opposite the motor phase fasteners 141.

Fig. 32 depicts a top view of a complete three-phase inverter with cooling blocks, in accordance with aspects of the present disclosure. As shown, the three-phase inverter includes motor phase fasteners 141, bus bars 129, 128, and the cooling block 130 includes a coolant inlet port 131 and a coolant outlet port 138. Fig. 33 illustrates a side view of a complete three-phase inverter with cooling blocks in accordance with aspects of the present disclosure. In side view, motor phase power linkage 140, half-bridge device 143, and passive circuit 142 can also be seen.

According to additional aspects of the present disclosure, the three-phase inverter device may be integrated into an electric vehicle, such as an electric automobile, an aircraft, a helicopter, a train, a ship, or a submarine.

Fig. 34 depicts a simple electric vehicle including a three-phase inverter according to aspects of the present disclosure. As shown, a simple electric vehicle may include a three-phase inverter and coolant block assembly 201 coupled to a three-phase motor 202. Each phase of motor 202 may be conductively coupled to a motor phase fastener of three-phase inverter 201. The output shaft of the electric motor 202 may be coupled to a differential (and optionally a gearbox) 203 configured to apply rotational speed to a shaft 204 that connects drive wheels 205. The three-phase inverter takes Direct Current (DC) power from a battery or other power source 206 and converts it to three-phase power, which the motor 202 can convert to rotational speed of its output shaft. The controller 208 may be coupled to the three-phase inverter and configured to control the phases to operate the motor. The battery or other power source 206 may receive power from a charging circuit 207, which may receive power from an external source, such as ac power from a wall outlet. The charging circuit 207 may be, for example, an ac-to-dc converter and may utilize the half-bridge devices described in this disclosure. The coolant block of the three-phase inverter may be coupled to a coolant system including a radiator 209 and a coolant pump 210. For stability, the electric vehicle may further include additional wheels 211.

Fig. 35 depicts a simple direct drive electric vehicle, such as an electric motorcycle. Unlike the electric vehicle depicted in fig. 34, the direct drive electric vehicle omits a differential, and the electric motor 202 directly drives the drive wheels 205. According to aspects of the present disclosure, a direct drive electric vehicle may include an electric motor 202 and a three-phase inverter 201 for each drive wheel 205. A direct drive vehicle according to aspects of the present disclosure may include any number of drive wheels with corresponding motors and inverters. According to some additional aspects of the present disclosure, a plurality of motors may be coupled to a three-phase inverter.

Fig. 36 shows an alternative embodiment of a direct drive electric vehicle. In the illustrated vehicle, a three-phase inverter 201 drives an electric motor 202 connected to a propeller, liquid screw, or other device for generating thrust 220 through liquid. The embodiments may be implemented in many vehicles, such as airplanes, ships, submarines, helicopters, quad-axis aircraft, and so forth. In some embodiments, multiple motors 202 and inverters 201 may be included on the same coolant circuit and share a radiator 209 and coolant pump 210.

Glossary of terms

MOSFET: metal oxide field effect transistor: power switch

IGBT: insulated gate bipolar transistor: power switch

V _ce(Sat) : collector-emitter voltage when saturated

RdsON: drain-source resistance in the on-state of a MOSFET transistor

PTI: electric traction inverter

OEM: original equipment manufacturer (i.e., automobile brand/manufacturer)

DC: direct current

AC: AC power

kW: kilowatt, 1000 watts

MW: megawatts, 1000kW

SAC305: solder paste in which Sn (tin), ag (silver) and Cu (copper) were mixed at 97%, 3% and 0.5%, respectively

W/mK: measurement of thermal impedance per meter (in three dimensions) per kelvin

IMS: insulated metal substrate

Rth: thermal impedance

And (3) kV: kilovolt, 1000 volts

SiC: silicon carbide, technique for producing transistors

mOhm: milliohms, ohms divided by 1000.

Tj: junction temperature, temperature of the silicon chip.

Claims (34)

1. A power device, comprising:

a first power electronic chip attached to a first copper substrate; and

a first diamond substrate attached to the first copper substrate, wherein the first copper substrate is sandwiched between a first side of the first diamond substrate and the first power electronic chip.

2. The device of claim 1, further comprising one or more pressure jets, each pressure jet configured to direct pressurized coolant toward a second side of the first diamond substrate opposite the first side of the first diamond substrate.

3. The device of claim 2, wherein the one or more pressure jets comprise one or more pressure jets configured to deliver a vertical impingement flow of coolant to the second side of the first diamond substrate.

4. The device of claim 1, wherein the first diamond substrate is a Single Crystal Diamond (SCD) substrate.

5. The device of claim 1, wherein the first power electronic chip is a gallium nitride chip, a silicon carbide chip, or an insulated gate bipolar transistor silicon chip.

6. The device of claim 1, wherein the first power electronic chip comprises one or more Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices.

7. The device of claim 6, wherein the one or more Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices comprise one or more silicon carbide (SiC) MOSFET devices.

8. The device of claim 7, wherein the one or more SiC MOSFET devices comprise three SiC MOSFET devices.

9. The device of claim 1, wherein a drain of the first power electronic chip is conductively coupled to the first copper substrate.

10. The device of claim 9, further comprising one or more conductive pillar structures coupled to the first copper substrate and conductively coupled to the drain of the first power electronic chip.

11. The device of claim 1, wherein the first power electronic chip comprises a conductive source pad on a side of the first power electronic chip opposite a side of the first power electronic chip attached to the first copper substrate, the conductive source pad conductively coupled to a source connection of the first power electronic chip.

12. The device of claim 11, further comprising a conductive clip coupled to the conductive source pad of the power electronic device, wherein the conductive clip is conductively coupled to the source connection of the first power electronic chip.

13. The device of claim 12, wherein the conductive clip is conductively coupled and physically attached to the conductive source pad.

14. The device of claim 1, wherein the first power electronic chip includes a conductive gate pad on a side of the first power electronic chip opposite a side of the first power electronic chip attached to the first copper substrate, the conductive gate pad conductively coupled to a gate input of the first power electronic chip.

15. The device of claim 14, further comprising a gate router circuit conductively coupled to the gate pad of the first power electronic chip.

16. The device of claim 15, wherein the gate router circuit comprises a gate power amplifier and a current sense circuit.

17. The device of claim 15, wherein the gate level router circuit comprises a thin flexible printed circuit board.

18. The device of claim 1, further comprising a second power electronic chip attached to a second copper substrate and a second diamond substrate attached to the second copper substrate, wherein the second copper substrate is sandwiched between a first side of the second diamond substrate and the power electronic chip, wherein the second power electronic chip, the second copper substrate, and the second diamond substrate are arranged such that the first side of the first diamond substrate and the first side of the second diamond substrate face each other.

19. The device of claim 18, wherein the second power electronic chip is configured to operate anti-parallel to the first power electronic chip, and the first power electronic chip and the second power electronic chip form a first half-bridge inverter.

20. The device of claim 19, further comprising a second half-bridge inverter arrangement conductively coupled to the first half-bridge inverter to form a full H-bridge inverter, wherein the second half-bridge device is configured as in claim 19.

21. The device of claim 19, further comprising two additional half-bridge inverter means conductively coupled to the first half-bridge inverter to form a three-phase power inverter, wherein the two additional half-bridge devices are configured as in claim 19.

22. The device of claim 21, further comprising at least one rigid conductive bus connecting the two additional half-bridge inverter devices and the first half-bridge inverter.

23. A power vehicle system, comprising:

at least one half-bridge device having a power electronic chip mounted to a copper substrate, and the copper substrate being sandwiched between the power electronic chip and a diamond substrate; and

a motor conductively coupled to the at least one half-bridge device.

24. The power carrier system of claim 23, further comprising a wheel coupled to an output shaft of the motor, wherein the output shaft of the motor rotates the wheel.

25. The power carrier system of claim 23, further comprising a propeller coupled to an output shaft of the motor, wherein the output shaft of the motor rotates the propeller and the propeller is configured to generate thrust in a medium.

26. The power carrier system of claim 23, further comprising a differential coupled to an output shaft of the electric motor, wherein the differential is configured to deliver rotation from the output shaft of the electric motor to a differential output shaft.

27. The power carrier system of claim 25, further comprising at least one wheel attached to the differential output shaft, wherein the differential output shaft delivers rotation to the wheel.

28. The power carrier system of claim 23, further comprising a gearbox coupled to the output shaft of the motor, wherein the gearbox is configured to convert a portion of a rotational speed of the output shaft of the motor to torque.

29. The power vehicle system of claim 23, further comprising at least one battery conductively coupled to the at least one half-bridge device.

30. The power vehicle system of claim 23, further comprising a controller communicatively coupled to the at least one half-bridge device.

31. The power carrier system of claim 23, further comprising a cooling block coupled to the at least one half-bridge device, wherein the coolant block comprises at least pressure jets, each pressure jet configured to direct pressurized coolant toward a side of the diamond substrate opposite a side of the diamond substrate to which the copper substrate is attached.

32. The power vehicle system of claim 31, wherein the at least one pressure jet comprises one or more pressure jets configured to deliver a vertical impingement flow of coolant to a second side of the first diamond substrate.

33. The power vehicle of claim 23, wherein the at least one half-bridge device comprises two half-bridge devices operating as a full H-bridge.

34. The power vehicle of claim 23, wherein the at least one half-bridge device comprises three half-bridge devices operating as a three-phase inverter.