CN117501422A

CN117501422A - Root cause analysis method and related equipment

Info

Publication number: CN117501422A
Application number: CN202180099370.3A
Authority: CN
Inventors: 秦旻; 黄鑫; 黄宇; 芮祥麟; 陈诚
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-06-22
Filing date: 2021-06-22
Publication date: 2024-02-02
Also published as: WO2022266833A1

Abstract

The embodiment of the application provides a root cause analysis method and related equipment, wherein in the method, firstly, a diagnosis report is acquired, and the diagnosis report is used for indicating diagnosis information of chip defects; then, extracting features according to the diagnosis report to obtain the feature information of the chip defects; and processing the characteristic information based on the first neural network to obtain root cause distribution information of the chip defects. The characteristic information processed by the neural network comprises the characteristic information extracted according to the diagnosis report, and the network parameter variable space contained in the neural network is large, so that root cause distribution information of the chip defects with relevance can be fitted on a high-dimensional space, and root cause analysis accuracy in the root cause analysis process based on the diagnosis report can be improved.

Description

Root cause analysis method and related equipment

Technical Field

The present disclosure relates to the field of chips, and in particular, to a root cause analysis method and related devices.

Background

Yield, which defines the ratio of the number of acceptable dies to the number of all dies in the chip manufacturing process, is a key factor affecting the profit margin of the product. During the fabrication of the chip, potential root cause distributions may be estimated from the batch of diagnostic data by a root cause analysis (root cause identification, RCI) tool to locate the true root cause (root cause), i.e., root cause, that leads to yield degradation.

Traditionally, the input of the RCI tool is a diagnostic report obtained by testing the dies on a test machine; then, the RCI tool calculates the diagnosis report through a Bayesian network (Bayesian network) model, and sequentially obtains the posterior probability of a logic fault and the posterior probability of a physical defect; and then calculating based on the obtained posterior probability of the logic error and the posterior probability of the physical defect, and determining and outputting the root cause. In the implementation process of the Bayesian network model, the assumption that different logic errors and physical defects are mutually independent is relied on.

However, it was found during the actual testing of the chip that the individual root causes are not completely independent of each other, e.g., there may be intersections between the root causes that produce different physical defects (and/or logic errors), resulting in poor root cause analysis accuracy of the RCI tool currently implemented based on bayesian network models.

Therefore, how to improve the root cause analysis accuracy of the RCI tool is a technical problem to be solved urgently.

Disclosure of Invention

The embodiment of the application provides a root cause analysis method and related equipment, which are used for improving root cause analysis precision in the root cause analysis process based on a diagnosis report.

The first aspect of the embodiments of the present application provides a root cause analysis method, which may be applied to a process of obtaining root cause distribution by root cause analysis based on a diagnostic report, for improving root cause analysis accuracy. In the method, a diagnostic report for indicating diagnostic information of a chip defect is first acquired; then, extracting features according to the diagnosis report to obtain the feature information of the chip defects; and then, processing the characteristic information based on the first neural network to obtain root cause distribution information of the chip defect, wherein the root cause distribution information is used for indicating root cause probability distribution of the chip defect.

Based on the technical scheme, after a diagnosis report for indicating the chip defect diagnosis information is obtained, determining the characteristic information of the chip defect according to the diagnosis report; thereafter, root cause distribution information of the chip defect is determined based on the characteristic information using a first neural network. Compared with an implementation mode of calculating only posterior probability based on a Bayesian network model, in an implementation mode of determining root cause distribution information through a neural network, because the characteristic information processed by the neural network comprises the characteristic information extracted according to a diagnosis report and the variable space of network parameters contained in the neural network is large, the root cause distribution information of chip defects with relevance can be fitted on a high-dimensional space, and therefore root cause analysis accuracy in a root cause analysis process based on the diagnosis report can be improved.

In a possible implementation manner of the first aspect of the embodiments of the present application, the feature information of the chip defect includes first feature information; the process of extracting the characteristics according to the diagnosis report to obtain the characteristic information of the chip defect specifically comprises the following steps: firstly, determining the posterior probability of the chip defect according to the diagnosis report, wherein the posterior probability is used for indicating the probability that the diagnosis information is detected when the chip defect occurs; and then, carrying out feature extraction on the posterior probability to obtain the first feature information.

Based on the above technical solution, after obtaining the diagnostic report, the posterior probability of the chip defect may be first determined based on the diagnostic report included in the diagnostic report; and then, carrying out feature extraction based on the posterior probability to obtain first feature information. The characteristic information of the chip defect at least comprises the first characteristic information, so that the characteristic information of the chip defect processed by the neural network at least is used for representing the posterior probability.

In a possible implementation manner of the first aspect of the embodiments of the present application, the feature information of the chip defect includes second feature information; the process of extracting the characteristics according to the diagnosis report to obtain the characteristic information of the chip defect specifically comprises the following steps: and extracting the characteristics of the diagnosis report to obtain the second characteristic information.

Based on the above technical solution, after the diagnostic report is acquired, feature extraction may be performed based on the diagnostic report included in the diagnostic report, and based on the diagnostic report, so as to obtain second feature information. The characteristic information of the chip defect at least comprises the second characteristic information, so that the characteristic information of the chip defect processed by the neural network is used for representing the diagnosis report.

It should be noted that, the feature information of the chip defect may include the first feature information and not include the second feature information; alternatively, the feature information of the chip defect may include the second feature information and not include the first feature information; or alternatively; the feature information of the chip defect may include the second feature information and the first feature information, which are not limited herein.

In a possible implementation manner of the first aspect of the embodiments of the present application, a process for obtaining root cause distribution information of the chip defect based on the feature information processed by the first neural network specifically includes: first, a first sample set is acquired, wherein the first sample set comprises a preconfigured diagnostic report and a root cause of the preconfigured diagnostic report; then, determining target root cause weight information according to the first sample set by using the first neural network, wherein the target root cause weight information is used for adjusting the weight of the characteristic information; thereafter, the root cause distribution information is determined from the target root cause weight information and the feature information.

Based on the above technical solution, the first neural network specifically trains through a preconfigured first sample set to obtain related network parameters, and then, the target root cause weight information for adjusting the weight of the feature information determined by the first neural network has the related characteristics of the first sample set.

Alternatively, the pre-configuration may indicate a vendor pre-configuration. Illustratively, the relevant parameters that are factory preconfigured in the root cause analysis apparatus that performs the root cause analysis method include a preconfigured diagnostic report, a root cause of the preconfigured diagnostic report, and the like. Thus, such that in this implementation, the target root weight information for adjusting the weight of the feature information is determined using the first neural network based on the vendor preconfigured first set of samples having diversity (and/or representativeness). That is, in the implementation manner of vendor pre-configuration, the pre-configured first sample set is obtained by sampling in the data set of the multiple chip designs and/or the multiple chip processes, so that the first sample set has the sample characteristics of the pre-configured diversity (and/or the representativeness), and the accuracy of the root cause analysis process of inputting the first sample set into the first neural network is further improved.

Alternatively, the pre-configuration may indicate a user pre-configuration. Illustratively, in the root cause analysis device, the user instructs the preconfigured relevant parameters including the preconfigured diagnostic report, the root cause of the preconfigured diagnostic report, and the like through the user operation in the process of performing root cause analysis by using the root cause analysis method. Thus, in this implementation, the target root weight information for adjusting the weight of the feature information is determined using the first neural network based on the user-preconfigured first sample set with the personalized configuration. In other words, in the implementation manner of user pre-configuration, the user can implement personalized configuration on the first neural network through the user operation instruction, so that the first sample set has sample characteristics of pre-configured personalized configuration, and the self-adaptive capacity of the root cause analysis method to different chip designs or different chip technologies is improved.

For example, the user operation instruction is an input instruction for the user to input data in the input module of the root cause analysis device; in another example, the user operation instruction is a communication instruction for the user to communicate with the communication module of the root cause analysis device, so that the root cause analysis device communicates with other devices based on the communication instruction.

It should be noted that, the implementation of the pre-configuration may include vendor pre-configuration but not user pre-configuration; alternatively, the implementation of the pre-configuration may include not vendor pre-configuration but user pre-configuration; alternatively, implementations of the pre-configuration may include vendor pre-configuration and user pre-configuration, without limitation.

In a possible implementation manner of the first aspect of the embodiments of the present application, after processing the feature information based on the first neural network to obtain root cause distribution information of the chip defect, the method further includes: firstly, updating the first sample set according to the diagnosis report and root cause distribution information of the chip defects to obtain a second sample set; then, the target root cause weight information is updated according to the second sample set.

Based on the technical scheme, after the characteristic information is processed based on the first neural network to obtain the root cause distribution information of the chip defects, the first sample set used by the first neural network can be updated according to the root cause distribution information of the chip defects obtained in the current root cause analysis process and the diagnosis report. And then updating the target root cause weight information according to the first sample set obtained in the updating process so as to enrich the sample set calculated by the first neural network and further improve the processing performance of the subsequent first neural network.

In a possible implementation manner of the first aspect of the embodiments of the present application, the process of updating the first sample set according to the diagnostic report and root cause distribution information of the chip defect to obtain the second sample set specifically includes: firstly, performing physical failure analysis (physical failure analysis, PFA) verification on the distribution information of the chip defects to obtain a first verification result; thereafter, the first sample set is updated according to the diagnostic report and the first verification result, resulting in a second sample set.

Based on the above technical solution, in the process of updating the first sample set according to the distribution information of the chip defect to obtain the second sample set, the updating may be specifically performed according to the PFA verification result corresponding to the distribution information of the chip defect. The PFA verification process is a process of manually verifying by a user, namely, a result of the manual verification is used as an updating basis of the sample set, so that the accuracy of a root cause analysis process of a second sample set updated according to the follow-up basis can be improved.

In a possible implementation manner of the first aspect of the embodiments of the present application, the updating the first sample set according to the diagnostic report and the first verification result, and the obtaining a second sample set specifically includes: and updating the first sample set according to the diagnosis report and a second verification result to obtain a second sample set, wherein the second verification result is a verification result corresponding to the root cause of the n-bit in the first verification result, which is the integer greater than 0, with the probability ranking.

Alternatively, n is an integer greater than 0, and the specific value of n may be 3,5, or other values, which are not limited herein.

Based on the above technical solution, in the process of updating the first sample set according to the first verification result and the diagnostic report to obtain the second sample set, the second verification result corresponding to the root cause of the top n bits in the first verification result may be specifically used as the update basis of the sample set. That is, the part with larger reference value in the first verification result is used as the update basis of the sample set, so that the update process is simplified, and the processing efficiency is improved.

In a possible implementation manner of the first aspect of the embodiments of the present application, the process of determining, using the first neural network, the target root cause weight information according to the first sample set specifically includes: firstly, obtaining pre-configured initial root cause weight information; then, determining a weight adjustment coefficient in the first neural network from the first set of samples; and then updating the initial root cause weight information according to the weight adjustment coefficient to obtain the target root cause weight information.

Based on the above technical solution, in the implementation process of the solution, the initial root cause weight information for adjusting the feature information may be preconfigured. In the process of determining the target root cause weight information according to the first sample set in the first neural network, a weight adjustment coefficient is determined according to the first sample set in the first neural network, and initial root cause weight information is updated according to the weight adjustment coefficient to obtain the target root cause weight information. Specifically, the user configures the weight adjustment coefficient obtained by the first neural network in a personalized way through the user operation instruction to obtain the weight adjustment coefficient, and then updates the initial root cause weight coefficient through the obtained weight adjustment coefficient to determine the target root cause weight coefficient.

In a possible implementation manner of the first aspect of the embodiments of the present application, the process of updating the initial root cause weight information according to the weight update information to obtain the target root cause weight information specifically includes: the initial root weight information is updated according to the weight update information to obtain the target root weight information using a gradient update algorithm including a random gradient descent (stochastic gradient descent, SGD) or an adaptive moment estimation gradient descent algorithm (adaptive moment estimation gradient descent, adam).

Based on the technical scheme, the initial root cause weight information is updated according to the weight updating information, and the process of obtaining the target root cause weight information can be realized based on a gradient updating algorithm. The gradient update algorithm may include SGD, adam, or other algorithms, which are not limited herein.

In a possible implementation manner of the first aspect of the embodiments of the present application, the initial root weight information is obtained through training of a sample set with correct root distribution information.

Based on the above technical solution, the pre-configured initial root weight information for adjusting the feature information may be information obtained by training a sample set having correct root distribution information. The initial root weight information has the performance of adjusting the characteristic information, and further, the target root weight information obtained subsequently according to the initial root weight information also has the corresponding performance of adjusting the characteristic information, so that the accuracy of the root analysis process is improved.

In a possible implementation manner of the first aspect of the embodiments of the present application, the diagnostic report includes a plurality of diagnostic information, and any one of the plurality of diagnostic information includes at least one of the following parameters:

a logic fault (logic fault), the logic fault being used to indicate a sequence number identification of the diagnostic information; or alternatively, the first and second heat exchangers may be,

a score (score) for indicating the credibility of the diagnostic information; or alternatively, the first and second heat exchangers may be,

a critical area (critical area) for indicating an area of an error area of the diagnostic information; or alternatively, the first and second heat exchangers may be,

fail match (fail match) for indicating the number of test items that cannot be interpreted using the diagnostic information; or alternatively, the first and second heat exchangers may be,

by mismatch (pass_mismatch), the number of test items that should be observed but not observed when diagnostic information occurs is indicated by the mismatch; or alternatively, the first and second heat exchangers may be,

type (type) for indicating a defect type of the diagnostic information; or alternatively, the first and second heat exchangers may be,

a layout layer (layout layer) for indicating the physical location where the diagnostic information is located.

Based on the above technical solution, the feature information is one of the bases for determining the distribution information of the chip defects, where multiple diagnostic information may be recorded as multiple suspicious (suspects) information, and the diagnostic information in the feature information may specifically include one or more of the above items, which is not limited herein.

In a possible implementation manner of the first aspect of the embodiments of the present application, the first sample set includes samples of at least two different chip designs and/or samples of at least two different chip processes.

Based on the above technical solution, the first sample set is used as one of the basis for determining root cause distribution information in the first neural network, and the first sample set may include samples of at least two different chip designs and/or samples of at least two different chip technologies. So that the root cause analysis tasks of different processes and/or different designs can be adapted in the process of calculating the first neural network based on the first sample set.

In a possible implementation manner of the first aspect of the embodiments of the present application, the first sample set includes samples compressed by a variational self-encoder (variational autoencoder, VAE) or a generation antagonism network (generative adversarial network, GAN).

Based on the above technical solution, the first neural network may be configured to compress samples obtained by VAE or GAN in the first sample set for calculation, so as to save a sample storage space.

In a possible implementation manner of the first aspect of the embodiments of the present application, the process of determining the root cause distribution information according to the target root cause weight information and the feature information specifically includes: firstly, adjusting the characteristic information according to the target root cause weight information to obtain adjusted characteristic information; and then, determining the distribution information of the root cause of the chip based on the adjusted characteristic information.

Based on the above technical solution, in the process of determining the root cause distribution information according to the target root cause weight information and the feature information, specifically, after the feature information is adjusted based on the target root cause weight information output by the first neural network, the distribution information of the root cause of the chip may be further determined.

In a possible implementation manner of the first aspect of the embodiments of the present application, the process of determining the distribution information of the root cause of the chip based on the adjusted feature information specifically includes: determining the distribution information of the root cause of the chip in an EM algorithm with the maximum expected value based on the adjusted characteristic information; or determining the distribution information of the chip root cause in the second neural network based on the adjusted characteristic information.

Based on the above technical solution, the process of determining the distribution information of the root cause of the chip based on the adjusted feature information may be implemented by an EM algorithm, or may be implemented by a neural network (e.g., a second neural network), which is not limited herein.

In a possible implementation manner of the first aspect of the embodiments of the present application, a process for obtaining root cause distribution information of the chip defect based on the feature information processed by the first neural network specifically includes: and taking the characteristic information as the input of the first neural network, and obtaining the root cause distribution information through the processing of the first neural network.

Based on the technical scheme, in the process of obtaining root cause distribution information based on the characteristic information processed by the first neural network, the characteristic information corresponding to the diagnosis report can be used as the input of the first neural network, and the root cause distribution information can be output through the processing of the first neural network. In other words, root cause analysis is realized through the reasoning process of the neural network, compared with the calculation process based on the Bayesian network model, the root cause distribution information of the chip defects with relevance can be fitted on a high-dimensional space due to the fact that the variable space of network parameters contained in the neural network is larger, and therefore the root cause analysis precision in the root cause analysis process based on the diagnosis report can be improved.

In a possible implementation manner of the first aspect of the embodiments of the present application, the first neural network includes a feature extraction module and a classification module, and the process of obtaining the root cause distribution information by using the feature information as an input of the first neural network and processing the feature information by the first neural network specifically includes: firstly, taking the characteristic information as input of the characteristic extraction module, and obtaining features corresponding to the characteristic information through processing of the characteristic extraction module; and then, taking the feature as the input of the classification module, and obtaining the distribution information of the chip root cause through the processing of the classification module.

Based on the technical scheme, the first neural network can sequentially realize the determination of the distribution information of the root cause of the chip through the operations of feature extraction, feature classification and the like in the calculation process.

In a possible implementation manner of the first aspect of the embodiments of the present application, the first neural network further includes a normalization module, and the process of obtaining the distribution information of the root cause of the chip by using the feature as the input of the classification module and processing the feature by the classification module specifically includes: firstly, taking the feature as input of the standardization module, and obtaining the feature in a standardized format through processing of the standardization module; and then, taking features in the standardized format as input of the classification module, and obtaining the distribution information of the chip root cause through processing of the classification module.

Based on the technical scheme, the first neural network can further comprise a standardization module for carrying out standardization processing on features so as to improve consistency of intermediate process data in the reasoning process of the first neural network.

In a possible implementation manner of the first aspect of the embodiments of the present application, the first neural network is a neural network that is trained based on a data set formed by a diagnostic report of a note obtained by error injection.

Based on the technical scheme, the data set formed on the basis of the annotation diagnosis report obtained by error injection is a data set which is manually verified by a user, and the manually verified data set is trained to obtain the first neural network. The calculation result obtained by calculation of the first neural network accords with the expectation of a user, and the accuracy of the distribution information obtained by calculation based on the first neural network is improved.

In a possible implementation manner of the first aspect of the embodiments of the present application, the first neural network is a multi-layer perceptron (multilayer perceptron, MLP) or a convolutional neural network (convolutional neural network, CNN).

Based on the above technical solution, the first neural network may be an MLP, a CNN, or another type of neural network, which is not limited herein.

A second aspect of the embodiments of the present application provides a root cause analysis device, including:

an acquisition unit configured to acquire a diagnostic report for indicating diagnostic information of a chip defect;

the feature extraction unit is used for carrying out feature extraction according to the diagnosis report to obtain feature information of the chip defect;

and the processing unit is used for processing the characteristic information based on the first neural network to obtain root cause distribution information of the chip defect, wherein the root cause distribution information is used for indicating root cause probability distribution of the chip defect.

In a possible implementation manner of the second aspect of the embodiments of the present application, the feature information of the chip defect includes first feature information; the feature extraction unit is specifically configured to:

determining a posterior probability of the chip defect according to the diagnostic report, wherein the posterior probability is used for indicating the probability that the diagnostic information is detected when the chip defect occurs;

and extracting features of the posterior probability to obtain the first feature information.

In a possible implementation manner of the second aspect of the embodiments of the present application, the feature information of the chip defect includes second feature information;

the feature extraction unit is specifically configured to:

and extracting the characteristics of the diagnosis report to obtain the second characteristic information.

In a possible implementation manner of the second aspect of the embodiments of the present application, the processing unit is specifically configured to:

obtaining a first set of samples, the first set of samples comprising a preconfigured diagnostic report, and a root cause of the preconfigured diagnostic report;

determining target root cause weight information according to the first sample set by using the first neural network, wherein the target root cause weight information is used for adjusting the weight of the characteristic information;

and determining root cause distribution information according to the target root cause weight information and the characteristic information.

In a possible implementation manner of the second aspect of the embodiments of the present application, the apparatus further includes:

a first updating unit, configured to update the first sample set according to the diagnostic report and root cause distribution information of the chip defect, to obtain a second sample set;

and the second updating unit is used for updating the target root cause weight information according to the second sample set.

In a possible implementation manner of the second aspect of the embodiments of the present application, the first updating unit is specifically configured to:

performing Physical Failure Analysis (PFA) verification on the distribution information of the chip defects to obtain a first verification result;

and updating the first sample set according to the diagnosis report and the first verification result to obtain a second sample set.

and updating the first sample set according to the diagnosis report and a second verification result to obtain a second sample set, wherein the second verification result is a verification result corresponding to the root cause of the n-bit in the first verification result, which is the integer greater than 0, with the probability ranking.

Acquiring pre-configured initial root cause weight information;

determining a weight adjustment coefficient in the first neural network from the first set of samples;

and updating the initial root cause weight information according to the weight adjustment coefficient to obtain the target root cause weight information.

and updating the initial root cause weight information according to the weight updating information by using a gradient updating algorithm to obtain the target root cause weight information, wherein the gradient updating algorithm comprises a random gradient descent SGD (generalized gradient descent) or a self-adaptive moment estimation gradient descent algorithm Adam.

In a possible implementation manner of the second aspect of the embodiments of the present application, the initial root cause weight information is obtained through training of a sample set with correct root cause distribution information.

In a possible implementation manner of the second aspect of the embodiments of the present application, the diagnostic report includes a plurality of diagnostic information, and any one of the plurality of diagnostic information includes at least one of the following parameters:

In a possible implementation manner of the second aspect of the embodiments of the present application, the first sample set includes samples of at least two different chip designs and/or samples of at least two different chip processes.

In a possible implementation manner of the second aspect of the embodiments of the present application, the first sample set includes samples obtained by the variational self-encoder VAE or the generation of the antagonistic network GAN compression.

adjusting the characteristic information according to the target root cause weight information to obtain adjusted characteristic information;

And determining the distribution information of the root cause of the chip based on the adjusted characteristic information.

determining the distribution information of the root cause of the chip in an EM algorithm with the maximum expected value based on the adjusted characteristic information; or alternatively, the first and second heat exchangers may be,

and determining the distribution information of the chip root cause in a second neural network based on the adjusted characteristic information.

and taking the characteristic information as the input of the first neural network, and obtaining the root cause distribution information through the processing of the first neural network.

In a possible implementation manner of the second aspect of the embodiments of the present application, the first neural network includes a feature extraction module and a classification module, and the processing unit is specifically configured to:

the feature information is used as input of the feature extraction module, and the feature corresponding to the feature information is obtained through the processing of the feature extraction module;

and taking the feature as the input of the classification module, and obtaining the distribution information of the chip root cause through the processing of the classification module.

In a possible implementation manner of the second aspect of the embodiments of the present application, the first neural network further includes a normalization module, and the processing unit is specifically configured to:

taking the feature as input of the standardization module, and processing by the standardization module to obtain the feature in a standardized format;

and taking the feature in the standardized format as the input of the classification module, and obtaining the distribution information of the root cause of the chip through the processing of the classification module.

In a possible implementation manner of the second aspect of the embodiments of the present application, the first neural network is a neural network that is trained based on a data set formed by a diagnostic report of a note obtained by error injection.

In a possible implementation manner of the second aspect of the embodiments of the present application, the first neural network is a multi-layer perceptron MLP or a convolutional neural network CNN.

In the second aspect of the embodiments of the present application, the constituent modules of the root cause analysis device may also be used to execute the steps executed in each possible implementation manner of the first aspect, and reference may be specifically made to the first aspect, which is not described herein.

A third aspect of the embodiments of the present application provides a root cause analysis device, comprising a processor, the processor being coupled to a memory, the memory being configured to store a computer program or instructions, the processor being configured to execute the computer program or instructions in the memory, such that the root cause analysis device implements the method of the first aspect or any one of the possible implementations of the first aspect.

A fourth aspect of the embodiments of the present application provides a computer-readable storage medium storing one or more computer-executable instructions which, when executed by a processor, perform a method as in the foregoing first aspect or any one of the possible implementations of the first aspect.

A fifth aspect of the embodiments of the present application provides a computer program product storing one or more computers, which when executed by the processor performs the method of the first aspect or any one of the possible implementations of the first aspect.

A sixth aspect of the embodiments of the present application provides a chip system, which includes at least one processor, for supporting the root cause analysis device to implement the method of the foregoing first aspect or any one of the possible implementation manners of the first aspect.

In one possible design, the system-on-chip may further include a memory for storing program instructions and data necessary for the root cause analysis device. The chip system can be composed of chips, and can also comprise chips and other discrete devices. Optionally, the system on a chip further comprises interface circuitry providing program instructions and/or data to the at least one processor.

The technical effects of the second aspect to the sixth aspect or any one of the possible implementation manners of the second aspect may be referred to technical effects of the first aspect or technical effects of different possible implementation manners of the first aspect, which are not described herein.

From the above technical solutions, the embodiments of the present application have the following advantages: after a diagnostic report for indicating the chip defect diagnosis information is acquired, determining the characteristic information of the chip defect according to the diagnostic report; thereafter, root cause distribution information of the chip defect is determined based on the characteristic information using a first neural network. Compared with an implementation mode of calculating only posterior probability based on a Bayesian network model, in an implementation mode of determining root cause distribution information through a neural network, because the characteristic information processed by the neural network comprises the characteristic information extracted according to a diagnosis report and the variable space of network parameters contained in the neural network is large, the root cause distribution information of chip defects with relevance can be fitted on a high-dimensional space, and therefore root cause analysis accuracy in a root cause analysis process based on the diagnosis report can be improved.

Drawings

FIG. 1 is a schematic diagram of a chip test process;

FIG. 2 is a schematic diagram of a root cause analysis method according to an embodiment of the present disclosure;

FIG. 3 is another schematic diagram of a root cause analysis method according to an embodiment of the present disclosure;

FIG. 4a is another schematic diagram of a root cause analysis method according to an embodiment of the present disclosure;

FIG. 4b is another schematic diagram of a root cause analysis method according to an embodiment of the present disclosure;

FIG. 5 is another schematic diagram of a root cause analysis method according to an embodiment of the present disclosure;

FIG. 6a is another schematic diagram of a root cause analysis method according to an embodiment of the present disclosure;

FIG. 6b is another schematic diagram of a root cause analysis method according to an embodiment of the present disclosure;

FIG. 6c is another schematic diagram of a root cause analysis method according to an embodiment of the present disclosure;

FIG. 7a is another schematic diagram of a root cause analysis method according to an embodiment of the present disclosure;

FIG. 7b is another schematic diagram of a root cause analysis method according to an embodiment of the present disclosure;

FIG. 7c is another schematic diagram of a root cause analysis method according to an embodiment of the present disclosure;

FIG. 7d is another schematic diagram of a root cause analysis method according to an embodiment of the present disclosure;

FIG. 8 is another schematic diagram of a root cause analysis method according to an embodiment of the present disclosure;

FIG. 9 is another schematic diagram of a root cause analysis method according to an embodiment of the present disclosure;

FIG. 10 is another schematic diagram of a root cause analysis method according to an embodiment of the present disclosure;

FIG. 11 is a schematic diagram of a root cause analysis device according to an embodiment of the present disclosure;

fig. 12 is another schematic diagram of a root cause analysis device according to an embodiment of the present application.

Detailed Description

Embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. The terms "first," "second," "third," and "fourth" and the like in the description and in the claims of this application and in the drawings, are used for distinguishing between different objects and not for describing a particular sequential order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus. Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

The root cause analysis method and the related equipment provided by the application are mainly applied to the field of chip manufacturing.

Yield, which defines the ratio of the number of acceptable dies to the number of all dies in the chip manufacturing process, is a key factor affecting the profit margin of the product. Traditional yield enhancement methods such as physical failure analysis (physical failure analysis, PFA), inline inspection (inline inspection) and structural testing (test structure) can locate systematic root causes. But these methods appear to be very inefficient in the iterative design process of the chip. For example, the cycle time and cost of PFA are very high, and it is substantially impossible to find systematic defects from a large number of failed chips using PFA. Thus, by statistically analyzing the batch diagnostic report, automatically finding the root cause of a physical defect is a better choice. RCI is the estimation of potential root cause distribution from batch diagnostic data by learning to locate the true root cause that leads to yield degradation.

Currently, methods for root cause analysis in the industry mainly include a maximum expectation algorithm (expectation maximization, EM), a local supervised learning method, and the like. The EM algorithm can rapidly calculate the posterior probability of each defect, summarize information of each diagnosis report, and optimize the information to obtain root cause probability distribution which enables the expectation to be maximum.

Taking the process of determining root cause by EM algorithm as an example, in the chip manufacturing process, it is first necessary to estimate the potential root cause distribution from the batch diagnostic report by root cause analysis (root cause identification, RCI) tool, thereby locating the true root cause (root cause) that leads to yield degradation. Typically, the input data of the RCI tool is a diagnostic report (diagnostic report) obtained from the chip test procedure, which will be described by the flow shown in fig. 1.

As shown in fig. 1, the chip test process includes the following steps.

Firstly, testing the files on a test machine by using test vectors generated by an automatic test generator (automatic test pattern generator, ATPG), finding out the type of errors according to a fault dictionary (fault dictionary) corresponding to the output result of a logic circuit, and obtaining error data (fail data) of automatic test equipment (auto test equipment, ATE);

thereafter, layout-aware diagnostics (layout aware diagnosis) are performed on the failed pins in ATE Fail Data in combination with multi-level Data such as netlist, pattern, layout (netlist pattern layout), and root information extraction (root cause information extraction) is performed in combination with root information (root cause information) in prior knowledge, so as to generate a diagnostic report (diagnosis report).

The netlist (netlist), the pattern (layout), the layout (layout), and the layout-aware diagnostics (layout aware diagnosis) are all intermediate steps (or intermediate parameters) for implementing a chip design through electronic design automation (electronic design automation, EDA). Illustratively, netlists (netlist), or netlists, refer to a description of the connection of digital circuits in EDA using basic logic gates; the array of logic gates is referred to as a "netlist" because it has the same appearance as a netlist.

Step 102, a Bayesian network module and an RCI root cause analysis module analyze and obtain root causes causing chip failure aiming at the generated diagnosis report. It can be seen that the RCI tool is an important step in the chip test procedure, and the EM algorithm can be applied in the root cause analysis tool.

Further, as shown in fig. 2, the EM algorithm may calculate based on the test result of the chip test process shown in fig. 1, and instruct the process design improvement of the chip through the calculation result. The process shown in fig. 2 includes the following implementation steps:

step 201, obtaining a diagnosis report by a chip test process, obtaining posterior probability (also called root posterior probability) based on the diagnosis report, and taking the posterior probability as input of a root cause analysis tool;

Step 202, calculating posterior probability by an EM algorithm based on the input root delay probability by a root analysis tool to obtain root distribution, and taking the root distribution as input of a PFA verification module;

in step 201 and step 202, the implementation process shown in fig. 1 corresponds. Specifically, in step 201 and step 202, the probability distribution of the root cause is calculated using a bayesian model.

The diagnostic report is shown in part in fig. 3. The diagnostic report of the chip is used to indicate diagnostic information of the chip defect, and generally, the diagnostic report includes a plurality of diagnostic information (the plurality of diagnostic information may be denoted as a plurality of suspicious (select) information). Illustratively, the diagnostic report includes a plurality of diagnostic information items including: the logic error corresponds to the diagnosis information in the diagnosis report, and different diagnosis information is marked by a serial number, such as a value of '1.1' in the figure; a score is a credibility score of the diagnosis information, which indicates the credibility of the diagnosis information for interpreting the observed ATE error data, and a value of '100' in the figure indicates that the diagnosis information is completely feasible; physical defect corresponding type and layout layer (type+layout_layer) information, wherein the type value is "OPEN", "BRIDGE", "CELL", etc. represent different physical defect types, the layout layer (layout_layer) represents the physical position of the physical defect, M represents a metal layer, VIA represents a connecting hole, etc.; the critical area is the area of the potentially erroneous area, the larger the area, the higher the likelihood of occurrence. Failure matches indicate the number of test items that cannot be interpreted with the diagnostic information, and mismatch indicates the number of test items that should be observed but not observed for the diagnostic information to occur.

The relevant parameters are defined as follows:

root cause-various root causes given by the corresponding RCI tool. For example, M1 Open, critiarea OPEN M1, from RCI tools, indicates that an Open circuit has occurred in the first metal layer of the chip; m1 Bridge, critiarea SHORT M1, from RCI tools, indicates that the first metal layer of the chip is bridged (shorted).

Physical defects: the physical defect in the corresponding diagnostic report is determined by the value of "type" and the value of "layout_layer" of each diagnostic information in the diagnostic report, see fig. 3. Physical defects are defects given by diagnostic reports that may lead to observed logic errors, which are caused by root causes. For example, open 0 corresponds to type being Open and layout_layer being M0.

Logic error: the observed logic error information is determined by the value of "select" in the diagnostic report when the test machine tests the chip, for example, as shown in fig. 3, the value of select corresponding to Fault 0 is 1.1.

Based on the diagnostic report, probabilistic connections between root cause, physical defects, and logical errors are established. Based on the probability relation, the probability distribution of the root cause can be calculated by using methods such as an EM algorithm and the like. The following are defined:

P (v) detecting the probability of obtaining the batch of diagnostic reports (v);

p (r) detecting the probability of getting a diagnostic report (report, denoted r);

p (f) probability of detecting logic fault (denoted as f);

p (d) probability of detecting physical errors (denoted as d);

p (c) probability of occurrence of a physical root cause (denoted as c);

p (r|f) probability of detecting the diagnostic report r when the logic error f occurs;

p (f|d) probability of detecting a logical error f when a physical error d occurs;

p (d|c) probability of detecting physical error d when physical root cause c occurs;

the posterior probabilities include P (r|f), P (f|d), and P (d|c).

Modeling P (v) by bayesian model, assuming that all diagnostic reports satisfy independent co-distributions (independent and identically distributed, i.i.d.) (remarks: die (dies) on the same wafer (wafer) are obtained in the middle of the same process, so it can be considered that the corresponding diagnostic report satisfies i.i.d, but P (c) is different between wafers of different lots (batch) due to the difference of process and middle noise _k ) Not guaranteed to be identical, so the diagnostic reports obtained by different wafer do not necessarily meet i.i.d.), one can obtain:

Or expressed in another form:

the two forms of the above formula (1) and formula (2) are equivalent. Furthermore, in both of the above forms, N represents the number of batch diagnostic reports, P (r _n ) Refers to the probability of occurrence of the nth physical root cause (noted c) in the N diagnostic reports; k represents the number of all root causes, P (c) _k ) Refers to the probability that the kth root causes occur among the K root causes.

In the calculation process of the EM algorithm, it is assumed that all different logic fault, physical defect and root cause variables are mutually independent. I.e. assuming a one-to-one correspondence of root causes with physical defects and/or a one-to-one correspondence of root causes with logical errors.

An exemplary complete causal link chain for a diagnostic report is shown in fig. 4a, for example. In one diagnostic report, different logic errors are independent of each other; each logical error is caused by a plurality of possible physical defects, noting that a logical error may be caused by a plurality of identical physical defect types, such as Open defect; different Fault may have the same root cause, e.g., M1 Open may result in both Fault0 and Fault1.

Step 203. The PFA verification module verifies based on the root cause distribution of the input and takes the diagnosis report with the correct verification result as the input of the process design improvement module;

Step 204. The process design improvement module improves the process design process of the chip based on the input verification result being a correct diagnostic report.

The root cause analysis process based on the EM algorithm mainly comprises the following two defects:

first, in the bayesian network modeling process, it is assumed that the logic errors, physical defects and root dependent variables in the diagnostic report are all independent and distributed, but some defects occur simultaneously in reality. Therefore, the precondition assumption of the EM algorithm is too strong, which results in insufficient accuracy of the resulting root cause probability distribution. That is, the EM algorithm cannot handle the correlation between each defect and each root cause based on independent co-distribution assumptions.

Second, because different processes have a greater impact on root cause analysis tool accuracy, particularly as process dimensions become smaller, the root cause of the middle process layer is more difficult to distinguish. The EM algorithm is poorly adapted to different processes.

In addition, root cause analysis by Deep Learning (Deep Learning) is a mainstream development direction in the current academia and industry. Deep learning methods are widely used for classification and detection tasks, both in information systems, industrial internet and medical systems. In the same way, in the root cause analysis field of the chip, the deep learning method can provide root cause distribution fitting capability with higher precision, and has the defect of insufficient generalization performance.

Illustratively, there is a root cause analysis process in the current industry based on a deep learning implementation as shown in fig. 4 b. In comparison with the implementation process shown in fig. 2, the difference is that a supervised deep learning module 205 located before the root cause analysis tool 202 is newly added, where the supervised deep learning module 205 adjusts the posterior probability distribution of a single diagnostic report by using a supervised learning method, so as to obtain and send the adjusted posterior probability to the root cause analysis tool 202, and the implementation process of the subsequent root cause analysis tool 202, PFA verification 203 and process design improvement 204 may refer to the foregoing description of fig. 2, which is not repeated herein.

However, the implementation shown in fig. 4b still has certain limitations. It is clear from the corresponding description of fig. 4a that not only the corresponding posterior probability but also a plurality of diagnostic information indicated by the diagnostic report, such as logic errors, physical defects, etc., can be obtained through the diagnostic report, while the implementation shown in fig. 4b is only used for local adjustment of the posterior probability of a single diagnostic report, and does not use supervised learning for global root cause analysis. I.e. the implementation shown in fig. 4b does not enable a global root cause analysis of other parameters (than posterior probability) that are involved in a single or batch of diagnostic reports.

In summary, in the above implementation manner, the EM algorithm cannot process the correlation between each defect and each root cause based on the independent same distribution assumption; in addition, the local supervised learning adjusts the posterior probability of a single diagnostic report by using a supervised machine learning method, and the global information of all diagnostic reports in the wafer cannot be fully utilized. Therefore, how to improve the root cause analysis accuracy of the RCI tool is a technical problem to be solved urgently.

Therefore, the embodiment of the application provides a root cause analysis method and related equipment, which are used for improving root cause analysis precision in the root cause analysis process based on a diagnosis report. The following detailed description will be given with reference to the accompanying drawings.

Referring to fig. 5, a schematic diagram of a root cause analysis method according to an embodiment of the present application is provided, and the method includes the following steps.

S100, obtaining a diagnosis report.

In this embodiment, the root cause analyzing apparatus acquires a diagnostic report (diagnostic report) indicating diagnostic information of a chip defect in step S100.

Optionally, the diagnostic information of the chip defect is diagnostic information obtained by performing a chip test process on a number k (k is an integer greater than 1) of chips; alternatively, the diagnostic information of the chip defect is diagnostic information obtained by performing a chip test process on a certain chip, and is not limited herein.

For example, the diagnostic information includes information related to a logic error, a physical defect, etc., and is described with reference to fig. 3, which is not repeated herein.

Specifically, the root cause analysis device may be a device capable of running a code (and/or a program, for example, electronic design automation (electronic design automation, EDA) software) corresponding to the root cause analysis method provided in the present application, for example, a server, a virtual machine, a data center, a mobile or user device, a network component, or a part of an execution module in a server, a virtual machine, a data center, a mobile or user device, a network component, or the like, which is not limited herein.

In step S100, the root cause analysis device may obtain the diagnostic report through the chip test process shown in fig. 1; the root cause analysis device can also obtain diagnosis reports obtained by real-time acquisition (or offline acquisition) in other equipment through a communication interaction mode with other equipment; the root cause analysis device can also respond to the input operation of a user to obtain the diagnosis report through an input/output module carried by the root cause analysis device; the root cause analysis device may also obtain the diagnostic report by other means, not limited herein.

In one possible implementation, the diagnostic report includes a plurality of diagnostic information, and any one of the plurality of diagnostic information includes at least one of the following parameters:

S200, extracting features according to the diagnosis report to obtain the feature information of the chip defects.

In this embodiment, the root cause analysis device performs feature extraction according to the diagnostic report obtained in step S100 in step S200 to obtain the feature information of the chip defect.

In one possible implementation, the feature information of the chip defect includes first feature information; the process of extracting the features of the chip defect by the root cause analysis device according to the diagnosis report in step S200 specifically includes: firstly, determining the posterior probability of the chip defect according to the diagnosis report, wherein the posterior probability is used for indicating the probability that the diagnosis information is detected when the chip defect occurs; and then, carrying out feature extraction on the posterior probability to obtain the first feature information.

Specifically, after the root cause analysis device acquires the diagnostic report at step S100, the posterior probability of the chip defect may be first determined based on the diagnostic report included in the diagnostic report; and then, carrying out feature extraction based on the posterior probability to obtain first feature information. The characteristic information of the chip defect at least comprises the first characteristic information, so that the characteristic information of the chip defect processed by the neural network at least is used for representing the posterior probability. The root cause analysis device extracts the diagnosis report obtained in the step S100 to obtain a diagnosis report in the characteristic information in the step S200; the root cause analysis device establishes a probabilistic connection among the root cause, the physical defect, and the logical error based on the diagnostic report acquired in step S100, to determine a posterior probability.

Illustratively, the posterior probabilities include P (r|f), P (f|d), and P (d|c). Specifically, P (r|f) indicates the probability that the diagnostic report r is detected when a logical error f occurs; p (f|d) indicates the probability that a logical error f is detected when a physical error d occurs; p (d|c) indicates the probability that a physical error d is detected when a physical root cause c occurs.

Furthermore, the posterior probability is derived based on the aforementioned diagnostic report, and the diagnostic report includes a plurality of diagnostic information items; therefore, the posterior probability and the diagnostic report also have a corresponding correlation. Illustratively, P (f|d) in the posterior probability is positively correlated to a confidence score (score) in the diagnostic information; p (d|c) in the posterior probability is positively related to the critical region in the diagnostic information, CELL; p (d|c) in the posterior probability is positively correlated to the number of occurrences of the same tpye of the diagnostic information.

In one possible implementation, the feature information of the chip defect includes second feature information; the process of extracting the features of the chip defect by the root cause analysis device according to the diagnosis report in step S200 specifically includes: and extracting the characteristics of the diagnosis report to obtain the second characteristic information.

Specifically, after the root cause analysis device acquires the diagnostic report in step S100, it may perform feature extraction based on the diagnostic report included in the diagnostic report, and obtain the second feature information based on the diagnostic report. The characteristic information of the chip defect at least comprises the second characteristic information, so that the characteristic information of the chip defect processed by the neural network is used for representing the diagnosis report.

S300, processing the characteristic information based on a first neural network to obtain root cause distribution information of the chip defects.

In this embodiment, the root cause analysis device processes the characteristic information in step S200 based on the first neural network to obtain root cause distribution information of the chip defect. The root distribution information is used for indicating the root probability distribution of the chip defect.

In one possible implementation, the first neural network is a multi-layer perceptron (multilayer perceptron, MLP), a convolutional neural network (convolutional neural network, CNN), or other type of neural network, without limitation.

Specifically, the implementation of the Neural Network (NN) has a great flexibility, that is, in order to solve the same technical problem, different designs based on the neural network may be optimized in different links of the technical problem.

For example, in one implementation, referring to the implementations shown in fig. 2 and 4b, the posterior probability is used as an input to the root cause analysis tool, and the root cause distribution information is output through the processing of the root cause analysis tool. In step S300, as shown in fig. 6a, compared with the implementation of fig. 2, the implementation process adds a first neural network 602 located before the root cause analysis module 603, optimizes the feature information obtained in step S200 through the first neural network 602 to obtain processed feature information, and inputs the processed feature information to the root cause analysis tool 603 to obtain root cause distribution information of the chip defect. The PFA verification module 604 and the process design improvement module 605 are optional modules, and the implementation process is similar to that described in fig. 2, and will not be repeated here.

As another example, in one implementation, in step S300, the implementation process is as shown in fig. 6b, and compared to the implementation of fig. 2, the root cause analysis tool 202 in fig. 2 is replaced by the first neural network 702, the feature information obtained in step S200 is used as an input of the first neural network 702, and the root cause distribution information of the chip defect is output through the processing of the first neural network 702, without using the root cause analysis tools in the implementation shown in fig. 2 and fig. 4 b. The PFA verification module 703 and the process design improvement module 704 are used as optional modules, and the implementation process is similar to that described in fig. 2, and will not be repeated here.

As another example, in one implementation, the process of outputting root cause distribution information is processed by a root cause analysis tool in the implementations shown with reference to fig. 2 and 4 b. In step S300, as shown in fig. 6c, in the implementation process, compared with the implementation manner of fig. 2, the first neural network 602 located after the root cause analysis module 603 is newly added, the feature information obtained in step S200 is used as the input of the root cause analysis tool 802, the initial root cause distribution information is obtained through the processing of the root cause analysis tool 802, and then the initial root cause distribution information is used as the input of the first neural network 803, and the optimized root cause distribution information is obtained through the processing of the first neural network 803. The PFA verification module 804 and the process design improvement module 805 are used as optional modules, and the implementation process is similar to that described in fig. 2, and will not be repeated here.

Optionally, in fig. 6c, in order to improve the processing effect of the first neural network 803, the feature information extracted from the diagnostic report 801 may also be used as a part of the input of the first neural network 803, so that the first neural network 803 performs the processing of the neural network according to more input information, and improves the confidence level of root cause distribution information obtained by the processing.

The two implementation examples of fig. 6a and 6b mentioned above will be described in detail below.

Implementation one, as shown in fig. 6 a.

In one possible implementation manner, the process of obtaining root cause distribution information of the chip defect by the root cause analysis device based on the first neural network in step S300 specifically includes: first, a first sample set is acquired, wherein the first sample set comprises a preconfigured diagnostic report and a root cause of the preconfigured diagnostic report; then, determining target root cause weight information according to the first sample set by using the first neural network, wherein the target root cause weight information is used for adjusting the weight of the characteristic information; thereafter, the root cause distribution information is determined from the target root cause weight information and the feature information.

Specifically, the first neural network is trained through a preconfigured first sample set to obtain relevant network parameters, and then target root cause weight information, which is determined by the first neural network and is used for adjusting the weight of the characteristic information, has relevant characteristics of the first sample set.

In addition, in the implementation process, the root cause analysis device determines the root cause distribution information according to the target root cause weight information and the feature information specifically includes: firstly, the root cause analysis device adjusts the characteristic information according to the target root cause weight information to obtain adjusted characteristic information; then, the root cause analyzing means determines distribution information of the root cause of the chip based on the adjusted characteristic information.

For example, referring to fig. 7a, a root cause weight adjustment 606 module is added in comparison to the implementation of fig. 6 a. Wherein a first set of samples is preconfigured in the first neural network 602; thereafter, the first neural network 602 processes based on the first sample set to obtain target root cause weight information, where the target root cause weight information is used to adjust the weight of the feature information; next, the target root weight information is input to the root weight adjustment module 606, and the feature information obtained in step S200 is processed by the root weight adjustment module 606 to obtain adjusted feature information.

Further, the process of determining the distribution information of the root cause of the chip (i.e. the implementation process of the root cause analysis tool 603 in fig. 6a or fig. 7 a) by the root cause analysis device based on the adjusted feature information specifically includes: the root cause analysis device determines the distribution information of the chip root cause in a maximum expected value (EM) algorithm based on the adjusted characteristic information; or, the root cause analysis device determines the distribution information of the chip root cause in the second neural network based on the adjusted characteristic information; or by other means, not limited herein.

Optionally, in the implementation process, the process of determining, by the root cause analysis device, the target root cause weight information in the first neural network according to the first sample set specifically includes: firstly, a root cause analysis device acquires initial root cause weight information; then, the root cause analysis device determines a weight adjustment coefficient in the first neural network according to the first sample set; thereafter, the root cause analysis device updates the initial root cause weight information based on the weight adjustment coefficient to obtain the target root cause weight information.

Specifically, in the implementation process of the scheme, initial root cause weight information for adjusting the feature information may be preconfigured. In the process of determining target root cause weight information according to the first sample set in the first neural network, determining a weight adjustment coefficient according to the first sample set in the first neural network, and updating initial root cause weight information according to the weight adjustment coefficient to obtain the target root cause weight information. Specifically, the user performs personalized configuration on the weight adjustment coefficient obtained by the first neural network in a user pre-configuration mode to obtain the weight adjustment coefficient, and further updates the initial root cause weight coefficient through the obtained weight adjustment coefficient to determine the target root cause weight coefficient.

For example, as shown in fig. 7b, the initial root weight information may be preconfigured in the root weight adjustment module 606, as compared to the implementation shown in fig. 7 a. Thus, the first neural network 602 may obtain the weight adjustment coefficient based on the first sample set processing, and compared with the implementation process shown in fig. 7a, the computational complexity may be reduced to a certain extent.

Optionally, in the implementation process, the process of obtaining the target root cause weight information specifically includes: the root cause analysis device updates the initial root cause weight information according to the weight update information to obtain the target root cause weight information using a gradient update algorithm including a random gradient descent (stochastic gradient descent, SGD) or an adaptive moment estimation gradient descent algorithm (adaptive moment estimation gradient descent, adam). The root cause analysis device updates the initial root cause weight information according to the weight update information, and can be realized based on a gradient update algorithm in the process of obtaining the target root cause weight information. The gradient update algorithm may include SGD, adam, or other algorithms, which are not limited herein.

Optionally, the initial root weight information is obtained through training of a sample set with correct root distribution information. The pre-configured initial root weight information for adjusting the feature information may be information obtained by training a sample set having correct root distribution information. The initial root weight information has the performance of adjusting the characteristic information, and further, the target root weight information obtained subsequently according to the initial root weight information also has the corresponding performance of adjusting the characteristic information, so that the accuracy of the root analysis process is improved.

Implementations of the pre-configuration may include vendor pre-configuration and user pre-configuration implementations are described below with respect to the example shown in FIG. 7 c. Illustratively, as shown in FIG. 7c, a sample pool 607 is added in comparison to the implementation shown in FIGS. 7a and 7 b. The sample pool 607 may store (vendor pre-configured) an initial sample set in advance, and then update the pre-stored initial sample set based on a user operation instruction (user pre-configured) to obtain a first sample set input into the first neural network 602.

Optionally, after step S300, the method further includes: firstly, updating the first sample set according to the distribution information of the chip defects by a root cause analysis device to obtain a second sample set; then, the root cause analysis device updates the target root cause weight information in the first neural network according to the second sample set.

Specifically, after step S300, the root cause analysis device may further update the first sample set used by the first neural network according to root cause distribution information of the chip defect obtained in the current root cause analysis process. And then updating the target root cause weight information according to the first sample set obtained in the updating process so as to enrich the sample set calculated by the first neural network and further improve the processing performance of the subsequent first neural network.

Optionally, in the implementation process, the process of updating the first sample set by the root cause analysis device according to the distribution information of the chip defects to obtain the second sample set specifically includes: firstly, performing physical failure analysis (physical failure analysis, PFA) verification on the distribution information of the chip defects to obtain a first verification result; then, the first sample set is updated according to the first verification result and the diagnosis report, and a second sample set is obtained.

Specifically, in the process of updating the first sample set according to the distribution information of the chip defect to obtain the second sample set, the updating may be specifically performed according to the PFA verification result corresponding to the distribution information of the chip defect. The PFA verification process is a process of manually verifying by a user, namely, a result of the manual verification is used as an updating basis of the sample set, so that the accuracy of a root cause analysis process of a second sample set updated according to the follow-up basis can be improved.

As illustrated in fig. 7d, compared to the implementation manner of fig. 7a to 7c, based on the user operation instruction, the samples in the sample pool 607 may be further expanded according to the verification result of the PFA verification 604, so that the subsequent first neural network 602 can achieve better prediction performance based on the expanded samples in the sample pool 607, and the accuracy of the subsequent root cause analysis process according to the updated second sample set is improved.

Optionally, in the implementation process, the root cause analysis device updates the first sample set according to the first verification result and the diagnostic report, and the process of obtaining the second sample set specifically includes: and updating the first sample set according to a second verification result and the diagnosis report to obtain a second sample set, wherein the second verification result is a verification result corresponding to the root cause of the n-bit before probability ranking in the first verification result, and n is an integer greater than 0.

Specifically, the process of updating the first sample set according to the first verification result and the diagnostic report to obtain a second sample set may specifically use the second verification result corresponding to the root cause of the top n bits in the first verification result as the update basis of the sample set. That is, the part with larger reference value in the first verification result is used as the update basis of the sample set, so that the update process is simplified, and the processing efficiency is improved.

Optionally, in the implementation, the first set of samples includes samples of at least two different chip designs and/or samples of at least two different chip processes. Wherein the first sample set is used as one of the basis for determining root cause distribution information in the first neural network, and the first sample set can comprise samples of at least two different chip designs and/or samples of at least two different chip processes. So that the root cause analysis tasks of different processes and/or different designs can be adapted in the process of calculating the first neural network based on the first sample set.

For example, samples of at least two different chip designs may indicate sample data of at least two chips corresponding to chip designs of different functions, such as a graphics processing unit (graphics processing unit, GPU) chip, a central processing unit (central processing units, CPU), wireless fidelity (wireless fidelity, wi-Fi), or chip designs of other chip functions, without limitation. Samples of at least two different chip processes may indicate sample data of at least two chips corresponding to the different chip processes, such as a 5 nanometer (nm) chip process, a 7nm chip process, a 14nm chip process, or other chip processes, without limitation. Thus, the above-described first sample set comprising samples of at least two different chip designs and/or samples of at least two different chip processes may particularly indicate that the first sample set comprises sample data of the same chip design (e.g. 5nm chip process) and different chip processes (e.g. CPU chip and Wi-Fi chip); alternatively, the first sample set includes sample data of different chip designs (e.g., 5nm chip process and 7nm chip process) and the same chip process (e.g., CPU chip); alternatively, the first sample set may include sample data of different chip designs (e.g., 5nm chip process and 7nm chip process) and different chip processes (e.g., CPU chip and Wi-Fi chip), and the user/vendor may configure corresponding sample data in the first sample set according to different application requirements.

It should be noted that, as defined above for the first sample set, the sample data herein includes at least a preconfigured (chip) diagnostic report, and a root cause of the preconfigured (chip) diagnostic report.

In one possible implementation, the first set of samples includes samples compressed by a variational self-encoder (variational autoencoder, VAE) or a generation antagonism network (generative adversarial network, GAN). The first set of samples used for calculation by the first neural network may include samples obtained by compression of VAE or GAN, so as to save sample storage space.

In this embodiment, the root cause analysis method provided in the present application is implemented by EDA software as an example. Typically, EDA software is provided by a software vendor, who can optimize the production process of the chip through the EDA software provided by the software vendor. As shown in the implementation scenario of fig. 8, in the EDA software of the factory configuration, the software vendor may initialize relevant parameters (including root weight m, operation parameters in the root analysis module, network parameters in the NN network, etc.) based on the diagnostic report in the data set of the software vendor.

The network parameters of the NN network comprise an initialization parameter and a user online updating parameter. The initialization parameters are provided by the software vendor and are divided into two phases. The first stage utilizes super-parametric search to obtain root cause weight m which enables the EM algorithm to have optimal performance in an offline data set; and fixing root cause weight in the second stage, training an AI module on the offline data set to obtain an optimal network parameter as the initialization parameter. Thereafter, the user obtains marked samples by misinjection or PFA during the process of using the EDA software, and can input the samples into the sample pool; after a certain number of samples are accumulated, the user can fix the network parameters of the NN network, online update the network parameters of the NN network by using the noted samples (such as the first sample set or the second sample set described above), and gradient update the parameters of the root cause weight adjustment module based on the updated network parameters.

In addition, the sample pool is used for pre-storing typical characteristics of a part of the diagnostic report (such as related characteristics corresponding to the initial sample set in the foregoing description) and user-labeled diagnostic report characteristics (such as related characteristics corresponding to the first sample set or the second sample set in the foregoing description). To maintain the update accuracy, a large number of features need to be pre-stored, which may occupy a large amount of memory space, compressed storage, such as VAE or GAN, may be implemented using an Encoder (Encoder) and a Decoder (Decoder), and the VAE storage features may be employed in the feature production module as shown in fig. 9. Alternatively, the storage space may be independent of each other, updated to obtain different weights, for user-labeled features of different designs and processes (e.g., 5nm/7nm, etc.).

Implementation two, as shown in fig. 6 b.

In one possible implementation manner, the implementation process of step S300 specifically includes: the root cause analysis device takes the characteristic information as the input of the first neural network, and obtains the root cause distribution information through the processing of the first neural network. Specifically, in the process of obtaining root cause distribution information based on the characteristic information processed by the first neural network, the root cause analysis device may use the characteristic information corresponding to the diagnostic report as an input to the first neural network, and output the root cause distribution information through the processing of the first neural network. In other words, root cause analysis is realized through the reasoning process of the neural network, compared with the calculation process based on the Bayesian network model, the root cause distribution information of the chip defects with relevance can be fitted on a high-dimensional space due to the fact that the variable space of network parameters contained in the neural network is larger, and therefore the root cause analysis precision in the root cause analysis process based on the diagnosis report can be improved.

Optionally, the first neural network includes a feature extraction (feature extractor) module and a classification module, and the process of obtaining the root cause distribution information by using the feature information as an input of the first neural network and processing the feature information by the first neural network specifically includes: firstly, taking the characteristic information as input of the characteristic extraction module, and obtaining features corresponding to the characteristic information through processing of the characteristic extraction module; and then, taking the feature as the input of the classification module, and obtaining the distribution information of the chip root cause through the processing of the classification module. That is, in the calculation process, the first neural network can sequentially implement the determination of the distribution information of the root cause of the chip through operations such as feature extraction, feature classification and the like.

Further, the first neural network further includes a standardization (standardization) module, and the process of obtaining the distribution information of the root cause of the chip by using the feature as the input of the classification module and processing the feature by the classification module specifically includes: firstly, taking the feature as input of the standardization module, and obtaining the feature in a standardized format through processing of the standardization module; and then, taking features in the standardized format as input of the classification module, and obtaining the distribution information of the chip root cause through processing of the classification module. The first neural network may further include a normalization module for performing normalization processing on features, so as to promote consistency of intermediate process data in the reasoning process of the first neural network.

For example, the implementation of the first neural network to obtain root cause distribution information based on the diagnostic report process may be as shown in fig. 10. The first neural network 702 at least includes a feature extraction module 7021, a classification module 7023, and a normalization module 7022 that may be included, and the distribution information of the root cause of the chip is obtained through processing of the relevant modules.

It should be noted that, in the first implementation manner, the implementation process of the first neural network may also be implemented in a similar manner, that is, the first neural network in the first implementation manner may also include a feature extraction module and a classification module, and a normalization module may be present, and the specific implementation process may refer to the description in the second implementation manner herein and will not be repeated herein.

Optionally, the first neural network is a neural network trained based on a data set formed by a diagnostic report of the annotation obtained by the fault injection. The method comprises the steps of obtaining a first neural network, wherein a data set formed on the basis of a labeling diagnosis report obtained by error injection is a data set which is manually verified by a user, and training the manually verified data set. The calculation result obtained by calculation of the first neural network accords with the expectation of a user, and the accuracy of the distribution information obtained by calculation based on the first neural network is improved.

Based on the technical scheme, the application at least has the following technical effects: on one hand, root cause distribution is fitted in a high-dimensional space by utilizing a neural network, so that root cause identification accuracy can be improved; in addition, the realization mode of the neural network can adapt to root cause analysis tasks of different processes and designs, on the premise of not reducing the original performance of the tool, the root cause analysis tool can adapt to different processes and designs, the estimation precision of root cause probability distribution of specific process designs can be further improved, the PFA efficiency is improved, and the cost is saved. On the other hand, the autonomy of the chip manufacturer for using and upgrading the tool can be effectively improved, after the new process is introduced, the root cause analysis precision improvement of the RCI tool depends on the interaction between the software manufacturer and the chip manufacturer, and the risk of data leakage exists, so that the chip manufacturer can update part of parameters of the root cause analysis tool by utilizing the data accumulated by the chip manufacturer, and the interaction frequency between the chip manufacturer and the software manufacturer can be reduced (for example, the descriptions of the foregoing figures 7a to 7 d).

The method of the embodiments of the present application is described above, and the embodiments of the present application are described below from the perspective of the apparatus.

Referring to fig. 11, a schematic diagram of a root cause analysis device according to an embodiment of the present application is provided. The root cause analysis device 1100 includes at least an acquisition unit 1101, a feature extraction unit 1102, and a processing unit 1103.

An acquisition unit 1101 for acquiring a diagnostic report for indicating diagnostic information of a chip defect;

the feature extraction unit 1102 is configured to perform feature extraction according to the diagnostic report, so as to obtain feature information of the chip defect;

the processing unit 1103 is configured to process the feature information based on the first neural network to obtain root cause distribution information of the chip defect, where the root cause distribution information is used to indicate root cause probability distribution of the chip defect.

In one possible implementation, the feature information of the chip defect includes first feature information; the feature extraction unit 1102 is specifically configured to:

In one possible implementation, the feature information of the chip defect includes second feature information;

the feature extraction unit 1102 is specifically configured to:

In one possible implementation, the processing unit 1103 is specifically configured to:

In one possible implementation, the apparatus further includes:

a first updating unit 1104, configured to update the first sample set according to the diagnostic report and root cause distribution information of the chip defect, to obtain a second sample set;

a second updating unit 1105, configured to update the target root cause weight information according to the second sample set.

In one possible implementation manner, the first updating unit 1104 is specifically configured to:

acquiring pre-configured initial root cause weight information;

In one possible implementation, the initial root weight information is trained from a set of samples with the correct root distribution information.

In one possible implementation, the first set of samples includes samples of at least two different chip designs and/or samples of at least two different chip processes.

In one possible implementation, the first set of samples includes samples compressed by the variational self-encoder VAE or the generation of the antagonism network GAN.

In one possible implementation manner, the first neural network includes a feature extraction module and a classification module, and the processing unit 1103 is specifically configured to:

In one possible implementation manner, the first neural network further includes a normalization module, and the processing unit 1103 is specifically configured to:

In one possible implementation, the first neural network is a neural network trained based on a data set formed from a misnoted diagnostic report.

In one possible implementation, the first neural network is a multi-layer perceptron MLP or a convolutional neural network CNN.

It should be noted that, the root cause analysis device shown in fig. 11 may be specifically used to implement the steps implemented by the root cause analysis device in the foregoing method embodiments, and implement the technical effects corresponding to the root cause analysis device, and the specific implementation manner of the root cause analysis device shown in fig. 11 may refer to the descriptions in the foregoing method embodiments, which are not described herein in detail.

Please refer to fig. 12, which is a schematic diagram of a hardware structure of a root cause analysis device according to an embodiment of the present application. Root cause analysis apparatus 1200 (the apparatus 1200 may be a computer device in particular) shown in fig. 12 includes a memory 1201, a processor 1202, a communication interface 1203, and a bus 1204. Wherein the memory 1201, the processor 1202 and the communication interface 1203 are communicatively coupled to each other via a bus 1204.

The memory 1201 may be a Read Only Memory (ROM), a static storage device, a dynamic storage device, or a random access memory (random access memory, RAM). The memory 1201 may store a program, and the processor 1202 and the communication interface 1203 are configured to execute respective steps of the model processing method of the embodiment of the present application when the program stored in the memory 1201 is executed by the processor 1202.

The processor 1202 may employ a general-purpose central processing unit (central processing unit, CPU), microprocessor, application specific integrated circuit (application specific integrated circuit, ASIC), graphics processor (graphics processing unit, GPU) or one or more integrated circuits for executing associated programs to perform functions required by the elements of the root cause analysis device of an embodiment of the present application or to perform model processing methods of an embodiment of the present application.

The processor 1202 may also be an integrated circuit chip with signal processing capabilities. In implementation, various steps of the model processing methods of the present application may be performed by integrated logic circuitry in hardware or instructions in software in processor 1202. The processor 1202 described above may also be a general purpose processor, a digital signal processor (digital signal processing, DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf programmable gate array (field programmable gate array, FPGA) or other programmable logic device, discrete gate or transistor logic device, discrete hardware components. The disclosed methods, steps, and logic blocks in the embodiments of the present application may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the embodiments of the present application may be embodied directly in hardware, in a decoded processor, or in a combination of hardware and software modules in a decoded processor. The software modules may be located in a random access memory, flash memory, read only memory, programmable read only memory, or electrically erasable programmable memory, registers, etc. as well known in the art. The storage medium is located in the memory 1201, and the processor 1202 reads information in the memory 1201, and in combination with its hardware, performs functions that need to be performed by units included in the root cause analysis device of the embodiment of the present application, or performs a model processing method of the embodiment of the method of the present application.

The communication interface 1203 uses a transceiver device, such as, but not limited to, a transceiver, to enable communication between the device 1200 and other devices or communication networks. For example, training data (e.g., training images as described in embodiments of the present application) may be obtained via the communication interface 1203.

The bus 1204 may include a path to transfer information between various components of the device 1200 (e.g., the memory 1201, the processor 1202, the communication interface 1203).

It should be noted that although the apparatus 1200 shown in fig. 12 shows only a memory, a processor, and a communication interface, those skilled in the art will appreciate that in a particular implementation, the apparatus 1200 also includes other devices necessary to achieve proper operation. Also, as will be appreciated by those of skill in the art, the apparatus 1200 may also include hardware devices that implement other additional functions, as desired. Furthermore, it will be appreciated by those skilled in the art that the apparatus 1200 may also include only the devices necessary to implement the embodiments of the present application, and not necessarily all of the devices shown in fig. 12.

It should be noted that, the root cause analysis device shown in fig. 12 may be specifically used to implement the steps implemented by the root cause analysis device in the foregoing method embodiments, and implement the technical effects corresponding to the root cause analysis device, and the specific implementation manner of the root cause analysis device shown in fig. 12 may refer to the descriptions in the foregoing method embodiments, which are not described herein in detail.

Embodiments of the present application also provide a computer-readable storage medium storing one or more computer-executable instructions that, when executed by a processor, perform a method as in the previous embodiments, according to a possible implementation of the analysis device.

Embodiments of the present application also provide a computer program product (or computer program) storing one or more computers, which when executed by the processor performs the method of the possible implementation of the root cause analysis device described above.

The embodiment of the application also provides a chip system, which comprises at least one processor and is used for supporting the terminal equipment to realize the functions related to the possible realization mode of the root cause analysis device. Optionally, the system on a chip further comprises interface circuitry providing program instructions and/or data to the at least one processor. In one possible design, the system on a chip may further include a memory to hold the necessary program instructions and data for the terminal device. The chip system can be composed of chips, and can also comprise chips and other discrete devices.

In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods may be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units. The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a storage medium, including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method of the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

The above embodiments are merely for illustrating the technical solution of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

A root cause analysis method, comprising:

acquiring a diagnosis report, wherein the diagnosis report is used for indicating diagnosis information of the chip defect;

extracting features according to the diagnosis report to obtain feature information of the chip defects;

and processing the characteristic information based on a first neural network to obtain root cause distribution information of the chip defects, wherein the root cause distribution information is used for indicating root cause probability distribution of the chip defects.
The method of claim 1, wherein the characteristic information of the chip defect includes first characteristic information;

the step of extracting the characteristics according to the diagnosis report, and the step of obtaining the characteristic information of the chip defects comprises the following steps:

Determining a posterior probability of the chip defect according to the diagnosis report, wherein the posterior probability is used for indicating the probability that the diagnosis information is detected when the chip defect occurs;

and extracting features of the posterior probability to obtain the first feature information.
The method according to claim 1 or 2, wherein the characteristic information of the chip defect comprises second characteristic information;

the step of extracting the characteristics according to the diagnosis report, and the step of obtaining the characteristic information of the chip defects comprises the following steps:

and extracting the characteristics of the diagnosis report to obtain the second characteristic information.
A method according to any one of claims 1 to 3, wherein processing the feature information based on a first neural network to obtain root cause distribution information of the chip defect comprises:

obtaining a first sample set, the first sample set comprising a preconfigured diagnostic report, and a root cause of the preconfigured diagnostic report;

determining target root cause weight information according to the first sample set by using the first neural network, wherein the target root cause weight information is used for adjusting the weight of the characteristic information;

and determining the root cause distribution information according to the target root cause weight information and the characteristic information.
The method of claim 4, wherein after the processing the feature information based on the first neural network to obtain root cause distribution information of the chip defect, the method further comprises:

updating the first sample set according to the diagnosis report and root cause distribution information of the chip defects to obtain a second sample set;

and updating the target root cause weight information according to the second sample set.
The method of claim 5, wherein updating the first set of samples based on the diagnostic report and root cause distribution information for the chip defects, the obtaining a second set of samples comprises:

performing Physical Failure Analysis (PFA) verification on the distribution information of the chip defects to obtain a first verification result;

and updating the first sample set according to the diagnosis report and the first verification result to obtain a second sample set.
The method of claim 6, wherein updating the first set of samples based on the diagnostic report and the first validation result, resulting in a second set of samples comprises:

and updating the first sample set according to the diagnosis report and a second verification result to obtain a second sample set, wherein the second verification result is a verification result corresponding to the root cause of the n top probability ranking bits in the first verification result, and n is an integer greater than 0.
The method of any of claims 4 to 7, wherein the determining target root cause weight information from the first set of samples using the first neural network comprises:

acquiring pre-configured initial root cause weight information;

determining a weight adjustment coefficient in the first neural network from the first set of samples;

and updating the initial root cause weight information according to the weight adjustment coefficient to obtain the target root cause weight information.
The method of claim 8, wherein updating the initial root cause weight information based on the weight update information to obtain the target root cause weight information comprises:

and updating the initial root cause weight information according to the weight updating information by using a gradient updating algorithm to obtain the target root cause weight information, wherein the gradient updating algorithm comprises a random gradient descent SGD (generalized discrete cosine model) or an adaptive moment estimation gradient descent algorithm Adam.
The method according to claim 8 or 9, wherein the initial root weight information is obtained by training a sample set with correct root distribution information.
The method according to any one of claims 2 to 10, wherein the diagnostic report comprises a plurality of diagnostic information, and wherein any one of the plurality of diagnostic information comprises at least one of the following parameters:

Logic error fault, wherein the logic fault is used for indicating sequence number identification of diagnostic information; or alternatively, the first and second heat exchangers may be,

a score, the score being used to indicate the trustworthiness of the diagnostic information; or alternatively, the first and second heat exchangers may be,

a critical area for indicating an area of an error area of the diagnostic information; or alternatively, the first and second heat exchangers may be,

fail match, the fail match is used for indicating the number of test items that can't be interpreted using diagnostic information; or alternatively, the first and second heat exchangers may be,

by not matching pass_mismatch, the pass_mismatch is used to indicate the number of test items that should be observed but not observed when diagnostic information occurs; or alternatively, the first and second heat exchangers may be,

type for indicating a defect type of the diagnostic information; or alternatively, the first and second heat exchangers may be,

layout layer for indicating the physical location of the diagnostic information.
The method according to any of claims 4 to 11, wherein the first set of samples comprises samples of at least two different chip designs and/or samples of at least two different chip processes.
The method according to any of claims 4 to 12, wherein the first set of samples comprises samples obtained by varying the self-encoder VAE or generating an antagonistic network GAN compression.
The method of any of claims 4 to 13, wherein said determining said root cause distribution information from said target root cause weight information and said characteristic information comprises:

adjusting the characteristic information according to the target root cause weight information to obtain adjusted characteristic information;

and determining the distribution information of the chip root cause based on the adjusted characteristic information.
The method of claim 14, wherein determining distribution information of the chip root cause based on the adjusted feature information comprises:

determining the distribution information of the root cause of the chip in an EM algorithm with the maximum expected value based on the adjusted characteristic information; or alternatively, the first and second heat exchangers may be,

and determining the distribution information of the chip root cause in a second neural network based on the adjusted characteristic information.
A method according to any one of claims 1 to 3, wherein processing the feature information based on a first neural network to obtain root cause distribution information of the chip defect comprises:

and taking the characteristic information as input of the first neural network, and obtaining the root cause distribution information through processing of the first neural network.
The method of claim 16, wherein the first neural network includes a feature extraction module and a classification module, and wherein the processing the feature information as an input to the first neural network to obtain the root cause distribution information includes:

the characteristic information is used as input of the characteristic extraction module, and the characteristic feature corresponding to the characteristic information is obtained through the processing of the characteristic extraction module;

and taking the feature as the input of the classification module, and obtaining the distribution information of the chip root cause through the processing of the classification module.
The method of claim 17, wherein the first neural network further comprises a normalization module, and wherein the obtaining the distribution information of the root cause of the chip by processing the feature as the input of the classification module comprises:

taking the feature as input of the standardization module, and processing by the standardization module to obtain the feature in a standardized format;

and taking the feature in the standardized format as the input of the classification module, and obtaining the distribution information of the chip root cause through the processing of the classification module.
The method according to any one of claims 16 to 18, wherein the first neural network is a neural network trained based on a dataset formed by a misnoted diagnostic report.
The method according to any one of claims 1 to 19, wherein the first neural network is a multi-layer perceptron MLP or a convolutional neural network CNN.
A root cause analysis device, comprising:

a processor and a memory;

the memory is used for storing program instructions;

the processor is configured to execute the program instructions to cause the communication device to implement the method of any one of claims 1 to 20.
A computer program product comprising instructions which, when run on a computer, cause the computer to perform the method of any of claims 1 to 20.
A computer readable storage medium for storing program instructions which, when run on a computer, cause the computer to perform the method of any one of claims 1 to 20.