CN117499614B - 3D display method, device, equipment and storage medium - Google Patents
3D display method, device, equipment and storage medium Download PDFInfo
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- 238000004590 computer program Methods 0.000 claims description 7
- 230000011218 segmentation Effects 0.000 claims description 5
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N13/00—Stereoscopic video systems; Multi-view video systems; Details thereof
- H04N13/30—Image reproducers
- H04N13/398—Synchronisation thereof; Control thereof
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N13/00—Stereoscopic video systems; Multi-view video systems; Details thereof
- H04N13/10—Processing, recording or transmission of stereoscopic or multi-view image signals
- H04N13/106—Processing image signals
- H04N13/156—Mixing image signals
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N13/00—Stereoscopic video systems; Multi-view video systems; Details thereof
- H04N13/10—Processing, recording or transmission of stereoscopic or multi-view image signals
- H04N13/106—Processing image signals
- H04N13/161—Encoding, multiplexing or demultiplexing different image signal components
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N13/00—Stereoscopic video systems; Multi-view video systems; Details thereof
- H04N13/10—Processing, recording or transmission of stereoscopic or multi-view image signals
- H04N13/106—Processing image signals
- H04N13/167—Synchronising or controlling image signals
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Abstract
The invention provides a 3D display method, a device, equipment and a storage medium, belonging to the technical field of 3D display, wherein the method comprises the following steps: acquiring multiple paths of 4k signals and fusing to obtain a virtual signal source; dividing the virtual signal source to obtain a left eye part signal source and a right eye part signal source; preprocessing the left eye part signal source and the right eye part signal source according to a preset method; a phase-locked loop is configured to realize the synchronization of an input signal and an output signal; wherein the input signal comprises a preprocessed virtual signal source; determining the type of a first frame sequence of an output signal through a 3D synchronous interface and realizing point-to-point 3D display on display equipment; wherein the type of the first frame sequence is a left eye frame sequence or a right eye frame sequence. The invention can realize point-to-point 3D display on various display devices, can automatically identify the type of the first frame in the output 3D signal, and improves the effect of 3D display.
Description
Technical Field
The present invention relates to the field of 3D display technologies, and in particular, to a 3D display method, device, apparatus, and storage medium.
Background
When the resolution of the display device exceeds the resolution of one path of signal interface, point-to-point 3D display cannot be realized, and only the signal can be scaled, so that signal distortion is caused, and the optimal display effect cannot be achieved.
And is a continuous frame 3D when 3D display is performed, when a 3D signal is output, it cannot be determined whether the first frame belongs to a left-eye frame sequence or a right-eye frame sequence every time the device is accessed.
Disclosure of Invention
The invention provides a 3D display method, a device, equipment and a storage medium; the point-to-point 3D display can be realized on various display devices, the type of the first frame in the output 3D signal can be automatically identified, and the 3D display effect is improved.
In a first aspect, an embodiment of the present invention provides a 3D display method, the 3D display method including:
acquiring multiple paths of 4k signals and fusing to obtain a virtual signal source;
dividing the virtual signal source to obtain a left eye part signal source and a right eye part signal source;
Preprocessing the left eye part signal source and the right eye part signal source according to a preset method;
A phase-locked loop is configured to realize the synchronization of an input signal and an output signal; wherein the input signal comprises a preprocessed virtual signal source;
determining the type of a first frame sequence of an output signal through a 3D synchronous interface and realizing point-to-point 3D display on display equipment; wherein the type of the first frame sequence is a left eye frame sequence or a right eye frame sequence.
Optionally, obtaining multiple paths of 4k signals and fusing to obtain a virtual signal source includes:
Setting a virtual signal source layout; the virtual signal source layout is set to be m rows and n columns, wherein m is the number of 4K signal paths;
and fusing the multiple paths of 4K signals according to the virtual signal source layout to obtain the virtual signal source.
Optionally, dividing the virtual signal source to obtain a left eye part signal source and a right eye part signal source includes:
creating a 3D window according to the virtual signal source;
dividing the virtual signal source into a left eye part signal source and a right eye part signal source according to the mode of the 3D window;
Wherein the modes of the 3D window include: a left-right mode and an up-down mode.
Optionally, preprocessing the left eye part signal source and the right eye part signal source according to a preset method includes:
Horizontally dividing the left-eye part signal sources and the right-eye part signal sources according to the number of data channels of the signal sources to obtain a plurality of 3D sub-windows corresponding to the left-eye part signal sources and the right-eye part signal sources;
Writing the signal source content corresponding to the 3D sub-windows into the corresponding output board cards according to the position of each 3D sub-window, and marking the type and the display position of the sub-window;
Wherein, the sub-window type includes: a left eye sub-window and a right eye sub-window.
Optionally, configuring the phase-locked loop to synchronize the input signal with the output signal includes:
switching the synchronous channel to a designated input interface;
calculating and determining parameters m ', d ' and div ' of the phase-locked loop according to a preset algorithm; wherein m ' is a multiplication coefficient, d ' is a frequency division coefficient, div ' is a frequency division factor;
And configuring a phase-locked loop according to m ', d ' and div ', starting a tracking function, dynamically adjusting a phase-locked loop reference clock through a voltage-controlled oscillator, calibrating the phase between a frame synchronizing signal and an input synchronizing signal of equipment, and realizing the synchronization of the input signal and an output signal.
Optionally, determining parameters m ', d ' and div ' of the phase-locked loop according to a preset algorithm includes:
reading the total width and total height of the input signal and a reference clock count of the input signal;
Determining a target clock from the total width, the total height, and the reference clock count;
Reading an input clock and combining a target clock to determine parameters m, d and div corresponding to a phase-locked loop; wherein m is a multiplication coefficient, d is a frequency division coefficient, and div is a frequency division factor;
Determining a phase-locked loop parameter set of an equal proportion relation by taking m, d and div as references; wherein, the equal proportion relation is: m/(d×div) =m '/(d ' ×div ');
And traversing the phase-locked loop parameter set to determine a phase-locked loop parameter m ', d ' and div ' meeting the load range of all output ports.
In a second aspect, an embodiment of the present invention provides a 3D display device, the 3D display device including:
the acquisition module is used for acquiring multiple paths of 4k signals and fusing the multiple paths of 4k signals to obtain a virtual signal source;
the segmentation module is used for segmenting the virtual signal source to obtain a left eye part signal source and a right eye part signal source;
The preprocessing module is used for preprocessing the left eye part signal source and the right eye part signal source according to a preset method;
The synchronous module is used for configuring a phase-locked loop to realize the synchronization of an input signal and an output signal; wherein the input signal comprises a preprocessed virtual signal source;
The display module is used for determining the type of the first frame sequence of the output signal through the 3D synchronous interface and realizing point-to-point 3D display on the display equipment; wherein the type of the first frame sequence is a left eye frame sequence or a right eye frame sequence.
Optionally, the synchronization module includes:
A determining unit for reading the total width and total height of the input signal and a reference clock count of the input signal;
Determining a target clock from the total width, the total height, and the reference clock count;
Reading an input clock and combining a target clock to determine parameters m, d and div corresponding to a phase-locked loop; wherein m is a multiplication coefficient, d is a frequency division coefficient, and div is a frequency division factor;
Determining a phase-locked loop parameter set of an equal proportion relation by taking m, d and div as references; wherein, the equal proportion relation is: m/(d×div) =m '/(d ' ×div ');
And traversing the phase-locked loop parameter set to determine a phase-locked loop parameter m ', d ' and div ' meeting the load range of all output ports.
In a third aspect, an embodiment of the present invention provides an electronic device, including a memory and a processor, where the memory stores a computer program, and the processor implements the method according to any implementation manner of the first aspect when executing the program.
In a fourth aspect, embodiments of the present invention provide a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements a method according to any of the implementations of the first aspect.
The invention provides a 3D display method, a device, equipment and a storage medium, wherein the method comprises the following steps: acquiring multiple paths of 4k signals and fusing to obtain a virtual signal source; dividing the virtual signal source to obtain a left eye part signal source and a right eye part signal source; preprocessing the left eye part signal source and the right eye part signal source according to a preset method; a phase-locked loop is configured to realize the synchronization of an input signal and an output signal; wherein the input signal comprises a preprocessed virtual signal source; determining the type of a first frame sequence of an output signal through a 3D synchronous interface and realizing point-to-point 3D display on display equipment; wherein the type of the first frame sequence is a left eye frame sequence or a right eye frame sequence. The invention can realize point-to-point 3D display on various display devices, can automatically identify the type of the first frame in the output 3D signal, and improves the effect of 3D display.
It should be understood that the description in this summary is not intended to limit the critical or essential features of the embodiments of the invention, nor is it intended to limit the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
The above and other features, advantages and aspects of embodiments of the present invention will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, the same or similar reference numerals denote the same or similar elements.
FIG. 1 is a flow chart of a 3D display method according to an embodiment of the invention;
Fig. 2 is a flow chart of an implementation of a phase locked loop according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a 3D display device according to an embodiment of the present invention;
Fig. 4 is a block diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
In order to enable a person skilled in the art to better understand the technical solutions in one or more embodiments of the present specification, the technical solutions in one or more embodiments of the present specification will be clearly and completely described below with reference to the drawings in one or more embodiments of the present specification, and it is obvious that the described embodiments are only some embodiments of the present specification, not all embodiments. All other embodiments, which can be made by one or more embodiments of the present disclosure without inventive faculty, are intended to be within the scope of the present disclosure.
It should be noted that, the description of the embodiment of the present invention is only for the purpose of more clearly describing the technical solution of the embodiment of the present invention, and does not constitute a limitation on the technical solution provided by the embodiment of the present invention.
FIG. 1 is a flow chart of a 3D display method according to an embodiment of the invention; as shown in fig. 1, the method includes:
S101, acquiring multiple paths of 4k signals and fusing to obtain a virtual signal source.
Optionally, obtaining multiple paths of 4k signals and fusing to obtain a virtual signal source includes:
Setting a virtual signal source layout; the virtual signal source layout is set to be m rows and n columns, wherein m is the number of 4K signal paths;
and fusing the multiple paths of 4k signals according to the virtual signal source layout to obtain the virtual signal source.
Illustratively, the signal source layout m rows by n columns may be set by a Multiplexer (MUX), and the multiple 4K signals are fused to form a virtual signal source; the MUX is a multiple-input single-output combinational logic circuit that can select one of multiple inputs to a common output terminal according to a channel selection control signal.
In this embodiment, the virtual signal source is not limited to be obtained by using a multiplexer, and a hybrid video matrix or the like may be used.
S102, dividing the virtual signal source to obtain a left eye part signal source and a right eye part signal source.
Optionally, dividing the virtual signal source to obtain a left eye part signal source and a right eye part signal source includes:
creating a 3D window according to the virtual signal source;
Dividing the virtual signal source into a left eye part signal source and a right eye part signal source according to the mode of the 3D window; wherein the modes of the 3D window include: a left-right mode and an up-down mode.
Illustratively, if in a left-right mode, the width of the virtual signal source is divided into left and right parts; if the mode is the up-down mode, dividing the height of the virtual signal source into an upper part and a lower part; for the left-right mode, the left half is taken as the left eye part, and the right half is taken as the right eye part; for the up-down mode, the upper half is taken as the left eye portion and the lower half is taken as the right eye portion.
S103, preprocessing the left eye part signal source and the right eye part signal source according to a preset method.
Optionally, preprocessing the left eye part signal source and the right eye part signal source according to a preset method includes:
Horizontally dividing the left-eye part signal sources and the right-eye part signal sources according to the number of data channels of the signal sources to obtain a plurality of 3D sub-windows corresponding to the left-eye part signal sources and the right-eye part signal sources;
Writing the signal source content corresponding to the 3D sub-windows into the corresponding output board cards according to the position of each 3D sub-window, and marking the type and the display position of the sub-window;
Wherein, the sub-window type includes: a left eye sub-window and a right eye sub-window.
Alternatively, left-eye sub-window and right-eye sub-window contents are alternately output when video frames are output.
S104, a phase-locked loop is configured to realize the synchronization of the input signal and the output signal.
Wherein the input signal comprises a preprocessed virtual signal source.
Optionally, configuring the phase-locked loop to synchronize the input signal with the output signal includes:
switching the synchronous channel to a designated input interface;
calculating and determining parameters m ', d ' and div ' of the phase-locked loop according to a preset algorithm; wherein m ' is a multiplication coefficient, d ' is a frequency division coefficient, div ' is a frequency division factor;
And configuring a phase-locked loop according to m ', d ' and div ', starting a tracking function, dynamically adjusting a phase-locked loop reference clock through a voltage-controlled oscillator, calibrating the phase between a frame synchronizing signal and an input synchronizing signal of equipment, and realizing the synchronization of the input signal and an output signal.
Optionally, determining parameters m ', d ' and div ' of the phase-locked loop according to a preset algorithm includes:
reading the total width and total height of the input signal and a reference clock count of the input signal;
Illustratively, the total width of the input signal, htotal, total height, vtotal, and reference clock count of the input signal RefCount (count of one frame signal with a local 48M clock) are read.
Determining a target clock from the total width, the total height, and the reference clock count;
Illustratively, the target clock ref_clk= (Htotal Vtotal) Frame;
Wherein 1 m=1000000;
48M clock count: the time of each clock cycle is t=1/48M;
the time of one frame of the input signal is tf=t RefCount;
The Frame rate of the input signal is frame=1/Tf;
thus ref_clk=htotal Vtotal 48/RefCount can be obtained.
Reading an input clock and combining a target clock to determine parameters m, d and div corresponding to a phase-locked loop; wherein m is a multiplication coefficient, d is a frequency division coefficient, and div is a frequency division factor;
illustratively, if ref_clk= 148,500,000, the input clock in_clk=27,000,000;
the maximum value of the phase-locked loop VCO is vco_max= 1,200,000,000;
div=vco_max/ref_clk= 1,200,000,000/148,500,000 =8.08;
Taking down the even number of div to obtain div=8;
back-deriving vco=ref_clk div= 1,188,000,000;
According to the chip data manual: the value range of D is 1-127, and the value of M is 10-8206;
All M, D combinations are determined according to the formula vco=in_clk M/D, and a group equal or closest to the VCO is found, i.e. M and D.
Determining a phase-locked loop parameter set of an equal proportion relation by taking m, d and div as references; wherein, the equal proportion relation is: m/(d×div) =m '/(d ' ×div ');
And traversing the phase-locked loop parameter set to determine a phase-locked loop parameter m ', d ' and div ' meeting the load range of all output ports.
Illustratively, the output clock out_clk=27×m '/(d ' ×div '), the output payload area s=out_clk/frame rate;
Wherein, each output interface can be split into different HTotal, VTotal, s=htotal×vtotal, HTotal, vtotal should satisfy: HTotal > =wn, VTotal > =hn, wn is the set of widths of the outlets and Hn is the set of heights of the outlets.
Fig. 2 is a flowchart illustrating an implementation of a phase locked loop according to an embodiment of the present invention; as shown in fig. 2:
the input clock is processed by a phase-locked loop to obtain a final output clock, the input clock is processed by a voltage-controlled oscillator VCO according to a D value and an M value in the phase-locked loop, and the output clock processed by the voltage-controlled oscillator VCO is processed by a DIV value to obtain the final output clock.
Wherein M is a multiplication factor that determines the rate of change of the output frequency of the VCO with respect to the input control voltage; the M coefficient may amplify or reduce the output frequency of the VCO when the input control voltage varies.
D is a division factor that is used to lower the output frequency of the VCO to obtain the desired output clock frequency. By adjusting the value of D, fine adjustments can be made to the output clock.
The DIV is a division factor, and is mainly used for reducing the output frequency of the voltage-controlled oscillator, so as to obtain the required output clock frequency. By adjusting the value of the division factor, a finer adjustment of the output clock frequency can be made.
Optionally, the VCO refers to an oscillating circuit having a correspondence between an output frequency and an input control voltage;
VCO value = input clock x M/D; output clock = VCO value/DIV;
Illustratively, the voltage controlled oscillator may be a VCXO, which is a crystal oscillator whose output frequency varies according to an applied control voltage, the VCXO being used to fine tune the operating frequency, typically in conjunction with a phase locked loop; the input clock can be dynamically adjusted by the characteristic that the frequency range is adjustable, thereby affecting the output clock.
S105, determining the type of the first frame sequence of the output signal through the 3D synchronous interface and realizing point-to-point 3D display on the display device.
Wherein the type of the first frame sequence is a left eye frame sequence or a right eye frame sequence.
Optionally, the technical solution in the present invention supports multiple 3D patch sources, for example: a left-right format, an up-down format, and a continuous frame format; support multiple 3D output modes, such as: active shutter mode, polarized mode (interlaced, spaced, checkerboard); and the 3D film source in any format can be converted into a 3D mode which is matched with the target display screen.
The embodiment of the invention provides a 3D display method, which comprises the following steps: acquiring multiple paths of 4k signals and fusing to obtain a virtual signal source; dividing the virtual signal source to obtain a left eye part signal source and a right eye part signal source; preprocessing the left eye part signal source and the right eye part signal source according to a preset method; a phase-locked loop is configured to realize the synchronization of an input signal and an output signal; wherein the input signal comprises a preprocessed virtual signal source; determining the type of a first frame sequence of an output signal through a 3D synchronous interface and realizing point-to-point 3D display on display equipment; wherein the type of the first frame sequence is a left eye frame sequence or a right eye frame sequence. The invention can realize point-to-point 3D display on various display devices, can automatically identify the type of the first frame in the output 3D signal, and improves the effect of 3D display.
The following describes in detail the device capable of executing the above 3D display method according to the embodiment of the present invention with reference to fig. 3.
Fig. 3 is a schematic structural diagram of a 3D display device according to an embodiment of the present invention; as shown in fig. 3, the 3D display device 30 includes:
the acquisition module 301 is configured to acquire multiple paths of 4k signals and perform fusion to obtain a virtual signal source;
The segmentation module 302 is configured to segment the virtual signal source to obtain a left eye part signal source and a right eye part signal source;
A preprocessing module 303, configured to preprocess the left eye part signal source and the right eye part signal source according to a preset method;
A synchronization module 304, configured to configure a phase-locked loop to synchronize an input signal with an output signal; wherein the input signal comprises a preprocessed virtual signal source;
a display module 305, configured to determine a type of the first frame sequence of the output signal through the 3D synchronization interface and implement a point-to-point 3D display on the display device; wherein the type of the first frame sequence is a left eye frame sequence or a right eye frame sequence.
Optionally, the obtaining module 301 is further configured to set a virtual signal source layout; the virtual signal source layout is set to be m rows and n columns, wherein m is the number of 4K signal paths; and fusing the multiple paths of 4K signals according to the virtual signal source layout to obtain the virtual signal source.
Optionally, the segmentation module 302 is further configured to create a 3D window according to the virtual signal source; dividing the virtual signal source into a left eye part signal source and a right eye part signal source according to the mode of the 3D window; wherein the modes of the 3D window include: a left-right mode and an up-down mode.
Optionally, the preprocessing module 303 is further configured to horizontally divide the left-eye part signal source and the right-eye part signal source according to the number of data channels of the signal sources, so as to obtain 3D sub-windows corresponding to the plurality of left-eye part signal sources and the plurality of right-eye part signal sources; writing the signal source content corresponding to the 3D sub-windows into the corresponding output board cards according to the position of each 3D sub-window, and marking the type and the display position of the sub-window; wherein, the sub-window type includes: a left eye sub-window and a right eye sub-window.
Optionally, the synchronization module 304 is further configured to switch the synchronization channel to a designated input interface; calculating and determining parameters m ', d ' and div ' of the phase-locked loop according to a preset algorithm; wherein m ' is a multiplication coefficient, d ' is a frequency division coefficient, div ' is a frequency division factor; and configuring a phase-locked loop according to m ', d ' and div ', starting a tracking function, dynamically adjusting a phase-locked loop reference clock through a voltage-controlled oscillator, calibrating the phase between a frame synchronizing signal and an input synchronizing signal of equipment, and realizing the synchronization of the input signal and an output signal.
Optionally, the synchronization module 304 includes:
a determining unit 3041 for reading the total width and total height of the input signal and the reference clock count of the input signal; determining a target clock from the total width, the total height, and the reference clock count; reading an input clock and combining a target clock to determine parameters m, d and div corresponding to a phase-locked loop; wherein m is a multiplication coefficient, d is a frequency division coefficient, and div is a frequency division factor; determining a phase-locked loop parameter set of an equal proportion relation by taking m, d and div as references; wherein, the equal proportion relation is: m/(d×div) =m '/(d ' ×div '); and traversing the phase-locked loop parameter set to determine a phase-locked loop parameter m ', d ' and div ' meeting the load range of all output ports.
The embodiment of the present invention also provides a computer electronic device, fig. 4 shows a schematic diagram of the structure of an electronic device to which the embodiment of the present invention can be applied, and as shown in fig. 4, the computer electronic device includes a central processing module (CPU) 401 that can perform various appropriate actions and processes according to a program stored in a Read Only Memory (ROM) 402 or a program loaded from a storage section 408 into a Random Access Memory (RAM) 403. In the RAM 403, various programs and data required for the system operation are also stored. The CPU 401, ROM 402, and RAM 403 are connected to each other by a bus 404. An input/output (I/O) interface 405 is also connected to bus 404.
The following components are connected to the I/O interface 405: an input section 406 including a keyboard, a mouse, and the like; an output portion 407 including a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), and the like, and a speaker, and the like; a storage section 408 including a hard disk or the like; and a communication section 409 including a network interface card such as a LAN card, a modem, or the like. The communication section 409 performs communication processing via a network such as the internet. The drive 410 is also connected to the I/O interface 405 as needed. A removable medium 411 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, or the like is installed on the drive 410 as needed, so that a computer program read out therefrom is installed into the storage section 408 as needed.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The modules or modules involved in the embodiments of the present invention may be implemented in software or in hardware. The described modules or modules may also be provided in a processor, for example, as: a processor includes an acquisition module 301, a segmentation module 302, a preprocessing module 303, a synchronization module 304, and a display module 305, where the names of these modules do not in some cases limit the module itself, for example, the acquisition module 301 may also be described as "an acquisition module 301 for acquiring multiple 4k signals and fusing to obtain a virtual signal source".
As another aspect, the present invention also provides a computer-readable storage medium, which may be a computer-readable storage medium contained in a 3D display device as described in the above embodiments; or may be a computer-readable storage medium, alone, that is not incorporated into an electronic device. The computer-readable storage medium stores one or more programs for use by one or more processors in performing a 3D display method described in the present invention.
The above description is only illustrative of the preferred embodiments of the present invention and of the principles of the technology employed. It will be appreciated by persons skilled in the art that the scope of the invention referred to in the present invention is not limited to the specific combinations of the technical features described above, but also covers other technical features formed by any combination of the technical features described above or their equivalents without departing from the inventive concept. Such as the above-mentioned features and the technical features disclosed in the present invention (but not limited to) having similar functions are replaced with each other.
Claims (5)
1. A 3D display method, the 3D display method comprising:
acquiring multiple paths of 4k signals and fusing to obtain a virtual signal source;
dividing the virtual signal source to obtain a left eye part signal source and a right eye part signal source;
Preprocessing the left eye part signal source and the right eye part signal source according to a preset method;
A phase-locked loop is configured to realize the synchronization of an input signal and an output signal; wherein the input signal comprises a preprocessed virtual signal source;
Determining the type of a first frame sequence of an output signal through a 3D synchronous interface and realizing point-to-point 3D display on display equipment; wherein the type of the first frame sequence is a left eye frame sequence or a right eye frame sequence;
the obtaining the multipath 4k signals and fusing to obtain a virtual signal source comprises the following steps:
Setting a virtual signal source layout; the virtual signal source layout is set to be m rows and n columns, wherein m is the number of 4K signal paths;
fusing multiple paths of 4K signals according to the virtual signal source layout to obtain the virtual signal source;
The preprocessing of the left eye part signal source and the right eye part signal source according to a preset method comprises the following steps:
The left eye part signal source and the right eye part signal source are horizontally divided according to the number of data channels of the signal sources, and a plurality of 3D sub-windows corresponding to the left eye part signal source and the right eye part signal source are obtained;
Writing the signal source content corresponding to the 3D sub-windows into corresponding output boards according to the position of each 3D sub-window, and marking the type and the display position of the sub-window; the sub-window types include: a left eye sub-window and a right eye sub-window;
the configuration phase-locked loop realizes the synchronization of an input signal and an output signal, and comprises the following steps:
switching the synchronous channel to a designated input interface;
reading the total width and total height of the input signal and a reference clock count of the input signal;
determining a target clock from the total width, total height, and reference clock count;
Reading an input clock and combining the target clock to determine parameters m, d and div corresponding to a phase-locked loop; wherein m is a multiplication coefficient, d is a frequency division coefficient, and div is a frequency division factor;
Determining a phase-locked loop parameter set of an equal proportion relation by taking m, d and div as references; wherein, the equal proportion relation is: m/(d×div) =m '/(d ' ×div ');
traversing the phase-locked loop parameter set to determine phase-locked loop parameters m ', d ' and div ' meeting the load range of all output ports;
wherein m ' is a multiplication coefficient, d ' is a frequency division coefficient, div ' is a frequency division factor;
And configuring a phase-locked loop according to m ', d ' and div ', starting a tracking function, dynamically adjusting a phase-locked loop reference clock through a voltage-controlled oscillator, calibrating the phase between a frame synchronizing signal and an input synchronizing signal of equipment, and realizing the synchronization of the input signal and an output signal.
2. The 3D display method according to claim 1, wherein the dividing the virtual signal source to obtain a left eye portion signal source and a right eye portion signal source includes:
Creating a 3D window according to the virtual signal source;
Dividing the virtual signal source into a left eye part signal source and a right eye part signal source according to the mode of the 3D window; the modes of the 3D window include: a left-right mode and an up-down mode.
3. A 3D display device, characterized in that the 3D display device comprises:
the acquisition module is used for acquiring multiple paths of 4k signals and fusing the multiple paths of 4k signals to obtain a virtual signal source;
the segmentation module is used for segmenting the virtual signal source to obtain a left eye part signal source and a right eye part signal source;
the preprocessing module is used for preprocessing the left eye part signal source and the right eye part signal source according to a preset method;
The synchronous module is used for configuring a phase-locked loop to realize the synchronization of an input signal and an output signal; wherein the input signal comprises a preprocessed virtual signal source;
the display module is used for determining the type of the first frame sequence of the output signal through the 3D synchronous interface and realizing point-to-point 3D display on the display equipment; wherein the type of the first frame sequence is a left eye frame sequence or a right eye frame sequence;
The acquisition module is also used for setting virtual signal source layout; the virtual signal source layout is set to be m rows and n columns, wherein m is the number of 4K signal paths; fusing multiple paths of 4K signals according to the virtual signal source layout to obtain the virtual signal source;
The preprocessing module is further used for horizontally dividing the left eye part signal sources and the right eye part signal sources according to the number of data channels of the signal sources to obtain a plurality of 3D sub-windows corresponding to the left eye part signal sources and the right eye part signal sources; writing the signal source content corresponding to the 3D sub-windows into corresponding output boards according to the position of each 3D sub-window, and marking the type and the display position of the sub-window; the sub-window types include: a left eye sub-window and a right eye sub-window;
The synchronous module is also used for switching the synchronous channel to a designated input interface; reading the total width and total height of the input signal and a reference clock count of the input signal; determining a target clock from the total width, total height, and reference clock count; reading an input clock and combining the target clock to determine parameters m, d and div corresponding to a phase-locked loop; wherein m is a multiplication coefficient, d is a frequency division coefficient, and div is a frequency division factor; determining a phase-locked loop parameter set of an equal proportion relation by taking m, d and div as references; wherein, the equal proportion relation is: m/(d×div) =m '/(d ' ×div '); traversing the phase-locked loop parameter set to determine phase-locked loop parameters m ', d ' and div ' meeting the load range of all output ports; wherein m ' is a multiplication coefficient, d ' is a frequency division coefficient, div ' is a frequency division factor; and configuring a phase-locked loop according to m ', d ' and div ', starting a tracking function, dynamically adjusting a phase-locked loop reference clock through a voltage-controlled oscillator, calibrating the phase between a frame synchronizing signal and an input synchronizing signal of equipment, and realizing the synchronization of the input signal and an output signal.
4. An electronic device comprising a memory and a processor, the memory having stored thereon a computer program, the processor implementing the method of claim 1 or 2 when executing the computer program.
5. A computer-readable storage medium, characterized in that a computer program is stored, which, when being executed by a processor, implements the method according to claim 1 or 2.
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