CN117497508A - Semiconductor packaging structure - Google Patents

Abstract

The invention discloses a semiconductor packaging structure, which includes: a substrate including a wiring structure located in a dielectric layer; a dummy conductive mesh structure embedded in the substrate and separated from the wiring structure by the dielectric layer; An interposer layer is disposed above the substrate; an underfill material extends between the substrate and the interposer layer and extends over the dummy conductive mesh structure; and semiconductor grains are disposed between the interposer layer on and electrically coupled to the wiring structure through the interposer. The semiconductor packaging structure of the present invention includes a dummy conductive mesh structure, which can prevent cracks from extending into the wiring structure of the substrate and causing electrical failures. The mesh structure has stronger toughness, mechanical strength, and greater resistance to cracking. ability to further resist cracks and protect the substrate and wiring structure.

Description

Semiconductor packaging structure

Technical field

The present invention relates to the field of semiconductor technology, and in particular, to a semiconductor packaging structure.

Background technique

In addition to providing protection of the semiconductor die from environmental contaminants, the semiconductor packaging structure may also provide electrical connections between the semiconductor die packaged within the semiconductor packaging structure and a substrate such as a printed circuit board (PCB). .

Although the existing semiconductor packaging structure can meet the requirements in general, it is not satisfactory in all aspects. For example, when a semiconductor package structure is subjected to heat treatment or reliability testing, stress may cause the semiconductor package structure to crack. Therefore, there is a need to further improve semiconductor packaging structures.

Contents of the invention

In view of this, the present invention provides a semiconductor packaging structure to solve the above problems.

According to a first aspect of the present invention, a semiconductor packaging structure is disclosed, including:

a substrate, including a wiring structure located in a dielectric layer;

a dummy conductive mesh structure embedded in the substrate and spaced from the wiring structure by the dielectric layer;

An interposer layer is provided above the substrate;

an underfill material extending between the substrate and the interposer and over the dummy conductive mesh structure; and

Semiconductor die disposed over the interposer and electrically coupled to the wiring structure through the interposer.

Further, when viewed in a direction perpendicular to the upper surface of the substrate, the dummy conductive mesh structure partially overlaps the corner of the interposer. The dummy conductive mesh structure at least partially overlaps the corner or corner area of the interposer, which can prevent or delay the expansion of cracks caused by the corner area of the interposer into the substrate, thereby protecting the substrate and the wiring structure in the substrate.

Further, it also includes a plurality of dummy conductive mesh structures embedded in the substrate, and when viewed in a direction substantially perpendicular to the upper surface of the substrate, the plurality of dummy conductive mesh structures are in contact with the intermediary Each corner of the layer partially overlaps. Thus, the portion of the substrate corresponding to each corner area is protected.

Further, the dummy conductive mesh structure includes metal. Metal materials can improve crack resistance and are easy to manufacture.

Further, it also includes a conductive ring surrounding the dummy conductive mesh structure and spaced from the wiring structure through the dielectric layer. Improve the overall mechanical strength to further enhance the ability to resist cracks.

Further, the substrate includes a packaging core disposed under the dummy conductive mesh structure. Thereby enhancing the mechanical strength of the substrate and further preventing or mitigating the negative impact of cracks on the substrate.

Further, a bump structure electrically coupling the interposer to the wiring structure is included, wherein the underfill material extends between the dummy conductive mesh structure and the bump structure. Underfill material protects the bump structure and reduces stress on the substrate.

Further, it also includes a frame, which is attached to the substrate through an adhesive layer. to reduce warpage, prevent bending, and maintain the flatness of the substrate.

According to a second aspect of the present invention, a semiconductor packaging structure is disclosed, including:

A substrate including a wiring structure located in an inter-metal dielectric layer;

a plurality of dummy conductive structures extending below the upper surface of the substrate and spaced from the wiring structures by the inter-metal dielectric layer;

an underfill material covering the plurality of dummy conductive structures;

an interposer disposed above the substrate and electrically coupled to the wiring structure, wherein the interposer partially overlaps the plurality of dummy conductive structures in a top view; and

Semiconductor die disposed over the interposer and electrically coupled to the interposer.

Further, a molding compound disposed above the interposer and surrounding the semiconductor die is included. Molding compounds can protect semiconductor die and improve the overall strength of the package.

Further, the side walls of the molding compound are coplanar with the side walls of the interposer layer. This maintains the stability and ease of use of the packaging structure.

Further, a bump structure is included, the bump structure is surrounded by the molding compound and electrically connects the semiconductor die to the interposer layer. The bump structure is used to electrically connect the semiconductor die to the substrate.

Further, in a top view, each of the plurality of dummy conductive structures partially overlaps a corner of the interposer layer. Thereby, the portion of the substrate corresponding to the corner of the interposer is protected, and the wiring structure is protected.

Further, the plurality of dummy conductive structures and the wiring structure are formed of the same material. Therefore, it is convenient to form in the same process, facilitate manufacturing, reduce cost increase or barely increase cost.

Further, at least one of the plurality of dummy conductive structures has a quadrangular shape in a top view, and has a size ranging from about 50 μm to about 300 μm. To protect the substrate and wiring structure while occupying a small area.

Further, at least one of the plurality of dummy conductive structures has an elliptical shape in a top view and has a size ranging from about 50 μm to about 300 μm. To protect the substrate and wiring structure while occupying a small area.

According to a third aspect of the present invention, a semiconductor packaging structure is disclosed, including:

A substrate including a wiring structure located in an inter-metal dielectric layer;

A dummy metal structure is provided in the inter-metal dielectric layer, wherein the upper surface of the dummy metal structure is not lower than the upper surface of the wiring structure;

An interposer layer is provided above the dummy metal structure;

a bump structure adjacent to the dummy metal structure and electrically coupling the interposer to the wiring structure;

Semiconductor die disposed over the interposer and electrically coupled to the interposer; and

Underfill material surrounding the bump structure and covering the dummy metal structure.

Further, a part of the wiring structure extends below the bottom surface of the dummy metal structure. This allows the dummy metal structure to protect the wiring structure.

Further, in a top view, the first edge of the dummy metal structure is covered by the interposer layer, and the second edge of the dummy metal structure is located outside the interposer layer. Thus, cracks corresponding to the corners of the interposer can be effectively blocked by the dummy metal structure.

Further, in a top view, the underfill material covers the first edge and the second edge of the dummy metal structure. Underfill materials can reduce the negative effects of stress on the substrate.

The semiconductor packaging structure of the present invention includes: a substrate including a wiring structure located in a dielectric layer; a dummy conductive mesh structure embedded in the substrate and separated from the wiring structure by the dielectric layer; and an intermediary layer , disposed above the substrate; an underfill material extending between the substrate and the interposer and extending over the dummy conductive mesh structure; and semiconductor dies disposed above the interposer and Electrically coupled to the wiring structure through the interposer. The semiconductor packaging structure of the present invention includes a dummy conductive mesh structure, which can prevent cracks from extending into the wiring structure of the substrate and causing electrical failures. The mesh structure has stronger toughness, mechanical strength, and greater resistance to cracking. ability to further resist cracks and protect the substrate and wiring structure.

Description of the drawings

1 is a cross-sectional view of an exemplary semiconductor packaging structure according to some embodiments of the present invention;

Figure 2 is a top view of an exemplary semiconductor packaging structure according to some embodiments of the invention;

3 is a cross-sectional view of a portion of an exemplary semiconductor package structure in accordance with some embodiments of the invention; and

4A and 4B are top views of a portion of an exemplary semiconductor package structure in accordance with some embodiments of the invention.

Detailed ways

In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which form a part hereof and which illustrate by way of illustration certain preferred embodiments in which the invention may be practiced. . These embodiments are described in sufficient detail to enable those skilled in the art to practice them, and it is to be understood that other embodiments may be utilized and mechanical, structural and structural changes may be made without departing from the spirit and scope of the invention. and procedural changes. this invention. Accordingly, the following detailed description is not to be construed as limiting, and the scope of embodiments of the invention is defined only by the appended claims. The drawings described are illustrative only and not restrictive. In the drawings, the dimensions of some elements may be exaggerated and not drawn to scale for illustrative purposes. In the practice of the invention, dimensions and relative dimensions do not correspond to actual dimensions.

It will be understood that, although the terms "first," "second," "third," "primary," "secondary," etc. may be used herein to describe various components, components, regions, layers and/or sections , but these components, components, regions, layers and/or portions shall not be limited by these terms. These terms are only used to distinguish one component, component, region, layer or section from another region, layer or section. Thus, a first or primary component, component, region, layer or section discussed below could be termed a secondary or secondary component, component, region, layer or section without departing from the teachings of the inventive concept.

In addition, for convenience of description, terms such as “below”, “under”, “below”, “above”, “between” may be used herein. Spatially relative terms such as "on" to describe the relationship of a component or feature to it. Another component or feature as shown in a figure. In addition to the orientation depicted in the figures, the spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, it will also be understood that when a "layer" is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

The terms "about", "approximately" and "approximately" generally mean ±20% of the stated value, or ±10% of the stated value, or ±5% of the stated value, or ±3% of the stated value , or within the range of ±2% of the specified value, or ±1% of the specified value, or ±0.5% of the specified value. The values specified in this invention are approximate. When not specifically described, stated values include the meanings of "about," "approximately," and "approximately." The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular terms "a", "an" and "the" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the inventive concept. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It will be understood that when a "component" or "layer" is referred to as being "on," "connected to," "coupled to" or "adjacent" another component or layer, it can be directly on the other component or layer Intermediate components or layers may be present on, connected to, coupled to, or adjacent thereto. In contrast, when a component is referred to as being "directly on," "directly connected to," "directly coupled to" or "immediately adjacent" another component or layer, there are no intervening components or layers present.

Note: (i) like features will be designated by the same reference numerals throughout the Figures and will not necessarily be described in detail in every Figure in which they appear, and (ii) a series of Figures may show a single item Each aspect is associated with various reference labels that may appear throughout the sequence, or may appear only in selected plots of the sequence.

Semiconductor packaging structures including dummy conductive structures are described in accordance with some embodiments of the invention. Dummy conductive structures are embedded in the substrate to prevent cracks from propagating into the substrate, thereby avoiding electrical (electrical) failures.

Figure 1 is a cross-sectional view of a semiconductor packaging structure 100 in accordance with some embodiments of the invention. Additional features may be added to semiconductor packaging structure 100 . Some of the features described below may be substituted or eliminated for different embodiments. To simplify the drawing, only a portion of the semiconductor package structure 100 is shown.

As shown in FIG. 1 , according to some embodiments, a semiconductor packaging structure 100 includes a substrate 102 . The substrate 102 may be a coreless substrate or a cored substrate to prevent the substrate 102 from warping. The substrate 102 may have wiring structures in it. In some embodiments, the wiring structure includes conductive pads, conductive vias, conductive lines, conductive pillars, etc. or combinations thereof. The wiring structure may be formed from conductive materials, including metals such as copper, aluminum, tungsten, etc., alloys thereof, or combinations thereof.

Wiring structures may be provided in the dielectric layer. The dielectric layer may also be called an inter-metal dielectric (IMD) layer. In some embodiments, the dielectric layer may be formed from organic materials such as polymer base materials, inorganic materials including silicon nitride, silicon oxide, silicon oxynitride, etc., or combinations thereof.

It should be noted that the configuration of the substrate 102 shown in the drawings is exemplary only and is not intended to limit the present invention. Any desired semiconductor components may be formed in and on substrate 102 . However, to simplify the diagram, only the flat substrate 102 is shown.

According to some embodiments, the semiconductor package structure 100 includes a plurality of conductive terminals 104 disposed beneath the substrate 102 and electrically coupled to the wiring structure. The conductive terminals 104 may include micro-bumps, controlled collapse chip connection (C4) bumps, solder balls, ball grid array (BGA) balls, etc., or combinations thereof. The conductive terminals 104 may be formed of conductive materials, including metals (eg, tungsten, titanium, tantalum, ruthenium, cobalt, copper, aluminum, platinum, tin, silver, gold), metal compounds (eg, tantalum nitride, titanium nitride, Tungsten nitride), etc., their alloys, or their combinations.

According to some embodiments, the semiconductor packaging structure 100 includes an interposer 110 disposed over the substrate 102 . One or more vias 112 may be included in the interposer 110 . Via 112 may be formed from a conductive material, and exemplary conductive materials were previously described. The via 112 may extend from a first surface of the interposer 110 to a second surface of the interposer 110 opposite the first surface.

The vias 112 may be electrically coupled to the wiring structure of the substrate 102 through the plurality of bump structures 106 . Bump structures 106 may include microbumps, controlled collapse chip attach (C4) bumps, solder balls, ball grid array (BGA) balls, etc., or combinations thereof. Bump structure 106 may include the materials discussed above with respect to conductive terminals 104 and will not be repeated.

According to some embodiments, semiconductor packaging structure 100 includes underfill material 108 extending between interposer 110 and substrate 102 . Underfill material 108 may surround bump structures 106 and may fill gaps between bump structures 106 to provide structural support. In some embodiments, underfill material 108 includes a polymer, such as epoxy. The underfill material 108 may be dispensed using capillary forces and may then be cured by any suitable curing process.

According to some embodiments, semiconductor packaging structure 100 includes one or more semiconductor dies 120 and 122 disposed over interposer 110 . In some embodiments, semiconductor dies 120 and 122 each independently include a system-on-a-chip (SoC) die, a logic device, a memory device, a radio frequency (RF) device, etc., or any combination thereof. For example, semiconductor dies 120 and 122 may each include a micro control unit (MCU) die, a microprocessor unit (MPU) die, or a power management integrated circuit (PMIC) die. , radio frequency front end (RFFE) die, accelerated processing unit (APU) die, central processing unit (CPU) die, graphics processing unit (GPU) die Granules, input-output (IO) chips, dynamic random access memory (DRAM) controllers, static random-access memory (SRAM), high bandwidth memory (high bandwidth memory, HBM), application processor (application processor, AP) chip, application specific integrated circuit (application specific integrated circuit, ASIC) die, etc. or any combination thereof.

Semiconductor dies 120 and 122 may include the same or different devices. For example, semiconductor die 120 may include an ASIC die and semiconductor die 122 may include an HBM. Semiconductor package structure 100 may include more than two semiconductor dies, and may also include one or more passive components, such as resistors, capacitors, or inductors, disposed above interposer 110 .

Semiconductor dies 120 and 122 may be electrically coupled to interposer 110 through plurality of bump structures 116 . Bump structures 116 may include microbumps, controlled collapse chip attach (C4) bumps, solder balls, ball grid array (BGA) balls, etc., or combinations thereof. Bump structure 116 may include the materials discussed above with respect to bump structure 106 and will not be repeated.

According to some embodiments, semiconductor packaging structure 100 includes underfill material 118 extending between interposer 110 and semiconductor dies 120 and 122 . Underfill material 118 may surround bump structures 116 and may fill gaps between bump structures 116 to provide structural support. Underfill material 118 may be similar to underfill material 108 and will not be repeated.

According to some embodiments, the semiconductor packaging structure 100 includes a molding material 124 disposed over the interposer 110 . Molding compound 124 may surround semiconductor dies 120 , 122 , bump structures 116 , and underfill material 118 to protect these components from the environment, thereby preventing them from damage due to stress, chemicals, and moisture. Molding compound 124 may be formed from a non-conductive material including moldable polymers, epoxies, resins, etc. or combinations thereof.

As shown in FIG. 1 , the sidewalls of the molding compound 124 may be substantially coplanar with the sidewalls of the interposer 110 . In some embodiments, the top surfaces (upper surfaces) of semiconductor dies 120, 122 are exposed by molding compound 124, as shown in FIG. 1 .

According to some embodiments, semiconductor package structure 100 includes frame 130 attached to substrate 102 via adhesive layer 128 . The frame 130 may be disposed along the sidewalls of the substrate 102 to reduce warping, prevent bending, and maintain the flatness of the substrate 102. Frame 130 may surround interposer 110 and semiconductor dies 120 , 122 .

In some embodiments, frame 130 and adhesive layer 128 are spaced apart from underfill layer 128 . A portion of the top surface of substrate 102 is thus exposed, and one or more passive components 126 (eg, resistors, capacitors, or inductors) may be disposed over the portion of the top surface of substrate 102 . Passive components 126 may also be disposed beneath the substrate 102 and between the conductive terminals 104 .

According to some embodiments, cracks may form in the underfill material 108 when the semiconductor package structure 100 is subjected to heat treatment or reliability testing. In the embodiment of the present invention, the semiconductor packaging structure 100 includes one or more dummy conductive structures to prevent cracks from extending into the wiring structure of the substrate 102 and causing electrical failures. The semiconductor package structure 100 including the dummy conductive structure will be described with reference to FIG. 2 .

FIG. 2 is a top view of the semiconductor package structure 100 of FIG. 1 according to some embodiments. FIG. 1 is a cross-sectional view of the semiconductor package structure 100 taken along line I-I' shown in FIG. 2 .

As shown in FIG. 2 , according to some embodiments, semiconductor packaging structure 100 includes additional (or additional) semiconductor die 122 disposed over interposer 110 and adjacent semiconductor die 120 . Semiconductor dies 120 and 122 may include the same or different devices, and exemplary devices or devices were previously described.

According to some embodiments, the semiconductor package structure 100 includes a plurality of dummy conductive structures 200 , each dummy conductive structure 200 partially overlaps a corner (or corner, corner) of the interposer 110 , and causes cracks corresponding to the corners of the interposer 110 Can be effectively blocked by dummy metal structures; cracks may appear near corners since corners are prone to stress. Therefore, the dummy conductive structure 200 disposed under (or just below) the corner of the interposer 110 can resist crack propagation into the wiring structure of the substrate 102 while occupying less space. A portion of a semiconductor package structure 100 including one of the dummy conductive structures 200 will be described below with reference to FIG. 3 . In the embodiment of the present invention, the wiring structure is a wiring used for electrical connection and signal connection in the substrate, and is a wiring having substantial electrical functions. The dummy conductive structure 200 does not have substantial electrical functions and is not used for electrical connection or signal connection.

Figure 3 is a cross-sectional view of a portion of a semiconductor packaging structure 100 in accordance with some embodiments of the invention. Portions of the semiconductor package structure in FIG. 3 may include the same or similar components as the semiconductor package structure 100 in FIG. 1 , and for simplicity, these components will not be discussed in detail.

As shown in FIG. 3 , the wiring structure of the substrate 102 includes horizontal interconnects (eg, conductive layer 202 ) and vertical interconnects (eg, conductive vias 204 ). The conductive vias 204 can electrically couple the conductive layers 202 on different layers. Conductive layer 202 and conductive vias 204 may be provided in dielectric layer (or inter-metal dielectric layer) 206 .

Dummy conductive structure 200 may be formed from conductive materials, including metals such as copper, aluminum, tungsten, etc., alloys thereof, or combinations thereof. The dummy conductive structure 200 may also be referred to as a dummy metal structure. In some embodiments, the dummy conductive structure 200 and the conductive layer 202 are made of the same material and formed in the same process to reduce costs and simplify the process. Dummy conductive structure 200 may be surrounded by dielectric layer 206 and not electrically coupled to the wiring structure. For example, the dummy conductive structure 200 is electrically floating, eg not connected to any voltage (not connected to positive voltage, ground or negative voltage).

Dummy conductive structure 200 may be disposed adjacent bump structure 106 . Underfill material 108 may cover the top surface (upper surface) of dummy conductive structure 200 . Specifically, underfill material 108 may extend from an edge of dummy conductive structure 200 to another edge of dummy conductive structure 200 .

The dummy conductive structure 200 may be provided on the topmost layer to resist crack propagation. Specifically, the top surface (upper surface) of dummy conductive structure 200 may be substantially flush with or higher than the top surface (upper surface) of the wiring structure (eg, the topmost layer of conductive layer 202). In one embodiment, the dummy conductive structure 200 may include a topmost metal layer in the substrate 102 that belongs to the dummy conductive structure 200 and is higher than the topmost layer of the wiring structure of the substrate 102 (eg, the topmost layer of the wiring structure). conductive layer). In one embodiment, the dummy conductive structure 200 may be located in the substrate 102 and at the uppermost layer of the substrate 102. For example, the upper surface of the dummy conductive layer 208 on the topmost layer of the dummy conductive structure 200 is flush with the upper surface of the substrate 102, so that It is convenient to manufacture and can better protect the substrate and wiring structure. In one embodiment, the dummy conductive structure 200 may be located in the substrate 102 . For example, the upper surface of the dummy conductive layer 208 at the topmost layer of the dummy conductive structure 200 is higher than the upper surface of the substrate 102 (for example, part of it is in direct contact with the underfill material 108 ), and the remaining parts can be in the substrate 102 (that is, under the upper surface of the substrate 102), thereby facilitating manufacturing and better protecting the substrate and wiring structure, and thus reducing the need for rearrangement of the wiring structure. In order to facilitate the arrangement of the wiring structure in the substrate while protecting the substrate and the wiring structure. In one embodiment, the dummy conductive structure 200 may be located above the substrate 102 (located on the upper surface of the substrate 102). At this time, the dummy conductive structure 200 is in direct contact with the underfill material 108 and is directly covered by the underfill material 108, thereby facilitating The substrate and wiring structure can be manufactured and better protected, and this can reduce the requirement for re-layout of the wiring structure, and even eliminate the need to re-layout the wiring structure, so as to facilitate the placement of the wiring structure in the substrate while protecting the substrate and wiring structure.

In some embodiments, dummy conductive structure 200 has one or more dummy conductive layers 208 . As shown in FIG. 3 , the dummy conductive structure 200 may include two dummy conductive layers 208 , but is not limited thereto. For example, dummy conductive structure 200 may include one dummy conductive layer 208 or more than two dummy conductive layers 208 . In some embodiments, adjacent dummy conductive layers 208 are staggered, as shown in FIG. 3 . In some other embodiments, adjacent dummy conductive layers 208 are aligned with each other.

As shown in FIG. 3 , adjacent dummy conductive layers 208 may be separated by dielectric layers 206 , but are not limited thereto. For example, dummy conductive structure 200 may include one or more conductive vias (not shown) connecting adjacent dummy conductive layers 208 . Dielectric layer 206 may cover the top surface (upper surface) of dummy conductive structure 200 .

The dummy conductive structure 200 may be surrounded by wiring structures. Specifically, some conductive layers 202 and conductive vias 204 may be disposed on opposite sides of the dummy conductive structure 200 (or around or around the dummy conductive structure 200 ), and some of the conductive layers 202 may extend to the bottom surface of the dummy conductive structure 200 (lower surface) below. In one embodiment, the wiring structure may be arranged to leave an area or space for forming the dummy conductive structure 200, and in this case, the dummy conductive structure 200 may be at least partially located in the substrate. In one embodiment, there is no need to reset the wiring structure. In this case, for example, the dummy conductive structure 200 can be disposed on the upper surface of the substrate. The dummy conductive structure 200 can be in direct contact with the upper surface of the substrate to reduce the impact on the substrate. Interference of wiring structure, while protecting the substrate and wiring structure. In one embodiment of the present invention, the dummy conductive structure 200 can be used to protect the wiring structure before cracks reach the wiring structure to prevent the wiring structure from being damaged, or to delay the wiring structure from being damaged; thereby extending the service life and normal working time of the substrate.

As previously mentioned, in some embodiments, the substrate 102 may be a cored substrate. In these embodiments, substrate 102 includes a package core (not shown) disposed beneath dummy conductive structures 200 . The setting of the packaging core can enhance the mechanical strength of the substrate and further prevent or reduce the negative impact of cracks on the substrate. Depending on the design, a portion of the wiring structure may be disposed between the dummy conductive structure 200 and the package core. This can further protect the wiring structure and reduce the possibility of damage to the wiring structure, thereby protecting the mechanical and electrical properties of the wiring structure in a better state and ensuring the stability of the semiconductor operation. In one embodiment of the present invention, the adjacent dummy conductive layers 208 are staggered so that, for example, when the upper dummy conductive layer 208 cracks, the adjacent lower dummy conductive layers can resist cracks because the corresponding positions are made of metal. Continue to extend to protect the substrate and the wiring structure in the substrate. Therefore, the above design of the present invention can further resist crack extension, protect the structural integrity of the substrate, improve the mechanical strength of the substrate, and protect the safety of the wiring structure within the substrate. In one embodiment of the present invention, all adjacent dummy conductive layers 208 may be arranged in a staggered manner to improve the resistance of the substrate to cracking. In one embodiment of the present invention, the staggered arrangement may mean that the metal area in the lower dummy conductive layer 208 is aligned with the non-metal area in the upper dummy conductive layer 208 (for example, the area is a dielectric material, etc.), so that Improve the resistance of the substrate to cracking. In one embodiment, the upper dummy conductive layer 20 and the lower dummy conductive layer 208 are arranged in a staggered manner. The upper layer and the lower layer may be two closely adjacent layers, or other layers may be spaced between them. Therefore, when the dummy conductive structure 200 has multiple dummy conductive layers 208, at least two layers of dummy conductive layers 208 are arranged alternately. In this way, the arrangement of the dummy conductive structure 200 can be more flexible and diverse, and at the same time, the resistance to cracking of the substrate can be improved. In one embodiment, the dummy conductive structure 200 may be provided only in the corner (or corner) area corresponding to the interposer 110 , thereby reducing interference to the wiring structure in the substrate 102 and ensuring the normal arrangement and functional integrity of the wiring structure. In one embodiment, the dummy conductive structure 200 may be disposed in other areas in addition to the corner (or corner) area corresponding to the interposer 110 to facilitate manufacturing or resist crack extension in a specific area. In one embodiment, the dummy conductive structure 200 may have one or more dummy conductive structures 200. For example, the dummy conductive structures 200 are connected to each other and thus can be regarded as one dummy conductive structure 200 to facilitate manufacturing; for another example, the dummy conductive structures 200 may be composed of multiple dummy conductive structures 200. separate dummy conductive structures 200 to correspond to crack resistance at different locations.

The configuration of the dummy conductive layer 208 will be described below with reference to FIGS. 4A and 4B. Figures 4A and 4B are top views of dummy conductive layer 208 of Figure 3, according to some embodiments.

Figure 4A is a top view of dummy conductive layer 208a according to some embodiments. To simplify the drawing, only a portion of the dummy conductive layer 208a is shown. As shown in Figure 4A, according to some embodiments, dummy conductive layer 208a includes a mesh structure 209. The dummy conductive structure may also be referred to as a dummy conductive mesh structure.

In some embodiments, the mesh (dummy conductive mesh) 209 is continuous, as shown in Figure 4A. In some other embodiments, the mesh structure 209 is discontinuous, such as including multiple dashed conductive lines. In some embodiments, the space in the mesh structure 209 (eg, the hollow portion in the middle) is filled with dielectric material, such as the dielectric layer 206 shown in FIG. 3 .

The dummy conductive layer 208a may have a quadrangular shape, an elliptical shape, or any suitable shape in a top view. For example, the dummy conductive layer 208a may have a rectangular shape (the periphery is generally rectangular), as shown in FIG. 4A. As another example, the dummy conductive layer 208a may be circular.

The dummy conductive layer 208a may have a size in the range of about 50 μm to about 300 μm, such as 200 μm. For example, in an embodiment in which the dummy conductive layer 208a has a quadrilateral shape, the length L1 or L2 of the dummy conductive layer 208a may be in the range of about 50 μm to about 300 μm, such as 200 μm, and the quadrilateral shape of the dummy conductive layer 208a may facilitate the protection of the substrate. at the corner of the interposer and is easy to manufacture. As another example, in an embodiment in which the dummy conductive layer 208a has an elliptical shape, the length of the major axis or the minor axis of the dummy conductive layer 208 may be in the range of about 50 μm to about 300 μm, such as 200 μm. The elliptical shape of the dummy conductive layer 208a The portion of the substrate corresponding to the corner of the interposer can be easily protected, and manufacturing can be facilitated. The dummy conductive layer 208a may also have, for example, a circular shape, a triangular shape, or other shapes.

The dummy conductive structures of different layers may have the same or different dimensions. For example, an upper layer of dummy conductive structures may have larger dimensions than a lower layer of dummy conductive structures. Different layers of dummy conductive structures may have the same or different densities of the mesh 209 (ie, the distance between conductors). For example, an upper layer of dummy conductive structures may have a greater density of mesh structure 209 than a lower layer of dummy conductive structures. In one embodiment of the present invention, the mesh structure 209 has stronger toughness, mechanical strength, and greater ability to resist cracking, so it is suitable to be used as a component of a dummy conductive structure, thereby further resisting cracks and protecting the substrate. and wiring structure. In one embodiment, the dummy conductive layer 208 may also have other shapes or patterns. In one embodiment, the dummy conductive layer 208 of each layer may be composed of one or more mesh structures 209 as shown in FIG. 4A or/and FIG. 4B. For example, the dummy conductive layer 208 of each layer may have a mesh structure 209 as shown in FIG. 4A or/and FIG. 4B. Therefore, in the above description, the lower dummy conductive layer 208 (mesh structure 209) The metal area corresponds to the middle hollow area of the upper dummy conductive layer 208 (mesh structure 209), thereby using a multi-layer staggered approach to improve the protection of the substrate and wiring structure and prevent or delay the extension of cracks to the wiring structure. For another example, the dummy conductive layer 208 of each layer may have multiple mesh structures 209 as shown in FIG. 4A or/and FIG. 4B. The mesh structures 209 in each layer are spaced apart from each other, so that the above-mentioned In the description, the lower dummy conductive layer 208 (mesh structure 209) is arranged corresponding to the interval between the upper dummy conductive layers 208 (mesh structure 209). For example, part of the dummy conductive layer 208 has a network structure 209 as shown in FIG. 4A or/and FIG. 4B , and another part of the dummy conductive layer 208 has multiple structures as shown in FIG. 4A or/and FIG. 4B . Such a mesh structure 209 is shown, so in the above description, one mesh structure 209 in the upper or lower layer is arranged to correspond to the intervals of multiple mesh structures 209 in other layers; and so on. In an embodiment of the present invention, other staggered arrangements are also possible, so that if a crack occurs in the upper layer, the crack will not easily continue to extend downward.

Figure 4B is a top view of dummy conductive layer 208b according to some embodiments. To simplify the drawing, only a portion of the dummy conductive layer 208b is shown. Dummy conductive layer 208b in Figure 4B may include the same or similar components as dummy conductive layer 208a in Figure 4A, and for simplicity, these components will not be discussed in detail.

As shown in Figure 4B, according to some embodiments, the dummy conductive layer 208b includes a mesh structure 209 and a conductive ring 210. The conductive ring 210 may be formed of conductive materials, including metals such as copper, aluminum, tungsten, etc., alloys thereof, or combinations thereof. The conductive ring 210 may also be called a metal ring. Mesh structure 209 and conductive ring 210 may be formed from the same or different materials.

The mesh structure 209 may be in contact (including mechanical and electrical contact) with the conductive ring 210, as shown in Figure 4B. Alternatively, as shown in FIG. 3 , mesh structure 209 and conductive ring 210 may be separated by dielectric layer 206 . The mesh structure 209 and the conductive ring 210 may have the same or different thicknesses in a direction perpendicular to the top surface of the dummy conductive layer 208b.

In some embodiments, mesh structure 209 is continuous, as shown in Figure 4B. In some other embodiments, mesh structure 209 is discontinuous, such as including multiple virtual conductive lines. In some embodiments, the spaces in mesh structure 209 are filled with dielectric material, such as dielectric layer 206 shown in FIG. 3 . Similarly, conductive ring 210 may be continuous or discontinuous.

The dummy conductive layer 208b may have a quadrangular shape, an elliptical shape, or any suitable shape in a top view. For example, dummy conductive layer 208b may have a rectangular shape as shown in Figure 4B. As another example, the dummy conductive layer 208b may be circular. The mesh structure 209 and the conductive ring 210 may have corresponding shapes. The arrangement of the conductive ring can further enhance the mechanical strength of the mesh structure 209 and prevent the mesh structure 209 from easily deforming, thereby further improving the ability to resist cracks.

The dummy conductive layer 208b may have a size in the range of about 50 μm to about 300 μm, such as 200 μm. For example, in embodiments where the dummy conductive layer 208b has a quadrilateral shape, the length L3 or L4 of the edge of the conductive ring 210 may be in the range of about 50 μm to about 300 μm, such as 200 μm. As another example, in an embodiment in which the dummy conductive layer 208b has an elliptical shape, the length of the major or minor axis of the conductive ring 210 may range from about 50 μm to about 300 μm, such as 200 μm.

Different layers of dummy conductive structures may have the same or different configurations. For example, the top (or upper) dummy conductive layer may include conductive ring 210, as shown in FIG. 4B, and the bottom (or lower) dummy conductive layer may not include conductive ring 210, such as as shown in FIG. 4A.

In summary, the semiconductor packaging structure according to the present invention includes one or more dummy conductive structures embedded in the substrate, thereby preventing crack propagation. Therefore, the failure rate during system assembly can be reduced. In addition, partially overlapping the corner portion (corner or corner) of the interposer by the dummy conductive structure can reduce the occupied space, and allow cracks corresponding to the corners of the interposer to be effectively blocked by the dummy metal structure. Additionally, the dummy conductive structures may be formed during formation of the wiring structures in the substrate to avoid additional costs and process complications.

While the invention has been described by way of example and in accordance with preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements as will be apparent to those skilled in the art. Therefore, the scope of the appended claims is to be given the broadest interpretation to cover all such modifications and similar arrangements.

Claims (19)

1. A semiconductor package structure, comprising:

a substrate including a wiring structure in a dielectric layer;

a dummy conductive mesh structure embedded in the substrate and spaced apart from the wiring structure by the dielectric layer;

an interposer disposed over the substrate;

an underfill material extending between the substrate and the interposer and extending over the dummy conductive mesh structure; and

a semiconductor die is disposed over the interposer and electrically coupled to the wiring structure through the interposer.

2. The semiconductor package according to claim 1, wherein the dummy conductive mesh structure partially overlaps with a corner of the interposer when viewed in a direction perpendicular to the upper surface of the substrate.

3. The semiconductor package according to claim 1, further comprising a plurality of dummy conductive mesh structures embedded in the substrate and partially overlapping each corner of the interposer when viewed in a direction substantially perpendicular to the upper surface of the substrate.

4. The semiconductor package according to claim 1, wherein the dummy conductive mesh structure comprises a metal.

5. The semiconductor package according to claim 1, further comprising a conductive ring surrounding the dummy conductive mesh structure and spaced apart from the wiring structure by the dielectric layer.

6. The semiconductor package according to claim 1, wherein the substrate comprises a package core disposed under the dummy conductive mesh structure.

7. The semiconductor package structure of claim 1, further comprising a bump structure electrically coupling the interposer to the wiring structure, wherein the underfill material extends between the dummy conductive mesh structure and the bump structure.

8. The semiconductor package according to claim 1, further comprising a frame attached to the substrate by an adhesive layer.

9. A semiconductor package structure, comprising:

a substrate including a wiring structure in the inter-metal dielectric layer;

a plurality of dummy conductive structures extending below the upper surface of the substrate and spaced apart from the wiring structure by the inter-metal dielectric layer;

an underfill material covering the plurality of dummy conductive structures;

an interposer disposed over the substrate and electrically coupled to the wiring structures, wherein the interposer partially overlaps the plurality of dummy conductive structures in a top view; and

a semiconductor die is disposed over and electrically coupled to the interposer.

10. The semiconductor package according to claim 9, further comprising a molding compound disposed over the interposer and surrounding the semiconductor die.

11. The semiconductor package according to claim 10, wherein sidewalls of the molding compound are coplanar with sidewalls of the interposer.

12. The semiconductor package according to claim 10, further comprising a bump structure surrounded by the molding compound and electrically connecting the semiconductor die to the interposer.

13. The semiconductor package according to claim 9, wherein each of the plurality of dummy conductive structures partially overlaps one corner of the interposer in a top view.

14. The semiconductor package according to claim 9, wherein the plurality of dummy conductive structures and the wiring structure are formed of the same material.

15. The semiconductor package according to claim 9, wherein at least one of the plurality of dummy conductive structures has a quadrilateral shape in a top view and has a dimension in a range of about 50 μιη to about 300 μιη; alternatively, at least one of the plurality of dummy conductive structures has an elliptical shape in a top view and has a size in a range of about 50 μm to about 300 μm.

16. A semiconductor package structure, comprising:

a substrate including a wiring structure in the inter-metal dielectric layer;

a dummy metal structure disposed in the inter-metal dielectric layer, wherein an upper surface of the dummy metal structure is not lower than an upper surface of the wiring structure;

an interposer disposed over the dummy metal structure;

a bump structure adjacent to the dummy metal structure and electrically coupling the interposer to the wiring structure;

a semiconductor die disposed over and electrically coupled to the interposer; and

an underfill material surrounding the bump structure and covering the dummy metal structure.

17. The semiconductor package structure of claim 16, wherein a portion of the wiring structure extends below a bottom surface of the dummy metal structure.

18. The semiconductor package according to claim 16, wherein, in a top view, a first edge of the dummy metal structure is covered by the interposer and a second edge of the dummy metal structure is located outside the interposer.

19. The semiconductor package according to claim 18, wherein the underfill material covers the first and second edges of the dummy metal structure in a top view.