CN117497508A - Semiconductor packaging structure - Google Patents

Semiconductor packaging structure Download PDF

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Publication number
CN117497508A
CN117497508A CN202310939155.0A CN202310939155A CN117497508A CN 117497508 A CN117497508 A CN 117497508A CN 202310939155 A CN202310939155 A CN 202310939155A CN 117497508 A CN117497508 A CN 117497508A
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CN
China
Prior art keywords
interposer
substrate
dummy conductive
semiconductor package
dummy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310939155.0A
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Chinese (zh)
Inventor
蔡宜霖
刘乃玮
许文松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MediaTek Inc
Original Assignee
MediaTek Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US18/342,149 external-priority patent/US20240038614A1/en
Application filed by MediaTek Inc filed Critical MediaTek Inc
Publication of CN117497508A publication Critical patent/CN117497508A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention discloses a semiconductor packaging structure, which comprises: a substrate including a wiring structure in a dielectric layer; a dummy conductive mesh structure embedded in the substrate and spaced apart from the wiring structure by the dielectric layer; an interposer disposed over the substrate; an underfill material extending between the substrate and the interposer and extending over the dummy conductive mesh structure; and a semiconductor die disposed over the interposer and electrically coupled to the wiring structure through the interposer. The semiconductor packaging structure comprises the dummy conductive net structure, can prevent cracks from expanding into the wiring structure of the substrate to cause electrical faults, has stronger toughness and mechanical strength, and has stronger fracture resistance, thereby further resisting the cracks and protecting the substrate and the wiring structure.

Description

Semiconductor packaging structure
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a semiconductor package structure.
Background
In addition to providing protection of the semiconductor die from environmental contaminants, the semiconductor package structure may also provide electrical connection between the semiconductor die packaged inside the semiconductor package structure and a substrate, such as a printed circuit board (printed circuit board, PCB).
While generally satisfactory, the existing semiconductor packages are not satisfactory in all respects. For example, when the semiconductor package is subjected to a heat treatment or reliability test, stress may cause the semiconductor package to crack. Accordingly, further improvements in semiconductor package structures are needed.
Disclosure of Invention
In view of the above, the present invention provides a semiconductor package structure to solve the above-mentioned problems.
According to a first aspect of the present invention, there is disclosed a semiconductor package structure comprising:
a substrate including a wiring structure in a dielectric layer;
a dummy conductive mesh structure embedded in the substrate and spaced apart from the wiring structure by the dielectric layer;
an interposer disposed over the substrate;
an underfill material extending between the substrate and the interposer and extending over the dummy conductive mesh structure; and
a semiconductor die is disposed over the interposer and electrically coupled to the wiring structure through the interposer.
Further, the dummy conductive mesh structure partially overlaps with a corner of the interposer when viewed in a direction perpendicular to the upper surface of the substrate. The dummy conductive mesh structure at least partially overlaps a corner or corner region of the interposer, which may prevent or delay crack propagation into the substrate caused by the interposer corner region, thereby protecting the substrate and wiring structures in the substrate.
Further, a plurality of dummy conductive mesh structures are embedded in the substrate and partially overlap each corner of the interposer when viewed in a direction substantially perpendicular to the upper surface of the substrate. So that the substrate portion corresponding to each corner region is protected.
Further, the dummy conductive mesh structure includes a metal. The metal material can improve the effect of crack resistance and is convenient to manufacture.
Further, a conductive ring surrounds the dummy conductive mesh structure and is spaced apart from the wiring structure by the dielectric layer. The overall mechanical strength is increased to further enhance resistance to cracking.
Further, the substrate includes a package core disposed under the dummy conductive mesh structure. Thereby enhancing the mechanical strength of the substrate and further preventing or alleviating the negative impact of cracks on the substrate.
Further, a bump structure electrically coupling the interposer to the wiring structure is also included, wherein the underfill material extends between the dummy conductive mesh structure and the bump structure. The underfill material protects the bump structure and mitigates the effects of stress on the substrate.
Further, the device also comprises a frame attached to the substrate through an adhesive layer. To reduce warpage, prevent warpage, and maintain flatness of the substrate.
According to a second aspect of the present invention, there is disclosed a semiconductor package structure comprising:
a substrate including a wiring structure in the inter-metal dielectric layer;
a plurality of dummy conductive structures extending below the upper surface of the substrate and spaced apart from the wiring structure by the inter-metal dielectric layer;
an underfill material covering the plurality of dummy conductive structures;
an interposer disposed over the substrate and electrically coupled to the wiring structures, wherein the interposer partially overlaps the plurality of dummy conductive structures in a top view; and
a semiconductor die is disposed over and electrically coupled to the interposer.
Further, a molding compound disposed over the interposer and surrounding the semiconductor die is included. The molding compound can protect the semiconductor die and improve the overall strength of the package.
Further, the sidewalls of the molding compound are coplanar with the sidewalls of the interposer. Thereby maintaining the stability and ease of use of the package structure.
Further, a bump structure is included, the bump structure being surrounded by the molding compound and electrically connecting the semiconductor die to the interposer. The bump structure is used for electrically connecting the semiconductor die with the substrate.
Further, in a top view, each of the plurality of dummy conductive structures partially overlaps one corner of the interposer. Thereby protecting the substrate portion corresponding to the corner of the interposer, protecting the wiring structure.
Further, the plurality of dummy conductive structures and the wiring structure are formed of the same material. Thereby facilitating the formation in the same process, facilitating the manufacture, reducing the cost increase or hardly increasing the cost.
Further, at least one of the plurality of dummy conductive structures has a quadrilateral shape in a top view and has a dimension in a range of about 50 μm to about 300 μm. To protect the substrate and the wiring structure with a small area.
Further, at least one of the plurality of dummy conductive structures has an elliptical shape in a top view and has a size in a range of about 50 μm to about 300 μm. To protect the substrate and the wiring structure with a small area.
According to a third aspect of the present invention, there is disclosed a semiconductor package structure comprising:
a substrate including a wiring structure in the inter-metal dielectric layer;
a dummy metal structure disposed in the inter-metal dielectric layer, wherein an upper surface of the dummy metal structure is not lower than an upper surface of the wiring structure;
an interposer disposed over the dummy metal structure;
a bump structure adjacent to the dummy metal structure and electrically coupling the interposer to the wiring structure;
a semiconductor die disposed over and electrically coupled to the interposer; and
an underfill material surrounding the bump structure and covering the dummy metal structure.
Further, a portion of the wiring structure extends below a bottom surface of the dummy metal structure. So that the dummy metal structure can protect the wiring structure.
Further, in a top view, a first edge of the dummy metal structure is covered by the interposer and a second edge of the dummy metal structure is located outside of the interposer. So that cracks corresponding to corners of the interposer can be effectively blocked by the dummy metal structure.
Further, in a top view, the underfill material covers the first and second edges of the dummy metal structures. The underfill material may mitigate the negative effects of stress on the substrate.
The semiconductor packaging structure of the invention comprises: a substrate including a wiring structure in a dielectric layer; a dummy conductive mesh structure embedded in the substrate and spaced apart from the wiring structure by the dielectric layer; an interposer disposed over the substrate; an underfill material extending between the substrate and the interposer and extending over the dummy conductive mesh structure; and a semiconductor die disposed over the interposer and electrically coupled to the wiring structure through the interposer. The semiconductor packaging structure comprises the dummy conductive net structure, can prevent cracks from expanding into the wiring structure of the substrate to cause electrical faults, has stronger toughness and mechanical strength, and has stronger fracture resistance, thereby further resisting the cracks and protecting the substrate and the wiring structure.
Drawings
Fig. 1 is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments of the invention;
FIG. 2 is a top view of an exemplary semiconductor package structure according to some embodiments of the invention;
fig. 3 is a cross-sectional view of a portion of an exemplary semiconductor package according to some embodiments of the invention; and
fig. 4A and 4B are top views of a portion of an exemplary semiconductor package according to some embodiments of the present invention.
Detailed Description
In the following detailed description of the embodiments of the present invention, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice them, and it is to be understood that other embodiments may be utilized and that mechanical, structural and procedural changes may be made without departing from the spirit and scope of the present invention. The invention relates to a method for manufacturing a semiconductor device. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of embodiments of the present invention is defined only by the appended claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. In the practice of the present invention, the dimensions and relative dimensions do not correspond to actual dimensions.
It will be understood that, although the terms "first," "second," "third," "primary," "secondary," etc. may be used herein to describe various components, elements, regions, layers and/or sections, these components, elements, regions, these layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first or primary component, region, layer or section discussed below could be termed a second or secondary component, region, layer or section without departing from the teachings of the present inventive concept.
Further, spatially relative terms such as "below," "under," "above," "over," and the like may be used herein for ease of description to describe one component or feature's relationship thereto. Another component or feature as shown. In addition to the orientations depicted in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, it will also be understood that when a "layer" is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
The terms "about", "approximately" and "approximately" generally mean within a range of ±20% of a specified value, or ±10% of the specified value, or ±5% of the specified value, or ±3% of the specified value, or ±2% of the specified value, or ±1% of the specified value, or ±0.5% of the specified value. The prescribed value of the present invention is an approximation. When not specifically described, the stated values include the meaning of "about," approximately, "and" about. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular terms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concepts. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It will be understood that when an "element" or "layer" is referred to as being "on," "connected to," "coupled to" or "adjacent to" another element or layer, it can be directly on, connected to, coupled to or adjacent to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to," or "directly adjacent to" another element or layer, there are no intervening elements or layers present.
Note that: (i) The same features will be denoted by the same reference numerals throughout the figures and not necessarily described in detail in each of the figures in which they appear, and (ii) a series of figures may show different aspects of a single item, each of which is associated with various reference labels that may appear in the entire sequence or may appear only in selected figures of the sequence.
Semiconductor package structures including dummy conductive structures are described according to some embodiments of the invention. A dummy conductive structure is embedded in the substrate to prevent crack propagation into the substrate, thereby avoiding electrical (electrical) failure.
Fig. 1 is a cross-sectional view of a semiconductor package 100 according to some embodiments of the invention. Additional features may be added to the semiconductor package 100. Some features described below may be replaced or eliminated for different embodiments. To simplify the drawing, only a portion of the semiconductor package 100 is shown.
As shown in fig. 1, a semiconductor package 100 includes a substrate 102, according to some embodiments. The substrate 102 may be a coreless substrate or a cored substrate (coreless substrate) to prevent warpage of the substrate 102. The substrate 102 may have a wiring structure therein. In some embodiments, the wiring structure includes conductive pads, conductive vias, conductive lines, conductive posts, and the like, or combinations thereof. The wiring structure may be formed of a conductive material including a metal such as copper, aluminum, tungsten, or the like, an alloy thereof, or a combination thereof.
The wiring structure may be disposed in the dielectric layer. The dielectric layer may also be referred to as an inter-metal dielectric (IMD) layer. In some embodiments, the dielectric layer may be formed of an organic material such as a polymer base material, an inorganic material including silicon nitride, silicon oxide, silicon oxynitride, or the like, or a combination thereof.
It should be noted that the configuration of the substrate 102 shown in the drawings is merely exemplary and is not intended to limit the present invention. Any desired semiconductor elements may be formed in the substrate 102 and on the substrate 102. However, for simplicity of the drawing, only the flat substrate 102 is shown.
According to some embodiments, the semiconductor package structure 100 includes a plurality of conductive terminals (conductive terminal) 104 disposed below the substrate 102 and electrically coupled to the wiring structure. The conductive terminals 104 may include micro bumps, controlled collapse chip connection (controlled collapse chip connection, C4) bumps, solder balls, ball Grid Array (BGA) balls, or the like, or combinations thereof. The conductive terminals 104 may be formed from conductive materials including metals (e.g., tungsten, titanium, tantalum, ruthenium, cobalt, copper, aluminum, platinum, tin, silver, gold), metal compounds (e.g., tantalum nitride, titanium nitride, tungsten nitride), and the like, alloys thereof, or combinations thereof.
According to some embodiments, the semiconductor package 100 includes an interposer (interposer) 110 disposed over the substrate 102. One or more vias 112 may be included in interposer 110. The via 112 may be formed of a conductive material, and exemplary conductive materials are previously described. The vias 112 may extend from a first surface of the interposer 110 to a second surface of the interposer 110 opposite the first surface.
The via 112 may be electrically coupled to the wiring structure of the substrate 102 through the plurality of bump structures 106. Bump structures 106 may include micro bumps, controlled collapse chip connection (C4) bumps, solder balls, ball Grid Array (BGA) balls, and the like, or combinations thereof. Bump structure 106 may include the materials discussed above with respect to conductive terminal 104 and will not be repeated.
According to some embodiments, the semiconductor package 100 includes an underfill material 108 extending between the interposer 110 and the substrate 102. The underfill material 108 may surround the bump structures 106 and may fill gaps between the bump structures 106 to provide structural support. In some embodiments, the underfill material 108 comprises a polymer, such as an epoxy. The underfill material 108 may be dispensed using capillary force (capillarity force) and then cured by any suitable curing process.
According to some embodiments, semiconductor package structure 100 includes one or more semiconductor die 120 and 122 disposed over interposer 110. In some embodiments, semiconductor dies 120 and 122 each independently comprise a system on a chip (SoC) die, a logic device, a memory device, a Radio Frequency (RF) device, or the like, or any combination thereof. For example, semiconductor die 120 and 122 may each include a micro control unit (micro control unit, MCU) die, a microprocessor unit (microprocessor unit, MPU) die, a power management integrated circuit (power management integrated circuit, PMIC) die, a radio frequency front end (radio frequency front end, RFFE) die, an acceleration processing unit (accelerated processing unit, APU) die, a central processing unit (central processing unit, CPU) die, a graphics processing unit (graphics processing unit, GPU) die, an input-output (IO) chip, a dynamic random access memory (dynamic random access memory, DRAM) controller, a Static Random Access Memory (SRAM), a high bandwidth memory (high bandwidth memory, HBM), an application processor (application processor, AP) chip, an application specific integrated circuit (application specific integrated circuit, ASIC) die, or the like, or any combination thereof.
Semiconductor dies 120 and 122 can include the same or different devices. For example, semiconductor die 120 may include an ASIC die, and semiconductor die 122 may include an HBM. The semiconductor package 100 may include more than two semiconductor die and may also include one or more passive components, such as resistors, capacitors, or inductors, disposed over the interposer 110.
Semiconductor dies 120 and 122 can be electrically coupled to interposer 110 through a plurality of bump structures 116. Bump structures 116 may include micro bumps, controlled collapse chip connection (C4) bumps, solder balls, ball Grid Array (BGA) balls, and the like, or combinations thereof. Bump structure 116 may include the materials discussed above with respect to bump structure 106 and will not be repeated.
According to some embodiments, semiconductor package structure 100 includes an underfill material 118 that extends between interposer 110 and semiconductor dies 120 and 122. An underfill material 118 may surround the bump structures 116 and may fill gaps between the bump structures 116 to provide structural support. Underfill material 118 may be similar to underfill material 108 and will not be repeated.
According to some embodiments, the semiconductor package structure 100 includes a molding material 124 disposed over the interposer 110. The molding compound 124 may surround the semiconductor die 120, 122, bump structure 116, and underfill material 118 to protect these components from environmental effects, thereby preventing them from damage due to stress, chemicals, and moisture. The molding compound 124 may be formed of a non-conductive material including moldable polymers, epoxies, resins, and the like, or combinations thereof.
As shown in fig. 1, the sidewalls of the molding compound 124 may be substantially coplanar with the sidewalls of the interposer 110. In some embodiments, the top surfaces (upper surfaces) of the semiconductor die 120, 122 are exposed by the molding compound 124, as shown in fig. 1.
According to some embodiments, the semiconductor package 100 includes a frame 130 attached to the substrate 102 by an adhesive layer 128. The frame 130 may be disposed along the sidewalls of the substrate 102 to reduce warpage, prevent bending, and maintain flatness of the substrate 102. The frame 130 may surround the interposer 110 and the semiconductor dies 120, 122.
In some embodiments, the frame 130 and the adhesive layer 128 are separated from the underfill layer 128 by a gap. A portion of the top surface of the substrate 102 is thus exposed, and one or more passive components 126 (e.g., resistors, capacitors, or inductors) may be disposed over a portion of the top surface of the substrate 102. Passive components 126 may also be disposed under substrate 102 and between conductive terminals 104.
According to some embodiments, cracks may form in the underfill material 108 when the semiconductor package 100 is subjected to heat treatment or reliability testing. In an embodiment of the present invention, the semiconductor package 100 includes one or more dummy conductive structures to prevent cracks from propagating into the wiring structure of the substrate 102 to cause electrical failure. A semiconductor package structure 100 including the dummy conductive structure will be described with reference to fig. 2.
Fig. 2 is a top view of the semiconductor package structure 100 of fig. 1, according to some embodiments. Fig. 1 is a cross-sectional view of a semiconductor package 100 taken along line I-I' shown in fig. 2.
As shown in fig. 2, the semiconductor package structure 100 includes an additional (or extra) semiconductor die 122 disposed over the interposer 110 and adjacent to the semiconductor die 120, according to some embodiments. Semiconductor dies 120 and 122 may include the same or different devices, and exemplary devices or apparatus have been previously described.
According to some embodiments, the semiconductor package structure 100 includes a plurality of dummy conductive structures 200, each dummy conductive structure 200 partially overlapping a corner (or corner, corner) of the interposer 110, and such that cracks corresponding to the corner of the interposer may be effectively blocked by the dummy metal structure; cracks may occur near the corners because the corners are prone to stress. Accordingly, the dummy conductive structures 200 disposed under (or directly under) the corners of the interposer 110 may resist crack propagation into the wiring structure of the substrate 102 while taking up less space. A portion of the semiconductor package structure 100 including one of the dummy conductive structures 200 will be described below with reference to fig. 3. In the embodiment of the invention, the wiring structure is a wiring for electrical connection and signal connection in the substrate, and is a wiring with substantial electrical function. The dummy conductive structure 200 does not have a substantial electrical function, and is not used for electrical connection and signal connection.
Fig. 3 is a cross-sectional view of a portion of a semiconductor package 100 according to some embodiments of the invention. Portions of the semiconductor package structure in fig. 3 may include the same or similar components as the semiconductor package structure 100 in fig. 1, which will not be discussed in detail for simplicity.
As shown in fig. 3, the wiring structure of the substrate 102 includes horizontal interconnects (horizontal interconnect) (e.g., conductive layer 202) and vertical interconnects (vertical interconnect) (e.g., conductive vias 204). The conductive vias 204 may be electrically coupled to the conductive layers 202 at different layers. Conductive layer 202 and conductive via 204 may be disposed in a dielectric layer (or inter-metal dielectric layer) 206.
The dummy conductive structure 200 may be formed of a conductive material including a metal such as copper, aluminum, tungsten, or the like, an alloy thereof, or a combination thereof. The dummy conductive structure 200 may also be referred to as a dummy metal structure. In some embodiments, the dummy conductive structure 200 and the conductive layer 202 are made of the same material and formed in the same process to reduce costs and simplify the process. The dummy conductive structure 200 may be surrounded by the dielectric layer 206 and not electrically coupled to the wiring structure. For example, the dummy conductive structure 200 is electrically floating, e.g., not connected to any voltage (not connected to a positive voltage, ground, or negative voltage).
The dummy conductive structure 200 may be disposed adjacent to the bump structure 106. The underfill material 108 may cover a top surface (upper surface) of the dummy conductive structure 200. Specifically, the underfill material 108 may extend from an edge of the dummy conductive structure 200 to another edge of the dummy conductive structure 200.
The dummy conductive structure 200 may be disposed at the topmost layer to resist crack propagation. In particular, a top surface (upper surface) of the dummy conductive structure 200 may be substantially flush or higher than a top surface (upper surface) of the wiring structure (e.g., a topmost layer of the conductive layer 202). In one embodiment, the dummy conductive structure 200 may include a topmost metal layer in the substrate 102 that belongs to the dummy conductive structure 200 and is higher than a topmost layer of the wiring structure of the substrate 102 (e.g., a topmost conductive layer of the wiring structure). In one embodiment, the dummy conductive structure 200 may be located in the substrate 102 and on the uppermost layer of the substrate 102, for example, the upper surface of the dummy conductive layer 208 on the uppermost layer of the dummy conductive structure 200 is flush with the upper surface of the substrate 102, so as to facilitate manufacturing and better protect the substrate and the wiring structure. In one embodiment, the dummy conductive structure 200 may be located within the substrate 102, e.g., the upper surface of the dummy conductive layer 208 of the topmost layer of the dummy conductive structure 200 may be higher than the upper surface of the substrate 102 (e.g., with portions in direct contact with the underfill material 108), while the remaining portions may be within the substrate 102 (i.e., below the upper surface of the substrate 102) to facilitate fabrication and better protect the substrate and wiring structures, and thus reduce the need for wiring structure re-placement to facilitate placement of wiring structures within the substrate while protecting the substrate and wiring structures. In one embodiment, the dummy conductive structure 200 may be located over the substrate 102 (on the upper surface of the substrate 102) where the dummy conductive structure 200 is in direct contact with the underfill material 108 and is directly covered by the underfill material 108, thereby facilitating fabrication and better protecting the substrate and wiring structures, and thus reducing the need for re-routing the wiring structures, even eliminating the need for re-routing the wiring structures, so that the placement of the wiring structures in the substrate protects both the substrate and the wiring structures.
In some embodiments, the dummy conductive structure 200 has one or more dummy conductive layers 208. As shown in fig. 3, the dummy conductive structure 200 may include two dummy conductive layers 208, but is not limited thereto. For example, the dummy conductive structure 200 may include one dummy conductive layer 208 or more than two dummy conductive layers 208. In some embodiments, adjacent dummy conductive layers 208 are staggered, as shown in fig. 3. In some other embodiments, adjacent dummy conductive layers 208 are aligned with each other.
As shown in fig. 3, adjacent dummy conductive layers 208 may be separated by a dielectric layer 206, but are not limited thereto. For example, the dummy conductive structure 200 may include one or more conductive vias (not shown) connecting adjacent dummy conductive layers 208. The dielectric layer 206 may cover a top surface (upper surface) of the dummy conductive structure 200.
The dummy conductive structure 200 may be surrounded by a wiring structure. In particular, some of the conductive layers 202 and conductive vias 204 may be disposed on opposite sides of the dummy conductive structure 200 (or around, peripheral to the dummy conductive structure 200), and some of the conductive layers 202 may extend below a bottom surface (lower surface) of the dummy conductive structure 200. In one embodiment, the routing structures may be arranged to leave areas or spaces for forming the dummy conductive structures 200, where, for example, the dummy conductive structures 200 may be at least partially located within the substrate. In one embodiment, the wiring structure may not need to be rearranged, and at this time, for example, the dummy conductive structure 200 may be disposed on the upper surface of the substrate, and the dummy conductive structure 200 may be in direct contact with the upper surface of the substrate, so as to reduce interference to the wiring structure of the substrate, and protect the substrate and the wiring structure. In one embodiment of the present invention, the dummy conductive structure 200 may be used to protect the wiring structure from damage or delay the wiring structure from damage before a crack reaches the wiring structure; thereby prolonging the service life and the normal working time of the substrate.
As previously described, in some embodiments, the substrate 102 may be a cored substrate. In these embodiments, the substrate 102 includes a package core (not shown) disposed under the dummy conductive structure 200. The provision of the package core may enhance the mechanical strength of the substrate, further preventing or mitigating the negative impact of cracks on the substrate. Depending on the design, a portion of the routing structure may be disposed between the dummy conductive structure 200 and the package core. Therefore, the wiring structure can be further protected, the possibility of damaging the wiring structure is reduced, the mechanical and electrical properties of the wiring structure are protected to be in a better state, and the working stability of the semiconductor is ensured. In one embodiment of the present invention, the adjacent dummy conductive layers 208 are staggered such that, for example, when the dummy conductive layer 208 of the upper layer breaks, the adjacent dummy conductive layer of the lower layer is metal at the corresponding position, so that the crack is prevented from continuing to extend, and thus the substrate and the wiring structure in the substrate can be protected. Therefore, the design of the invention can further resist crack extension, protect the structural integrity of the substrate, improve the mechanical strength of the substrate and protect the safety of the wiring structure in the substrate. In one embodiment of the present invention, all adjacent dummy conductive layers 208 may be arranged in a staggered arrangement to improve the resistance of the substrate to cracking. In one embodiment of the present invention, the staggered arrangement may refer to the regions of the underlying dummy conductive layer 208 having metal aligned with non-metallic regions of the overlying dummy conductive layer 208 (e.g., the regions being dielectric material, etc.), thereby improving the resistance of the substrate to cracking. In one embodiment, in the staggered arrangement of the upper dummy conductive layer 20 and the lower dummy conductive layer 208, the upper layer and the lower layer may be two layers immediately adjacent to each other, or may be other layers spaced therebetween. Thus, when the dummy conductive structure 200 has a plurality of dummy conductive layers 208, at least two of the dummy conductive layers 208 are staggered. This allows for more flexibility in the placement of the dummy conductive structures 200 while improving the resistance of the substrate to cracking. In one embodiment, the dummy conductive structures 200 may be disposed only in corner (or corner) areas corresponding to the interposer 110, thereby reducing interference with the wiring structures in the substrate 102, ensuring proper placement and functional integrity of the wiring structures. In one embodiment, the dummy conductive structures 200 may be disposed in other areas in addition to the corner (or corner) areas corresponding to the interposer 110 to facilitate fabrication or resist crack propagation in particular areas. In one embodiment, the dummy conductive structures 200 may have one or more, e.g., interconnected, dummy conductive structures 200, and thus may be considered a dummy conductive structure 200 for ease of fabrication; as another example, the dummy conductive structure 200 is a plurality of discrete dummy conductive structures 200 to correspond to crack resistance at different locations.
The configuration of the dummy conductive layer 208 will be described below with reference to fig. 4A and 4B. Fig. 4A and 4B are top views of the dummy conductive layer 208 of fig. 3, according to some embodiments.
Fig. 4A is a top view of a dummy conductive layer 208a according to some embodiments. For simplicity of the drawing, only a portion of the dummy conductive layer 208a is shown. As shown in fig. 4A, the dummy conductive layer 208a includes a mesh (mesh) structure 209, according to some embodiments. The dummy conductive structure may also be referred to as a dummy conductive mesh structure.
In some embodiments, the mesh structure (dummy conductive mesh structure) 209 is continuous, as shown in fig. 4A. In some other embodiments, the mesh structure 209 is discontinuous, for example comprising a plurality of virtual conductive lines (dashed conductive line). In some embodiments, the space (e.g., the hollowed-out portion) in the mesh structure 209 is filled with a dielectric material, such as the dielectric layer 206 shown in fig. 3.
The dummy conductive layer 208a may have a quadrilateral shape, an elliptical shape, or any suitable shape in plan view. For example, the dummy conductive layer 208a may have a rectangular shape (the periphery is substantially rectangular), as shown in fig. 4A. For another example, the dummy conductive layer 208a may be circular.
The dummy conductive layer 208a may have a size in the range of about 50 μm to about 300 μm, such as 200 μm. For example, in an embodiment in which the dummy conductive layer 208a has a quadrilateral shape, the length L1 or L2 of the dummy conductive layer 208a may be in the range of about 50 μm to about 300 μm, such as 200 μm, and the quadrilateral shape of the dummy conductive layer 208a may facilitate protecting a portion of the substrate corresponding to a corner of the interposer and facilitating fabrication. Also for example, in embodiments where the dummy conductive layer 208a has an elliptical shape, the length of the major or minor axis of the dummy conductive layer 208 may be in the range of about 50 μm to about 300 μm, such as 200 μm, and the elliptical shape of the dummy conductive layer 208a may facilitate protecting portions of the substrate corresponding to corners of the interposer and ease fabrication. The dummy conductive layer 208a may also have, for example, a circular shape, a triangular shape, or other shapes.
The dummy conductive structures of the different layers may have the same or different dimensions. For example, the upper layer of the dummy conductive structure may have a larger size than the lower layer of the dummy conductive structure. The dummy conductive structures of different layers may have the same or different densities (i.e., distances between the wires) of the mesh structure 209. For example, the upper layer of the dummy conductive structure may have a greater density of mesh structures 209 than the lower layer of the dummy conductive structure. In one embodiment of the present invention, the mesh structure 209 has stronger toughness, mechanical strength, and resistance to cracking, and thus is suitable for use as an integral part of a dummy conductive structure, thereby further resisting cracking, protecting the substrate and wiring structure. In one embodiment, the dummy conductive layer 208 may also be other shapes or patterns. In one embodiment, the dummy conductive layer 208 of each layer may have one or more such mesh structures 209 compositions as shown in fig. 4A or/and fig. 4B. For example, each layer of dummy conductive layer 208 may have a mesh structure 209 as shown in fig. 4A or/and 4B, whereby in the above description, the metal region of the lower layer of dummy conductive layer 208 (mesh structure 209) corresponds to the middle hollowed-out region of the upper layer of dummy conductive layer 208 (mesh structure 209), thereby improving the protection of the substrate and wiring structure using a multi-layer staggered manner, preventing or delaying crack extension to the wiring structure. As another example, each layer of the dummy conductive layers 208 may have a plurality of such mesh structures 209 as shown in fig. 4A or/and 4B, with the mesh structures 209 in each layer being spaced apart, whereby in the above description, the dummy conductive layers 208 (mesh structures 209) of the lower layer are disposed corresponding to the spacing between the dummy conductive layers 208 (mesh structures 209) of the upper layer. Also for example, the dummy conductive layer 208 of a part of the layers has one such mesh structure 209 as shown in fig. 4A or/and 4B, and the dummy conductive layer 208 of another part of the layers has a plurality of such mesh structures 209 as shown in fig. 4A or/and 4B, whereby in the above description, one mesh structure 209 of an upper layer or a lower layer is provided to correspond to the intervals of the plurality of mesh structures 209 of the other layers; etc. In one embodiment of the present invention, there may be other staggered arrangements so that if a crack occurs in the upper layer, the crack does not easily continue to extend downward.
Fig. 4B is a top view of the dummy conductive layer 208B, according to some embodiments. For simplicity of the drawing, only a portion of the dummy conductive layer 208b is shown. The dummy conductive layer 208B in fig. 4B may include the same or similar components as the dummy conductive layer 208a in fig. 4A, and for simplicity, these components will not be discussed in detail.
As shown in fig. 4B, the dummy conductive layer 208B includes a mesh structure 209 and a conductive ring (conductive ring) 210, according to some embodiments. The conductive ring 210 may be formed of a conductive material including a metal such as copper, aluminum, tungsten, and the like, alloys thereof, or combinations thereof. The conductive ring 210 may also be referred to as a metal ring. The mesh structure 209 and the conductive ring 210 may be formed of the same or different materials.
The mesh structure 209 may be in contact (including mechanical and electrical contact) with the conductive ring 210, as shown in fig. 4B. Alternatively, as shown in fig. 3, the mesh structure 209 and the conductive ring 210 may be spaced apart by the dielectric layer 206. The mesh structure 209 and the conductive ring 210 may have the same or different thicknesses in a direction perpendicular to the top surface of the dummy conductive layer 208 b.
In some embodiments, the mesh structure 209 is continuous, as shown in fig. 4B. In some other embodiments, the mesh structure 209 is discontinuous, for example, comprising a plurality of virtual conductive lines. In some embodiments, the spaces in the mesh structure 209 are filled with a dielectric material, such as the dielectric layer 206 shown in fig. 3. Similarly, the conductive ring 210 may be continuous or discontinuous.
The dummy conductive layer 208b may have a quadrilateral shape, an elliptical shape, or any suitable shape in top view. For example, the dummy conductive layer 208B may have a rectangular shape as shown in fig. 4B. For another example, the dummy conductive layer 208b may be circular. The mesh structure 209 and the conductive ring 210 may have corresponding shapes. The provision of the conductive ring can further strengthen the mechanical strength of the mesh structure 209 and prevent the mesh structure 209 from being easily deformed or the like, thereby further improving the resistance to cracking.
The dummy conductive layer 208b may have a size in the range of about 50 μm to about 300 μm, such as 200 μm. For example, in an embodiment in which the dummy conductive layer 208b has a quadrilateral shape, the length L3 or L4 of the edge of the conductive ring 210 may be in the range of about 50 μm to about 300 μm, such as 200 μm. Also for example, in embodiments where the dummy conductive layer 208b has an elliptical shape, the length of the major or minor axis of the conductive ring 210 may be in the range of about 50 μm to about 300 μm, such as 200 μm.
The dummy conductive structures of the different layers may have the same or different configurations. For example, the top (or upper) dummy conductive layer may include conductive rings 210 as shown in fig. 4B, and the bottom (or lower) dummy conductive layer may not include conductive rings 210, as shown in fig. 4A, for example.
In summary, the semiconductor package structure according to the present invention includes one or more dummy conductive structures embedded in a substrate, so that crack propagation may be prevented. Therefore, the failure rate during the system assembly can be reduced. In addition, the dummy conductive structures partially overlap corners (corners or corners) of the interposer may reduce occupied space and enable cracks corresponding to the corners of the interposer to be effectively blocked by the dummy metal structures. In addition, the dummy conductive structures may be formed during the formation of the wiring structures in the substrate to avoid additional costs and complicating the process.
While the invention has been described by way of example and in terms of preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). The scope of the appended claims is therefore to be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims (19)

1. A semiconductor package structure, comprising:
a substrate including a wiring structure in a dielectric layer;
a dummy conductive mesh structure embedded in the substrate and spaced apart from the wiring structure by the dielectric layer;
an interposer disposed over the substrate;
an underfill material extending between the substrate and the interposer and extending over the dummy conductive mesh structure; and
a semiconductor die is disposed over the interposer and electrically coupled to the wiring structure through the interposer.
2. The semiconductor package according to claim 1, wherein the dummy conductive mesh structure partially overlaps with a corner of the interposer when viewed in a direction perpendicular to the upper surface of the substrate.
3. The semiconductor package according to claim 1, further comprising a plurality of dummy conductive mesh structures embedded in the substrate and partially overlapping each corner of the interposer when viewed in a direction substantially perpendicular to the upper surface of the substrate.
4. The semiconductor package according to claim 1, wherein the dummy conductive mesh structure comprises a metal.
5. The semiconductor package according to claim 1, further comprising a conductive ring surrounding the dummy conductive mesh structure and spaced apart from the wiring structure by the dielectric layer.
6. The semiconductor package according to claim 1, wherein the substrate comprises a package core disposed under the dummy conductive mesh structure.
7. The semiconductor package structure of claim 1, further comprising a bump structure electrically coupling the interposer to the wiring structure, wherein the underfill material extends between the dummy conductive mesh structure and the bump structure.
8. The semiconductor package according to claim 1, further comprising a frame attached to the substrate by an adhesive layer.
9. A semiconductor package structure, comprising:
a substrate including a wiring structure in the inter-metal dielectric layer;
a plurality of dummy conductive structures extending below the upper surface of the substrate and spaced apart from the wiring structure by the inter-metal dielectric layer;
an underfill material covering the plurality of dummy conductive structures;
an interposer disposed over the substrate and electrically coupled to the wiring structures, wherein the interposer partially overlaps the plurality of dummy conductive structures in a top view; and
a semiconductor die is disposed over and electrically coupled to the interposer.
10. The semiconductor package according to claim 9, further comprising a molding compound disposed over the interposer and surrounding the semiconductor die.
11. The semiconductor package according to claim 10, wherein sidewalls of the molding compound are coplanar with sidewalls of the interposer.
12. The semiconductor package according to claim 10, further comprising a bump structure surrounded by the molding compound and electrically connecting the semiconductor die to the interposer.
13. The semiconductor package according to claim 9, wherein each of the plurality of dummy conductive structures partially overlaps one corner of the interposer in a top view.
14. The semiconductor package according to claim 9, wherein the plurality of dummy conductive structures and the wiring structure are formed of the same material.
15. The semiconductor package according to claim 9, wherein at least one of the plurality of dummy conductive structures has a quadrilateral shape in a top view and has a dimension in a range of about 50 μιη to about 300 μιη; alternatively, at least one of the plurality of dummy conductive structures has an elliptical shape in a top view and has a size in a range of about 50 μm to about 300 μm.
16. A semiconductor package structure, comprising:
a substrate including a wiring structure in the inter-metal dielectric layer;
a dummy metal structure disposed in the inter-metal dielectric layer, wherein an upper surface of the dummy metal structure is not lower than an upper surface of the wiring structure;
an interposer disposed over the dummy metal structure;
a bump structure adjacent to the dummy metal structure and electrically coupling the interposer to the wiring structure;
a semiconductor die disposed over and electrically coupled to the interposer; and
an underfill material surrounding the bump structure and covering the dummy metal structure.
17. The semiconductor package structure of claim 16, wherein a portion of the wiring structure extends below a bottom surface of the dummy metal structure.
18. The semiconductor package according to claim 16, wherein, in a top view, a first edge of the dummy metal structure is covered by the interposer and a second edge of the dummy metal structure is located outside the interposer.
19. The semiconductor package according to claim 18, wherein the underfill material covers the first and second edges of the dummy metal structure in a top view.
CN202310939155.0A 2022-08-01 2023-07-28 Semiconductor packaging structure Pending CN117497508A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US63/369,977 2022-08-01
US18/342,149 2023-06-27
US18/342,149 US20240038614A1 (en) 2022-08-01 2023-06-27 Semiconductor package structure

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CN117497508A true CN117497508A (en) 2024-02-02

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