CN117495990B - PET sinogram data compression storage method, system and equipment based on monolithic FPGA - Google Patents
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Abstract
The invention discloses a PET sinogram compression storage method, system and equipment based on a single-chip FPGA, belonging to the field of digital data processing of medical images. The method can compress, store and output the sinogram data acquired in the PET imaging process in real time in the FPGA, and comprises the following steps: after the PET detector and the electronic system measure the binary data of the distance and the angle of the corresponding response line of each coincidence event in real time, the corresponding compression address and the corresponding counting label are respectively obtained by a bit cutting and splicing mode, the compression address and the corresponding multiple counts are counted and stored in the FPGA, new data obtained by subsequent measurement are inserted or accumulated on the existing data according to the compression address and by a traversing comparison mode, and sine graph data is finally output according to the coordinate sequence after the number of the required instance of statistical imaging. The invention can obviously reduce the storage space required by storing the sinogram in the FPGA, realize the real-time statistics and storage of the sinogram in the FPGA and improve the reconstruction speed of the PET image.
Description
Technical Field
The invention relates to the field of digital data processing of medical images, in particular to a PET sinogram data compression storage method, system and equipment based on a single-chip FPGA.
Background
Positron emission tomography (Positron Emission Tomography, PET) is an advanced nuclear medicine imaging mode, the basic imaging principle of which is that a radionuclide is injected into a living body to mark a tracer, the radionuclide decays to generate positrons, the positrons annihilate with negative electrons of organism tissues and emit a pair of annihilation photons in opposite directions, a detector is combined with an electronic system to detect a pair of photons generated by the same annihilation event by conforming to a measurement technology, and a Line of the positions of each pair of photons is used for locating the position where annihilation occurs, wherein the Line is called a Line of Response (LOR). The sinogram (Sinogram) is a two-dimensional statistical histogram using projection coordinate data of a large number of response lines as storage addresses and counts as storage data, and a final PET image is obtained by performing data correction and image reconstruction on the sinogram.
The electronics system in a conventional PET system typically outputs raw position information corresponding to the event and stores and calculates the position information in a computer system to obtain sinogram data. In an application scenario requiring fast PET imaging, for example, in a scenario of conducting real-time guidance on radiotherapy by using PET imaging information in image-guided radiotherapy, a process of acquiring a sinogram by using an FPGA in an electronic system needs to be accelerated, which includes a storage and output process of the sinogram.
For the current high-precision PET system, the addresses of the sinograms are finely divided, which can make the storage space required for completely storing the sinograms greater than or equal to 1Mb, for example, the size of the sinograms is 512×256, and the length of each count storage is 8 bits. While current PET systems typically use more detector rings to construct longer axial detector systems in order to achieve higher sensitivity, this can result in PET systems having tens or even hundreds of imaging slices, i.e., the sinograms corresponding to these imaging slices need to be stored in the FPGA at the same time. The RAM storage resources in the FPGA are very limited, for example, the maximum RAM storage resources that can be provided by the Xilinx Spartan-7, artix-7 and Kintex-7 series FPGAs are 4.32, 13.14 and 34.38Mb respectively, so that it is difficult to completely store the sinogram in a monolithic FPGA in a manner of taking the projection coordinate data as a storage address and counting as storage data, and further, it is impossible to implement acceleration of PET imaging based on the monolithic FPGA, or the system integration is poor and the cost is high due to using multiple FPGAs.
In view of this, the present invention has been made.
Disclosure of Invention
The invention aims to provide a PET sinogram data compression storage method, a system and equipment of a monolithic FPGA, which can compress and store sinogram data in a PET rapid imaging application scene, greatly reduce RAM storage resources required by sinogram storage, store all sinograms of the system in the monolithic FPGA, realize acceleration of PET imaging process, improve system integration level and reduce cost, and further solve the technical problems in the prior art.
The invention aims at realizing the following technical scheme:
A PET sinogram data compression storage method of a monolithic FPGA comprises the following steps:
Step 1: real-time measurement system composed of PET detector and electronic system is used to obtain the corresponding response line data of each annihilation event by real-time measurement according to the measurement method, and each response line data is represented by its projection space coordinates and is recorded as Wherein/>For the length of the perpendicular from the origin of coordinates to the line of response,/>An included angle between the vertical line and the x axis;
step 2: obtaining corresponding compressed addresses of each response line data obtained in the step 1 in a bit cutting mode, and marking the corresponding compressed addresses as Meanwhile, a counting label corresponding to each response line data is obtained in a bit splicing mode and is marked as N;
step 3: for each response line data processed in step2 Is stored according to the data format of each response line data and corresponds to the compressed address/>After the sizes are sequenced, the data are inserted into the RAM of the monolithic FPGA as new response line data or accumulated on stored response line data, so that statistics and storage of the response line data are realized; in the data format of the response line data storage/>A count index representing corresponding data in the sinogram;
Step 4: judging whether the number of cases of response line data stored in the RAM of the monolithic FPGA meets the PET imaging requirement, if not, repeating the steps 1 to 3, and if so, executing the step 5;
step 5: and outputting the response line data stored in the RAM of the FPGA according to the coordinate sequence of the sinogram.
A PET sinogram data compression storage system of a monolithic FPGA is used for realizing the method of the invention, which comprises the following steps:
the system comprises a real-time measurement system and a sinogram data processing module comprising a single-chip FPGA; wherein,
The real-time measurement system consists of a PET detector and an electronic system, and can obtain response line data corresponding to each annihilation event by real-time measurement according to a measurement method, wherein each response line data is represented by projection space coordinates and is recorded asWherein/>For the length of the perpendicular from the origin of coordinates to the line of response,/>An included angle between the vertical line and the x axis;
The sinogram data processing module is used for receiving response line data output by the real-time measurement system, and obtaining a corresponding compressed address in an FPGA (field programmable gate array) in a bit truncation manner for each received response line data Meanwhile, the counting label N of the response line data is obtained in a bit splicing mode; each response line is then dataData format of/>Count marks representing corresponding data in the sinogram and compressing addresses/>, corresponding to the data of each response lineAfter the sizes are sequenced, the data are inserted into the RAM of the monolithic FPGA as new response line data or accumulated on stored response line data, so that statistics and storage of the response line data are realized; and repeating the processing until the number of the cases of the response line data stored in the RAM of the single-chip FPGA meets the requirement of PET imaging, and outputting the response line data stored in the RAM of the single-chip FPGA according to the coordinate sequence of the sinogram.
A processing apparatus, comprising:
At least one memory for storing one or more programs;
At least one processor capable of executing one or more programs stored in the memory, which when executed by the processor, enable the processor to implement the methods of the present invention.
Compared with the prior art, the PET sinogram data compression storage method, system and equipment for the monolithic FPGA have the beneficial effects that:
By utilizing the continuity and sparsity of the sinogram in the PET rapid imaging application scene, address data of a plurality of adjacent counts are compressed and stored in a mode of combining the plurality of counts according to compressed addresses, so that the storage of invalid count data is greatly avoided, compared with the mode of completely storing the sinogram, the storage resource of a RAM is greatly saved, the fact that all sinograms of a system are stored in a single-chip FPGA is realized, the acceleration of the PET imaging process by the single-chip FPGA is further realized, and meanwhile, the system integration level is improved and the cost is reduced.
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In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a small animal PET system imaging principle according to an embodiment of the present invention.
Fig. 2 is a flowchart of a method for storing PET sinogram data based on a monolithic FPGA according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of a sinogram data compression storage method according to an embodiment of the present invention.
FIG. 4 is a schematic diagram of test results provided by an embodiment of the present invention, wherein (a) is the maximum number of instances received by each of the 39 sinograms; (b) The maximum number of compression cases stored for each sinogram RAM after data compression.
Detailed Description
The technical scheme in the embodiment of the invention is clearly and completely described below in combination with the specific content of the invention; it will be apparent that the described embodiments are only some embodiments of the invention, but not all embodiments, which do not constitute limitations of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
The terms that may be used herein will first be described as follows:
The term "and/or" is intended to mean that either or both may be implemented, e.g., X and/or Y are intended to include both the cases of "X" or "Y" and the cases of "X and Y".
The terms "comprises," "comprising," "includes," "including," "has," "having" or other similar referents are to be construed to cover a non-exclusive inclusion. For example: including a particular feature (e.g., a starting material, component, ingredient, carrier, formulation, material, dimension, part, means, mechanism, apparatus, step, procedure, method, reaction condition, processing condition, parameter, algorithm, signal, data, product or article of manufacture, etc.), should be construed as including not only a particular feature but also other features known in the art that are not explicitly recited.
The term "consisting of … …" is meant to exclude any technical feature element not explicitly listed. If such term is used in a claim, the term will cause the claim to be closed, such that it does not include technical features other than those specifically listed, except for conventional impurities associated therewith. If the term is intended to appear in only a clause of a claim, it is intended to limit only the elements explicitly recited in that clause, and the elements recited in other clauses are not excluded from the overall claim.
Unless specifically stated or limited otherwise, the terms "mounted," "connected," "secured," and the like should be construed broadly to include, for example: the connecting device can be fixedly connected, detachably connected or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms herein above will be understood by those of ordinary skill in the art as the case may be.
The terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," etc. refer to an orientation or positional relationship based on that shown in the drawings, merely for ease of description and to simplify the description, and do not explicitly or implicitly indicate that the apparatus or element in question must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the present disclosure.
The PET sinogram data compression storage method and system based on the monolithic FPGA provided by the invention are described in detail below. What is not described in detail in the embodiments of the present invention belongs to the prior art known to those skilled in the art. The specific conditions are not noted in the examples of the present invention and are carried out according to the conditions conventional in the art or suggested by the manufacturer. The reagents or apparatus used in the examples of the present invention were conventional products commercially available without the manufacturer's knowledge.
As shown in fig. 2, an embodiment of the present invention provides a PET sinogram data compression storage method based on a monolithic FPGA, including the following steps:
Step 1: real-time measurement system composed of PET detector and electronic system is used to obtain the corresponding response line data of each annihilation event by real-time measurement according to the measurement method, and each response line data is represented by its projection space coordinates and is recorded as Wherein/>For the length of the perpendicular from the origin of coordinates to the line of response,/>An included angle between the vertical line and the x axis;
step 2: obtaining corresponding compressed addresses of each response line data obtained in the step 1 in a bit cutting mode, and marking the corresponding compressed addresses as Meanwhile, a counting label corresponding to each response line data is obtained in a bit splicing mode and is marked as N;
For a sinogram of size A B, the projection space coordinates of the original LOR data are in The corresponding value range is 0-A-1, and the number of bits required by binary storage in the FPGA is/>，/>The corresponding value range is 0-B-1, and the number of bits required by binary number storage in the FPGA is/>Compressing and storing data of 2 m×2n adjacent count addresses in the sinogram, wherein m and n are non-negative integers and are not 0 at the same time, and using compressed address/>, corresponding to each response line data obtained in a bit truncation mode under a binary data format, of each response line dataThe method comprises the following steps:
；
；
meanwhile, the counting index N can be calculated by the following formula:
；
The counting label N of each response line data can be obtained directly by a bit-wise splicing mode under a binary data format, and is expressed as follows:
。
the data format stored in the RAM of the FPGA can be expressed as WhereinCounting marks of corresponding data in the sinogram, wherein the total number of the counts is 2 m×2n;
Step 3: counting and storing LOR data in RAM of FPGA, and storing the data Ordering according to the size. For any LOR data obtained by real-time measurement, performing traversal comparison between a compressed address serving as new LOR data and a compressed address of stored LOR data in RAM, determining a RAM address where the new LOR data is stored, if the compressed address is stored in RAM, calculating a calculation label/>, corresponding to the stored LOR data, according to the calculation label obtained by calculating in the step 2Adding 1; if the compressed address is not stored in the RAM, the new LOR data is processed according to the corresponding compressed address/>Is inserted into RAM, and the calculation label/>, corresponding to the LOR data, is calculatedLet 1, others/>And is noted as 0.
Step 4: judging whether the instance number of LOR data stored in the RAM of the monolithic FPGA meets the PET imaging requirement, if not, repeating the steps 1 to 3, and if so, executing the step 5;
Step 5: the LOR data stored in the RAM of the monolithic FPGA are output according to the coordinate sequence of the sinogram, and the following 3 modes are adopted according to different specific application occasions:
Mode one: directly according to storage The data format is read out sequentially from front to back according to the stored RAM address;
Mode two: restoring the compressed address and the count label into original LOR coordinate data, combining the count obtained by statistics under the coordinate, and according to the following steps Is read out according to the data format of the data;
mode three: and outputting the complete sinogram count according to the coordinate sequence without outputting LOR coordinate data, namely outputting A multiplied by B count data in sequence, wherein the count output which is not counted is 0.
The embodiment of the invention also provides a PET sinogram data compression storage system of the monolithic FPGA, which is used for realizing the method, and comprises the following steps:
the system comprises a real-time measurement system and a sinogram data processing module comprising a single-chip FPGA; wherein,
The real-time measurement system consists of a PET detector and an electronic system, and can obtain response line data corresponding to each annihilation event by real-time measurement according to a measurement method, wherein each response line data is represented by projection space coordinates and is recorded asWherein/>For the length of the perpendicular from the origin of coordinates to the line of response,/>An included angle between the vertical line and the x axis;
The sinogram data processing module is used for receiving response line data output by the real-time measurement system, and obtaining a corresponding compressed address in an FPGA (field programmable gate array) in a bit truncation manner for each received response line data Meanwhile, the counting label N of the response line data is obtained in a bit splicing mode; each response line is then dataData format of/>Count marks representing corresponding data in the sinogram and compressing addresses/>, corresponding to the data of each response lineAfter the sizes are sequenced, the data are inserted into the RAM of the monolithic FPGA as new response line data or accumulated on stored response line data, so that statistics and storage of the response line data are realized; and repeating the processing until the number of the cases of the response line data stored in the RAM of the single-chip FPGA meets the requirement of PET imaging, and outputting the response line data stored in the RAM of the single-chip FPGA according to the coordinate sequence of the sinogram.
The embodiment of the invention further provides a processing device, which comprises:
At least one memory for storing one or more programs;
at least one processor capable of executing one or more programs stored in the memory, which when executed by the processor, enable the processor to implement the methods described above.
In order to clearly show the technical scheme and the technical effects provided by the invention, the PET sinogram data compression storage method and system based on the monolithic FPGA provided by the embodiment of the invention are described in detail in the following by using a specific embodiment.
Example 1
The complete exemplary implementation of the invention is accomplished based on a small animal PET prototype electronics system autonomously designed by a nuclear detection and nuclear power national emphasis laboratory, which constitutes a complete small animal PET system with a PET detector and an image reconstruction system. In the imaging process of the PET system, as shown in fig. 1, the PET detector is composed of 20 detector sub-rings, 20×20 sinograms are generated by adopting a 3D data acquisition mode, in order to realize rapid imaging, the system stores acquired data in 39 2D sinograms by adopting a data recombination mode, and finally, image reconstruction is realized through a 2D filtered back projection (Filtered Back Projection, FBP) algorithm. In the PET imaging process, the FPGA is used for accelerating the sinogram acquisition process, and the storage resource limitation of the FPGA and the subsequent expandability of the system are considered, so that the complete storage of all sinograms is difficult to realize in a single-chip FPGA.
The embodiment provides a single-chip FPGA-based PET sinogram data compression and storage method, which is used for compressing and storing the sinogram data, and the flow of the method is shown in a figure 2, and the method comprises the following steps:
Step 1: real-time measurement system composed of PET detector and electronic system, and each LOR data corresponding to each annihilation event is obtained by real-time measurement according to the measurement method, and each LOR data is represented by its projection space coordinates and is recorded as Wherein/>For the length of the perpendicular from the origin of coordinates to the line of response,/>An included angle between the vertical line and the x axis;
In this embodiment, the distance coordinate of the sinogram is divided into 512 steps, the angle coordinate is divided into 256 steps, the total address number of each sinogram is 131072, the depth of the storage count under each address is 8 bits, and the total required storage space is the total required storage space when all 39 sinograms are completely stored in the FPGA The method comprises the following steps:
。
step 2: the compressed address is recorded as For a sinogram of size A B, the original LOR data is/>The corresponding value range is 0-A-1, and the number of bits required by binary storage in the FPGA is/>，/>The corresponding value range is 0-B-1, and the number of bits required by binary number storage in the FPGA is/>Compressing and storing address data of 2 m×2n adjacent counts in the sinogram, wherein m and n are non-negative integers and are not 0 at the same time, and the compressed address stored under a binary data format obtained in a bit truncation mode is as follows:
；
；
meanwhile, the counting label can be directly calculated by the following formula:
，
And can be directly obtained by a bit-wise splicing mode under a binary data format, which is expressed as follows:
。
The data format stored in the FPGA can be expressed as Wherein/>Counting marks of corresponding data in the sinogram, wherein the total number of the counts is 2 m×2n;
in this embodiment, the size of the sinogram is 512×256, address data of adjacent 1×4 counts in the sinogram is compressed and stored, that is, m=0 and n=2 are taken, and the calculation of the compressed address can be expressed as:
；
；
the calculation of the count index may be expressed as:
；
the data format stored in the RAM of the FPGA can be expressed as A schematic diagram of the sinogram data compression process is shown in fig. 3.
Step 3: in RAM of FPGA, LOR data is counted and stored, and the stored data is according to the following stepsOrdering the sizes of (3); for any LOR data obtained by real-time measurement, performing traversal comparison on the compressed address of the new data and the compressed address of the data stored in the RAM, determining the RAM address where the new data is stored, and if the compressed address is stored in the RAM, calculating the stored/>, according to the counting label obtained by the step 2Adding 1; if the compressed address is not stored in the RAM, the new data is pressed/>Is inserted into RAM and the LOR data therein is corresponding/>Let 1, others/>And is noted as 0.
Step 4: judging whether the LOR instance number stored in the RAM of the monolithic FPGA meets the PET imaging requirement, if not, repeating the steps 1 to 3, and if so, executing the step 5.
Step 5: the stored data are output according to the coordinate sequence of the sinogram, and the following 3 types are different according to specific application occasions:
Mode one: directly according to storage The data format is read out sequentially from front to back according to the stored RAM address;
Mode two: restoring the compressed address and the count label into original LOR coordinate data, combining the count obtained by statistics under the coordinate, and according to the following steps Is read out according to the data format of the data;
mode three: and outputting the complete sinogram count according to the coordinate sequence without outputting LOR coordinate data, namely outputting A multiplied by B count data in sequence, wherein the count output which is not counted is 0.
In this embodiment, in order to reduce the pressure stored and calculated by the back-end computer, the data is outputted by using the output method 2.
The data compression method used in the examples was tested using simulation data generated by the GATE monte carlo simulation platform, with the simulation time set to 50ms. Fig. 4 (a) is a maximum number of cases received by each of the 39 sinograms, the total number of cases is 157541, wherein the maximum number of cases of a single sinogram is 8049, which is far smaller than the total number of addresses of the sinograms, so that the data of the sinograms have sparseness; in FIG. 4 (b), the maximum number of compression cases is stored in each sinogram RAM after data compression, the total number of compression cases is 41955, and the maximum count is 15, so that the data is compressed in binaryThe storage depth of the compressed data is set to be 4 bits, the total data length of the compressed data is 31 bits, and then the size/> -of the storage space required after the compression can be calculatedThe method comprises the following steps:
；
By adopting the sinogram data compression method in the embodiment, all sinogram data can be stored in the monolithic FPGA, and the data compression rate R can be calculated as follows:
。
In summary, the embodiment of the invention utilizes the continuity and sparsity of the sinogram in the PET rapid imaging application scene, compresses address data of a plurality of adjacent counts and stores the address data in a mode of combining the compressed addresses with the plurality of counts, thereby greatly avoiding the storage of invalid count data, greatly saving RAM storage resources compared with a mode of completely storing the sinogram, realizing the storage of all sinograms of the system in a single-chip FPGA, further realizing the acceleration of the PET imaging process by the single-chip FPGA, and improving the integration level of the system and reducing the cost.
Those of ordinary skill in the art will appreciate that: all or part of the flow of the method implementing the above embodiments may be implemented by a program to instruct related hardware, where the program may be stored in a computer readable storage medium, and the program may include the flow of the embodiment of each method as described above when executed. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a random-access Memory (Random Access Memory, RAM), or the like.
The foregoing is only a preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims. The information disclosed in the background section herein is only for enhancement of understanding of the general background of the invention and is not to be taken as an admission or any form of suggestion that this information forms the prior art already known to those of ordinary skill in the art.
Claims (5)
1. A PET sinogram data compression storage method of a monolithic FPGA is characterized by comprising the following steps:
Step 1: real-time measurement system composed of PET detector and electronic system is used to obtain the corresponding response line data of each annihilation event by real-time measurement according to the measurement method, and each response line data is represented by its projection space coordinates and is recorded as Wherein/>For the length of the perpendicular from the origin of coordinates to the line of response,/>An included angle between the vertical line and the x axis;
step 2: obtaining corresponding compressed addresses of each response line data obtained in the step 1 in a bit cutting mode, and marking the corresponding compressed addresses as Meanwhile, a counting label corresponding to each response line data is obtained in a bit splicing mode and is marked as N; if the sinogram size to be PET imaged is A×B, in the projection space coordinates of the original response line data,/>, the sinogram size to be PET imaged is A×BThe corresponding value range is 0-A-1, and the number of bits required by binary storage in the FPGA is/>，/>The corresponding value range is 0-B-1, and the number of bits required by binary number storage in the FPGA is/>Compressing and storing data of 2 m×2n adjacent count addresses in the sinogram, wherein m and n are non-negative integers and are not 0 at the same time, and using compressed address/>, corresponding to each response line data obtained in a bit truncation mode under a binary data format, of each response line dataThe method comprises the following steps:
；
；
Meanwhile, the counting label N of each response line data obtained in a bit splicing mode under a binary data format is as follows:
；
step 3: for each response line data processed in step2 Is stored according to the data format of each response line data and corresponds to the compressed address/>After the sizes are sequenced, the data are inserted into the RAM of the monolithic FPGA as new response line data or accumulated on stored response line data, so that statistics and storage of the response line data are realized; data format of response line data storage/>A count index representing corresponding data in the sinogram;
Step 4: judging whether the number of cases of response line data stored in the RAM of the monolithic FPGA meets the PET imaging requirement, if not, repeating the steps 1 to 3, and if so, executing the step 5;
step 5: and outputting the response line data stored in the RAM of the FPGA according to the coordinate sequence of the sinogram.
2. The method for storing PET sinogram data of a monolithic FPGA according to claim 1, wherein in step 3, any response line data measured in real time is inserted as new response line data in a RAM of the monolithic FPGA or accumulated on stored response line data in the following manner, comprising:
Performing traversal comparison on the compressed address of the new response line data and the compressed address of the stored response line data in the RAM of the monolithic FPGA, determining the RAM address where the new response line data is stored, and if the compressed address is stored in the RAM, counting the number of the stored response line data according to the number of the numbers calculated in the step 2 Adding 1; if the compressed address is not stored in the RAM, the new response line data is processed according to the corresponding compressed address/>Is inserted into RAM, and the corresponding counting label/>, of the response line data is added to the RAMLet 1, others/>And is noted as 0.
3. The method for storing PET sinogram data of a monolithic FPGA according to claim 1, wherein in step 5, the outputting the response line data stored in the RAM of the FPGA according to the coordinate sequence of the sinogram includes:
mode one: directly stored as The data format is read out sequentially from front to back according to the stored RAM address;
mode two: restoring the compressed address and the count label into original response line data coordinates, combining the count counted under the coordinates, and according to the following steps Is read out according to the data format of the data;
Mode three: and outputting complete sinogram count according to the coordinate sequence without outputting the coordinates of the response line data, namely outputting A multiplied by B count data in sequence, wherein the count output without statistics is 0.
4. A monolithic FPGA-based PET sinogram data compression storage system for implementing the method of any one of claims 1-3, comprising:
the system comprises a real-time measurement system and a sinogram data processing module comprising a single-chip FPGA; wherein,
The real-time measurement system consists of a PET detector and an electronic system, and can obtain response line data corresponding to each annihilation event by real-time measurement according to a measurement method, wherein each response line data is represented by projection space coordinates and is recorded asWherein/>For the length of the perpendicular from the origin of coordinates to the line of response,/>An included angle between the vertical line and the x axis;
The sinogram data processing module is used for receiving response line data output by the real-time measurement system, and obtaining a corresponding compressed address in an FPGA (field programmable gate array) in a bit truncation manner for each received response line data Meanwhile, the counting label N of the response line data is obtained in a bit splicing mode; each response line is then dataData format of/>Count marks representing corresponding data in the sinogram and compressing addresses/>, corresponding to the data of each response lineAfter the sizes are sequenced, the data are inserted into the RAM of the monolithic FPGA as new response line data or accumulated on stored response line data, so that statistics and storage of the response line data are realized; and repeating the processing until the number of the cases of the response line data stored in the RAM of the single-chip FPGA meets the requirement of PET imaging, and outputting the response line data stored in the RAM of the single-chip FPGA according to the coordinate sequence of the sinogram.
5. A processing apparatus, comprising:
At least one memory for storing one or more programs;
At least one processor capable of executing one or more programs stored in the memory, which when executed by the processor, cause the processor to implement the method of any of claims 1-3.
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